2 * Copyright (c) 2013, The Linux Foundation. All rights reserved.
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
14 #include <linux/kernel.h>
15 #include <linux/bitops.h>
16 #include <linux/err.h>
17 #include <linux/bug.h>
18 #include <linux/export.h>
19 #include <linux/clk-provider.h>
20 #include <linux/delay.h>
21 #include <linux/regmap.h>
22 #include <linux/math64.h>
24 #include <asm/div64.h>
30 #define CMD_UPDATE BIT(0)
31 #define CMD_ROOT_EN BIT(1)
32 #define CMD_DIRTY_CFG BIT(4)
33 #define CMD_DIRTY_N BIT(5)
34 #define CMD_DIRTY_M BIT(6)
35 #define CMD_DIRTY_D BIT(7)
36 #define CMD_ROOT_OFF BIT(31)
39 #define CFG_SRC_DIV_SHIFT 0
40 #define CFG_SRC_SEL_SHIFT 8
41 #define CFG_SRC_SEL_MASK (0x7 << CFG_SRC_SEL_SHIFT)
42 #define CFG_MODE_SHIFT 12
43 #define CFG_MODE_MASK (0x3 << CFG_MODE_SHIFT)
44 #define CFG_MODE_DUAL_EDGE (0x2 << CFG_MODE_SHIFT)
50 static int clk_rcg2_is_enabled(struct clk_hw *hw)
52 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
56 ret = regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG, &cmd);
60 return (cmd & CMD_ROOT_OFF) == 0;
63 static u8 clk_rcg2_get_parent(struct clk_hw *hw)
65 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
66 int num_parents = __clk_get_num_parents(hw->clk);
70 ret = regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &cfg);
74 cfg &= CFG_SRC_SEL_MASK;
75 cfg >>= CFG_SRC_SEL_SHIFT;
77 for (i = 0; i < num_parents; i++)
78 if (cfg == rcg->parent_map[i])
84 static int update_config(struct clk_rcg2 *rcg)
88 struct clk_hw *hw = &rcg->clkr.hw;
89 const char *name = __clk_get_name(hw->clk);
91 ret = regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG,
92 CMD_UPDATE, CMD_UPDATE);
96 /* Wait for update to take effect */
97 for (count = 500; count > 0; count--) {
98 ret = regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG, &cmd);
101 if (!(cmd & CMD_UPDATE))
106 WARN(1, "%s: rcg didn't update its configuration.", name);
110 static int clk_rcg2_set_parent(struct clk_hw *hw, u8 index)
112 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
115 ret = regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG,
117 rcg->parent_map[index] << CFG_SRC_SEL_SHIFT);
121 return update_config(rcg);
125 * Calculate m/n:d rate
128 * rate = ----------- x ---
132 calc_rate(unsigned long rate, u32 m, u32 n, u32 mode, u32 hid_div)
150 clk_rcg2_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
152 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
153 u32 cfg, hid_div, m = 0, n = 0, mode = 0, mask;
155 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &cfg);
157 if (rcg->mnd_width) {
158 mask = BIT(rcg->mnd_width) - 1;
159 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + M_REG, &m);
161 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + N_REG, &n);
165 mode = cfg & CFG_MODE_MASK;
166 mode >>= CFG_MODE_SHIFT;
169 mask = BIT(rcg->hid_width) - 1;
170 hid_div = cfg >> CFG_SRC_DIV_SHIFT;
173 return calc_rate(parent_rate, m, n, mode, hid_div);
176 static long _freq_tbl_determine_rate(struct clk_hw *hw,
177 const struct freq_tbl *f, unsigned long rate,
178 unsigned long *p_rate, struct clk_hw **p_hw)
180 unsigned long clk_flags;
183 f = qcom_find_freq(f, rate);
187 clk_flags = __clk_get_flags(hw->clk);
188 p = clk_get_parent_by_index(hw->clk, f->src);
189 if (clk_flags & CLK_SET_RATE_PARENT) {
192 rate *= f->pre_div + 1;
202 rate = __clk_get_rate(p);
204 *p_hw = __clk_get_hw(p);
210 static long clk_rcg2_determine_rate(struct clk_hw *hw, unsigned long rate,
211 unsigned long *p_rate, struct clk_hw **p)
213 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
215 return _freq_tbl_determine_rate(hw, rcg->freq_tbl, rate, p_rate, p);
218 static int clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f)
223 if (rcg->mnd_width && f->n) {
224 mask = BIT(rcg->mnd_width) - 1;
225 ret = regmap_update_bits(rcg->clkr.regmap,
226 rcg->cmd_rcgr + M_REG, mask, f->m);
230 ret = regmap_update_bits(rcg->clkr.regmap,
231 rcg->cmd_rcgr + N_REG, mask, ~(f->n - f->m));
235 ret = regmap_update_bits(rcg->clkr.regmap,
236 rcg->cmd_rcgr + D_REG, mask, ~f->n);
241 mask = BIT(rcg->hid_width) - 1;
242 mask |= CFG_SRC_SEL_MASK | CFG_MODE_MASK;
243 cfg = f->pre_div << CFG_SRC_DIV_SHIFT;
244 cfg |= rcg->parent_map[f->src] << CFG_SRC_SEL_SHIFT;
245 if (rcg->mnd_width && f->n)
246 cfg |= CFG_MODE_DUAL_EDGE;
247 ret = regmap_update_bits(rcg->clkr.regmap,
248 rcg->cmd_rcgr + CFG_REG, mask, cfg);
252 return update_config(rcg);
255 static int __clk_rcg2_set_rate(struct clk_hw *hw, unsigned long rate)
257 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
258 const struct freq_tbl *f;
260 f = qcom_find_freq(rcg->freq_tbl, rate);
264 return clk_rcg2_configure(rcg, f);
267 static int clk_rcg2_set_rate(struct clk_hw *hw, unsigned long rate,
268 unsigned long parent_rate)
270 return __clk_rcg2_set_rate(hw, rate);
273 static int clk_rcg2_set_rate_and_parent(struct clk_hw *hw,
274 unsigned long rate, unsigned long parent_rate, u8 index)
276 return __clk_rcg2_set_rate(hw, rate);
279 const struct clk_ops clk_rcg2_ops = {
280 .is_enabled = clk_rcg2_is_enabled,
281 .get_parent = clk_rcg2_get_parent,
282 .set_parent = clk_rcg2_set_parent,
283 .recalc_rate = clk_rcg2_recalc_rate,
284 .determine_rate = clk_rcg2_determine_rate,
285 .set_rate = clk_rcg2_set_rate,
286 .set_rate_and_parent = clk_rcg2_set_rate_and_parent,
288 EXPORT_SYMBOL_GPL(clk_rcg2_ops);
295 static const struct frac_entry frac_table_675m[] = { /* link rate of 270M */
296 { 52, 295 }, /* 119 M */
297 { 11, 57 }, /* 130.25 M */
298 { 63, 307 }, /* 138.50 M */
299 { 11, 50 }, /* 148.50 M */
300 { 47, 206 }, /* 154 M */
301 { 31, 100 }, /* 205.25 M */
302 { 107, 269 }, /* 268.50 M */
306 static struct frac_entry frac_table_810m[] = { /* Link rate of 162M */
307 { 31, 211 }, /* 119 M */
308 { 32, 199 }, /* 130.25 M */
309 { 63, 307 }, /* 138.50 M */
310 { 11, 60 }, /* 148.50 M */
311 { 50, 263 }, /* 154 M */
312 { 31, 120 }, /* 205.25 M */
313 { 119, 359 }, /* 268.50 M */
317 static int clk_edp_pixel_set_rate(struct clk_hw *hw, unsigned long rate,
318 unsigned long parent_rate)
320 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
321 struct freq_tbl f = *rcg->freq_tbl;
322 const struct frac_entry *frac;
324 s64 src_rate = parent_rate;
326 u32 mask = BIT(rcg->hid_width) - 1;
329 if (src_rate == 810000000)
330 frac = frac_table_810m;
332 frac = frac_table_675m;
334 for (; frac->num; frac++) {
336 request *= frac->den;
337 request = div_s64(request, frac->num);
338 if ((src_rate < (request - delta)) ||
339 (src_rate > (request + delta)))
342 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG,
345 f.pre_div >>= CFG_SRC_DIV_SHIFT;
350 return clk_rcg2_configure(rcg, &f);
356 static int clk_edp_pixel_set_rate_and_parent(struct clk_hw *hw,
357 unsigned long rate, unsigned long parent_rate, u8 index)
359 /* Parent index is set statically in frequency table */
360 return clk_edp_pixel_set_rate(hw, rate, parent_rate);
363 static long clk_edp_pixel_determine_rate(struct clk_hw *hw, unsigned long rate,
364 unsigned long *p_rate, struct clk_hw **p)
366 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
367 const struct freq_tbl *f = rcg->freq_tbl;
368 const struct frac_entry *frac;
370 s64 src_rate = *p_rate;
372 u32 mask = BIT(rcg->hid_width) - 1;
375 /* Force the correct parent */
376 *p = __clk_get_hw(clk_get_parent_by_index(hw->clk, f->src));
378 if (src_rate == 810000000)
379 frac = frac_table_810m;
381 frac = frac_table_675m;
383 for (; frac->num; frac++) {
385 request *= frac->den;
386 request = div_s64(request, frac->num);
387 if ((src_rate < (request - delta)) ||
388 (src_rate > (request + delta)))
391 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG,
393 hid_div >>= CFG_SRC_DIV_SHIFT;
396 return calc_rate(src_rate, frac->num, frac->den, !!frac->den,
403 const struct clk_ops clk_edp_pixel_ops = {
404 .is_enabled = clk_rcg2_is_enabled,
405 .get_parent = clk_rcg2_get_parent,
406 .set_parent = clk_rcg2_set_parent,
407 .recalc_rate = clk_rcg2_recalc_rate,
408 .set_rate = clk_edp_pixel_set_rate,
409 .set_rate_and_parent = clk_edp_pixel_set_rate_and_parent,
410 .determine_rate = clk_edp_pixel_determine_rate,
412 EXPORT_SYMBOL_GPL(clk_edp_pixel_ops);
414 static long clk_byte_determine_rate(struct clk_hw *hw, unsigned long rate,
415 unsigned long *p_rate, struct clk_hw **p_hw)
417 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
418 const struct freq_tbl *f = rcg->freq_tbl;
419 unsigned long parent_rate, div;
420 u32 mask = BIT(rcg->hid_width) - 1;
426 p = clk_get_parent_by_index(hw->clk, f->src);
427 *p_hw = __clk_get_hw(p);
428 *p_rate = parent_rate = __clk_round_rate(p, rate);
430 div = DIV_ROUND_UP((2 * parent_rate), rate) - 1;
431 div = min_t(u32, div, mask);
433 return calc_rate(parent_rate, 0, 0, 0, div);
436 static int clk_byte_set_rate(struct clk_hw *hw, unsigned long rate,
437 unsigned long parent_rate)
439 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
440 struct freq_tbl f = *rcg->freq_tbl;
442 u32 mask = BIT(rcg->hid_width) - 1;
444 div = DIV_ROUND_UP((2 * parent_rate), rate) - 1;
445 div = min_t(u32, div, mask);
449 return clk_rcg2_configure(rcg, &f);
452 static int clk_byte_set_rate_and_parent(struct clk_hw *hw,
453 unsigned long rate, unsigned long parent_rate, u8 index)
455 /* Parent index is set statically in frequency table */
456 return clk_byte_set_rate(hw, rate, parent_rate);
459 const struct clk_ops clk_byte_ops = {
460 .is_enabled = clk_rcg2_is_enabled,
461 .get_parent = clk_rcg2_get_parent,
462 .set_parent = clk_rcg2_set_parent,
463 .recalc_rate = clk_rcg2_recalc_rate,
464 .set_rate = clk_byte_set_rate,
465 .set_rate_and_parent = clk_byte_set_rate_and_parent,
466 .determine_rate = clk_byte_determine_rate,
468 EXPORT_SYMBOL_GPL(clk_byte_ops);
470 static const struct frac_entry frac_table_pixel[] = {
478 static long clk_pixel_determine_rate(struct clk_hw *hw, unsigned long rate,
479 unsigned long *p_rate, struct clk_hw **p)
481 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
482 unsigned long request, src_rate;
484 const struct freq_tbl *f = rcg->freq_tbl;
485 const struct frac_entry *frac = frac_table_pixel;
486 struct clk *parent = clk_get_parent_by_index(hw->clk, f->src);
488 *p = __clk_get_hw(parent);
490 for (; frac->num; frac++) {
491 request = (rate * frac->den) / frac->num;
493 src_rate = __clk_round_rate(parent, request);
494 if ((src_rate < (request - delta)) ||
495 (src_rate > (request + delta)))
499 return (src_rate * frac->num) / frac->den;
505 static int clk_pixel_set_rate(struct clk_hw *hw, unsigned long rate,
506 unsigned long parent_rate)
508 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
509 struct freq_tbl f = *rcg->freq_tbl;
510 const struct frac_entry *frac = frac_table_pixel;
511 unsigned long request, src_rate;
513 u32 mask = BIT(rcg->hid_width) - 1;
515 struct clk *parent = clk_get_parent_by_index(hw->clk, f.src);
517 for (; frac->num; frac++) {
518 request = (rate * frac->den) / frac->num;
520 src_rate = __clk_round_rate(parent, request);
521 if ((src_rate < (request - delta)) ||
522 (src_rate > (request + delta)))
525 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG,
528 f.pre_div >>= CFG_SRC_DIV_SHIFT;
533 return clk_rcg2_configure(rcg, &f);
538 static int clk_pixel_set_rate_and_parent(struct clk_hw *hw, unsigned long rate,
539 unsigned long parent_rate, u8 index)
541 /* Parent index is set statically in frequency table */
542 return clk_pixel_set_rate(hw, rate, parent_rate);
545 const struct clk_ops clk_pixel_ops = {
546 .is_enabled = clk_rcg2_is_enabled,
547 .get_parent = clk_rcg2_get_parent,
548 .set_parent = clk_rcg2_set_parent,
549 .recalc_rate = clk_rcg2_recalc_rate,
550 .set_rate = clk_pixel_set_rate,
551 .set_rate_and_parent = clk_pixel_set_rate_and_parent,
552 .determine_rate = clk_pixel_determine_rate,
554 EXPORT_SYMBOL_GPL(clk_pixel_ops);