2 * Copyright (c) 2013, The Linux Foundation. All rights reserved.
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
14 #include <linux/kernel.h>
15 #include <linux/bitops.h>
16 #include <linux/err.h>
17 #include <linux/bug.h>
18 #include <linux/export.h>
19 #include <linux/clk-provider.h>
20 #include <linux/delay.h>
21 #include <linux/regmap.h>
22 #include <linux/math64.h>
24 #include <asm/div64.h>
29 #define CMD_UPDATE BIT(0)
30 #define CMD_ROOT_EN BIT(1)
31 #define CMD_DIRTY_CFG BIT(4)
32 #define CMD_DIRTY_N BIT(5)
33 #define CMD_DIRTY_M BIT(6)
34 #define CMD_DIRTY_D BIT(7)
35 #define CMD_ROOT_OFF BIT(31)
38 #define CFG_SRC_DIV_SHIFT 0
39 #define CFG_SRC_SEL_SHIFT 8
40 #define CFG_SRC_SEL_MASK (0x7 << CFG_SRC_SEL_SHIFT)
41 #define CFG_MODE_SHIFT 12
42 #define CFG_MODE_MASK (0x3 << CFG_MODE_SHIFT)
43 #define CFG_MODE_DUAL_EDGE (0x2 << CFG_MODE_SHIFT)
49 static int clk_rcg2_is_enabled(struct clk_hw *hw)
51 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
55 ret = regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG, &cmd);
59 return (cmd & CMD_ROOT_OFF) == 0;
62 static u8 clk_rcg2_get_parent(struct clk_hw *hw)
64 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
65 int num_parents = __clk_get_num_parents(hw->clk);
69 ret = regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &cfg);
73 cfg &= CFG_SRC_SEL_MASK;
74 cfg >>= CFG_SRC_SEL_SHIFT;
76 for (i = 0; i < num_parents; i++)
77 if (cfg == rcg->parent_map[i])
83 static int update_config(struct clk_rcg2 *rcg)
87 struct clk_hw *hw = &rcg->clkr.hw;
88 const char *name = __clk_get_name(hw->clk);
90 ret = regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG,
91 CMD_UPDATE, CMD_UPDATE);
95 /* Wait for update to take effect */
96 for (count = 500; count > 0; count--) {
97 ret = regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG, &cmd);
100 if (!(cmd & CMD_UPDATE))
105 WARN(1, "%s: rcg didn't update its configuration.", name);
109 static int clk_rcg2_set_parent(struct clk_hw *hw, u8 index)
111 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
114 ret = regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG,
116 rcg->parent_map[index] << CFG_SRC_SEL_SHIFT);
120 return update_config(rcg);
124 * Calculate m/n:d rate
127 * rate = ----------- x ---
131 calc_rate(unsigned long rate, u32 m, u32 n, u32 mode, u32 hid_div)
149 clk_rcg2_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
151 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
152 u32 cfg, hid_div, m = 0, n = 0, mode = 0, mask;
154 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &cfg);
156 if (rcg->mnd_width) {
157 mask = BIT(rcg->mnd_width) - 1;
158 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + M_REG, &m);
160 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + N_REG, &n);
164 mode = cfg & CFG_MODE_MASK;
165 mode >>= CFG_MODE_SHIFT;
168 mask = BIT(rcg->hid_width) - 1;
169 hid_div = cfg >> CFG_SRC_DIV_SHIFT;
172 return calc_rate(parent_rate, m, n, mode, hid_div);
176 struct freq_tbl *find_freq(const struct freq_tbl *f, unsigned long rate)
185 /* Default to our fastest rate */
189 static long _freq_tbl_determine_rate(struct clk_hw *hw,
190 const struct freq_tbl *f, unsigned long rate,
191 unsigned long *p_rate, struct clk **p)
193 unsigned long clk_flags;
195 f = find_freq(f, rate);
199 clk_flags = __clk_get_flags(hw->clk);
200 *p = clk_get_parent_by_index(hw->clk, f->src);
201 if (clk_flags & CLK_SET_RATE_PARENT) {
204 rate *= f->pre_div + 1;
214 rate = __clk_get_rate(*p);
221 static long clk_rcg2_determine_rate(struct clk_hw *hw, unsigned long rate,
222 unsigned long *p_rate, struct clk **p)
224 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
226 return _freq_tbl_determine_rate(hw, rcg->freq_tbl, rate, p_rate, p);
229 static int clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f)
234 if (rcg->mnd_width && f->n) {
235 mask = BIT(rcg->mnd_width) - 1;
236 ret = regmap_update_bits(rcg->clkr.regmap,
237 rcg->cmd_rcgr + M_REG, mask, f->m);
241 ret = regmap_update_bits(rcg->clkr.regmap,
242 rcg->cmd_rcgr + N_REG, mask, ~(f->n - f->m));
246 ret = regmap_update_bits(rcg->clkr.regmap,
247 rcg->cmd_rcgr + D_REG, mask, ~f->n);
252 mask = BIT(rcg->hid_width) - 1;
253 mask |= CFG_SRC_SEL_MASK | CFG_MODE_MASK;
254 cfg = f->pre_div << CFG_SRC_DIV_SHIFT;
255 cfg |= rcg->parent_map[f->src] << CFG_SRC_SEL_SHIFT;
256 if (rcg->mnd_width && f->n)
257 cfg |= CFG_MODE_DUAL_EDGE;
258 ret = regmap_update_bits(rcg->clkr.regmap,
259 rcg->cmd_rcgr + CFG_REG, mask, cfg);
263 return update_config(rcg);
266 static int __clk_rcg2_set_rate(struct clk_hw *hw, unsigned long rate)
268 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
269 const struct freq_tbl *f;
271 f = find_freq(rcg->freq_tbl, rate);
275 return clk_rcg2_configure(rcg, f);
278 static int clk_rcg2_set_rate(struct clk_hw *hw, unsigned long rate,
279 unsigned long parent_rate)
281 return __clk_rcg2_set_rate(hw, rate);
284 static int clk_rcg2_set_rate_and_parent(struct clk_hw *hw,
285 unsigned long rate, unsigned long parent_rate, u8 index)
287 return __clk_rcg2_set_rate(hw, rate);
290 const struct clk_ops clk_rcg2_ops = {
291 .is_enabled = clk_rcg2_is_enabled,
292 .get_parent = clk_rcg2_get_parent,
293 .set_parent = clk_rcg2_set_parent,
294 .recalc_rate = clk_rcg2_recalc_rate,
295 .determine_rate = clk_rcg2_determine_rate,
296 .set_rate = clk_rcg2_set_rate,
297 .set_rate_and_parent = clk_rcg2_set_rate_and_parent,
299 EXPORT_SYMBOL_GPL(clk_rcg2_ops);
306 static const struct frac_entry frac_table_675m[] = { /* link rate of 270M */
307 { 52, 295 }, /* 119 M */
308 { 11, 57 }, /* 130.25 M */
309 { 63, 307 }, /* 138.50 M */
310 { 11, 50 }, /* 148.50 M */
311 { 47, 206 }, /* 154 M */
312 { 31, 100 }, /* 205.25 M */
313 { 107, 269 }, /* 268.50 M */
317 static struct frac_entry frac_table_810m[] = { /* Link rate of 162M */
318 { 31, 211 }, /* 119 M */
319 { 32, 199 }, /* 130.25 M */
320 { 63, 307 }, /* 138.50 M */
321 { 11, 60 }, /* 148.50 M */
322 { 50, 263 }, /* 154 M */
323 { 31, 120 }, /* 205.25 M */
324 { 119, 359 }, /* 268.50 M */
328 static int clk_edp_pixel_set_rate(struct clk_hw *hw, unsigned long rate,
329 unsigned long parent_rate)
331 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
332 struct freq_tbl f = *rcg->freq_tbl;
333 const struct frac_entry *frac;
335 s64 src_rate = parent_rate;
337 u32 mask = BIT(rcg->hid_width) - 1;
340 if (src_rate == 810000000)
341 frac = frac_table_810m;
343 frac = frac_table_675m;
345 for (; frac->num; frac++) {
347 request *= frac->den;
348 request = div_s64(request, frac->num);
349 if ((src_rate < (request - delta)) ||
350 (src_rate > (request + delta)))
353 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG,
356 f.pre_div >>= CFG_SRC_DIV_SHIFT;
361 return clk_rcg2_configure(rcg, &f);
367 static int clk_edp_pixel_set_rate_and_parent(struct clk_hw *hw,
368 unsigned long rate, unsigned long parent_rate, u8 index)
370 /* Parent index is set statically in frequency table */
371 return clk_edp_pixel_set_rate(hw, rate, parent_rate);
374 static long clk_edp_pixel_determine_rate(struct clk_hw *hw, unsigned long rate,
375 unsigned long *p_rate, struct clk **p)
377 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
378 const struct freq_tbl *f = rcg->freq_tbl;
379 const struct frac_entry *frac;
381 s64 src_rate = *p_rate;
383 u32 mask = BIT(rcg->hid_width) - 1;
386 /* Force the correct parent */
387 *p = clk_get_parent_by_index(hw->clk, f->src);
389 if (src_rate == 810000000)
390 frac = frac_table_810m;
392 frac = frac_table_675m;
394 for (; frac->num; frac++) {
396 request *= frac->den;
397 request = div_s64(request, frac->num);
398 if ((src_rate < (request - delta)) ||
399 (src_rate > (request + delta)))
402 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG,
404 hid_div >>= CFG_SRC_DIV_SHIFT;
407 return calc_rate(src_rate, frac->num, frac->den, !!frac->den,
414 const struct clk_ops clk_edp_pixel_ops = {
415 .is_enabled = clk_rcg2_is_enabled,
416 .get_parent = clk_rcg2_get_parent,
417 .set_parent = clk_rcg2_set_parent,
418 .recalc_rate = clk_rcg2_recalc_rate,
419 .set_rate = clk_edp_pixel_set_rate,
420 .set_rate_and_parent = clk_edp_pixel_set_rate_and_parent,
421 .determine_rate = clk_edp_pixel_determine_rate,
423 EXPORT_SYMBOL_GPL(clk_edp_pixel_ops);
425 static long clk_byte_determine_rate(struct clk_hw *hw, unsigned long rate,
426 unsigned long *p_rate, struct clk **p)
428 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
429 const struct freq_tbl *f = rcg->freq_tbl;
430 unsigned long parent_rate, div;
431 u32 mask = BIT(rcg->hid_width) - 1;
436 *p = clk_get_parent_by_index(hw->clk, f->src);
437 *p_rate = parent_rate = __clk_round_rate(*p, rate);
439 div = DIV_ROUND_UP((2 * parent_rate), rate) - 1;
440 div = min_t(u32, div, mask);
442 return calc_rate(parent_rate, 0, 0, 0, div);
445 static int clk_byte_set_rate(struct clk_hw *hw, unsigned long rate,
446 unsigned long parent_rate)
448 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
449 struct freq_tbl f = *rcg->freq_tbl;
451 u32 mask = BIT(rcg->hid_width) - 1;
453 div = DIV_ROUND_UP((2 * parent_rate), rate) - 1;
454 div = min_t(u32, div, mask);
458 return clk_rcg2_configure(rcg, &f);
461 static int clk_byte_set_rate_and_parent(struct clk_hw *hw,
462 unsigned long rate, unsigned long parent_rate, u8 index)
464 /* Parent index is set statically in frequency table */
465 return clk_byte_set_rate(hw, rate, parent_rate);
468 const struct clk_ops clk_byte_ops = {
469 .is_enabled = clk_rcg2_is_enabled,
470 .get_parent = clk_rcg2_get_parent,
471 .set_parent = clk_rcg2_set_parent,
472 .recalc_rate = clk_rcg2_recalc_rate,
473 .set_rate = clk_byte_set_rate,
474 .set_rate_and_parent = clk_byte_set_rate_and_parent,
475 .determine_rate = clk_byte_determine_rate,
477 EXPORT_SYMBOL_GPL(clk_byte_ops);
479 static const struct frac_entry frac_table_pixel[] = {
487 static long clk_pixel_determine_rate(struct clk_hw *hw, unsigned long rate,
488 unsigned long *p_rate, struct clk **p)
490 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
491 unsigned long request, src_rate;
493 const struct freq_tbl *f = rcg->freq_tbl;
494 const struct frac_entry *frac = frac_table_pixel;
495 struct clk *parent = *p = clk_get_parent_by_index(hw->clk, f->src);
497 for (; frac->num; frac++) {
498 request = (rate * frac->den) / frac->num;
500 src_rate = __clk_round_rate(parent, request);
501 if ((src_rate < (request - delta)) ||
502 (src_rate > (request + delta)))
506 return (src_rate * frac->num) / frac->den;
512 static int clk_pixel_set_rate(struct clk_hw *hw, unsigned long rate,
513 unsigned long parent_rate)
515 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
516 struct freq_tbl f = *rcg->freq_tbl;
517 const struct frac_entry *frac = frac_table_pixel;
518 unsigned long request, src_rate;
520 u32 mask = BIT(rcg->hid_width) - 1;
522 struct clk *parent = clk_get_parent_by_index(hw->clk, f.src);
524 for (; frac->num; frac++) {
525 request = (rate * frac->den) / frac->num;
527 src_rate = __clk_round_rate(parent, request);
528 if ((src_rate < (request - delta)) ||
529 (src_rate > (request + delta)))
532 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG,
535 f.pre_div >>= CFG_SRC_DIV_SHIFT;
540 return clk_rcg2_configure(rcg, &f);
545 static int clk_pixel_set_rate_and_parent(struct clk_hw *hw, unsigned long rate,
546 unsigned long parent_rate, u8 index)
548 /* Parent index is set statically in frequency table */
549 return clk_pixel_set_rate(hw, rate, parent_rate);
552 const struct clk_ops clk_pixel_ops = {
553 .is_enabled = clk_rcg2_is_enabled,
554 .get_parent = clk_rcg2_get_parent,
555 .set_parent = clk_rcg2_set_parent,
556 .recalc_rate = clk_rcg2_recalc_rate,
557 .set_rate = clk_pixel_set_rate,
558 .set_rate_and_parent = clk_pixel_set_rate_and_parent,
559 .determine_rate = clk_pixel_determine_rate,
561 EXPORT_SYMBOL_GPL(clk_pixel_ops);