2 * Copyright (c) 2014, The Linux Foundation. All rights reserved.
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
14 #include <linux/kernel.h>
15 #include <linux/bitops.h>
16 #include <linux/err.h>
17 #include <linux/platform_device.h>
18 #include <linux/module.h>
20 #include <linux/of_device.h>
21 #include <linux/clk-provider.h>
22 #include <linux/regmap.h>
23 #include <linux/reset-controller.h>
25 #include <dt-bindings/clock/qcom,gcc-apq8084.h>
26 #include <dt-bindings/reset/qcom,gcc-apq8084.h>
29 #include "clk-regmap.h"
32 #include "clk-branch.h"
40 static const u8 gcc_xo_gpll0_map[] = {
45 static const char *gcc_xo_gpll0[] = {
50 static const u8 gcc_xo_gpll0_gpll4_map[] = {
56 static const char *gcc_xo_gpll0_gpll4[] = {
62 #define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
64 static struct clk_pll gpll0 = {
72 .clkr.hw.init = &(struct clk_init_data){
74 .parent_names = (const char *[]){ "xo" },
80 static struct clk_regmap gpll0_vote = {
82 .enable_mask = BIT(0),
83 .hw.init = &(struct clk_init_data){
85 .parent_names = (const char *[]){ "gpll0" },
87 .ops = &clk_pll_vote_ops,
91 static struct clk_rcg2 config_noc_clk_src = {
94 .parent_map = gcc_xo_gpll0_map,
95 .clkr.hw.init = &(struct clk_init_data){
96 .name = "config_noc_clk_src",
97 .parent_names = gcc_xo_gpll0,
103 static struct clk_rcg2 periph_noc_clk_src = {
106 .parent_map = gcc_xo_gpll0_map,
107 .clkr.hw.init = &(struct clk_init_data){
108 .name = "periph_noc_clk_src",
109 .parent_names = gcc_xo_gpll0,
111 .ops = &clk_rcg2_ops,
115 static struct clk_rcg2 system_noc_clk_src = {
118 .parent_map = gcc_xo_gpll0_map,
119 .clkr.hw.init = &(struct clk_init_data){
120 .name = "system_noc_clk_src",
121 .parent_names = gcc_xo_gpll0,
123 .ops = &clk_rcg2_ops,
127 static struct clk_pll gpll1 = {
131 .config_reg = 0x0054,
133 .status_reg = 0x005c,
135 .clkr.hw.init = &(struct clk_init_data){
137 .parent_names = (const char *[]){ "xo" },
143 static struct clk_regmap gpll1_vote = {
144 .enable_reg = 0x1480,
145 .enable_mask = BIT(1),
146 .hw.init = &(struct clk_init_data){
147 .name = "gpll1_vote",
148 .parent_names = (const char *[]){ "gpll1" },
150 .ops = &clk_pll_vote_ops,
154 static struct clk_pll gpll4 = {
158 .config_reg = 0x1dd4,
160 .status_reg = 0x1ddc,
162 .clkr.hw.init = &(struct clk_init_data){
164 .parent_names = (const char *[]){ "xo" },
170 static struct clk_regmap gpll4_vote = {
171 .enable_reg = 0x1480,
172 .enable_mask = BIT(4),
173 .hw.init = &(struct clk_init_data){
174 .name = "gpll4_vote",
175 .parent_names = (const char *[]){ "gpll4" },
177 .ops = &clk_pll_vote_ops,
181 static const struct freq_tbl ftbl_gcc_usb30_master_clk[] = {
182 F(125000000, P_GPLL0, 1, 5, 24),
186 static struct clk_rcg2 usb30_master_clk_src = {
190 .parent_map = gcc_xo_gpll0_map,
191 .freq_tbl = ftbl_gcc_usb30_master_clk,
192 .clkr.hw.init = &(struct clk_init_data){
193 .name = "usb30_master_clk_src",
194 .parent_names = gcc_xo_gpll0,
196 .ops = &clk_rcg2_ops,
200 static const struct freq_tbl ftbl_gcc_usb30_sec_master_clk[] = {
201 F(125000000, P_GPLL0, 1, 5, 24),
205 static struct clk_rcg2 usb30_sec_master_clk_src = {
209 .parent_map = gcc_xo_gpll0_map,
210 .freq_tbl = ftbl_gcc_usb30_sec_master_clk,
211 .clkr.hw.init = &(struct clk_init_data){
212 .name = "usb30_sec_master_clk_src",
213 .parent_names = gcc_xo_gpll0,
215 .ops = &clk_rcg2_ops,
219 static struct clk_branch gcc_usb30_sec_mock_utmi_clk = {
222 .enable_reg = 0x1bd0,
223 .enable_mask = BIT(0),
224 .hw.init = &(struct clk_init_data){
225 .name = "gcc_usb30_sec_mock_utmi_clk",
226 .parent_names = (const char *[]){
227 "usb30_sec_mock_utmi_clk_src",
230 .flags = CLK_SET_RATE_PARENT,
231 .ops = &clk_branch2_ops,
236 static struct clk_branch gcc_usb30_sec_sleep_clk = {
239 .enable_reg = 0x1bcc,
240 .enable_mask = BIT(0),
241 .hw.init = &(struct clk_init_data){
242 .name = "gcc_usb30_sec_sleep_clk",
243 .parent_names = (const char *[]){
247 .flags = CLK_SET_RATE_PARENT,
248 .ops = &clk_branch2_ops,
253 static const struct freq_tbl ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk[] = {
254 F(19200000, P_XO, 1, 0, 0),
255 F(50000000, P_GPLL0, 12, 0, 0),
259 static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
262 .parent_map = gcc_xo_gpll0_map,
263 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
264 .clkr.hw.init = &(struct clk_init_data){
265 .name = "blsp1_qup1_i2c_apps_clk_src",
266 .parent_names = gcc_xo_gpll0,
268 .ops = &clk_rcg2_ops,
272 static const struct freq_tbl ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk[] = {
273 F(960000, P_XO, 10, 1, 2),
274 F(4800000, P_XO, 4, 0, 0),
275 F(9600000, P_XO, 2, 0, 0),
276 F(15000000, P_GPLL0, 10, 1, 4),
277 F(19200000, P_XO, 1, 0, 0),
278 F(25000000, P_GPLL0, 12, 1, 2),
279 F(50000000, P_GPLL0, 12, 0, 0),
283 static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
287 .parent_map = gcc_xo_gpll0_map,
288 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
289 .clkr.hw.init = &(struct clk_init_data){
290 .name = "blsp1_qup1_spi_apps_clk_src",
291 .parent_names = gcc_xo_gpll0,
293 .ops = &clk_rcg2_ops,
297 static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
300 .parent_map = gcc_xo_gpll0_map,
301 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
302 .clkr.hw.init = &(struct clk_init_data){
303 .name = "blsp1_qup2_i2c_apps_clk_src",
304 .parent_names = gcc_xo_gpll0,
306 .ops = &clk_rcg2_ops,
310 static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
314 .parent_map = gcc_xo_gpll0_map,
315 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
316 .clkr.hw.init = &(struct clk_init_data){
317 .name = "blsp1_qup2_spi_apps_clk_src",
318 .parent_names = gcc_xo_gpll0,
320 .ops = &clk_rcg2_ops,
324 static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
327 .parent_map = gcc_xo_gpll0_map,
328 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
329 .clkr.hw.init = &(struct clk_init_data){
330 .name = "blsp1_qup3_i2c_apps_clk_src",
331 .parent_names = gcc_xo_gpll0,
333 .ops = &clk_rcg2_ops,
337 static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
341 .parent_map = gcc_xo_gpll0_map,
342 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
343 .clkr.hw.init = &(struct clk_init_data){
344 .name = "blsp1_qup3_spi_apps_clk_src",
345 .parent_names = gcc_xo_gpll0,
347 .ops = &clk_rcg2_ops,
351 static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
354 .parent_map = gcc_xo_gpll0_map,
355 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
356 .clkr.hw.init = &(struct clk_init_data){
357 .name = "blsp1_qup4_i2c_apps_clk_src",
358 .parent_names = gcc_xo_gpll0,
360 .ops = &clk_rcg2_ops,
364 static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
368 .parent_map = gcc_xo_gpll0_map,
369 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
370 .clkr.hw.init = &(struct clk_init_data){
371 .name = "blsp1_qup4_spi_apps_clk_src",
372 .parent_names = gcc_xo_gpll0,
374 .ops = &clk_rcg2_ops,
378 static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
381 .parent_map = gcc_xo_gpll0_map,
382 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
383 .clkr.hw.init = &(struct clk_init_data){
384 .name = "blsp1_qup5_i2c_apps_clk_src",
385 .parent_names = gcc_xo_gpll0,
387 .ops = &clk_rcg2_ops,
391 static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
395 .parent_map = gcc_xo_gpll0_map,
396 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
397 .clkr.hw.init = &(struct clk_init_data){
398 .name = "blsp1_qup5_spi_apps_clk_src",
399 .parent_names = gcc_xo_gpll0,
401 .ops = &clk_rcg2_ops,
405 static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
408 .parent_map = gcc_xo_gpll0_map,
409 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
410 .clkr.hw.init = &(struct clk_init_data){
411 .name = "blsp1_qup6_i2c_apps_clk_src",
412 .parent_names = gcc_xo_gpll0,
414 .ops = &clk_rcg2_ops,
418 static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
422 .parent_map = gcc_xo_gpll0_map,
423 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
424 .clkr.hw.init = &(struct clk_init_data){
425 .name = "blsp1_qup6_spi_apps_clk_src",
426 .parent_names = gcc_xo_gpll0,
428 .ops = &clk_rcg2_ops,
432 static const struct freq_tbl ftbl_gcc_blsp1_2_uart1_6_apps_clk[] = {
433 F(3686400, P_GPLL0, 1, 96, 15625),
434 F(7372800, P_GPLL0, 1, 192, 15625),
435 F(14745600, P_GPLL0, 1, 384, 15625),
436 F(16000000, P_GPLL0, 5, 2, 15),
437 F(19200000, P_XO, 1, 0, 0),
438 F(24000000, P_GPLL0, 5, 1, 5),
439 F(32000000, P_GPLL0, 1, 4, 75),
440 F(40000000, P_GPLL0, 15, 0, 0),
441 F(46400000, P_GPLL0, 1, 29, 375),
442 F(48000000, P_GPLL0, 12.5, 0, 0),
443 F(51200000, P_GPLL0, 1, 32, 375),
444 F(56000000, P_GPLL0, 1, 7, 75),
445 F(58982400, P_GPLL0, 1, 1536, 15625),
446 F(60000000, P_GPLL0, 10, 0, 0),
447 F(63160000, P_GPLL0, 9.5, 0, 0),
451 static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
455 .parent_map = gcc_xo_gpll0_map,
456 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
457 .clkr.hw.init = &(struct clk_init_data){
458 .name = "blsp1_uart1_apps_clk_src",
459 .parent_names = gcc_xo_gpll0,
461 .ops = &clk_rcg2_ops,
465 static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
469 .parent_map = gcc_xo_gpll0_map,
470 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
471 .clkr.hw.init = &(struct clk_init_data){
472 .name = "blsp1_uart2_apps_clk_src",
473 .parent_names = gcc_xo_gpll0,
475 .ops = &clk_rcg2_ops,
479 static struct clk_rcg2 blsp1_uart3_apps_clk_src = {
483 .parent_map = gcc_xo_gpll0_map,
484 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
485 .clkr.hw.init = &(struct clk_init_data){
486 .name = "blsp1_uart3_apps_clk_src",
487 .parent_names = gcc_xo_gpll0,
489 .ops = &clk_rcg2_ops,
493 static struct clk_rcg2 blsp1_uart4_apps_clk_src = {
497 .parent_map = gcc_xo_gpll0_map,
498 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
499 .clkr.hw.init = &(struct clk_init_data){
500 .name = "blsp1_uart4_apps_clk_src",
501 .parent_names = gcc_xo_gpll0,
503 .ops = &clk_rcg2_ops,
507 static struct clk_rcg2 blsp1_uart5_apps_clk_src = {
511 .parent_map = gcc_xo_gpll0_map,
512 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
513 .clkr.hw.init = &(struct clk_init_data){
514 .name = "blsp1_uart5_apps_clk_src",
515 .parent_names = gcc_xo_gpll0,
517 .ops = &clk_rcg2_ops,
521 static struct clk_rcg2 blsp1_uart6_apps_clk_src = {
525 .parent_map = gcc_xo_gpll0_map,
526 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
527 .clkr.hw.init = &(struct clk_init_data){
528 .name = "blsp1_uart6_apps_clk_src",
529 .parent_names = gcc_xo_gpll0,
531 .ops = &clk_rcg2_ops,
535 static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = {
538 .parent_map = gcc_xo_gpll0_map,
539 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
540 .clkr.hw.init = &(struct clk_init_data){
541 .name = "blsp2_qup1_i2c_apps_clk_src",
542 .parent_names = gcc_xo_gpll0,
544 .ops = &clk_rcg2_ops,
548 static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = {
552 .parent_map = gcc_xo_gpll0_map,
553 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
554 .clkr.hw.init = &(struct clk_init_data){
555 .name = "blsp2_qup1_spi_apps_clk_src",
556 .parent_names = gcc_xo_gpll0,
558 .ops = &clk_rcg2_ops,
562 static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = {
565 .parent_map = gcc_xo_gpll0_map,
566 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
567 .clkr.hw.init = &(struct clk_init_data){
568 .name = "blsp2_qup2_i2c_apps_clk_src",
569 .parent_names = gcc_xo_gpll0,
571 .ops = &clk_rcg2_ops,
575 static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = {
579 .parent_map = gcc_xo_gpll0_map,
580 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
581 .clkr.hw.init = &(struct clk_init_data){
582 .name = "blsp2_qup2_spi_apps_clk_src",
583 .parent_names = gcc_xo_gpll0,
585 .ops = &clk_rcg2_ops,
589 static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = {
592 .parent_map = gcc_xo_gpll0_map,
593 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
594 .clkr.hw.init = &(struct clk_init_data){
595 .name = "blsp2_qup3_i2c_apps_clk_src",
596 .parent_names = gcc_xo_gpll0,
598 .ops = &clk_rcg2_ops,
602 static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = {
606 .parent_map = gcc_xo_gpll0_map,
607 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
608 .clkr.hw.init = &(struct clk_init_data){
609 .name = "blsp2_qup3_spi_apps_clk_src",
610 .parent_names = gcc_xo_gpll0,
612 .ops = &clk_rcg2_ops,
616 static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = {
619 .parent_map = gcc_xo_gpll0_map,
620 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
621 .clkr.hw.init = &(struct clk_init_data){
622 .name = "blsp2_qup4_i2c_apps_clk_src",
623 .parent_names = gcc_xo_gpll0,
625 .ops = &clk_rcg2_ops,
629 static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = {
633 .parent_map = gcc_xo_gpll0_map,
634 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
635 .clkr.hw.init = &(struct clk_init_data){
636 .name = "blsp2_qup4_spi_apps_clk_src",
637 .parent_names = gcc_xo_gpll0,
639 .ops = &clk_rcg2_ops,
643 static struct clk_rcg2 blsp2_qup5_i2c_apps_clk_src = {
646 .parent_map = gcc_xo_gpll0_map,
647 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
648 .clkr.hw.init = &(struct clk_init_data){
649 .name = "blsp2_qup5_i2c_apps_clk_src",
650 .parent_names = gcc_xo_gpll0,
652 .ops = &clk_rcg2_ops,
656 static struct clk_rcg2 blsp2_qup5_spi_apps_clk_src = {
660 .parent_map = gcc_xo_gpll0_map,
661 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
662 .clkr.hw.init = &(struct clk_init_data){
663 .name = "blsp2_qup5_spi_apps_clk_src",
664 .parent_names = gcc_xo_gpll0,
666 .ops = &clk_rcg2_ops,
670 static struct clk_rcg2 blsp2_qup6_i2c_apps_clk_src = {
673 .parent_map = gcc_xo_gpll0_map,
674 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
675 .clkr.hw.init = &(struct clk_init_data){
676 .name = "blsp2_qup6_i2c_apps_clk_src",
677 .parent_names = gcc_xo_gpll0,
679 .ops = &clk_rcg2_ops,
683 static struct clk_rcg2 blsp2_qup6_spi_apps_clk_src = {
687 .parent_map = gcc_xo_gpll0_map,
688 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
689 .clkr.hw.init = &(struct clk_init_data){
690 .name = "blsp2_qup6_spi_apps_clk_src",
691 .parent_names = gcc_xo_gpll0,
693 .ops = &clk_rcg2_ops,
697 static struct clk_rcg2 blsp2_uart1_apps_clk_src = {
701 .parent_map = gcc_xo_gpll0_map,
702 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
703 .clkr.hw.init = &(struct clk_init_data){
704 .name = "blsp2_uart1_apps_clk_src",
705 .parent_names = gcc_xo_gpll0,
707 .ops = &clk_rcg2_ops,
711 static struct clk_rcg2 blsp2_uart2_apps_clk_src = {
715 .parent_map = gcc_xo_gpll0_map,
716 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
717 .clkr.hw.init = &(struct clk_init_data){
718 .name = "blsp2_uart2_apps_clk_src",
719 .parent_names = gcc_xo_gpll0,
721 .ops = &clk_rcg2_ops,
725 static struct clk_rcg2 blsp2_uart3_apps_clk_src = {
729 .parent_map = gcc_xo_gpll0_map,
730 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
731 .clkr.hw.init = &(struct clk_init_data){
732 .name = "blsp2_uart3_apps_clk_src",
733 .parent_names = gcc_xo_gpll0,
735 .ops = &clk_rcg2_ops,
739 static struct clk_rcg2 blsp2_uart4_apps_clk_src = {
743 .parent_map = gcc_xo_gpll0_map,
744 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
745 .clkr.hw.init = &(struct clk_init_data){
746 .name = "blsp2_uart4_apps_clk_src",
747 .parent_names = gcc_xo_gpll0,
749 .ops = &clk_rcg2_ops,
753 static struct clk_rcg2 blsp2_uart5_apps_clk_src = {
757 .parent_map = gcc_xo_gpll0_map,
758 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
759 .clkr.hw.init = &(struct clk_init_data){
760 .name = "blsp2_uart5_apps_clk_src",
761 .parent_names = gcc_xo_gpll0,
763 .ops = &clk_rcg2_ops,
767 static struct clk_rcg2 blsp2_uart6_apps_clk_src = {
771 .parent_map = gcc_xo_gpll0_map,
772 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
773 .clkr.hw.init = &(struct clk_init_data){
774 .name = "blsp2_uart6_apps_clk_src",
775 .parent_names = gcc_xo_gpll0,
777 .ops = &clk_rcg2_ops,
781 static const struct freq_tbl ftbl_gcc_ce1_clk[] = {
782 F(50000000, P_GPLL0, 12, 0, 0),
783 F(85710000, P_GPLL0, 7, 0, 0),
784 F(100000000, P_GPLL0, 6, 0, 0),
785 F(171430000, P_GPLL0, 3.5, 0, 0),
789 static struct clk_rcg2 ce1_clk_src = {
792 .parent_map = gcc_xo_gpll0_map,
793 .freq_tbl = ftbl_gcc_ce1_clk,
794 .clkr.hw.init = &(struct clk_init_data){
795 .name = "ce1_clk_src",
796 .parent_names = gcc_xo_gpll0,
798 .ops = &clk_rcg2_ops,
802 static const struct freq_tbl ftbl_gcc_ce2_clk[] = {
803 F(50000000, P_GPLL0, 12, 0, 0),
804 F(85710000, P_GPLL0, 7, 0, 0),
805 F(100000000, P_GPLL0, 6, 0, 0),
806 F(171430000, P_GPLL0, 3.5, 0, 0),
810 static struct clk_rcg2 ce2_clk_src = {
813 .parent_map = gcc_xo_gpll0_map,
814 .freq_tbl = ftbl_gcc_ce2_clk,
815 .clkr.hw.init = &(struct clk_init_data){
816 .name = "ce2_clk_src",
817 .parent_names = gcc_xo_gpll0,
819 .ops = &clk_rcg2_ops,
823 static const struct freq_tbl ftbl_gcc_ce3_clk[] = {
824 F(50000000, P_GPLL0, 12, 0, 0),
825 F(85710000, P_GPLL0, 7, 0, 0),
826 F(100000000, P_GPLL0, 6, 0, 0),
827 F(171430000, P_GPLL0, 3.5, 0, 0),
831 static struct clk_rcg2 ce3_clk_src = {
834 .parent_map = gcc_xo_gpll0_map,
835 .freq_tbl = ftbl_gcc_ce3_clk,
836 .clkr.hw.init = &(struct clk_init_data){
837 .name = "ce3_clk_src",
838 .parent_names = gcc_xo_gpll0,
840 .ops = &clk_rcg2_ops,
844 static const struct freq_tbl ftbl_gcc_gp_clk[] = {
845 F(19200000, P_XO, 1, 0, 0),
846 F(100000000, P_GPLL0, 6, 0, 0),
847 F(200000000, P_GPLL0, 3, 0, 0),
851 static struct clk_rcg2 gp1_clk_src = {
855 .parent_map = gcc_xo_gpll0_map,
856 .freq_tbl = ftbl_gcc_gp_clk,
857 .clkr.hw.init = &(struct clk_init_data){
858 .name = "gp1_clk_src",
859 .parent_names = gcc_xo_gpll0,
861 .ops = &clk_rcg2_ops,
865 static struct clk_rcg2 gp2_clk_src = {
869 .parent_map = gcc_xo_gpll0_map,
870 .freq_tbl = ftbl_gcc_gp_clk,
871 .clkr.hw.init = &(struct clk_init_data){
872 .name = "gp2_clk_src",
873 .parent_names = gcc_xo_gpll0,
875 .ops = &clk_rcg2_ops,
879 static struct clk_rcg2 gp3_clk_src = {
883 .parent_map = gcc_xo_gpll0_map,
884 .freq_tbl = ftbl_gcc_gp_clk,
885 .clkr.hw.init = &(struct clk_init_data){
886 .name = "gp3_clk_src",
887 .parent_names = gcc_xo_gpll0,
889 .ops = &clk_rcg2_ops,
893 static const struct freq_tbl ftbl_gcc_pdm2_clk[] = {
894 F(60000000, P_GPLL0, 10, 0, 0),
898 static struct clk_rcg2 pdm2_clk_src = {
901 .parent_map = gcc_xo_gpll0_map,
902 .freq_tbl = ftbl_gcc_pdm2_clk,
903 .clkr.hw.init = &(struct clk_init_data){
904 .name = "pdm2_clk_src",
905 .parent_names = gcc_xo_gpll0,
907 .ops = &clk_rcg2_ops,
911 static const struct freq_tbl ftbl_gcc_sdcc1_4_apps_clk[] = {
912 F(144000, P_XO, 16, 3, 25),
913 F(400000, P_XO, 12, 1, 4),
914 F(20000000, P_GPLL0, 15, 1, 2),
915 F(25000000, P_GPLL0, 12, 1, 2),
916 F(50000000, P_GPLL0, 12, 0, 0),
917 F(100000000, P_GPLL0, 6, 0, 0),
918 F(192000000, P_GPLL4, 4, 0, 0),
919 F(200000000, P_GPLL0, 3, 0, 0),
920 F(384000000, P_GPLL4, 2, 0, 0),
924 static struct clk_rcg2 sdcc1_apps_clk_src = {
928 .parent_map = gcc_xo_gpll0_gpll4_map,
929 .freq_tbl = ftbl_gcc_sdcc1_4_apps_clk,
930 .clkr.hw.init = &(struct clk_init_data){
931 .name = "sdcc1_apps_clk_src",
932 .parent_names = gcc_xo_gpll0_gpll4,
934 .ops = &clk_rcg2_ops,
938 static struct clk_rcg2 sdcc2_apps_clk_src = {
942 .parent_map = gcc_xo_gpll0_map,
943 .freq_tbl = ftbl_gcc_sdcc1_4_apps_clk,
944 .clkr.hw.init = &(struct clk_init_data){
945 .name = "sdcc2_apps_clk_src",
946 .parent_names = gcc_xo_gpll0,
948 .ops = &clk_rcg2_ops,
952 static struct clk_rcg2 sdcc3_apps_clk_src = {
956 .parent_map = gcc_xo_gpll0_map,
957 .freq_tbl = ftbl_gcc_sdcc1_4_apps_clk,
958 .clkr.hw.init = &(struct clk_init_data){
959 .name = "sdcc3_apps_clk_src",
960 .parent_names = gcc_xo_gpll0,
962 .ops = &clk_rcg2_ops,
966 static struct clk_rcg2 sdcc4_apps_clk_src = {
970 .parent_map = gcc_xo_gpll0_map,
971 .freq_tbl = ftbl_gcc_sdcc1_4_apps_clk,
972 .clkr.hw.init = &(struct clk_init_data){
973 .name = "sdcc4_apps_clk_src",
974 .parent_names = gcc_xo_gpll0,
976 .ops = &clk_rcg2_ops,
980 static const struct freq_tbl ftbl_gcc_tsif_ref_clk[] = {
981 F(105000, P_XO, 2, 1, 91),
985 static struct clk_rcg2 tsif_ref_clk_src = {
989 .parent_map = gcc_xo_gpll0_map,
990 .freq_tbl = ftbl_gcc_tsif_ref_clk,
991 .clkr.hw.init = &(struct clk_init_data){
992 .name = "tsif_ref_clk_src",
993 .parent_names = gcc_xo_gpll0,
995 .ops = &clk_rcg2_ops,
999 static const struct freq_tbl ftbl_gcc_usb30_mock_utmi_clk[] = {
1000 F(60000000, P_GPLL0, 10, 0, 0),
1004 static struct clk_rcg2 usb30_mock_utmi_clk_src = {
1007 .parent_map = gcc_xo_gpll0_map,
1008 .freq_tbl = ftbl_gcc_usb30_mock_utmi_clk,
1009 .clkr.hw.init = &(struct clk_init_data){
1010 .name = "usb30_mock_utmi_clk_src",
1011 .parent_names = gcc_xo_gpll0,
1013 .ops = &clk_rcg2_ops,
1017 static const struct freq_tbl ftbl_gcc_usb30_sec_mock_utmi_clk[] = {
1018 F(125000000, P_GPLL0, 1, 5, 24),
1022 static struct clk_rcg2 usb30_sec_mock_utmi_clk_src = {
1025 .parent_map = gcc_xo_gpll0_map,
1026 .freq_tbl = ftbl_gcc_usb30_sec_mock_utmi_clk,
1027 .clkr.hw.init = &(struct clk_init_data){
1028 .name = "usb30_sec_mock_utmi_clk_src",
1029 .parent_names = gcc_xo_gpll0,
1031 .ops = &clk_rcg2_ops,
1035 static const struct freq_tbl ftbl_gcc_usb_hs_system_clk[] = {
1036 F(75000000, P_GPLL0, 8, 0, 0),
1040 static struct clk_rcg2 usb_hs_system_clk_src = {
1043 .parent_map = gcc_xo_gpll0_map,
1044 .freq_tbl = ftbl_gcc_usb_hs_system_clk,
1045 .clkr.hw.init = &(struct clk_init_data){
1046 .name = "usb_hs_system_clk_src",
1047 .parent_names = gcc_xo_gpll0,
1049 .ops = &clk_rcg2_ops,
1053 static const struct freq_tbl ftbl_gcc_usb_hsic_clk[] = {
1054 F(480000000, P_GPLL1, 1, 0, 0),
1058 static u8 usb_hsic_clk_src_map[] = {
1063 static struct clk_rcg2 usb_hsic_clk_src = {
1066 .parent_map = usb_hsic_clk_src_map,
1067 .freq_tbl = ftbl_gcc_usb_hsic_clk,
1068 .clkr.hw.init = &(struct clk_init_data){
1069 .name = "usb_hsic_clk_src",
1070 .parent_names = (const char *[]){
1075 .ops = &clk_rcg2_ops,
1079 static const struct freq_tbl ftbl_gcc_usb_hsic_ahb_clk_src[] = {
1080 F(60000000, P_GPLL1, 8, 0, 0),
1084 static struct clk_rcg2 usb_hsic_ahb_clk_src = {
1088 .parent_map = usb_hsic_clk_src_map,
1089 .freq_tbl = ftbl_gcc_usb_hsic_ahb_clk_src,
1090 .clkr.hw.init = &(struct clk_init_data){
1091 .name = "usb_hsic_ahb_clk_src",
1092 .parent_names = (const char *[]){
1097 .ops = &clk_rcg2_ops,
1101 static const struct freq_tbl ftbl_gcc_usb_hsic_io_cal_clk[] = {
1102 F(9600000, P_XO, 2, 0, 0),
1106 static struct clk_rcg2 usb_hsic_io_cal_clk_src = {
1109 .parent_map = gcc_xo_gpll0_map,
1110 .freq_tbl = ftbl_gcc_usb_hsic_io_cal_clk,
1111 .clkr.hw.init = &(struct clk_init_data){
1112 .name = "usb_hsic_io_cal_clk_src",
1113 .parent_names = gcc_xo_gpll0,
1115 .ops = &clk_rcg2_ops,
1119 static struct clk_branch gcc_usb_hsic_mock_utmi_clk = {
1122 .enable_reg = 0x1f14,
1123 .enable_mask = BIT(0),
1124 .hw.init = &(struct clk_init_data){
1125 .name = "gcc_usb_hsic_mock_utmi_clk",
1126 .parent_names = (const char *[]){
1127 "usb_hsic_mock_utmi_clk_src",
1130 .flags = CLK_SET_RATE_PARENT,
1131 .ops = &clk_branch2_ops,
1136 static const struct freq_tbl ftbl_gcc_usb_hsic_mock_utmi_clk[] = {
1137 F(60000000, P_GPLL0, 10, 0, 0),
1141 static struct clk_rcg2 usb_hsic_mock_utmi_clk_src = {
1144 .parent_map = gcc_xo_gpll0_map,
1145 .freq_tbl = ftbl_gcc_usb_hsic_mock_utmi_clk,
1146 .clkr.hw.init = &(struct clk_init_data){
1147 .name = "usb_hsic_mock_utmi_clk_src",
1148 .parent_names = gcc_xo_gpll0,
1150 .ops = &clk_rcg2_ops,
1154 static const struct freq_tbl ftbl_gcc_usb_hsic_system_clk[] = {
1155 F(75000000, P_GPLL0, 8, 0, 0),
1159 static struct clk_rcg2 usb_hsic_system_clk_src = {
1162 .parent_map = gcc_xo_gpll0_map,
1163 .freq_tbl = ftbl_gcc_usb_hsic_system_clk,
1164 .clkr.hw.init = &(struct clk_init_data){
1165 .name = "usb_hsic_system_clk_src",
1166 .parent_names = gcc_xo_gpll0,
1168 .ops = &clk_rcg2_ops,
1172 static struct clk_branch gcc_bam_dma_ahb_clk = {
1174 .halt_check = BRANCH_HALT_VOTED,
1176 .enable_reg = 0x1484,
1177 .enable_mask = BIT(12),
1178 .hw.init = &(struct clk_init_data){
1179 .name = "gcc_bam_dma_ahb_clk",
1180 .parent_names = (const char *[]){
1181 "periph_noc_clk_src",
1184 .ops = &clk_branch2_ops,
1189 static struct clk_branch gcc_blsp1_ahb_clk = {
1191 .halt_check = BRANCH_HALT_VOTED,
1193 .enable_reg = 0x1484,
1194 .enable_mask = BIT(17),
1195 .hw.init = &(struct clk_init_data){
1196 .name = "gcc_blsp1_ahb_clk",
1197 .parent_names = (const char *[]){
1198 "periph_noc_clk_src",
1201 .ops = &clk_branch2_ops,
1206 static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
1209 .enable_reg = 0x0648,
1210 .enable_mask = BIT(0),
1211 .hw.init = &(struct clk_init_data){
1212 .name = "gcc_blsp1_qup1_i2c_apps_clk",
1213 .parent_names = (const char *[]){
1214 "blsp1_qup1_i2c_apps_clk_src",
1217 .flags = CLK_SET_RATE_PARENT,
1218 .ops = &clk_branch2_ops,
1223 static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
1226 .enable_reg = 0x0644,
1227 .enable_mask = BIT(0),
1228 .hw.init = &(struct clk_init_data){
1229 .name = "gcc_blsp1_qup1_spi_apps_clk",
1230 .parent_names = (const char *[]){
1231 "blsp1_qup1_spi_apps_clk_src",
1234 .flags = CLK_SET_RATE_PARENT,
1235 .ops = &clk_branch2_ops,
1240 static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
1243 .enable_reg = 0x06c8,
1244 .enable_mask = BIT(0),
1245 .hw.init = &(struct clk_init_data){
1246 .name = "gcc_blsp1_qup2_i2c_apps_clk",
1247 .parent_names = (const char *[]){
1248 "blsp1_qup2_i2c_apps_clk_src",
1251 .flags = CLK_SET_RATE_PARENT,
1252 .ops = &clk_branch2_ops,
1257 static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
1260 .enable_reg = 0x06c4,
1261 .enable_mask = BIT(0),
1262 .hw.init = &(struct clk_init_data){
1263 .name = "gcc_blsp1_qup2_spi_apps_clk",
1264 .parent_names = (const char *[]){
1265 "blsp1_qup2_spi_apps_clk_src",
1268 .flags = CLK_SET_RATE_PARENT,
1269 .ops = &clk_branch2_ops,
1274 static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
1277 .enable_reg = 0x0748,
1278 .enable_mask = BIT(0),
1279 .hw.init = &(struct clk_init_data){
1280 .name = "gcc_blsp1_qup3_i2c_apps_clk",
1281 .parent_names = (const char *[]){
1282 "blsp1_qup3_i2c_apps_clk_src",
1285 .flags = CLK_SET_RATE_PARENT,
1286 .ops = &clk_branch2_ops,
1291 static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
1294 .enable_reg = 0x0744,
1295 .enable_mask = BIT(0),
1296 .hw.init = &(struct clk_init_data){
1297 .name = "gcc_blsp1_qup3_spi_apps_clk",
1298 .parent_names = (const char *[]){
1299 "blsp1_qup3_spi_apps_clk_src",
1302 .flags = CLK_SET_RATE_PARENT,
1303 .ops = &clk_branch2_ops,
1308 static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
1311 .enable_reg = 0x07c8,
1312 .enable_mask = BIT(0),
1313 .hw.init = &(struct clk_init_data){
1314 .name = "gcc_blsp1_qup4_i2c_apps_clk",
1315 .parent_names = (const char *[]){
1316 "blsp1_qup4_i2c_apps_clk_src",
1319 .flags = CLK_SET_RATE_PARENT,
1320 .ops = &clk_branch2_ops,
1325 static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
1328 .enable_reg = 0x07c4,
1329 .enable_mask = BIT(0),
1330 .hw.init = &(struct clk_init_data){
1331 .name = "gcc_blsp1_qup4_spi_apps_clk",
1332 .parent_names = (const char *[]){
1333 "blsp1_qup4_spi_apps_clk_src",
1336 .flags = CLK_SET_RATE_PARENT,
1337 .ops = &clk_branch2_ops,
1342 static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = {
1345 .enable_reg = 0x0848,
1346 .enable_mask = BIT(0),
1347 .hw.init = &(struct clk_init_data){
1348 .name = "gcc_blsp1_qup5_i2c_apps_clk",
1349 .parent_names = (const char *[]){
1350 "blsp1_qup5_i2c_apps_clk_src",
1353 .flags = CLK_SET_RATE_PARENT,
1354 .ops = &clk_branch2_ops,
1359 static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = {
1362 .enable_reg = 0x0844,
1363 .enable_mask = BIT(0),
1364 .hw.init = &(struct clk_init_data){
1365 .name = "gcc_blsp1_qup5_spi_apps_clk",
1366 .parent_names = (const char *[]){
1367 "blsp1_qup5_spi_apps_clk_src",
1370 .flags = CLK_SET_RATE_PARENT,
1371 .ops = &clk_branch2_ops,
1376 static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
1379 .enable_reg = 0x08c8,
1380 .enable_mask = BIT(0),
1381 .hw.init = &(struct clk_init_data){
1382 .name = "gcc_blsp1_qup6_i2c_apps_clk",
1383 .parent_names = (const char *[]){
1384 "blsp1_qup6_i2c_apps_clk_src",
1387 .flags = CLK_SET_RATE_PARENT,
1388 .ops = &clk_branch2_ops,
1393 static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = {
1396 .enable_reg = 0x08c4,
1397 .enable_mask = BIT(0),
1398 .hw.init = &(struct clk_init_data){
1399 .name = "gcc_blsp1_qup6_spi_apps_clk",
1400 .parent_names = (const char *[]){
1401 "blsp1_qup6_spi_apps_clk_src",
1404 .flags = CLK_SET_RATE_PARENT,
1405 .ops = &clk_branch2_ops,
1410 static struct clk_branch gcc_blsp1_uart1_apps_clk = {
1413 .enable_reg = 0x0684,
1414 .enable_mask = BIT(0),
1415 .hw.init = &(struct clk_init_data){
1416 .name = "gcc_blsp1_uart1_apps_clk",
1417 .parent_names = (const char *[]){
1418 "blsp1_uart1_apps_clk_src",
1421 .flags = CLK_SET_RATE_PARENT,
1422 .ops = &clk_branch2_ops,
1427 static struct clk_branch gcc_blsp1_uart2_apps_clk = {
1430 .enable_reg = 0x0704,
1431 .enable_mask = BIT(0),
1432 .hw.init = &(struct clk_init_data){
1433 .name = "gcc_blsp1_uart2_apps_clk",
1434 .parent_names = (const char *[]){
1435 "blsp1_uart2_apps_clk_src",
1438 .flags = CLK_SET_RATE_PARENT,
1439 .ops = &clk_branch2_ops,
1444 static struct clk_branch gcc_blsp1_uart3_apps_clk = {
1447 .enable_reg = 0x0784,
1448 .enable_mask = BIT(0),
1449 .hw.init = &(struct clk_init_data){
1450 .name = "gcc_blsp1_uart3_apps_clk",
1451 .parent_names = (const char *[]){
1452 "blsp1_uart3_apps_clk_src",
1455 .flags = CLK_SET_RATE_PARENT,
1456 .ops = &clk_branch2_ops,
1461 static struct clk_branch gcc_blsp1_uart4_apps_clk = {
1464 .enable_reg = 0x0804,
1465 .enable_mask = BIT(0),
1466 .hw.init = &(struct clk_init_data){
1467 .name = "gcc_blsp1_uart4_apps_clk",
1468 .parent_names = (const char *[]){
1469 "blsp1_uart4_apps_clk_src",
1472 .flags = CLK_SET_RATE_PARENT,
1473 .ops = &clk_branch2_ops,
1478 static struct clk_branch gcc_blsp1_uart5_apps_clk = {
1481 .enable_reg = 0x0884,
1482 .enable_mask = BIT(0),
1483 .hw.init = &(struct clk_init_data){
1484 .name = "gcc_blsp1_uart5_apps_clk",
1485 .parent_names = (const char *[]){
1486 "blsp1_uart5_apps_clk_src",
1489 .flags = CLK_SET_RATE_PARENT,
1490 .ops = &clk_branch2_ops,
1495 static struct clk_branch gcc_blsp1_uart6_apps_clk = {
1498 .enable_reg = 0x0904,
1499 .enable_mask = BIT(0),
1500 .hw.init = &(struct clk_init_data){
1501 .name = "gcc_blsp1_uart6_apps_clk",
1502 .parent_names = (const char *[]){
1503 "blsp1_uart6_apps_clk_src",
1506 .flags = CLK_SET_RATE_PARENT,
1507 .ops = &clk_branch2_ops,
1512 static struct clk_branch gcc_blsp2_ahb_clk = {
1514 .halt_check = BRANCH_HALT_VOTED,
1516 .enable_reg = 0x1484,
1517 .enable_mask = BIT(15),
1518 .hw.init = &(struct clk_init_data){
1519 .name = "gcc_blsp2_ahb_clk",
1520 .parent_names = (const char *[]){
1521 "periph_noc_clk_src",
1524 .ops = &clk_branch2_ops,
1529 static struct clk_branch gcc_blsp2_qup1_i2c_apps_clk = {
1532 .enable_reg = 0x0988,
1533 .enable_mask = BIT(0),
1534 .hw.init = &(struct clk_init_data){
1535 .name = "gcc_blsp2_qup1_i2c_apps_clk",
1536 .parent_names = (const char *[]){
1537 "blsp2_qup1_i2c_apps_clk_src",
1540 .flags = CLK_SET_RATE_PARENT,
1541 .ops = &clk_branch2_ops,
1546 static struct clk_branch gcc_blsp2_qup1_spi_apps_clk = {
1549 .enable_reg = 0x0984,
1550 .enable_mask = BIT(0),
1551 .hw.init = &(struct clk_init_data){
1552 .name = "gcc_blsp2_qup1_spi_apps_clk",
1553 .parent_names = (const char *[]){
1554 "blsp2_qup1_spi_apps_clk_src",
1557 .flags = CLK_SET_RATE_PARENT,
1558 .ops = &clk_branch2_ops,
1563 static struct clk_branch gcc_blsp2_qup2_i2c_apps_clk = {
1566 .enable_reg = 0x0a08,
1567 .enable_mask = BIT(0),
1568 .hw.init = &(struct clk_init_data){
1569 .name = "gcc_blsp2_qup2_i2c_apps_clk",
1570 .parent_names = (const char *[]){
1571 "blsp2_qup2_i2c_apps_clk_src",
1574 .flags = CLK_SET_RATE_PARENT,
1575 .ops = &clk_branch2_ops,
1580 static struct clk_branch gcc_blsp2_qup2_spi_apps_clk = {
1583 .enable_reg = 0x0a04,
1584 .enable_mask = BIT(0),
1585 .hw.init = &(struct clk_init_data){
1586 .name = "gcc_blsp2_qup2_spi_apps_clk",
1587 .parent_names = (const char *[]){
1588 "blsp2_qup2_spi_apps_clk_src",
1591 .flags = CLK_SET_RATE_PARENT,
1592 .ops = &clk_branch2_ops,
1597 static struct clk_branch gcc_blsp2_qup3_i2c_apps_clk = {
1600 .enable_reg = 0x0a88,
1601 .enable_mask = BIT(0),
1602 .hw.init = &(struct clk_init_data){
1603 .name = "gcc_blsp2_qup3_i2c_apps_clk",
1604 .parent_names = (const char *[]){
1605 "blsp2_qup3_i2c_apps_clk_src",
1608 .flags = CLK_SET_RATE_PARENT,
1609 .ops = &clk_branch2_ops,
1614 static struct clk_branch gcc_blsp2_qup3_spi_apps_clk = {
1617 .enable_reg = 0x0a84,
1618 .enable_mask = BIT(0),
1619 .hw.init = &(struct clk_init_data){
1620 .name = "gcc_blsp2_qup3_spi_apps_clk",
1621 .parent_names = (const char *[]){
1622 "blsp2_qup3_spi_apps_clk_src",
1625 .flags = CLK_SET_RATE_PARENT,
1626 .ops = &clk_branch2_ops,
1631 static struct clk_branch gcc_blsp2_qup4_i2c_apps_clk = {
1634 .enable_reg = 0x0b08,
1635 .enable_mask = BIT(0),
1636 .hw.init = &(struct clk_init_data){
1637 .name = "gcc_blsp2_qup4_i2c_apps_clk",
1638 .parent_names = (const char *[]){
1639 "blsp2_qup4_i2c_apps_clk_src",
1642 .flags = CLK_SET_RATE_PARENT,
1643 .ops = &clk_branch2_ops,
1648 static struct clk_branch gcc_blsp2_qup4_spi_apps_clk = {
1651 .enable_reg = 0x0b04,
1652 .enable_mask = BIT(0),
1653 .hw.init = &(struct clk_init_data){
1654 .name = "gcc_blsp2_qup4_spi_apps_clk",
1655 .parent_names = (const char *[]){
1656 "blsp2_qup4_spi_apps_clk_src",
1659 .flags = CLK_SET_RATE_PARENT,
1660 .ops = &clk_branch2_ops,
1665 static struct clk_branch gcc_blsp2_qup5_i2c_apps_clk = {
1668 .enable_reg = 0x0b88,
1669 .enable_mask = BIT(0),
1670 .hw.init = &(struct clk_init_data){
1671 .name = "gcc_blsp2_qup5_i2c_apps_clk",
1672 .parent_names = (const char *[]){
1673 "blsp2_qup5_i2c_apps_clk_src",
1676 .flags = CLK_SET_RATE_PARENT,
1677 .ops = &clk_branch2_ops,
1682 static struct clk_branch gcc_blsp2_qup5_spi_apps_clk = {
1685 .enable_reg = 0x0b84,
1686 .enable_mask = BIT(0),
1687 .hw.init = &(struct clk_init_data){
1688 .name = "gcc_blsp2_qup5_spi_apps_clk",
1689 .parent_names = (const char *[]){
1690 "blsp2_qup5_spi_apps_clk_src",
1693 .flags = CLK_SET_RATE_PARENT,
1694 .ops = &clk_branch2_ops,
1699 static struct clk_branch gcc_blsp2_qup6_i2c_apps_clk = {
1702 .enable_reg = 0x0c08,
1703 .enable_mask = BIT(0),
1704 .hw.init = &(struct clk_init_data){
1705 .name = "gcc_blsp2_qup6_i2c_apps_clk",
1706 .parent_names = (const char *[]){
1707 "blsp2_qup6_i2c_apps_clk_src",
1710 .flags = CLK_SET_RATE_PARENT,
1711 .ops = &clk_branch2_ops,
1716 static struct clk_branch gcc_blsp2_qup6_spi_apps_clk = {
1719 .enable_reg = 0x0c04,
1720 .enable_mask = BIT(0),
1721 .hw.init = &(struct clk_init_data){
1722 .name = "gcc_blsp2_qup6_spi_apps_clk",
1723 .parent_names = (const char *[]){
1724 "blsp2_qup6_spi_apps_clk_src",
1727 .flags = CLK_SET_RATE_PARENT,
1728 .ops = &clk_branch2_ops,
1733 static struct clk_branch gcc_blsp2_uart1_apps_clk = {
1736 .enable_reg = 0x09c4,
1737 .enable_mask = BIT(0),
1738 .hw.init = &(struct clk_init_data){
1739 .name = "gcc_blsp2_uart1_apps_clk",
1740 .parent_names = (const char *[]){
1741 "blsp2_uart1_apps_clk_src",
1744 .flags = CLK_SET_RATE_PARENT,
1745 .ops = &clk_branch2_ops,
1750 static struct clk_branch gcc_blsp2_uart2_apps_clk = {
1753 .enable_reg = 0x0a44,
1754 .enable_mask = BIT(0),
1755 .hw.init = &(struct clk_init_data){
1756 .name = "gcc_blsp2_uart2_apps_clk",
1757 .parent_names = (const char *[]){
1758 "blsp2_uart2_apps_clk_src",
1761 .flags = CLK_SET_RATE_PARENT,
1762 .ops = &clk_branch2_ops,
1767 static struct clk_branch gcc_blsp2_uart3_apps_clk = {
1770 .enable_reg = 0x0ac4,
1771 .enable_mask = BIT(0),
1772 .hw.init = &(struct clk_init_data){
1773 .name = "gcc_blsp2_uart3_apps_clk",
1774 .parent_names = (const char *[]){
1775 "blsp2_uart3_apps_clk_src",
1778 .flags = CLK_SET_RATE_PARENT,
1779 .ops = &clk_branch2_ops,
1784 static struct clk_branch gcc_blsp2_uart4_apps_clk = {
1787 .enable_reg = 0x0b44,
1788 .enable_mask = BIT(0),
1789 .hw.init = &(struct clk_init_data){
1790 .name = "gcc_blsp2_uart4_apps_clk",
1791 .parent_names = (const char *[]){
1792 "blsp2_uart4_apps_clk_src",
1795 .flags = CLK_SET_RATE_PARENT,
1796 .ops = &clk_branch2_ops,
1801 static struct clk_branch gcc_blsp2_uart5_apps_clk = {
1804 .enable_reg = 0x0bc4,
1805 .enable_mask = BIT(0),
1806 .hw.init = &(struct clk_init_data){
1807 .name = "gcc_blsp2_uart5_apps_clk",
1808 .parent_names = (const char *[]){
1809 "blsp2_uart5_apps_clk_src",
1812 .flags = CLK_SET_RATE_PARENT,
1813 .ops = &clk_branch2_ops,
1818 static struct clk_branch gcc_blsp2_uart6_apps_clk = {
1821 .enable_reg = 0x0c44,
1822 .enable_mask = BIT(0),
1823 .hw.init = &(struct clk_init_data){
1824 .name = "gcc_blsp2_uart6_apps_clk",
1825 .parent_names = (const char *[]){
1826 "blsp2_uart6_apps_clk_src",
1829 .flags = CLK_SET_RATE_PARENT,
1830 .ops = &clk_branch2_ops,
1835 static struct clk_branch gcc_boot_rom_ahb_clk = {
1837 .halt_check = BRANCH_HALT_VOTED,
1839 .enable_reg = 0x1484,
1840 .enable_mask = BIT(10),
1841 .hw.init = &(struct clk_init_data){
1842 .name = "gcc_boot_rom_ahb_clk",
1843 .parent_names = (const char *[]){
1844 "config_noc_clk_src",
1847 .ops = &clk_branch2_ops,
1852 static struct clk_branch gcc_ce1_ahb_clk = {
1854 .halt_check = BRANCH_HALT_VOTED,
1856 .enable_reg = 0x1484,
1857 .enable_mask = BIT(3),
1858 .hw.init = &(struct clk_init_data){
1859 .name = "gcc_ce1_ahb_clk",
1860 .parent_names = (const char *[]){
1861 "config_noc_clk_src",
1864 .ops = &clk_branch2_ops,
1869 static struct clk_branch gcc_ce1_axi_clk = {
1871 .halt_check = BRANCH_HALT_VOTED,
1873 .enable_reg = 0x1484,
1874 .enable_mask = BIT(4),
1875 .hw.init = &(struct clk_init_data){
1876 .name = "gcc_ce1_axi_clk",
1877 .parent_names = (const char *[]){
1878 "system_noc_clk_src",
1881 .ops = &clk_branch2_ops,
1886 static struct clk_branch gcc_ce1_clk = {
1888 .halt_check = BRANCH_HALT_VOTED,
1890 .enable_reg = 0x1484,
1891 .enable_mask = BIT(5),
1892 .hw.init = &(struct clk_init_data){
1893 .name = "gcc_ce1_clk",
1894 .parent_names = (const char *[]){
1898 .ops = &clk_branch2_ops,
1903 static struct clk_branch gcc_ce2_ahb_clk = {
1905 .halt_check = BRANCH_HALT_VOTED,
1907 .enable_reg = 0x1484,
1908 .enable_mask = BIT(0),
1909 .hw.init = &(struct clk_init_data){
1910 .name = "gcc_ce2_ahb_clk",
1911 .parent_names = (const char *[]){
1912 "config_noc_clk_src",
1915 .ops = &clk_branch2_ops,
1920 static struct clk_branch gcc_ce2_axi_clk = {
1922 .halt_check = BRANCH_HALT_VOTED,
1924 .enable_reg = 0x1484,
1925 .enable_mask = BIT(1),
1926 .hw.init = &(struct clk_init_data){
1927 .name = "gcc_ce2_axi_clk",
1928 .parent_names = (const char *[]){
1929 "system_noc_clk_src",
1932 .ops = &clk_branch2_ops,
1937 static struct clk_branch gcc_ce2_clk = {
1939 .halt_check = BRANCH_HALT_VOTED,
1941 .enable_reg = 0x1484,
1942 .enable_mask = BIT(2),
1943 .hw.init = &(struct clk_init_data){
1944 .name = "gcc_ce2_clk",
1945 .parent_names = (const char *[]){
1949 .flags = CLK_SET_RATE_PARENT,
1950 .ops = &clk_branch2_ops,
1955 static struct clk_branch gcc_ce3_ahb_clk = {
1957 .halt_check = BRANCH_HALT_VOTED,
1959 .enable_reg = 0x1d0c,
1960 .enable_mask = BIT(0),
1961 .hw.init = &(struct clk_init_data){
1962 .name = "gcc_ce3_ahb_clk",
1963 .parent_names = (const char *[]){
1964 "config_noc_clk_src",
1967 .ops = &clk_branch2_ops,
1972 static struct clk_branch gcc_ce3_axi_clk = {
1974 .halt_check = BRANCH_HALT_VOTED,
1976 .enable_reg = 0x1d08,
1977 .enable_mask = BIT(0),
1978 .hw.init = &(struct clk_init_data){
1979 .name = "gcc_ce3_axi_clk",
1980 .parent_names = (const char *[]){
1981 "system_noc_clk_src",
1984 .ops = &clk_branch2_ops,
1989 static struct clk_branch gcc_ce3_clk = {
1991 .halt_check = BRANCH_HALT_VOTED,
1993 .enable_reg = 0x1d04,
1994 .enable_mask = BIT(0),
1995 .hw.init = &(struct clk_init_data){
1996 .name = "gcc_ce3_clk",
1997 .parent_names = (const char *[]){
2001 .flags = CLK_SET_RATE_PARENT,
2002 .ops = &clk_branch2_ops,
2007 static struct clk_branch gcc_gp1_clk = {
2010 .enable_reg = 0x1900,
2011 .enable_mask = BIT(0),
2012 .hw.init = &(struct clk_init_data){
2013 .name = "gcc_gp1_clk",
2014 .parent_names = (const char *[]){
2018 .flags = CLK_SET_RATE_PARENT,
2019 .ops = &clk_branch2_ops,
2024 static struct clk_branch gcc_gp2_clk = {
2027 .enable_reg = 0x1940,
2028 .enable_mask = BIT(0),
2029 .hw.init = &(struct clk_init_data){
2030 .name = "gcc_gp2_clk",
2031 .parent_names = (const char *[]){
2035 .flags = CLK_SET_RATE_PARENT,
2036 .ops = &clk_branch2_ops,
2041 static struct clk_branch gcc_gp3_clk = {
2044 .enable_reg = 0x1980,
2045 .enable_mask = BIT(0),
2046 .hw.init = &(struct clk_init_data){
2047 .name = "gcc_gp3_clk",
2048 .parent_names = (const char *[]){
2052 .flags = CLK_SET_RATE_PARENT,
2053 .ops = &clk_branch2_ops,
2058 static struct clk_branch gcc_ocmem_noc_cfg_ahb_clk = {
2061 .enable_reg = 0x0248,
2062 .enable_mask = BIT(0),
2063 .hw.init = &(struct clk_init_data){
2064 .name = "gcc_ocmem_noc_cfg_ahb_clk",
2065 .parent_names = (const char *[]){
2066 "config_noc_clk_src",
2069 .ops = &clk_branch2_ops,
2074 static struct clk_branch gcc_pdm2_clk = {
2077 .enable_reg = 0x0ccc,
2078 .enable_mask = BIT(0),
2079 .hw.init = &(struct clk_init_data){
2080 .name = "gcc_pdm2_clk",
2081 .parent_names = (const char *[]){
2085 .flags = CLK_SET_RATE_PARENT,
2086 .ops = &clk_branch2_ops,
2091 static struct clk_branch gcc_pdm_ahb_clk = {
2094 .enable_reg = 0x0cc4,
2095 .enable_mask = BIT(0),
2096 .hw.init = &(struct clk_init_data){
2097 .name = "gcc_pdm_ahb_clk",
2098 .parent_names = (const char *[]){
2099 "periph_noc_clk_src",
2102 .ops = &clk_branch2_ops,
2107 static struct clk_branch gcc_periph_noc_usb_hsic_ahb_clk = {
2110 .enable_reg = 0x01a4,
2111 .enable_mask = BIT(0),
2112 .hw.init = &(struct clk_init_data){
2113 .name = "gcc_periph_noc_usb_hsic_ahb_clk",
2114 .parent_names = (const char *[]){
2115 "usb_hsic_ahb_clk_src",
2118 .flags = CLK_SET_RATE_PARENT,
2119 .ops = &clk_branch2_ops,
2124 static struct clk_branch gcc_prng_ahb_clk = {
2126 .halt_check = BRANCH_HALT_VOTED,
2128 .enable_reg = 0x1484,
2129 .enable_mask = BIT(13),
2130 .hw.init = &(struct clk_init_data){
2131 .name = "gcc_prng_ahb_clk",
2132 .parent_names = (const char *[]){
2133 "periph_noc_clk_src",
2136 .ops = &clk_branch2_ops,
2141 static struct clk_branch gcc_sdcc1_ahb_clk = {
2144 .enable_reg = 0x04c8,
2145 .enable_mask = BIT(0),
2146 .hw.init = &(struct clk_init_data){
2147 .name = "gcc_sdcc1_ahb_clk",
2148 .parent_names = (const char *[]){
2149 "periph_noc_clk_src",
2152 .ops = &clk_branch2_ops,
2157 static struct clk_branch gcc_sdcc1_apps_clk = {
2160 .enable_reg = 0x04c4,
2161 .enable_mask = BIT(0),
2162 .hw.init = &(struct clk_init_data){
2163 .name = "gcc_sdcc1_apps_clk",
2164 .parent_names = (const char *[]){
2165 "sdcc1_apps_clk_src",
2168 .flags = CLK_SET_RATE_PARENT,
2169 .ops = &clk_branch2_ops,
2174 static struct clk_branch gcc_sdcc1_cdccal_ff_clk = {
2177 .enable_reg = 0x04e8,
2178 .enable_mask = BIT(0),
2179 .hw.init = &(struct clk_init_data){
2180 .name = "gcc_sdcc1_cdccal_ff_clk",
2181 .parent_names = (const char *[]){
2185 .ops = &clk_branch2_ops,
2190 static struct clk_branch gcc_sdcc1_cdccal_sleep_clk = {
2193 .enable_reg = 0x04e4,
2194 .enable_mask = BIT(0),
2195 .hw.init = &(struct clk_init_data){
2196 .name = "gcc_sdcc1_cdccal_sleep_clk",
2197 .parent_names = (const char *[]){
2201 .ops = &clk_branch2_ops,
2206 static struct clk_branch gcc_sdcc2_ahb_clk = {
2209 .enable_reg = 0x0508,
2210 .enable_mask = BIT(0),
2211 .hw.init = &(struct clk_init_data){
2212 .name = "gcc_sdcc2_ahb_clk",
2213 .parent_names = (const char *[]){
2214 "periph_noc_clk_src",
2217 .ops = &clk_branch2_ops,
2222 static struct clk_branch gcc_sdcc2_apps_clk = {
2225 .enable_reg = 0x0504,
2226 .enable_mask = BIT(0),
2227 .hw.init = &(struct clk_init_data){
2228 .name = "gcc_sdcc2_apps_clk",
2229 .parent_names = (const char *[]){
2230 "sdcc2_apps_clk_src",
2233 .flags = CLK_SET_RATE_PARENT,
2234 .ops = &clk_branch2_ops,
2239 static struct clk_branch gcc_sdcc3_ahb_clk = {
2242 .enable_reg = 0x0548,
2243 .enable_mask = BIT(0),
2244 .hw.init = &(struct clk_init_data){
2245 .name = "gcc_sdcc3_ahb_clk",
2246 .parent_names = (const char *[]){
2247 "periph_noc_clk_src",
2250 .ops = &clk_branch2_ops,
2255 static struct clk_branch gcc_sdcc3_apps_clk = {
2258 .enable_reg = 0x0544,
2259 .enable_mask = BIT(0),
2260 .hw.init = &(struct clk_init_data){
2261 .name = "gcc_sdcc3_apps_clk",
2262 .parent_names = (const char *[]){
2263 "sdcc3_apps_clk_src",
2266 .flags = CLK_SET_RATE_PARENT,
2267 .ops = &clk_branch2_ops,
2272 static struct clk_branch gcc_sdcc4_ahb_clk = {
2275 .enable_reg = 0x0588,
2276 .enable_mask = BIT(0),
2277 .hw.init = &(struct clk_init_data){
2278 .name = "gcc_sdcc4_ahb_clk",
2279 .parent_names = (const char *[]){
2280 "periph_noc_clk_src",
2283 .ops = &clk_branch2_ops,
2288 static struct clk_branch gcc_sdcc4_apps_clk = {
2291 .enable_reg = 0x0584,
2292 .enable_mask = BIT(0),
2293 .hw.init = &(struct clk_init_data){
2294 .name = "gcc_sdcc4_apps_clk",
2295 .parent_names = (const char *[]){
2296 "sdcc4_apps_clk_src",
2299 .flags = CLK_SET_RATE_PARENT,
2300 .ops = &clk_branch2_ops,
2305 static struct clk_branch gcc_sys_noc_usb3_axi_clk = {
2308 .enable_reg = 0x0108,
2309 .enable_mask = BIT(0),
2310 .hw.init = &(struct clk_init_data){
2311 .name = "gcc_sys_noc_usb3_axi_clk",
2312 .parent_names = (const char *[]){
2313 "usb30_master_clk_src",
2316 .flags = CLK_SET_RATE_PARENT,
2317 .ops = &clk_branch2_ops,
2322 static struct clk_branch gcc_sys_noc_usb3_sec_axi_clk = {
2325 .enable_reg = 0x0138,
2326 .enable_mask = BIT(0),
2327 .hw.init = &(struct clk_init_data){
2328 .name = "gcc_sys_noc_usb3_sec_axi_clk",
2329 .parent_names = (const char *[]){
2330 "usb30_sec_master_clk_src",
2333 .flags = CLK_SET_RATE_PARENT,
2334 .ops = &clk_branch2_ops,
2339 static struct clk_branch gcc_tsif_ahb_clk = {
2342 .enable_reg = 0x0d84,
2343 .enable_mask = BIT(0),
2344 .hw.init = &(struct clk_init_data){
2345 .name = "gcc_tsif_ahb_clk",
2346 .parent_names = (const char *[]){
2347 "periph_noc_clk_src",
2350 .ops = &clk_branch2_ops,
2355 static struct clk_branch gcc_tsif_inactivity_timers_clk = {
2358 .enable_reg = 0x0d8c,
2359 .enable_mask = BIT(0),
2360 .hw.init = &(struct clk_init_data){
2361 .name = "gcc_tsif_inactivity_timers_clk",
2362 .parent_names = (const char *[]){
2366 .flags = CLK_SET_RATE_PARENT,
2367 .ops = &clk_branch2_ops,
2372 static struct clk_branch gcc_tsif_ref_clk = {
2375 .enable_reg = 0x0d88,
2376 .enable_mask = BIT(0),
2377 .hw.init = &(struct clk_init_data){
2378 .name = "gcc_tsif_ref_clk",
2379 .parent_names = (const char *[]){
2383 .flags = CLK_SET_RATE_PARENT,
2384 .ops = &clk_branch2_ops,
2389 static struct clk_branch gcc_usb2a_phy_sleep_clk = {
2392 .enable_reg = 0x04ac,
2393 .enable_mask = BIT(0),
2394 .hw.init = &(struct clk_init_data){
2395 .name = "gcc_usb2a_phy_sleep_clk",
2396 .parent_names = (const char *[]){
2400 .ops = &clk_branch2_ops,
2405 static struct clk_branch gcc_usb2b_phy_sleep_clk = {
2408 .enable_reg = 0x04b4,
2409 .enable_mask = BIT(0),
2410 .hw.init = &(struct clk_init_data){
2411 .name = "gcc_usb2b_phy_sleep_clk",
2412 .parent_names = (const char *[]){
2416 .ops = &clk_branch2_ops,
2421 static struct clk_branch gcc_usb30_master_clk = {
2424 .enable_reg = 0x03c8,
2425 .enable_mask = BIT(0),
2426 .hw.init = &(struct clk_init_data){
2427 .name = "gcc_usb30_master_clk",
2428 .parent_names = (const char *[]){
2429 "usb30_master_clk_src",
2432 .flags = CLK_SET_RATE_PARENT,
2433 .ops = &clk_branch2_ops,
2438 static struct clk_branch gcc_usb30_sec_master_clk = {
2441 .enable_reg = 0x1bc8,
2442 .enable_mask = BIT(0),
2443 .hw.init = &(struct clk_init_data){
2444 .name = "gcc_usb30_sec_master_clk",
2445 .parent_names = (const char *[]){
2446 "usb30_sec_master_clk_src",
2449 .flags = CLK_SET_RATE_PARENT,
2450 .ops = &clk_branch2_ops,
2455 static struct clk_branch gcc_usb30_mock_utmi_clk = {
2458 .enable_reg = 0x03d0,
2459 .enable_mask = BIT(0),
2460 .hw.init = &(struct clk_init_data){
2461 .name = "gcc_usb30_mock_utmi_clk",
2462 .parent_names = (const char *[]){
2463 "usb30_mock_utmi_clk_src",
2466 .flags = CLK_SET_RATE_PARENT,
2467 .ops = &clk_branch2_ops,
2472 static struct clk_branch gcc_usb30_sleep_clk = {
2475 .enable_reg = 0x03cc,
2476 .enable_mask = BIT(0),
2477 .hw.init = &(struct clk_init_data){
2478 .name = "gcc_usb30_sleep_clk",
2479 .parent_names = (const char *[]){
2483 .ops = &clk_branch2_ops,
2488 static struct clk_branch gcc_usb_hs_ahb_clk = {
2491 .enable_reg = 0x0488,
2492 .enable_mask = BIT(0),
2493 .hw.init = &(struct clk_init_data){
2494 .name = "gcc_usb_hs_ahb_clk",
2495 .parent_names = (const char *[]){
2496 "periph_noc_clk_src",
2499 .ops = &clk_branch2_ops,
2504 static struct clk_branch gcc_usb_hs_inactivity_timers_clk = {
2507 .enable_reg = 0x048c,
2508 .enable_mask = BIT(0),
2509 .hw.init = &(struct clk_init_data){
2510 .name = "gcc_usb_hs_inactivity_timers_clk",
2511 .parent_names = (const char *[]){
2515 .flags = CLK_SET_RATE_PARENT,
2516 .ops = &clk_branch2_ops,
2521 static struct clk_branch gcc_usb_hs_system_clk = {
2524 .enable_reg = 0x0484,
2525 .enable_mask = BIT(0),
2526 .hw.init = &(struct clk_init_data){
2527 .name = "gcc_usb_hs_system_clk",
2528 .parent_names = (const char *[]){
2529 "usb_hs_system_clk_src",
2532 .flags = CLK_SET_RATE_PARENT,
2533 .ops = &clk_branch2_ops,
2538 static struct clk_branch gcc_usb_hsic_ahb_clk = {
2541 .enable_reg = 0x0408,
2542 .enable_mask = BIT(0),
2543 .hw.init = &(struct clk_init_data){
2544 .name = "gcc_usb_hsic_ahb_clk",
2545 .parent_names = (const char *[]){
2546 "periph_noc_clk_src",
2549 .ops = &clk_branch2_ops,
2554 static struct clk_branch gcc_usb_hsic_clk = {
2557 .enable_reg = 0x0410,
2558 .enable_mask = BIT(0),
2559 .hw.init = &(struct clk_init_data){
2560 .name = "gcc_usb_hsic_clk",
2561 .parent_names = (const char *[]){
2565 .flags = CLK_SET_RATE_PARENT,
2566 .ops = &clk_branch2_ops,
2571 static struct clk_branch gcc_usb_hsic_io_cal_clk = {
2574 .enable_reg = 0x0414,
2575 .enable_mask = BIT(0),
2576 .hw.init = &(struct clk_init_data){
2577 .name = "gcc_usb_hsic_io_cal_clk",
2578 .parent_names = (const char *[]){
2579 "usb_hsic_io_cal_clk_src",
2582 .flags = CLK_SET_RATE_PARENT,
2583 .ops = &clk_branch2_ops,
2588 static struct clk_branch gcc_usb_hsic_io_cal_sleep_clk = {
2591 .enable_reg = 0x0418,
2592 .enable_mask = BIT(0),
2593 .hw.init = &(struct clk_init_data){
2594 .name = "gcc_usb_hsic_io_cal_sleep_clk",
2595 .parent_names = (const char *[]){
2599 .ops = &clk_branch2_ops,
2604 static struct clk_branch gcc_usb_hsic_system_clk = {
2607 .enable_reg = 0x040c,
2608 .enable_mask = BIT(0),
2609 .hw.init = &(struct clk_init_data){
2610 .name = "gcc_usb_hsic_system_clk",
2611 .parent_names = (const char *[]){
2612 "usb_hsic_system_clk_src",
2615 .flags = CLK_SET_RATE_PARENT,
2616 .ops = &clk_branch2_ops,
2621 static struct clk_regmap *gcc_apq8084_clocks[] = {
2622 [GPLL0] = &gpll0.clkr,
2623 [GPLL0_VOTE] = &gpll0_vote,
2624 [GPLL1] = &gpll1.clkr,
2625 [GPLL1_VOTE] = &gpll1_vote,
2626 [GPLL4] = &gpll4.clkr,
2627 [GPLL4_VOTE] = &gpll4_vote,
2628 [CONFIG_NOC_CLK_SRC] = &config_noc_clk_src.clkr,
2629 [PERIPH_NOC_CLK_SRC] = &periph_noc_clk_src.clkr,
2630 [SYSTEM_NOC_CLK_SRC] = &system_noc_clk_src.clkr,
2631 [USB30_MASTER_CLK_SRC] = &usb30_master_clk_src.clkr,
2632 [USB30_SEC_MASTER_CLK_SRC] = &usb30_sec_master_clk_src.clkr,
2633 [USB_HSIC_AHB_CLK_SRC] = &usb_hsic_ahb_clk_src.clkr,
2634 [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
2635 [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
2636 [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
2637 [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
2638 [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
2639 [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
2640 [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
2641 [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
2642 [BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr,
2643 [BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr,
2644 [BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr,
2645 [BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr,
2646 [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
2647 [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
2648 [BLSP1_UART3_APPS_CLK_SRC] = &blsp1_uart3_apps_clk_src.clkr,
2649 [BLSP1_UART4_APPS_CLK_SRC] = &blsp1_uart4_apps_clk_src.clkr,
2650 [BLSP1_UART5_APPS_CLK_SRC] = &blsp1_uart5_apps_clk_src.clkr,
2651 [BLSP1_UART6_APPS_CLK_SRC] = &blsp1_uart6_apps_clk_src.clkr,
2652 [BLSP2_QUP1_I2C_APPS_CLK_SRC] = &blsp2_qup1_i2c_apps_clk_src.clkr,
2653 [BLSP2_QUP1_SPI_APPS_CLK_SRC] = &blsp2_qup1_spi_apps_clk_src.clkr,
2654 [BLSP2_QUP2_I2C_APPS_CLK_SRC] = &blsp2_qup2_i2c_apps_clk_src.clkr,
2655 [BLSP2_QUP2_SPI_APPS_CLK_SRC] = &blsp2_qup2_spi_apps_clk_src.clkr,
2656 [BLSP2_QUP3_I2C_APPS_CLK_SRC] = &blsp2_qup3_i2c_apps_clk_src.clkr,
2657 [BLSP2_QUP3_SPI_APPS_CLK_SRC] = &blsp2_qup3_spi_apps_clk_src.clkr,
2658 [BLSP2_QUP4_I2C_APPS_CLK_SRC] = &blsp2_qup4_i2c_apps_clk_src.clkr,
2659 [BLSP2_QUP4_SPI_APPS_CLK_SRC] = &blsp2_qup4_spi_apps_clk_src.clkr,
2660 [BLSP2_QUP5_I2C_APPS_CLK_SRC] = &blsp2_qup5_i2c_apps_clk_src.clkr,
2661 [BLSP2_QUP5_SPI_APPS_CLK_SRC] = &blsp2_qup5_spi_apps_clk_src.clkr,
2662 [BLSP2_QUP6_I2C_APPS_CLK_SRC] = &blsp2_qup6_i2c_apps_clk_src.clkr,
2663 [BLSP2_QUP6_SPI_APPS_CLK_SRC] = &blsp2_qup6_spi_apps_clk_src.clkr,
2664 [BLSP2_UART1_APPS_CLK_SRC] = &blsp2_uart1_apps_clk_src.clkr,
2665 [BLSP2_UART2_APPS_CLK_SRC] = &blsp2_uart2_apps_clk_src.clkr,
2666 [BLSP2_UART3_APPS_CLK_SRC] = &blsp2_uart3_apps_clk_src.clkr,
2667 [BLSP2_UART4_APPS_CLK_SRC] = &blsp2_uart4_apps_clk_src.clkr,
2668 [BLSP2_UART5_APPS_CLK_SRC] = &blsp2_uart5_apps_clk_src.clkr,
2669 [BLSP2_UART6_APPS_CLK_SRC] = &blsp2_uart6_apps_clk_src.clkr,
2670 [CE1_CLK_SRC] = &ce1_clk_src.clkr,
2671 [CE2_CLK_SRC] = &ce2_clk_src.clkr,
2672 [CE3_CLK_SRC] = &ce3_clk_src.clkr,
2673 [GP1_CLK_SRC] = &gp1_clk_src.clkr,
2674 [GP2_CLK_SRC] = &gp2_clk_src.clkr,
2675 [GP3_CLK_SRC] = &gp3_clk_src.clkr,
2676 [PDM2_CLK_SRC] = &pdm2_clk_src.clkr,
2677 [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
2678 [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,
2679 [SDCC3_APPS_CLK_SRC] = &sdcc3_apps_clk_src.clkr,
2680 [SDCC4_APPS_CLK_SRC] = &sdcc4_apps_clk_src.clkr,
2681 [TSIF_REF_CLK_SRC] = &tsif_ref_clk_src.clkr,
2682 [USB30_MOCK_UTMI_CLK_SRC] = &usb30_mock_utmi_clk_src.clkr,
2683 [USB30_SEC_MOCK_UTMI_CLK_SRC] = &usb30_sec_mock_utmi_clk_src.clkr,
2684 [USB_HS_SYSTEM_CLK_SRC] = &usb_hs_system_clk_src.clkr,
2685 [USB_HSIC_CLK_SRC] = &usb_hsic_clk_src.clkr,
2686 [USB_HSIC_IO_CAL_CLK_SRC] = &usb_hsic_io_cal_clk_src.clkr,
2687 [USB_HSIC_MOCK_UTMI_CLK_SRC] = &usb_hsic_mock_utmi_clk_src.clkr,
2688 [USB_HSIC_SYSTEM_CLK_SRC] = &usb_hsic_system_clk_src.clkr,
2689 [GCC_BAM_DMA_AHB_CLK] = &gcc_bam_dma_ahb_clk.clkr,
2690 [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
2691 [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
2692 [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
2693 [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
2694 [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
2695 [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
2696 [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
2697 [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
2698 [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
2699 [GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr,
2700 [GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr,
2701 [GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr,
2702 [GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr,
2703 [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
2704 [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
2705 [GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr,
2706 [GCC_BLSP1_UART4_APPS_CLK] = &gcc_blsp1_uart4_apps_clk.clkr,
2707 [GCC_BLSP1_UART5_APPS_CLK] = &gcc_blsp1_uart5_apps_clk.clkr,
2708 [GCC_BLSP1_UART6_APPS_CLK] = &gcc_blsp1_uart6_apps_clk.clkr,
2709 [GCC_BLSP2_AHB_CLK] = &gcc_blsp2_ahb_clk.clkr,
2710 [GCC_BLSP2_QUP1_I2C_APPS_CLK] = &gcc_blsp2_qup1_i2c_apps_clk.clkr,
2711 [GCC_BLSP2_QUP1_SPI_APPS_CLK] = &gcc_blsp2_qup1_spi_apps_clk.clkr,
2712 [GCC_BLSP2_QUP2_I2C_APPS_CLK] = &gcc_blsp2_qup2_i2c_apps_clk.clkr,
2713 [GCC_BLSP2_QUP2_SPI_APPS_CLK] = &gcc_blsp2_qup2_spi_apps_clk.clkr,
2714 [GCC_BLSP2_QUP3_I2C_APPS_CLK] = &gcc_blsp2_qup3_i2c_apps_clk.clkr,
2715 [GCC_BLSP2_QUP3_SPI_APPS_CLK] = &gcc_blsp2_qup3_spi_apps_clk.clkr,
2716 [GCC_BLSP2_QUP4_I2C_APPS_CLK] = &gcc_blsp2_qup4_i2c_apps_clk.clkr,
2717 [GCC_BLSP2_QUP4_SPI_APPS_CLK] = &gcc_blsp2_qup4_spi_apps_clk.clkr,
2718 [GCC_BLSP2_QUP5_I2C_APPS_CLK] = &gcc_blsp2_qup5_i2c_apps_clk.clkr,
2719 [GCC_BLSP2_QUP5_SPI_APPS_CLK] = &gcc_blsp2_qup5_spi_apps_clk.clkr,
2720 [GCC_BLSP2_QUP6_I2C_APPS_CLK] = &gcc_blsp2_qup6_i2c_apps_clk.clkr,
2721 [GCC_BLSP2_QUP6_SPI_APPS_CLK] = &gcc_blsp2_qup6_spi_apps_clk.clkr,
2722 [GCC_BLSP2_UART1_APPS_CLK] = &gcc_blsp2_uart1_apps_clk.clkr,
2723 [GCC_BLSP2_UART2_APPS_CLK] = &gcc_blsp2_uart2_apps_clk.clkr,
2724 [GCC_BLSP2_UART3_APPS_CLK] = &gcc_blsp2_uart3_apps_clk.clkr,
2725 [GCC_BLSP2_UART4_APPS_CLK] = &gcc_blsp2_uart4_apps_clk.clkr,
2726 [GCC_BLSP2_UART5_APPS_CLK] = &gcc_blsp2_uart5_apps_clk.clkr,
2727 [GCC_BLSP2_UART6_APPS_CLK] = &gcc_blsp2_uart6_apps_clk.clkr,
2728 [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
2729 [GCC_CE1_AHB_CLK] = &gcc_ce1_ahb_clk.clkr,
2730 [GCC_CE1_AXI_CLK] = &gcc_ce1_axi_clk.clkr,
2731 [GCC_CE1_CLK] = &gcc_ce1_clk.clkr,
2732 [GCC_CE2_AHB_CLK] = &gcc_ce2_ahb_clk.clkr,
2733 [GCC_CE2_AXI_CLK] = &gcc_ce2_axi_clk.clkr,
2734 [GCC_CE2_CLK] = &gcc_ce2_clk.clkr,
2735 [GCC_CE3_AHB_CLK] = &gcc_ce3_ahb_clk.clkr,
2736 [GCC_CE3_AXI_CLK] = &gcc_ce3_axi_clk.clkr,
2737 [GCC_CE3_CLK] = &gcc_ce3_clk.clkr,
2738 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
2739 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
2740 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
2741 [GCC_OCMEM_NOC_CFG_AHB_CLK] = &gcc_ocmem_noc_cfg_ahb_clk.clkr,
2742 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
2743 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
2744 [GCC_PERIPH_NOC_USB_HSIC_AHB_CLK] = &gcc_periph_noc_usb_hsic_ahb_clk.clkr,
2745 [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
2746 [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
2747 [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
2748 [GCC_SDCC1_CDCCAL_FF_CLK] = &gcc_sdcc1_cdccal_ff_clk.clkr,
2749 [GCC_SDCC1_CDCCAL_SLEEP_CLK] = &gcc_sdcc1_cdccal_sleep_clk.clkr,
2750 [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
2751 [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
2752 [GCC_SDCC3_AHB_CLK] = &gcc_sdcc3_ahb_clk.clkr,
2753 [GCC_SDCC3_APPS_CLK] = &gcc_sdcc3_apps_clk.clkr,
2754 [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr,
2755 [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr,
2756 [GCC_SYS_NOC_USB3_AXI_CLK] = &gcc_sys_noc_usb3_axi_clk.clkr,
2757 [GCC_SYS_NOC_USB3_SEC_AXI_CLK] = &gcc_sys_noc_usb3_sec_axi_clk.clkr,
2758 [GCC_TSIF_AHB_CLK] = &gcc_tsif_ahb_clk.clkr,
2759 [GCC_TSIF_INACTIVITY_TIMERS_CLK] = &gcc_tsif_inactivity_timers_clk.clkr,
2760 [GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr,
2761 [GCC_USB2A_PHY_SLEEP_CLK] = &gcc_usb2a_phy_sleep_clk.clkr,
2762 [GCC_USB2B_PHY_SLEEP_CLK] = &gcc_usb2b_phy_sleep_clk.clkr,
2763 [GCC_USB30_MASTER_CLK] = &gcc_usb30_master_clk.clkr,
2764 [GCC_USB30_MOCK_UTMI_CLK] = &gcc_usb30_mock_utmi_clk.clkr,
2765 [GCC_USB30_SLEEP_CLK] = &gcc_usb30_sleep_clk.clkr,
2766 [GCC_USB30_SEC_MASTER_CLK] = &gcc_usb30_sec_master_clk.clkr,
2767 [GCC_USB30_SEC_MOCK_UTMI_CLK] = &gcc_usb30_sec_mock_utmi_clk.clkr,
2768 [GCC_USB30_SEC_SLEEP_CLK] = &gcc_usb30_sec_sleep_clk.clkr,
2769 [GCC_USB_HS_AHB_CLK] = &gcc_usb_hs_ahb_clk.clkr,
2770 [GCC_USB_HS_INACTIVITY_TIMERS_CLK] = &gcc_usb_hs_inactivity_timers_clk.clkr,
2771 [GCC_USB_HS_SYSTEM_CLK] = &gcc_usb_hs_system_clk.clkr,
2772 [GCC_USB_HSIC_AHB_CLK] = &gcc_usb_hsic_ahb_clk.clkr,
2773 [GCC_USB_HSIC_CLK] = &gcc_usb_hsic_clk.clkr,
2774 [GCC_USB_HSIC_IO_CAL_CLK] = &gcc_usb_hsic_io_cal_clk.clkr,
2775 [GCC_USB_HSIC_IO_CAL_SLEEP_CLK] = &gcc_usb_hsic_io_cal_sleep_clk.clkr,
2776 [GCC_USB_HSIC_MOCK_UTMI_CLK] = &gcc_usb_hsic_mock_utmi_clk.clkr,
2777 [GCC_USB_HSIC_SYSTEM_CLK] = &gcc_usb_hsic_system_clk.clkr,
2780 static const struct qcom_reset_map gcc_apq8084_resets[] = {
2781 [GCC_SYSTEM_NOC_BCR] = { 0x0100 },
2782 [GCC_CONFIG_NOC_BCR] = { 0x0140 },
2783 [GCC_PERIPH_NOC_BCR] = { 0x0180 },
2784 [GCC_IMEM_BCR] = { 0x0200 },
2785 [GCC_MMSS_BCR] = { 0x0240 },
2786 [GCC_QDSS_BCR] = { 0x0300 },
2787 [GCC_USB_30_BCR] = { 0x03c0 },
2788 [GCC_USB3_PHY_BCR] = { 0x03fc },
2789 [GCC_USB_HS_HSIC_BCR] = { 0x0400 },
2790 [GCC_USB_HS_BCR] = { 0x0480 },
2791 [GCC_USB2A_PHY_BCR] = { 0x04a8 },
2792 [GCC_USB2B_PHY_BCR] = { 0x04b0 },
2793 [GCC_SDCC1_BCR] = { 0x04c0 },
2794 [GCC_SDCC2_BCR] = { 0x0500 },
2795 [GCC_SDCC3_BCR] = { 0x0540 },
2796 [GCC_SDCC4_BCR] = { 0x0580 },
2797 [GCC_BLSP1_BCR] = { 0x05c0 },
2798 [GCC_BLSP1_QUP1_BCR] = { 0x0640 },
2799 [GCC_BLSP1_UART1_BCR] = { 0x0680 },
2800 [GCC_BLSP1_QUP2_BCR] = { 0x06c0 },
2801 [GCC_BLSP1_UART2_BCR] = { 0x0700 },
2802 [GCC_BLSP1_QUP3_BCR] = { 0x0740 },
2803 [GCC_BLSP1_UART3_BCR] = { 0x0780 },
2804 [GCC_BLSP1_QUP4_BCR] = { 0x07c0 },
2805 [GCC_BLSP1_UART4_BCR] = { 0x0800 },
2806 [GCC_BLSP1_QUP5_BCR] = { 0x0840 },
2807 [GCC_BLSP1_UART5_BCR] = { 0x0880 },
2808 [GCC_BLSP1_QUP6_BCR] = { 0x08c0 },
2809 [GCC_BLSP1_UART6_BCR] = { 0x0900 },
2810 [GCC_BLSP2_BCR] = { 0x0940 },
2811 [GCC_BLSP2_QUP1_BCR] = { 0x0980 },
2812 [GCC_BLSP2_UART1_BCR] = { 0x09c0 },
2813 [GCC_BLSP2_QUP2_BCR] = { 0x0a00 },
2814 [GCC_BLSP2_UART2_BCR] = { 0x0a40 },
2815 [GCC_BLSP2_QUP3_BCR] = { 0x0a80 },
2816 [GCC_BLSP2_UART3_BCR] = { 0x0ac0 },
2817 [GCC_BLSP2_QUP4_BCR] = { 0x0b00 },
2818 [GCC_BLSP2_UART4_BCR] = { 0x0b40 },
2819 [GCC_BLSP2_QUP5_BCR] = { 0x0b80 },
2820 [GCC_BLSP2_UART5_BCR] = { 0x0bc0 },
2821 [GCC_BLSP2_QUP6_BCR] = { 0x0c00 },
2822 [GCC_BLSP2_UART6_BCR] = { 0x0c40 },
2823 [GCC_PDM_BCR] = { 0x0cc0 },
2824 [GCC_PRNG_BCR] = { 0x0d00 },
2825 [GCC_BAM_DMA_BCR] = { 0x0d40 },
2826 [GCC_TSIF_BCR] = { 0x0d80 },
2827 [GCC_TCSR_BCR] = { 0x0dc0 },
2828 [GCC_BOOT_ROM_BCR] = { 0x0e00 },
2829 [GCC_MSG_RAM_BCR] = { 0x0e40 },
2830 [GCC_TLMM_BCR] = { 0x0e80 },
2831 [GCC_MPM_BCR] = { 0x0ec0 },
2832 [GCC_MPM_AHB_RESET] = { 0x0ec4, 1 },
2833 [GCC_MPM_NON_AHB_RESET] = { 0x0ec4, 2 },
2834 [GCC_SEC_CTRL_BCR] = { 0x0f40 },
2835 [GCC_SPMI_BCR] = { 0x0fc0 },
2836 [GCC_SPDM_BCR] = { 0x1000 },
2837 [GCC_CE1_BCR] = { 0x1040 },
2838 [GCC_CE2_BCR] = { 0x1080 },
2839 [GCC_BIMC_BCR] = { 0x1100 },
2840 [GCC_SNOC_BUS_TIMEOUT0_BCR] = { 0x1240 },
2841 [GCC_SNOC_BUS_TIMEOUT2_BCR] = { 0x1248 },
2842 [GCC_PNOC_BUS_TIMEOUT0_BCR] = { 0x1280 },
2843 [GCC_PNOC_BUS_TIMEOUT1_BCR] = { 0x1288 },
2844 [GCC_PNOC_BUS_TIMEOUT2_BCR] = { 0x1290 },
2845 [GCC_PNOC_BUS_TIMEOUT3_BCR] = { 0x1298 },
2846 [GCC_PNOC_BUS_TIMEOUT4_BCR] = { 0x12a0 },
2847 [GCC_CNOC_BUS_TIMEOUT0_BCR] = { 0x12c0 },
2848 [GCC_CNOC_BUS_TIMEOUT1_BCR] = { 0x12c8 },
2849 [GCC_CNOC_BUS_TIMEOUT2_BCR] = { 0x12d0 },
2850 [GCC_CNOC_BUS_TIMEOUT3_BCR] = { 0x12d8 },
2851 [GCC_CNOC_BUS_TIMEOUT4_BCR] = { 0x12e0 },
2852 [GCC_CNOC_BUS_TIMEOUT5_BCR] = { 0x12e8 },
2853 [GCC_CNOC_BUS_TIMEOUT6_BCR] = { 0x12f0 },
2854 [GCC_DEHR_BCR] = { 0x1300 },
2855 [GCC_RBCPR_BCR] = { 0x1380 },
2856 [GCC_MSS_RESTART] = { 0x1680 },
2857 [GCC_LPASS_RESTART] = { 0x16c0 },
2858 [GCC_WCSS_RESTART] = { 0x1700 },
2859 [GCC_VENUS_RESTART] = { 0x1740 },
2860 [GCC_COPSS_SMMU_BCR] = { 0x1a40 },
2861 [GCC_SPSS_BCR] = { 0x1a80 },
2862 [GCC_PCIE_0_BCR] = { 0x1ac0 },
2863 [GCC_PCIE_0_PHY_BCR] = { 0x1b00 },
2864 [GCC_PCIE_1_BCR] = { 0x1b40 },
2865 [GCC_PCIE_1_PHY_BCR] = { 0x1b80 },
2866 [GCC_USB_30_SEC_BCR] = { 0x1bc0 },
2867 [GCC_USB3_SEC_PHY_BCR] = { 0x1bfc },
2868 [GCC_SATA_BCR] = { 0x1c40 },
2869 [GCC_CE3_BCR] = { 0x1d00 },
2870 [GCC_UFS_BCR] = { 0x1d40 },
2871 [GCC_USB30_PHY_COM_BCR] = { 0x1e80 },
2874 static const struct regmap_config gcc_apq8084_regmap_config = {
2878 .max_register = 0x1fc0,
2882 static const struct qcom_cc_desc gcc_apq8084_desc = {
2883 .config = &gcc_apq8084_regmap_config,
2884 .clks = gcc_apq8084_clocks,
2885 .num_clks = ARRAY_SIZE(gcc_apq8084_clocks),
2886 .resets = gcc_apq8084_resets,
2887 .num_resets = ARRAY_SIZE(gcc_apq8084_resets),
2890 static const struct of_device_id gcc_apq8084_match_table[] = {
2891 { .compatible = "qcom,gcc-apq8084" },
2894 MODULE_DEVICE_TABLE(of, gcc_apq8084_match_table);
2896 static int gcc_apq8084_probe(struct platform_device *pdev)
2899 struct device *dev = &pdev->dev;
2901 /* Temporary until RPM clocks supported */
2902 clk = clk_register_fixed_rate(dev, "xo", NULL, CLK_IS_ROOT, 19200000);
2904 return PTR_ERR(clk);
2906 clk = clk_register_fixed_rate(dev, "sleep_clk_src", NULL,
2907 CLK_IS_ROOT, 32768);
2909 return PTR_ERR(clk);
2911 return qcom_cc_probe(pdev, &gcc_apq8084_desc);
2914 static int gcc_apq8084_remove(struct platform_device *pdev)
2916 qcom_cc_remove(pdev);
2920 static struct platform_driver gcc_apq8084_driver = {
2921 .probe = gcc_apq8084_probe,
2922 .remove = gcc_apq8084_remove,
2924 .name = "gcc-apq8084",
2925 .owner = THIS_MODULE,
2926 .of_match_table = gcc_apq8084_match_table,
2930 static int __init gcc_apq8084_init(void)
2932 return platform_driver_register(&gcc_apq8084_driver);
2934 core_initcall(gcc_apq8084_init);
2936 static void __exit gcc_apq8084_exit(void)
2938 platform_driver_unregister(&gcc_apq8084_driver);
2940 module_exit(gcc_apq8084_exit);
2942 MODULE_DESCRIPTION("QCOM GCC APQ8084 Driver");
2943 MODULE_LICENSE("GPL v2");
2944 MODULE_ALIAS("platform:gcc-apq8084");