2 * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
14 #include <linux/kernel.h>
15 #include <linux/bitops.h>
16 #include <linux/err.h>
17 #include <linux/platform_device.h>
18 #include <linux/module.h>
20 #include <linux/of_device.h>
21 #include <linux/clk-provider.h>
22 #include <linux/regmap.h>
23 #include <linux/reset-controller.h>
25 #include <dt-bindings/clock/qcom,gcc-msm8960.h>
26 #include <dt-bindings/reset/qcom,gcc-msm8960.h>
29 #include "clk-regmap.h"
32 #include "clk-branch.h"
35 static struct clk_pll pll3 = {
43 .clkr.hw.init = &(struct clk_init_data){
45 .parent_names = (const char *[]){ "pxo" },
51 static struct clk_pll pll8 = {
59 .clkr.hw.init = &(struct clk_init_data){
61 .parent_names = (const char *[]){ "pxo" },
67 static struct clk_regmap pll8_vote = {
69 .enable_mask = BIT(8),
70 .hw.init = &(struct clk_init_data){
72 .parent_names = (const char *[]){ "pll8" },
74 .ops = &clk_pll_vote_ops,
78 static struct clk_pll pll14 = {
86 .clkr.hw.init = &(struct clk_init_data){
88 .parent_names = (const char *[]){ "pxo" },
94 static struct clk_regmap pll14_vote = {
96 .enable_mask = BIT(14),
97 .hw.init = &(struct clk_init_data){
99 .parent_names = (const char *[]){ "pll14" },
101 .ops = &clk_pll_vote_ops,
110 static const u8 gcc_pxo_pll8_map[] = {
115 static const char *gcc_pxo_pll8[] = {
120 static const u8 gcc_pxo_pll8_cxo_map[] = {
126 static const char *gcc_pxo_pll8_cxo[] = {
132 static const u8 gcc_pxo_pll8_pll3_map[] = {
138 static const char *gcc_pxo_pll8_pll3[] = {
144 static struct freq_tbl clk_tbl_gsbi_uart[] = {
145 { 1843200, P_PLL8, 2, 6, 625 },
146 { 3686400, P_PLL8, 2, 12, 625 },
147 { 7372800, P_PLL8, 2, 24, 625 },
148 { 14745600, P_PLL8, 2, 48, 625 },
149 { 16000000, P_PLL8, 4, 1, 6 },
150 { 24000000, P_PLL8, 4, 1, 4 },
151 { 32000000, P_PLL8, 4, 1, 3 },
152 { 40000000, P_PLL8, 1, 5, 48 },
153 { 46400000, P_PLL8, 1, 29, 240 },
154 { 48000000, P_PLL8, 4, 1, 2 },
155 { 51200000, P_PLL8, 1, 2, 15 },
156 { 56000000, P_PLL8, 1, 7, 48 },
157 { 58982400, P_PLL8, 1, 96, 625 },
158 { 64000000, P_PLL8, 2, 1, 3 },
162 static struct clk_rcg gsbi1_uart_src = {
167 .mnctr_reset_bit = 7,
168 .mnctr_mode_shift = 5,
179 .parent_map = gcc_pxo_pll8_map,
181 .freq_tbl = clk_tbl_gsbi_uart,
183 .enable_reg = 0x29d4,
184 .enable_mask = BIT(11),
185 .hw.init = &(struct clk_init_data){
186 .name = "gsbi1_uart_src",
187 .parent_names = gcc_pxo_pll8,
190 .flags = CLK_SET_PARENT_GATE,
195 static struct clk_branch gsbi1_uart_clk = {
199 .enable_reg = 0x29d4,
200 .enable_mask = BIT(9),
201 .hw.init = &(struct clk_init_data){
202 .name = "gsbi1_uart_clk",
203 .parent_names = (const char *[]){
207 .ops = &clk_branch_ops,
208 .flags = CLK_SET_RATE_PARENT,
213 static struct clk_rcg gsbi2_uart_src = {
218 .mnctr_reset_bit = 7,
219 .mnctr_mode_shift = 5,
230 .parent_map = gcc_pxo_pll8_map,
232 .freq_tbl = clk_tbl_gsbi_uart,
234 .enable_reg = 0x29f4,
235 .enable_mask = BIT(11),
236 .hw.init = &(struct clk_init_data){
237 .name = "gsbi2_uart_src",
238 .parent_names = gcc_pxo_pll8,
241 .flags = CLK_SET_PARENT_GATE,
246 static struct clk_branch gsbi2_uart_clk = {
250 .enable_reg = 0x29f4,
251 .enable_mask = BIT(9),
252 .hw.init = &(struct clk_init_data){
253 .name = "gsbi2_uart_clk",
254 .parent_names = (const char *[]){
258 .ops = &clk_branch_ops,
259 .flags = CLK_SET_RATE_PARENT,
264 static struct clk_rcg gsbi3_uart_src = {
269 .mnctr_reset_bit = 7,
270 .mnctr_mode_shift = 5,
281 .parent_map = gcc_pxo_pll8_map,
283 .freq_tbl = clk_tbl_gsbi_uart,
285 .enable_reg = 0x2a14,
286 .enable_mask = BIT(11),
287 .hw.init = &(struct clk_init_data){
288 .name = "gsbi3_uart_src",
289 .parent_names = gcc_pxo_pll8,
292 .flags = CLK_SET_PARENT_GATE,
297 static struct clk_branch gsbi3_uart_clk = {
301 .enable_reg = 0x2a14,
302 .enable_mask = BIT(9),
303 .hw.init = &(struct clk_init_data){
304 .name = "gsbi3_uart_clk",
305 .parent_names = (const char *[]){
309 .ops = &clk_branch_ops,
310 .flags = CLK_SET_RATE_PARENT,
315 static struct clk_rcg gsbi4_uart_src = {
320 .mnctr_reset_bit = 7,
321 .mnctr_mode_shift = 5,
332 .parent_map = gcc_pxo_pll8_map,
334 .freq_tbl = clk_tbl_gsbi_uart,
336 .enable_reg = 0x2a34,
337 .enable_mask = BIT(11),
338 .hw.init = &(struct clk_init_data){
339 .name = "gsbi4_uart_src",
340 .parent_names = gcc_pxo_pll8,
343 .flags = CLK_SET_PARENT_GATE,
348 static struct clk_branch gsbi4_uart_clk = {
352 .enable_reg = 0x2a34,
353 .enable_mask = BIT(9),
354 .hw.init = &(struct clk_init_data){
355 .name = "gsbi4_uart_clk",
356 .parent_names = (const char *[]){
360 .ops = &clk_branch_ops,
361 .flags = CLK_SET_RATE_PARENT,
366 static struct clk_rcg gsbi5_uart_src = {
371 .mnctr_reset_bit = 7,
372 .mnctr_mode_shift = 5,
383 .parent_map = gcc_pxo_pll8_map,
385 .freq_tbl = clk_tbl_gsbi_uart,
387 .enable_reg = 0x2a54,
388 .enable_mask = BIT(11),
389 .hw.init = &(struct clk_init_data){
390 .name = "gsbi5_uart_src",
391 .parent_names = gcc_pxo_pll8,
394 .flags = CLK_SET_PARENT_GATE,
399 static struct clk_branch gsbi5_uart_clk = {
403 .enable_reg = 0x2a54,
404 .enable_mask = BIT(9),
405 .hw.init = &(struct clk_init_data){
406 .name = "gsbi5_uart_clk",
407 .parent_names = (const char *[]){
411 .ops = &clk_branch_ops,
412 .flags = CLK_SET_RATE_PARENT,
417 static struct clk_rcg gsbi6_uart_src = {
422 .mnctr_reset_bit = 7,
423 .mnctr_mode_shift = 5,
434 .parent_map = gcc_pxo_pll8_map,
436 .freq_tbl = clk_tbl_gsbi_uart,
438 .enable_reg = 0x2a74,
439 .enable_mask = BIT(11),
440 .hw.init = &(struct clk_init_data){
441 .name = "gsbi6_uart_src",
442 .parent_names = gcc_pxo_pll8,
445 .flags = CLK_SET_PARENT_GATE,
450 static struct clk_branch gsbi6_uart_clk = {
454 .enable_reg = 0x2a74,
455 .enable_mask = BIT(9),
456 .hw.init = &(struct clk_init_data){
457 .name = "gsbi6_uart_clk",
458 .parent_names = (const char *[]){
462 .ops = &clk_branch_ops,
463 .flags = CLK_SET_RATE_PARENT,
468 static struct clk_rcg gsbi7_uart_src = {
473 .mnctr_reset_bit = 7,
474 .mnctr_mode_shift = 5,
485 .parent_map = gcc_pxo_pll8_map,
487 .freq_tbl = clk_tbl_gsbi_uart,
489 .enable_reg = 0x2a94,
490 .enable_mask = BIT(11),
491 .hw.init = &(struct clk_init_data){
492 .name = "gsbi7_uart_src",
493 .parent_names = gcc_pxo_pll8,
496 .flags = CLK_SET_PARENT_GATE,
501 static struct clk_branch gsbi7_uart_clk = {
505 .enable_reg = 0x2a94,
506 .enable_mask = BIT(9),
507 .hw.init = &(struct clk_init_data){
508 .name = "gsbi7_uart_clk",
509 .parent_names = (const char *[]){
513 .ops = &clk_branch_ops,
514 .flags = CLK_SET_RATE_PARENT,
519 static struct clk_rcg gsbi8_uart_src = {
524 .mnctr_reset_bit = 7,
525 .mnctr_mode_shift = 5,
536 .parent_map = gcc_pxo_pll8_map,
538 .freq_tbl = clk_tbl_gsbi_uart,
540 .enable_reg = 0x2ab4,
541 .enable_mask = BIT(11),
542 .hw.init = &(struct clk_init_data){
543 .name = "gsbi8_uart_src",
544 .parent_names = gcc_pxo_pll8,
547 .flags = CLK_SET_PARENT_GATE,
552 static struct clk_branch gsbi8_uart_clk = {
556 .enable_reg = 0x2ab4,
557 .enable_mask = BIT(9),
558 .hw.init = &(struct clk_init_data){
559 .name = "gsbi8_uart_clk",
560 .parent_names = (const char *[]){ "gsbi8_uart_src" },
562 .ops = &clk_branch_ops,
563 .flags = CLK_SET_RATE_PARENT,
568 static struct clk_rcg gsbi9_uart_src = {
573 .mnctr_reset_bit = 7,
574 .mnctr_mode_shift = 5,
585 .parent_map = gcc_pxo_pll8_map,
587 .freq_tbl = clk_tbl_gsbi_uart,
589 .enable_reg = 0x2ad4,
590 .enable_mask = BIT(11),
591 .hw.init = &(struct clk_init_data){
592 .name = "gsbi9_uart_src",
593 .parent_names = gcc_pxo_pll8,
596 .flags = CLK_SET_PARENT_GATE,
601 static struct clk_branch gsbi9_uart_clk = {
605 .enable_reg = 0x2ad4,
606 .enable_mask = BIT(9),
607 .hw.init = &(struct clk_init_data){
608 .name = "gsbi9_uart_clk",
609 .parent_names = (const char *[]){ "gsbi9_uart_src" },
611 .ops = &clk_branch_ops,
612 .flags = CLK_SET_RATE_PARENT,
617 static struct clk_rcg gsbi10_uart_src = {
622 .mnctr_reset_bit = 7,
623 .mnctr_mode_shift = 5,
634 .parent_map = gcc_pxo_pll8_map,
636 .freq_tbl = clk_tbl_gsbi_uart,
638 .enable_reg = 0x2af4,
639 .enable_mask = BIT(11),
640 .hw.init = &(struct clk_init_data){
641 .name = "gsbi10_uart_src",
642 .parent_names = gcc_pxo_pll8,
645 .flags = CLK_SET_PARENT_GATE,
650 static struct clk_branch gsbi10_uart_clk = {
654 .enable_reg = 0x2af4,
655 .enable_mask = BIT(9),
656 .hw.init = &(struct clk_init_data){
657 .name = "gsbi10_uart_clk",
658 .parent_names = (const char *[]){ "gsbi10_uart_src" },
660 .ops = &clk_branch_ops,
661 .flags = CLK_SET_RATE_PARENT,
666 static struct clk_rcg gsbi11_uart_src = {
671 .mnctr_reset_bit = 7,
672 .mnctr_mode_shift = 5,
683 .parent_map = gcc_pxo_pll8_map,
685 .freq_tbl = clk_tbl_gsbi_uart,
687 .enable_reg = 0x2b14,
688 .enable_mask = BIT(11),
689 .hw.init = &(struct clk_init_data){
690 .name = "gsbi11_uart_src",
691 .parent_names = gcc_pxo_pll8,
694 .flags = CLK_SET_PARENT_GATE,
699 static struct clk_branch gsbi11_uart_clk = {
703 .enable_reg = 0x2b14,
704 .enable_mask = BIT(9),
705 .hw.init = &(struct clk_init_data){
706 .name = "gsbi11_uart_clk",
707 .parent_names = (const char *[]){ "gsbi11_uart_src" },
709 .ops = &clk_branch_ops,
710 .flags = CLK_SET_RATE_PARENT,
715 static struct clk_rcg gsbi12_uart_src = {
720 .mnctr_reset_bit = 7,
721 .mnctr_mode_shift = 5,
732 .parent_map = gcc_pxo_pll8_map,
734 .freq_tbl = clk_tbl_gsbi_uart,
736 .enable_reg = 0x2b34,
737 .enable_mask = BIT(11),
738 .hw.init = &(struct clk_init_data){
739 .name = "gsbi12_uart_src",
740 .parent_names = gcc_pxo_pll8,
743 .flags = CLK_SET_PARENT_GATE,
748 static struct clk_branch gsbi12_uart_clk = {
752 .enable_reg = 0x2b34,
753 .enable_mask = BIT(9),
754 .hw.init = &(struct clk_init_data){
755 .name = "gsbi12_uart_clk",
756 .parent_names = (const char *[]){ "gsbi12_uart_src" },
758 .ops = &clk_branch_ops,
759 .flags = CLK_SET_RATE_PARENT,
764 static struct freq_tbl clk_tbl_gsbi_qup[] = {
765 { 1100000, P_PXO, 1, 2, 49 },
766 { 5400000, P_PXO, 1, 1, 5 },
767 { 10800000, P_PXO, 1, 2, 5 },
768 { 15060000, P_PLL8, 1, 2, 51 },
769 { 24000000, P_PLL8, 4, 1, 4 },
770 { 25600000, P_PLL8, 1, 1, 15 },
771 { 27000000, P_PXO, 1, 0, 0 },
772 { 48000000, P_PLL8, 4, 1, 2 },
773 { 51200000, P_PLL8, 1, 2, 15 },
777 static struct clk_rcg gsbi1_qup_src = {
782 .mnctr_reset_bit = 7,
783 .mnctr_mode_shift = 5,
794 .parent_map = gcc_pxo_pll8_map,
796 .freq_tbl = clk_tbl_gsbi_qup,
798 .enable_reg = 0x29cc,
799 .enable_mask = BIT(11),
800 .hw.init = &(struct clk_init_data){
801 .name = "gsbi1_qup_src",
802 .parent_names = gcc_pxo_pll8,
805 .flags = CLK_SET_PARENT_GATE,
810 static struct clk_branch gsbi1_qup_clk = {
814 .enable_reg = 0x29cc,
815 .enable_mask = BIT(9),
816 .hw.init = &(struct clk_init_data){
817 .name = "gsbi1_qup_clk",
818 .parent_names = (const char *[]){ "gsbi1_qup_src" },
820 .ops = &clk_branch_ops,
821 .flags = CLK_SET_RATE_PARENT,
826 static struct clk_rcg gsbi2_qup_src = {
831 .mnctr_reset_bit = 7,
832 .mnctr_mode_shift = 5,
843 .parent_map = gcc_pxo_pll8_map,
845 .freq_tbl = clk_tbl_gsbi_qup,
847 .enable_reg = 0x29ec,
848 .enable_mask = BIT(11),
849 .hw.init = &(struct clk_init_data){
850 .name = "gsbi2_qup_src",
851 .parent_names = gcc_pxo_pll8,
854 .flags = CLK_SET_PARENT_GATE,
859 static struct clk_branch gsbi2_qup_clk = {
863 .enable_reg = 0x29ec,
864 .enable_mask = BIT(9),
865 .hw.init = &(struct clk_init_data){
866 .name = "gsbi2_qup_clk",
867 .parent_names = (const char *[]){ "gsbi2_qup_src" },
869 .ops = &clk_branch_ops,
870 .flags = CLK_SET_RATE_PARENT,
875 static struct clk_rcg gsbi3_qup_src = {
880 .mnctr_reset_bit = 7,
881 .mnctr_mode_shift = 5,
892 .parent_map = gcc_pxo_pll8_map,
894 .freq_tbl = clk_tbl_gsbi_qup,
896 .enable_reg = 0x2a0c,
897 .enable_mask = BIT(11),
898 .hw.init = &(struct clk_init_data){
899 .name = "gsbi3_qup_src",
900 .parent_names = gcc_pxo_pll8,
903 .flags = CLK_SET_PARENT_GATE,
908 static struct clk_branch gsbi3_qup_clk = {
912 .enable_reg = 0x2a0c,
913 .enable_mask = BIT(9),
914 .hw.init = &(struct clk_init_data){
915 .name = "gsbi3_qup_clk",
916 .parent_names = (const char *[]){ "gsbi3_qup_src" },
918 .ops = &clk_branch_ops,
919 .flags = CLK_SET_RATE_PARENT,
924 static struct clk_rcg gsbi4_qup_src = {
929 .mnctr_reset_bit = 7,
930 .mnctr_mode_shift = 5,
941 .parent_map = gcc_pxo_pll8_map,
943 .freq_tbl = clk_tbl_gsbi_qup,
945 .enable_reg = 0x2a2c,
946 .enable_mask = BIT(11),
947 .hw.init = &(struct clk_init_data){
948 .name = "gsbi4_qup_src",
949 .parent_names = gcc_pxo_pll8,
952 .flags = CLK_SET_PARENT_GATE,
957 static struct clk_branch gsbi4_qup_clk = {
961 .enable_reg = 0x2a2c,
962 .enable_mask = BIT(9),
963 .hw.init = &(struct clk_init_data){
964 .name = "gsbi4_qup_clk",
965 .parent_names = (const char *[]){ "gsbi4_qup_src" },
967 .ops = &clk_branch_ops,
968 .flags = CLK_SET_RATE_PARENT,
973 static struct clk_rcg gsbi5_qup_src = {
978 .mnctr_reset_bit = 7,
979 .mnctr_mode_shift = 5,
990 .parent_map = gcc_pxo_pll8_map,
992 .freq_tbl = clk_tbl_gsbi_qup,
994 .enable_reg = 0x2a4c,
995 .enable_mask = BIT(11),
996 .hw.init = &(struct clk_init_data){
997 .name = "gsbi5_qup_src",
998 .parent_names = gcc_pxo_pll8,
1000 .ops = &clk_rcg_ops,
1001 .flags = CLK_SET_PARENT_GATE,
1006 static struct clk_branch gsbi5_qup_clk = {
1010 .enable_reg = 0x2a4c,
1011 .enable_mask = BIT(9),
1012 .hw.init = &(struct clk_init_data){
1013 .name = "gsbi5_qup_clk",
1014 .parent_names = (const char *[]){ "gsbi5_qup_src" },
1016 .ops = &clk_branch_ops,
1017 .flags = CLK_SET_RATE_PARENT,
1022 static struct clk_rcg gsbi6_qup_src = {
1027 .mnctr_reset_bit = 7,
1028 .mnctr_mode_shift = 5,
1039 .parent_map = gcc_pxo_pll8_map,
1041 .freq_tbl = clk_tbl_gsbi_qup,
1043 .enable_reg = 0x2a6c,
1044 .enable_mask = BIT(11),
1045 .hw.init = &(struct clk_init_data){
1046 .name = "gsbi6_qup_src",
1047 .parent_names = gcc_pxo_pll8,
1049 .ops = &clk_rcg_ops,
1050 .flags = CLK_SET_PARENT_GATE,
1055 static struct clk_branch gsbi6_qup_clk = {
1059 .enable_reg = 0x2a6c,
1060 .enable_mask = BIT(9),
1061 .hw.init = &(struct clk_init_data){
1062 .name = "gsbi6_qup_clk",
1063 .parent_names = (const char *[]){ "gsbi6_qup_src" },
1065 .ops = &clk_branch_ops,
1066 .flags = CLK_SET_RATE_PARENT,
1071 static struct clk_rcg gsbi7_qup_src = {
1076 .mnctr_reset_bit = 7,
1077 .mnctr_mode_shift = 5,
1088 .parent_map = gcc_pxo_pll8_map,
1090 .freq_tbl = clk_tbl_gsbi_qup,
1092 .enable_reg = 0x2a8c,
1093 .enable_mask = BIT(11),
1094 .hw.init = &(struct clk_init_data){
1095 .name = "gsbi7_qup_src",
1096 .parent_names = gcc_pxo_pll8,
1098 .ops = &clk_rcg_ops,
1099 .flags = CLK_SET_PARENT_GATE,
1104 static struct clk_branch gsbi7_qup_clk = {
1108 .enable_reg = 0x2a8c,
1109 .enable_mask = BIT(9),
1110 .hw.init = &(struct clk_init_data){
1111 .name = "gsbi7_qup_clk",
1112 .parent_names = (const char *[]){ "gsbi7_qup_src" },
1114 .ops = &clk_branch_ops,
1115 .flags = CLK_SET_RATE_PARENT,
1120 static struct clk_rcg gsbi8_qup_src = {
1125 .mnctr_reset_bit = 7,
1126 .mnctr_mode_shift = 5,
1137 .parent_map = gcc_pxo_pll8_map,
1139 .freq_tbl = clk_tbl_gsbi_qup,
1141 .enable_reg = 0x2aac,
1142 .enable_mask = BIT(11),
1143 .hw.init = &(struct clk_init_data){
1144 .name = "gsbi8_qup_src",
1145 .parent_names = gcc_pxo_pll8,
1147 .ops = &clk_rcg_ops,
1148 .flags = CLK_SET_PARENT_GATE,
1153 static struct clk_branch gsbi8_qup_clk = {
1157 .enable_reg = 0x2aac,
1158 .enable_mask = BIT(9),
1159 .hw.init = &(struct clk_init_data){
1160 .name = "gsbi8_qup_clk",
1161 .parent_names = (const char *[]){ "gsbi8_qup_src" },
1163 .ops = &clk_branch_ops,
1164 .flags = CLK_SET_RATE_PARENT,
1169 static struct clk_rcg gsbi9_qup_src = {
1174 .mnctr_reset_bit = 7,
1175 .mnctr_mode_shift = 5,
1186 .parent_map = gcc_pxo_pll8_map,
1188 .freq_tbl = clk_tbl_gsbi_qup,
1190 .enable_reg = 0x2acc,
1191 .enable_mask = BIT(11),
1192 .hw.init = &(struct clk_init_data){
1193 .name = "gsbi9_qup_src",
1194 .parent_names = gcc_pxo_pll8,
1196 .ops = &clk_rcg_ops,
1197 .flags = CLK_SET_PARENT_GATE,
1202 static struct clk_branch gsbi9_qup_clk = {
1206 .enable_reg = 0x2acc,
1207 .enable_mask = BIT(9),
1208 .hw.init = &(struct clk_init_data){
1209 .name = "gsbi9_qup_clk",
1210 .parent_names = (const char *[]){ "gsbi9_qup_src" },
1212 .ops = &clk_branch_ops,
1213 .flags = CLK_SET_RATE_PARENT,
1218 static struct clk_rcg gsbi10_qup_src = {
1223 .mnctr_reset_bit = 7,
1224 .mnctr_mode_shift = 5,
1235 .parent_map = gcc_pxo_pll8_map,
1237 .freq_tbl = clk_tbl_gsbi_qup,
1239 .enable_reg = 0x2aec,
1240 .enable_mask = BIT(11),
1241 .hw.init = &(struct clk_init_data){
1242 .name = "gsbi10_qup_src",
1243 .parent_names = gcc_pxo_pll8,
1245 .ops = &clk_rcg_ops,
1246 .flags = CLK_SET_PARENT_GATE,
1251 static struct clk_branch gsbi10_qup_clk = {
1255 .enable_reg = 0x2aec,
1256 .enable_mask = BIT(9),
1257 .hw.init = &(struct clk_init_data){
1258 .name = "gsbi10_qup_clk",
1259 .parent_names = (const char *[]){ "gsbi10_qup_src" },
1261 .ops = &clk_branch_ops,
1262 .flags = CLK_SET_RATE_PARENT,
1267 static struct clk_rcg gsbi11_qup_src = {
1272 .mnctr_reset_bit = 7,
1273 .mnctr_mode_shift = 5,
1284 .parent_map = gcc_pxo_pll8_map,
1286 .freq_tbl = clk_tbl_gsbi_qup,
1288 .enable_reg = 0x2b0c,
1289 .enable_mask = BIT(11),
1290 .hw.init = &(struct clk_init_data){
1291 .name = "gsbi11_qup_src",
1292 .parent_names = gcc_pxo_pll8,
1294 .ops = &clk_rcg_ops,
1295 .flags = CLK_SET_PARENT_GATE,
1300 static struct clk_branch gsbi11_qup_clk = {
1304 .enable_reg = 0x2b0c,
1305 .enable_mask = BIT(9),
1306 .hw.init = &(struct clk_init_data){
1307 .name = "gsbi11_qup_clk",
1308 .parent_names = (const char *[]){ "gsbi11_qup_src" },
1310 .ops = &clk_branch_ops,
1311 .flags = CLK_SET_RATE_PARENT,
1316 static struct clk_rcg gsbi12_qup_src = {
1321 .mnctr_reset_bit = 7,
1322 .mnctr_mode_shift = 5,
1333 .parent_map = gcc_pxo_pll8_map,
1335 .freq_tbl = clk_tbl_gsbi_qup,
1337 .enable_reg = 0x2b2c,
1338 .enable_mask = BIT(11),
1339 .hw.init = &(struct clk_init_data){
1340 .name = "gsbi12_qup_src",
1341 .parent_names = gcc_pxo_pll8,
1343 .ops = &clk_rcg_ops,
1344 .flags = CLK_SET_PARENT_GATE,
1349 static struct clk_branch gsbi12_qup_clk = {
1353 .enable_reg = 0x2b2c,
1354 .enable_mask = BIT(9),
1355 .hw.init = &(struct clk_init_data){
1356 .name = "gsbi12_qup_clk",
1357 .parent_names = (const char *[]){ "gsbi12_qup_src" },
1359 .ops = &clk_branch_ops,
1360 .flags = CLK_SET_RATE_PARENT,
1365 static const struct freq_tbl clk_tbl_gp[] = {
1366 { 9600000, P_CXO, 2, 0, 0 },
1367 { 13500000, P_PXO, 2, 0, 0 },
1368 { 19200000, P_CXO, 1, 0, 0 },
1369 { 27000000, P_PXO, 1, 0, 0 },
1370 { 64000000, P_PLL8, 2, 1, 3 },
1371 { 76800000, P_PLL8, 1, 1, 5 },
1372 { 96000000, P_PLL8, 4, 0, 0 },
1373 { 128000000, P_PLL8, 3, 0, 0 },
1374 { 192000000, P_PLL8, 2, 0, 0 },
1378 static struct clk_rcg gp0_src = {
1383 .mnctr_reset_bit = 7,
1384 .mnctr_mode_shift = 5,
1395 .parent_map = gcc_pxo_pll8_cxo_map,
1397 .freq_tbl = clk_tbl_gp,
1399 .enable_reg = 0x2d24,
1400 .enable_mask = BIT(11),
1401 .hw.init = &(struct clk_init_data){
1403 .parent_names = gcc_pxo_pll8_cxo,
1405 .ops = &clk_rcg_ops,
1406 .flags = CLK_SET_PARENT_GATE,
1411 static struct clk_branch gp0_clk = {
1415 .enable_reg = 0x2d24,
1416 .enable_mask = BIT(9),
1417 .hw.init = &(struct clk_init_data){
1419 .parent_names = (const char *[]){ "gp0_src" },
1421 .ops = &clk_branch_ops,
1422 .flags = CLK_SET_RATE_PARENT,
1427 static struct clk_rcg gp1_src = {
1432 .mnctr_reset_bit = 7,
1433 .mnctr_mode_shift = 5,
1444 .parent_map = gcc_pxo_pll8_cxo_map,
1446 .freq_tbl = clk_tbl_gp,
1448 .enable_reg = 0x2d44,
1449 .enable_mask = BIT(11),
1450 .hw.init = &(struct clk_init_data){
1452 .parent_names = gcc_pxo_pll8_cxo,
1454 .ops = &clk_rcg_ops,
1455 .flags = CLK_SET_RATE_GATE,
1460 static struct clk_branch gp1_clk = {
1464 .enable_reg = 0x2d44,
1465 .enable_mask = BIT(9),
1466 .hw.init = &(struct clk_init_data){
1468 .parent_names = (const char *[]){ "gp1_src" },
1470 .ops = &clk_branch_ops,
1471 .flags = CLK_SET_RATE_PARENT,
1476 static struct clk_rcg gp2_src = {
1481 .mnctr_reset_bit = 7,
1482 .mnctr_mode_shift = 5,
1493 .parent_map = gcc_pxo_pll8_cxo_map,
1495 .freq_tbl = clk_tbl_gp,
1497 .enable_reg = 0x2d64,
1498 .enable_mask = BIT(11),
1499 .hw.init = &(struct clk_init_data){
1501 .parent_names = gcc_pxo_pll8_cxo,
1503 .ops = &clk_rcg_ops,
1504 .flags = CLK_SET_RATE_GATE,
1509 static struct clk_branch gp2_clk = {
1513 .enable_reg = 0x2d64,
1514 .enable_mask = BIT(9),
1515 .hw.init = &(struct clk_init_data){
1517 .parent_names = (const char *[]){ "gp2_src" },
1519 .ops = &clk_branch_ops,
1520 .flags = CLK_SET_RATE_PARENT,
1525 static struct clk_branch pmem_clk = {
1531 .enable_reg = 0x25a0,
1532 .enable_mask = BIT(4),
1533 .hw.init = &(struct clk_init_data){
1535 .ops = &clk_branch_ops,
1536 .flags = CLK_IS_ROOT,
1541 static struct clk_rcg prng_src = {
1549 .parent_map = gcc_pxo_pll8_map,
1552 .hw.init = &(struct clk_init_data){
1554 .parent_names = gcc_pxo_pll8,
1556 .ops = &clk_rcg_ops,
1561 static struct clk_branch prng_clk = {
1563 .halt_check = BRANCH_HALT_VOTED,
1566 .enable_reg = 0x3080,
1567 .enable_mask = BIT(10),
1568 .hw.init = &(struct clk_init_data){
1570 .parent_names = (const char *[]){ "prng_src" },
1572 .ops = &clk_branch_ops,
1577 static const struct freq_tbl clk_tbl_sdc[] = {
1578 { 144000, P_PXO, 3, 2, 125 },
1579 { 400000, P_PLL8, 4, 1, 240 },
1580 { 16000000, P_PLL8, 4, 1, 6 },
1581 { 17070000, P_PLL8, 1, 2, 45 },
1582 { 20210000, P_PLL8, 1, 1, 19 },
1583 { 24000000, P_PLL8, 4, 1, 4 },
1584 { 48000000, P_PLL8, 4, 1, 2 },
1585 { 64000000, P_PLL8, 3, 1, 2 },
1586 { 96000000, P_PLL8, 4, 0, 0 },
1587 { 192000000, P_PLL8, 2, 0, 0 },
1591 static struct clk_rcg sdc1_src = {
1596 .mnctr_reset_bit = 7,
1597 .mnctr_mode_shift = 5,
1608 .parent_map = gcc_pxo_pll8_map,
1610 .freq_tbl = clk_tbl_sdc,
1612 .enable_reg = 0x282c,
1613 .enable_mask = BIT(11),
1614 .hw.init = &(struct clk_init_data){
1616 .parent_names = gcc_pxo_pll8,
1618 .ops = &clk_rcg_ops,
1619 .flags = CLK_SET_RATE_GATE,
1624 static struct clk_branch sdc1_clk = {
1628 .enable_reg = 0x282c,
1629 .enable_mask = BIT(9),
1630 .hw.init = &(struct clk_init_data){
1632 .parent_names = (const char *[]){ "sdc1_src" },
1634 .ops = &clk_branch_ops,
1635 .flags = CLK_SET_RATE_PARENT,
1640 static struct clk_rcg sdc2_src = {
1645 .mnctr_reset_bit = 7,
1646 .mnctr_mode_shift = 5,
1657 .parent_map = gcc_pxo_pll8_map,
1659 .freq_tbl = clk_tbl_sdc,
1661 .enable_reg = 0x284c,
1662 .enable_mask = BIT(11),
1663 .hw.init = &(struct clk_init_data){
1665 .parent_names = gcc_pxo_pll8,
1667 .ops = &clk_rcg_ops,
1668 .flags = CLK_SET_RATE_GATE,
1673 static struct clk_branch sdc2_clk = {
1677 .enable_reg = 0x284c,
1678 .enable_mask = BIT(9),
1679 .hw.init = &(struct clk_init_data){
1681 .parent_names = (const char *[]){ "sdc2_src" },
1683 .ops = &clk_branch_ops,
1684 .flags = CLK_SET_RATE_PARENT,
1689 static struct clk_rcg sdc3_src = {
1694 .mnctr_reset_bit = 7,
1695 .mnctr_mode_shift = 5,
1706 .parent_map = gcc_pxo_pll8_map,
1708 .freq_tbl = clk_tbl_sdc,
1710 .enable_reg = 0x286c,
1711 .enable_mask = BIT(11),
1712 .hw.init = &(struct clk_init_data){
1714 .parent_names = gcc_pxo_pll8,
1716 .ops = &clk_rcg_ops,
1717 .flags = CLK_SET_RATE_GATE,
1722 static struct clk_branch sdc3_clk = {
1726 .enable_reg = 0x286c,
1727 .enable_mask = BIT(9),
1728 .hw.init = &(struct clk_init_data){
1730 .parent_names = (const char *[]){ "sdc3_src" },
1732 .ops = &clk_branch_ops,
1733 .flags = CLK_SET_RATE_PARENT,
1738 static struct clk_rcg sdc4_src = {
1743 .mnctr_reset_bit = 7,
1744 .mnctr_mode_shift = 5,
1755 .parent_map = gcc_pxo_pll8_map,
1757 .freq_tbl = clk_tbl_sdc,
1759 .enable_reg = 0x288c,
1760 .enable_mask = BIT(11),
1761 .hw.init = &(struct clk_init_data){
1763 .parent_names = gcc_pxo_pll8,
1765 .ops = &clk_rcg_ops,
1766 .flags = CLK_SET_RATE_GATE,
1771 static struct clk_branch sdc4_clk = {
1775 .enable_reg = 0x288c,
1776 .enable_mask = BIT(9),
1777 .hw.init = &(struct clk_init_data){
1779 .parent_names = (const char *[]){ "sdc4_src" },
1781 .ops = &clk_branch_ops,
1782 .flags = CLK_SET_RATE_PARENT,
1787 static struct clk_rcg sdc5_src = {
1792 .mnctr_reset_bit = 7,
1793 .mnctr_mode_shift = 5,
1804 .parent_map = gcc_pxo_pll8_map,
1806 .freq_tbl = clk_tbl_sdc,
1808 .enable_reg = 0x28ac,
1809 .enable_mask = BIT(11),
1810 .hw.init = &(struct clk_init_data){
1812 .parent_names = gcc_pxo_pll8,
1814 .ops = &clk_rcg_ops,
1815 .flags = CLK_SET_RATE_GATE,
1820 static struct clk_branch sdc5_clk = {
1824 .enable_reg = 0x28ac,
1825 .enable_mask = BIT(9),
1826 .hw.init = &(struct clk_init_data){
1828 .parent_names = (const char *[]){ "sdc5_src" },
1830 .ops = &clk_branch_ops,
1831 .flags = CLK_SET_RATE_PARENT,
1836 static const struct freq_tbl clk_tbl_tsif_ref[] = {
1837 { 105000, P_PXO, 1, 1, 256 },
1841 static struct clk_rcg tsif_ref_src = {
1846 .mnctr_reset_bit = 7,
1847 .mnctr_mode_shift = 5,
1858 .parent_map = gcc_pxo_pll8_map,
1860 .freq_tbl = clk_tbl_tsif_ref,
1862 .enable_reg = 0x2710,
1863 .enable_mask = BIT(11),
1864 .hw.init = &(struct clk_init_data){
1865 .name = "tsif_ref_src",
1866 .parent_names = gcc_pxo_pll8,
1868 .ops = &clk_rcg_ops,
1869 .flags = CLK_SET_RATE_GATE,
1874 static struct clk_branch tsif_ref_clk = {
1878 .enable_reg = 0x2710,
1879 .enable_mask = BIT(9),
1880 .hw.init = &(struct clk_init_data){
1881 .name = "tsif_ref_clk",
1882 .parent_names = (const char *[]){ "tsif_ref_src" },
1884 .ops = &clk_branch_ops,
1885 .flags = CLK_SET_RATE_PARENT,
1890 static const struct freq_tbl clk_tbl_usb[] = {
1891 { 60000000, P_PLL8, 1, 5, 32 },
1895 static struct clk_rcg usb_hs1_xcvr_src = {
1900 .mnctr_reset_bit = 7,
1901 .mnctr_mode_shift = 5,
1912 .parent_map = gcc_pxo_pll8_map,
1914 .freq_tbl = clk_tbl_usb,
1916 .enable_reg = 0x290c,
1917 .enable_mask = BIT(11),
1918 .hw.init = &(struct clk_init_data){
1919 .name = "usb_hs1_xcvr_src",
1920 .parent_names = gcc_pxo_pll8,
1922 .ops = &clk_rcg_ops,
1923 .flags = CLK_SET_RATE_GATE,
1928 static struct clk_branch usb_hs1_xcvr_clk = {
1932 .enable_reg = 0x290c,
1933 .enable_mask = BIT(9),
1934 .hw.init = &(struct clk_init_data){
1935 .name = "usb_hs1_xcvr_clk",
1936 .parent_names = (const char *[]){ "usb_hs1_xcvr_src" },
1938 .ops = &clk_branch_ops,
1939 .flags = CLK_SET_RATE_PARENT,
1944 static struct clk_rcg usb_hs3_xcvr_src = {
1949 .mnctr_reset_bit = 7,
1950 .mnctr_mode_shift = 5,
1961 .parent_map = gcc_pxo_pll8_map,
1963 .freq_tbl = clk_tbl_usb,
1965 .enable_reg = 0x370c,
1966 .enable_mask = BIT(11),
1967 .hw.init = &(struct clk_init_data){
1968 .name = "usb_hs3_xcvr_src",
1969 .parent_names = gcc_pxo_pll8,
1971 .ops = &clk_rcg_ops,
1972 .flags = CLK_SET_RATE_GATE,
1977 static struct clk_branch usb_hs3_xcvr_clk = {
1981 .enable_reg = 0x370c,
1982 .enable_mask = BIT(9),
1983 .hw.init = &(struct clk_init_data){
1984 .name = "usb_hs3_xcvr_clk",
1985 .parent_names = (const char *[]){ "usb_hs3_xcvr_src" },
1987 .ops = &clk_branch_ops,
1988 .flags = CLK_SET_RATE_PARENT,
1993 static struct clk_rcg usb_hs4_xcvr_src = {
1998 .mnctr_reset_bit = 7,
1999 .mnctr_mode_shift = 5,
2010 .parent_map = gcc_pxo_pll8_map,
2012 .freq_tbl = clk_tbl_usb,
2014 .enable_reg = 0x372c,
2015 .enable_mask = BIT(11),
2016 .hw.init = &(struct clk_init_data){
2017 .name = "usb_hs4_xcvr_src",
2018 .parent_names = gcc_pxo_pll8,
2020 .ops = &clk_rcg_ops,
2021 .flags = CLK_SET_RATE_GATE,
2026 static struct clk_branch usb_hs4_xcvr_clk = {
2030 .enable_reg = 0x372c,
2031 .enable_mask = BIT(9),
2032 .hw.init = &(struct clk_init_data){
2033 .name = "usb_hs4_xcvr_clk",
2034 .parent_names = (const char *[]){ "usb_hs4_xcvr_src" },
2036 .ops = &clk_branch_ops,
2037 .flags = CLK_SET_RATE_PARENT,
2042 static struct clk_rcg usb_hsic_xcvr_fs_src = {
2047 .mnctr_reset_bit = 7,
2048 .mnctr_mode_shift = 5,
2059 .parent_map = gcc_pxo_pll8_map,
2061 .freq_tbl = clk_tbl_usb,
2063 .enable_reg = 0x2928,
2064 .enable_mask = BIT(11),
2065 .hw.init = &(struct clk_init_data){
2066 .name = "usb_hsic_xcvr_fs_src",
2067 .parent_names = gcc_pxo_pll8,
2069 .ops = &clk_rcg_ops,
2070 .flags = CLK_SET_RATE_GATE,
2075 static const char *usb_hsic_xcvr_fs_src_p[] = { "usb_hsic_xcvr_fs_src" };
2077 static struct clk_branch usb_hsic_xcvr_fs_clk = {
2081 .enable_reg = 0x2928,
2082 .enable_mask = BIT(9),
2083 .hw.init = &(struct clk_init_data){
2084 .name = "usb_hsic_xcvr_fs_clk",
2085 .parent_names = usb_hsic_xcvr_fs_src_p,
2087 .ops = &clk_branch_ops,
2088 .flags = CLK_SET_RATE_PARENT,
2093 static struct clk_branch usb_hsic_system_clk = {
2097 .enable_reg = 0x292c,
2098 .enable_mask = BIT(4),
2099 .hw.init = &(struct clk_init_data){
2100 .parent_names = usb_hsic_xcvr_fs_src_p,
2102 .name = "usb_hsic_system_clk",
2103 .ops = &clk_branch_ops,
2104 .flags = CLK_SET_RATE_PARENT,
2109 static struct clk_branch usb_hsic_hsic_clk = {
2113 .enable_reg = 0x2b44,
2114 .enable_mask = BIT(0),
2115 .hw.init = &(struct clk_init_data){
2116 .parent_names = (const char *[]){ "pll14_vote" },
2118 .name = "usb_hsic_hsic_clk",
2119 .ops = &clk_branch_ops,
2124 static struct clk_branch usb_hsic_hsio_cal_clk = {
2128 .enable_reg = 0x2b48,
2129 .enable_mask = BIT(0),
2130 .hw.init = &(struct clk_init_data){
2131 .name = "usb_hsic_hsio_cal_clk",
2132 .ops = &clk_branch_ops,
2133 .flags = CLK_IS_ROOT,
2138 static struct clk_rcg usb_fs1_xcvr_fs_src = {
2143 .mnctr_reset_bit = 7,
2144 .mnctr_mode_shift = 5,
2155 .parent_map = gcc_pxo_pll8_map,
2157 .freq_tbl = clk_tbl_usb,
2159 .enable_reg = 0x2968,
2160 .enable_mask = BIT(11),
2161 .hw.init = &(struct clk_init_data){
2162 .name = "usb_fs1_xcvr_fs_src",
2163 .parent_names = gcc_pxo_pll8,
2165 .ops = &clk_rcg_ops,
2166 .flags = CLK_SET_RATE_GATE,
2171 static const char *usb_fs1_xcvr_fs_src_p[] = { "usb_fs1_xcvr_fs_src" };
2173 static struct clk_branch usb_fs1_xcvr_fs_clk = {
2177 .enable_reg = 0x2968,
2178 .enable_mask = BIT(9),
2179 .hw.init = &(struct clk_init_data){
2180 .name = "usb_fs1_xcvr_fs_clk",
2181 .parent_names = usb_fs1_xcvr_fs_src_p,
2183 .ops = &clk_branch_ops,
2184 .flags = CLK_SET_RATE_PARENT,
2189 static struct clk_branch usb_fs1_system_clk = {
2193 .enable_reg = 0x296c,
2194 .enable_mask = BIT(4),
2195 .hw.init = &(struct clk_init_data){
2196 .parent_names = usb_fs1_xcvr_fs_src_p,
2198 .name = "usb_fs1_system_clk",
2199 .ops = &clk_branch_ops,
2200 .flags = CLK_SET_RATE_PARENT,
2205 static struct clk_rcg usb_fs2_xcvr_fs_src = {
2210 .mnctr_reset_bit = 7,
2211 .mnctr_mode_shift = 5,
2222 .parent_map = gcc_pxo_pll8_map,
2224 .freq_tbl = clk_tbl_usb,
2226 .enable_reg = 0x2988,
2227 .enable_mask = BIT(11),
2228 .hw.init = &(struct clk_init_data){
2229 .name = "usb_fs2_xcvr_fs_src",
2230 .parent_names = gcc_pxo_pll8,
2232 .ops = &clk_rcg_ops,
2233 .flags = CLK_SET_RATE_GATE,
2238 static const char *usb_fs2_xcvr_fs_src_p[] = { "usb_fs2_xcvr_fs_src" };
2240 static struct clk_branch usb_fs2_xcvr_fs_clk = {
2244 .enable_reg = 0x2988,
2245 .enable_mask = BIT(9),
2246 .hw.init = &(struct clk_init_data){
2247 .name = "usb_fs2_xcvr_fs_clk",
2248 .parent_names = usb_fs2_xcvr_fs_src_p,
2250 .ops = &clk_branch_ops,
2251 .flags = CLK_SET_RATE_PARENT,
2256 static struct clk_branch usb_fs2_system_clk = {
2260 .enable_reg = 0x298c,
2261 .enable_mask = BIT(4),
2262 .hw.init = &(struct clk_init_data){
2263 .name = "usb_fs2_system_clk",
2264 .parent_names = usb_fs2_xcvr_fs_src_p,
2266 .ops = &clk_branch_ops,
2267 .flags = CLK_SET_RATE_PARENT,
2272 static struct clk_branch ce1_core_clk = {
2278 .enable_reg = 0x2724,
2279 .enable_mask = BIT(4),
2280 .hw.init = &(struct clk_init_data){
2281 .name = "ce1_core_clk",
2282 .ops = &clk_branch_ops,
2283 .flags = CLK_IS_ROOT,
2288 static struct clk_branch ce1_h_clk = {
2292 .enable_reg = 0x2720,
2293 .enable_mask = BIT(4),
2294 .hw.init = &(struct clk_init_data){
2295 .name = "ce1_h_clk",
2296 .ops = &clk_branch_ops,
2297 .flags = CLK_IS_ROOT,
2302 static struct clk_branch dma_bam_h_clk = {
2308 .enable_reg = 0x25c0,
2309 .enable_mask = BIT(4),
2310 .hw.init = &(struct clk_init_data){
2311 .name = "dma_bam_h_clk",
2312 .ops = &clk_branch_ops,
2313 .flags = CLK_IS_ROOT,
2318 static struct clk_branch gsbi1_h_clk = {
2324 .enable_reg = 0x29c0,
2325 .enable_mask = BIT(4),
2326 .hw.init = &(struct clk_init_data){
2327 .name = "gsbi1_h_clk",
2328 .ops = &clk_branch_ops,
2329 .flags = CLK_IS_ROOT,
2334 static struct clk_branch gsbi2_h_clk = {
2340 .enable_reg = 0x29e0,
2341 .enable_mask = BIT(4),
2342 .hw.init = &(struct clk_init_data){
2343 .name = "gsbi2_h_clk",
2344 .ops = &clk_branch_ops,
2345 .flags = CLK_IS_ROOT,
2350 static struct clk_branch gsbi3_h_clk = {
2356 .enable_reg = 0x2a00,
2357 .enable_mask = BIT(4),
2358 .hw.init = &(struct clk_init_data){
2359 .name = "gsbi3_h_clk",
2360 .ops = &clk_branch_ops,
2361 .flags = CLK_IS_ROOT,
2366 static struct clk_branch gsbi4_h_clk = {
2372 .enable_reg = 0x2a20,
2373 .enable_mask = BIT(4),
2374 .hw.init = &(struct clk_init_data){
2375 .name = "gsbi4_h_clk",
2376 .ops = &clk_branch_ops,
2377 .flags = CLK_IS_ROOT,
2382 static struct clk_branch gsbi5_h_clk = {
2388 .enable_reg = 0x2a40,
2389 .enable_mask = BIT(4),
2390 .hw.init = &(struct clk_init_data){
2391 .name = "gsbi5_h_clk",
2392 .ops = &clk_branch_ops,
2393 .flags = CLK_IS_ROOT,
2398 static struct clk_branch gsbi6_h_clk = {
2404 .enable_reg = 0x2a60,
2405 .enable_mask = BIT(4),
2406 .hw.init = &(struct clk_init_data){
2407 .name = "gsbi6_h_clk",
2408 .ops = &clk_branch_ops,
2409 .flags = CLK_IS_ROOT,
2414 static struct clk_branch gsbi7_h_clk = {
2420 .enable_reg = 0x2a80,
2421 .enable_mask = BIT(4),
2422 .hw.init = &(struct clk_init_data){
2423 .name = "gsbi7_h_clk",
2424 .ops = &clk_branch_ops,
2425 .flags = CLK_IS_ROOT,
2430 static struct clk_branch gsbi8_h_clk = {
2436 .enable_reg = 0x2aa0,
2437 .enable_mask = BIT(4),
2438 .hw.init = &(struct clk_init_data){
2439 .name = "gsbi8_h_clk",
2440 .ops = &clk_branch_ops,
2441 .flags = CLK_IS_ROOT,
2446 static struct clk_branch gsbi9_h_clk = {
2452 .enable_reg = 0x2ac0,
2453 .enable_mask = BIT(4),
2454 .hw.init = &(struct clk_init_data){
2455 .name = "gsbi9_h_clk",
2456 .ops = &clk_branch_ops,
2457 .flags = CLK_IS_ROOT,
2462 static struct clk_branch gsbi10_h_clk = {
2468 .enable_reg = 0x2ae0,
2469 .enable_mask = BIT(4),
2470 .hw.init = &(struct clk_init_data){
2471 .name = "gsbi10_h_clk",
2472 .ops = &clk_branch_ops,
2473 .flags = CLK_IS_ROOT,
2478 static struct clk_branch gsbi11_h_clk = {
2484 .enable_reg = 0x2b00,
2485 .enable_mask = BIT(4),
2486 .hw.init = &(struct clk_init_data){
2487 .name = "gsbi11_h_clk",
2488 .ops = &clk_branch_ops,
2489 .flags = CLK_IS_ROOT,
2494 static struct clk_branch gsbi12_h_clk = {
2500 .enable_reg = 0x2b20,
2501 .enable_mask = BIT(4),
2502 .hw.init = &(struct clk_init_data){
2503 .name = "gsbi12_h_clk",
2504 .ops = &clk_branch_ops,
2505 .flags = CLK_IS_ROOT,
2510 static struct clk_branch tsif_h_clk = {
2516 .enable_reg = 0x2700,
2517 .enable_mask = BIT(4),
2518 .hw.init = &(struct clk_init_data){
2519 .name = "tsif_h_clk",
2520 .ops = &clk_branch_ops,
2521 .flags = CLK_IS_ROOT,
2526 static struct clk_branch usb_fs1_h_clk = {
2530 .enable_reg = 0x2960,
2531 .enable_mask = BIT(4),
2532 .hw.init = &(struct clk_init_data){
2533 .name = "usb_fs1_h_clk",
2534 .ops = &clk_branch_ops,
2535 .flags = CLK_IS_ROOT,
2540 static struct clk_branch usb_fs2_h_clk = {
2544 .enable_reg = 0x2980,
2545 .enable_mask = BIT(4),
2546 .hw.init = &(struct clk_init_data){
2547 .name = "usb_fs2_h_clk",
2548 .ops = &clk_branch_ops,
2549 .flags = CLK_IS_ROOT,
2554 static struct clk_branch usb_hs1_h_clk = {
2560 .enable_reg = 0x2900,
2561 .enable_mask = BIT(4),
2562 .hw.init = &(struct clk_init_data){
2563 .name = "usb_hs1_h_clk",
2564 .ops = &clk_branch_ops,
2565 .flags = CLK_IS_ROOT,
2570 static struct clk_branch usb_hs3_h_clk = {
2574 .enable_reg = 0x3700,
2575 .enable_mask = BIT(4),
2576 .hw.init = &(struct clk_init_data){
2577 .name = "usb_hs3_h_clk",
2578 .ops = &clk_branch_ops,
2579 .flags = CLK_IS_ROOT,
2584 static struct clk_branch usb_hs4_h_clk = {
2588 .enable_reg = 0x3720,
2589 .enable_mask = BIT(4),
2590 .hw.init = &(struct clk_init_data){
2591 .name = "usb_hs4_h_clk",
2592 .ops = &clk_branch_ops,
2593 .flags = CLK_IS_ROOT,
2598 static struct clk_branch usb_hsic_h_clk = {
2602 .enable_reg = 0x2920,
2603 .enable_mask = BIT(4),
2604 .hw.init = &(struct clk_init_data){
2605 .name = "usb_hsic_h_clk",
2606 .ops = &clk_branch_ops,
2607 .flags = CLK_IS_ROOT,
2612 static struct clk_branch sdc1_h_clk = {
2618 .enable_reg = 0x2820,
2619 .enable_mask = BIT(4),
2620 .hw.init = &(struct clk_init_data){
2621 .name = "sdc1_h_clk",
2622 .ops = &clk_branch_ops,
2623 .flags = CLK_IS_ROOT,
2628 static struct clk_branch sdc2_h_clk = {
2634 .enable_reg = 0x2840,
2635 .enable_mask = BIT(4),
2636 .hw.init = &(struct clk_init_data){
2637 .name = "sdc2_h_clk",
2638 .ops = &clk_branch_ops,
2639 .flags = CLK_IS_ROOT,
2644 static struct clk_branch sdc3_h_clk = {
2650 .enable_reg = 0x2860,
2651 .enable_mask = BIT(4),
2652 .hw.init = &(struct clk_init_data){
2653 .name = "sdc3_h_clk",
2654 .ops = &clk_branch_ops,
2655 .flags = CLK_IS_ROOT,
2660 static struct clk_branch sdc4_h_clk = {
2666 .enable_reg = 0x2880,
2667 .enable_mask = BIT(4),
2668 .hw.init = &(struct clk_init_data){
2669 .name = "sdc4_h_clk",
2670 .ops = &clk_branch_ops,
2671 .flags = CLK_IS_ROOT,
2676 static struct clk_branch sdc5_h_clk = {
2682 .enable_reg = 0x28a0,
2683 .enable_mask = BIT(4),
2684 .hw.init = &(struct clk_init_data){
2685 .name = "sdc5_h_clk",
2686 .ops = &clk_branch_ops,
2687 .flags = CLK_IS_ROOT,
2692 static struct clk_branch adm0_clk = {
2694 .halt_check = BRANCH_HALT_VOTED,
2697 .enable_reg = 0x3080,
2698 .enable_mask = BIT(2),
2699 .hw.init = &(struct clk_init_data){
2701 .ops = &clk_branch_ops,
2702 .flags = CLK_IS_ROOT,
2707 static struct clk_branch adm0_pbus_clk = {
2711 .halt_check = BRANCH_HALT_VOTED,
2714 .enable_reg = 0x3080,
2715 .enable_mask = BIT(3),
2716 .hw.init = &(struct clk_init_data){
2717 .name = "adm0_pbus_clk",
2718 .ops = &clk_branch_ops,
2719 .flags = CLK_IS_ROOT,
2724 static struct freq_tbl clk_tbl_ce3[] = {
2725 { 48000000, P_PLL8, 8 },
2726 { 100000000, P_PLL3, 12 },
2727 { 120000000, P_PLL3, 10 },
2731 static struct clk_rcg ce3_src = {
2739 .parent_map = gcc_pxo_pll8_pll3_map,
2741 .freq_tbl = clk_tbl_ce3,
2743 .enable_reg = 0x2c08,
2744 .enable_mask = BIT(7),
2745 .hw.init = &(struct clk_init_data){
2747 .parent_names = gcc_pxo_pll8_pll3,
2749 .ops = &clk_rcg_ops,
2750 .flags = CLK_SET_RATE_GATE,
2755 static struct clk_branch ce3_core_clk = {
2759 .enable_reg = 0x36c4,
2760 .enable_mask = BIT(4),
2761 .hw.init = &(struct clk_init_data){
2762 .name = "ce3_core_clk",
2763 .parent_names = (const char *[]){ "ce3_src" },
2765 .ops = &clk_branch_ops,
2766 .flags = CLK_SET_RATE_PARENT,
2771 static struct clk_branch ce3_h_clk = {
2775 .enable_reg = 0x36c4,
2776 .enable_mask = BIT(4),
2777 .hw.init = &(struct clk_init_data){
2778 .name = "ce3_h_clk",
2779 .parent_names = (const char *[]){ "ce3_src" },
2781 .ops = &clk_branch_ops,
2782 .flags = CLK_SET_RATE_PARENT,
2787 static const struct freq_tbl clk_tbl_sata_ref[] = {
2788 { 48000000, P_PLL8, 8, 0, 0 },
2789 { 100000000, P_PLL3, 12, 0, 0 },
2793 static struct clk_rcg sata_clk_src = {
2801 .parent_map = gcc_pxo_pll8_pll3_map,
2803 .freq_tbl = clk_tbl_sata_ref,
2805 .enable_reg = 0x2c08,
2806 .enable_mask = BIT(7),
2807 .hw.init = &(struct clk_init_data){
2808 .name = "sata_clk_src",
2809 .parent_names = gcc_pxo_pll8_pll3,
2811 .ops = &clk_rcg_ops,
2812 .flags = CLK_SET_RATE_GATE,
2817 static struct clk_branch sata_rxoob_clk = {
2821 .enable_reg = 0x2c0c,
2822 .enable_mask = BIT(4),
2823 .hw.init = &(struct clk_init_data){
2824 .name = "sata_rxoob_clk",
2825 .parent_names = (const char *[]){ "sata_clk_src" },
2827 .ops = &clk_branch_ops,
2828 .flags = CLK_SET_RATE_PARENT,
2833 static struct clk_branch sata_pmalive_clk = {
2837 .enable_reg = 0x2c10,
2838 .enable_mask = BIT(4),
2839 .hw.init = &(struct clk_init_data){
2840 .name = "sata_pmalive_clk",
2841 .parent_names = (const char *[]){ "sata_clk_src" },
2843 .ops = &clk_branch_ops,
2844 .flags = CLK_SET_RATE_PARENT,
2849 static struct clk_branch sata_phy_ref_clk = {
2853 .enable_reg = 0x2c14,
2854 .enable_mask = BIT(4),
2855 .hw.init = &(struct clk_init_data){
2856 .name = "sata_phy_ref_clk",
2857 .parent_names = (const char *[]){ "pxo" },
2859 .ops = &clk_branch_ops,
2864 static struct clk_branch sata_a_clk = {
2868 .enable_reg = 0x2c20,
2869 .enable_mask = BIT(4),
2870 .hw.init = &(struct clk_init_data){
2871 .name = "sata_a_clk",
2872 .ops = &clk_branch_ops,
2873 .flags = CLK_IS_ROOT,
2878 static struct clk_branch sata_h_clk = {
2882 .enable_reg = 0x2c00,
2883 .enable_mask = BIT(4),
2884 .hw.init = &(struct clk_init_data){
2885 .name = "sata_h_clk",
2886 .ops = &clk_branch_ops,
2887 .flags = CLK_IS_ROOT,
2892 static struct clk_branch sfab_sata_s_h_clk = {
2896 .enable_reg = 0x2480,
2897 .enable_mask = BIT(4),
2898 .hw.init = &(struct clk_init_data){
2899 .name = "sfab_sata_s_h_clk",
2900 .ops = &clk_branch_ops,
2901 .flags = CLK_IS_ROOT,
2906 static struct clk_branch sata_phy_cfg_clk = {
2910 .enable_reg = 0x2c40,
2911 .enable_mask = BIT(4),
2912 .hw.init = &(struct clk_init_data){
2913 .name = "sata_phy_cfg_clk",
2914 .ops = &clk_branch_ops,
2915 .flags = CLK_IS_ROOT,
2920 static struct clk_branch pcie_phy_ref_clk = {
2924 .enable_reg = 0x22d0,
2925 .enable_mask = BIT(4),
2926 .hw.init = &(struct clk_init_data){
2927 .name = "pcie_phy_ref_clk",
2928 .ops = &clk_branch_ops,
2929 .flags = CLK_IS_ROOT,
2934 static struct clk_branch pcie_h_clk = {
2938 .enable_reg = 0x22cc,
2939 .enable_mask = BIT(4),
2940 .hw.init = &(struct clk_init_data){
2941 .name = "pcie_h_clk",
2942 .ops = &clk_branch_ops,
2943 .flags = CLK_IS_ROOT,
2948 static struct clk_branch pcie_a_clk = {
2952 .enable_reg = 0x22c0,
2953 .enable_mask = BIT(4),
2954 .hw.init = &(struct clk_init_data){
2955 .name = "pcie_a_clk",
2956 .ops = &clk_branch_ops,
2957 .flags = CLK_IS_ROOT,
2962 static struct clk_branch pmic_arb0_h_clk = {
2964 .halt_check = BRANCH_HALT_VOTED,
2967 .enable_reg = 0x3080,
2968 .enable_mask = BIT(8),
2969 .hw.init = &(struct clk_init_data){
2970 .name = "pmic_arb0_h_clk",
2971 .ops = &clk_branch_ops,
2972 .flags = CLK_IS_ROOT,
2977 static struct clk_branch pmic_arb1_h_clk = {
2979 .halt_check = BRANCH_HALT_VOTED,
2982 .enable_reg = 0x3080,
2983 .enable_mask = BIT(9),
2984 .hw.init = &(struct clk_init_data){
2985 .name = "pmic_arb1_h_clk",
2986 .ops = &clk_branch_ops,
2987 .flags = CLK_IS_ROOT,
2992 static struct clk_branch pmic_ssbi2_clk = {
2994 .halt_check = BRANCH_HALT_VOTED,
2997 .enable_reg = 0x3080,
2998 .enable_mask = BIT(7),
2999 .hw.init = &(struct clk_init_data){
3000 .name = "pmic_ssbi2_clk",
3001 .ops = &clk_branch_ops,
3002 .flags = CLK_IS_ROOT,
3007 static struct clk_branch rpm_msg_ram_h_clk = {
3011 .halt_check = BRANCH_HALT_VOTED,
3014 .enable_reg = 0x3080,
3015 .enable_mask = BIT(6),
3016 .hw.init = &(struct clk_init_data){
3017 .name = "rpm_msg_ram_h_clk",
3018 .ops = &clk_branch_ops,
3019 .flags = CLK_IS_ROOT,
3024 static struct clk_regmap *gcc_msm8960_clks[] = {
3025 [PLL3] = &pll3.clkr,
3026 [PLL8] = &pll8.clkr,
3027 [PLL8_VOTE] = &pll8_vote,
3028 [PLL14] = &pll14.clkr,
3029 [PLL14_VOTE] = &pll14_vote,
3030 [GSBI1_UART_SRC] = &gsbi1_uart_src.clkr,
3031 [GSBI1_UART_CLK] = &gsbi1_uart_clk.clkr,
3032 [GSBI2_UART_SRC] = &gsbi2_uart_src.clkr,
3033 [GSBI2_UART_CLK] = &gsbi2_uart_clk.clkr,
3034 [GSBI3_UART_SRC] = &gsbi3_uart_src.clkr,
3035 [GSBI3_UART_CLK] = &gsbi3_uart_clk.clkr,
3036 [GSBI4_UART_SRC] = &gsbi4_uart_src.clkr,
3037 [GSBI4_UART_CLK] = &gsbi4_uart_clk.clkr,
3038 [GSBI5_UART_SRC] = &gsbi5_uart_src.clkr,
3039 [GSBI5_UART_CLK] = &gsbi5_uart_clk.clkr,
3040 [GSBI6_UART_SRC] = &gsbi6_uart_src.clkr,
3041 [GSBI6_UART_CLK] = &gsbi6_uart_clk.clkr,
3042 [GSBI7_UART_SRC] = &gsbi7_uart_src.clkr,
3043 [GSBI7_UART_CLK] = &gsbi7_uart_clk.clkr,
3044 [GSBI8_UART_SRC] = &gsbi8_uart_src.clkr,
3045 [GSBI8_UART_CLK] = &gsbi8_uart_clk.clkr,
3046 [GSBI9_UART_SRC] = &gsbi9_uart_src.clkr,
3047 [GSBI9_UART_CLK] = &gsbi9_uart_clk.clkr,
3048 [GSBI10_UART_SRC] = &gsbi10_uart_src.clkr,
3049 [GSBI10_UART_CLK] = &gsbi10_uart_clk.clkr,
3050 [GSBI11_UART_SRC] = &gsbi11_uart_src.clkr,
3051 [GSBI11_UART_CLK] = &gsbi11_uart_clk.clkr,
3052 [GSBI12_UART_SRC] = &gsbi12_uart_src.clkr,
3053 [GSBI12_UART_CLK] = &gsbi12_uart_clk.clkr,
3054 [GSBI1_QUP_SRC] = &gsbi1_qup_src.clkr,
3055 [GSBI1_QUP_CLK] = &gsbi1_qup_clk.clkr,
3056 [GSBI2_QUP_SRC] = &gsbi2_qup_src.clkr,
3057 [GSBI2_QUP_CLK] = &gsbi2_qup_clk.clkr,
3058 [GSBI3_QUP_SRC] = &gsbi3_qup_src.clkr,
3059 [GSBI3_QUP_CLK] = &gsbi3_qup_clk.clkr,
3060 [GSBI4_QUP_SRC] = &gsbi4_qup_src.clkr,
3061 [GSBI4_QUP_CLK] = &gsbi4_qup_clk.clkr,
3062 [GSBI5_QUP_SRC] = &gsbi5_qup_src.clkr,
3063 [GSBI5_QUP_CLK] = &gsbi5_qup_clk.clkr,
3064 [GSBI6_QUP_SRC] = &gsbi6_qup_src.clkr,
3065 [GSBI6_QUP_CLK] = &gsbi6_qup_clk.clkr,
3066 [GSBI7_QUP_SRC] = &gsbi7_qup_src.clkr,
3067 [GSBI7_QUP_CLK] = &gsbi7_qup_clk.clkr,
3068 [GSBI8_QUP_SRC] = &gsbi8_qup_src.clkr,
3069 [GSBI8_QUP_CLK] = &gsbi8_qup_clk.clkr,
3070 [GSBI9_QUP_SRC] = &gsbi9_qup_src.clkr,
3071 [GSBI9_QUP_CLK] = &gsbi9_qup_clk.clkr,
3072 [GSBI10_QUP_SRC] = &gsbi10_qup_src.clkr,
3073 [GSBI10_QUP_CLK] = &gsbi10_qup_clk.clkr,
3074 [GSBI11_QUP_SRC] = &gsbi11_qup_src.clkr,
3075 [GSBI11_QUP_CLK] = &gsbi11_qup_clk.clkr,
3076 [GSBI12_QUP_SRC] = &gsbi12_qup_src.clkr,
3077 [GSBI12_QUP_CLK] = &gsbi12_qup_clk.clkr,
3078 [GP0_SRC] = &gp0_src.clkr,
3079 [GP0_CLK] = &gp0_clk.clkr,
3080 [GP1_SRC] = &gp1_src.clkr,
3081 [GP1_CLK] = &gp1_clk.clkr,
3082 [GP2_SRC] = &gp2_src.clkr,
3083 [GP2_CLK] = &gp2_clk.clkr,
3084 [PMEM_A_CLK] = &pmem_clk.clkr,
3085 [PRNG_SRC] = &prng_src.clkr,
3086 [PRNG_CLK] = &prng_clk.clkr,
3087 [SDC1_SRC] = &sdc1_src.clkr,
3088 [SDC1_CLK] = &sdc1_clk.clkr,
3089 [SDC2_SRC] = &sdc2_src.clkr,
3090 [SDC2_CLK] = &sdc2_clk.clkr,
3091 [SDC3_SRC] = &sdc3_src.clkr,
3092 [SDC3_CLK] = &sdc3_clk.clkr,
3093 [SDC4_SRC] = &sdc4_src.clkr,
3094 [SDC4_CLK] = &sdc4_clk.clkr,
3095 [SDC5_SRC] = &sdc5_src.clkr,
3096 [SDC5_CLK] = &sdc5_clk.clkr,
3097 [TSIF_REF_SRC] = &tsif_ref_src.clkr,
3098 [TSIF_REF_CLK] = &tsif_ref_clk.clkr,
3099 [USB_HS1_XCVR_SRC] = &usb_hs1_xcvr_src.clkr,
3100 [USB_HS1_XCVR_CLK] = &usb_hs1_xcvr_clk.clkr,
3101 [USB_HSIC_XCVR_FS_SRC] = &usb_hsic_xcvr_fs_src.clkr,
3102 [USB_HSIC_XCVR_FS_CLK] = &usb_hsic_xcvr_fs_clk.clkr,
3103 [USB_HSIC_SYSTEM_CLK] = &usb_hsic_system_clk.clkr,
3104 [USB_HSIC_HSIC_CLK] = &usb_hsic_hsic_clk.clkr,
3105 [USB_HSIC_HSIO_CAL_CLK] = &usb_hsic_hsio_cal_clk.clkr,
3106 [USB_FS1_XCVR_FS_SRC] = &usb_fs1_xcvr_fs_src.clkr,
3107 [USB_FS1_XCVR_FS_CLK] = &usb_fs1_xcvr_fs_clk.clkr,
3108 [USB_FS1_SYSTEM_CLK] = &usb_fs1_system_clk.clkr,
3109 [USB_FS2_XCVR_FS_SRC] = &usb_fs2_xcvr_fs_src.clkr,
3110 [USB_FS2_XCVR_FS_CLK] = &usb_fs2_xcvr_fs_clk.clkr,
3111 [USB_FS2_SYSTEM_CLK] = &usb_fs2_system_clk.clkr,
3112 [CE1_CORE_CLK] = &ce1_core_clk.clkr,
3113 [CE1_H_CLK] = &ce1_h_clk.clkr,
3114 [DMA_BAM_H_CLK] = &dma_bam_h_clk.clkr,
3115 [GSBI1_H_CLK] = &gsbi1_h_clk.clkr,
3116 [GSBI2_H_CLK] = &gsbi2_h_clk.clkr,
3117 [GSBI3_H_CLK] = &gsbi3_h_clk.clkr,
3118 [GSBI4_H_CLK] = &gsbi4_h_clk.clkr,
3119 [GSBI5_H_CLK] = &gsbi5_h_clk.clkr,
3120 [GSBI6_H_CLK] = &gsbi6_h_clk.clkr,
3121 [GSBI7_H_CLK] = &gsbi7_h_clk.clkr,
3122 [GSBI8_H_CLK] = &gsbi8_h_clk.clkr,
3123 [GSBI9_H_CLK] = &gsbi9_h_clk.clkr,
3124 [GSBI10_H_CLK] = &gsbi10_h_clk.clkr,
3125 [GSBI11_H_CLK] = &gsbi11_h_clk.clkr,
3126 [GSBI12_H_CLK] = &gsbi12_h_clk.clkr,
3127 [TSIF_H_CLK] = &tsif_h_clk.clkr,
3128 [USB_FS1_H_CLK] = &usb_fs1_h_clk.clkr,
3129 [USB_FS2_H_CLK] = &usb_fs2_h_clk.clkr,
3130 [USB_HS1_H_CLK] = &usb_hs1_h_clk.clkr,
3131 [USB_HSIC_H_CLK] = &usb_hsic_h_clk.clkr,
3132 [SDC1_H_CLK] = &sdc1_h_clk.clkr,
3133 [SDC2_H_CLK] = &sdc2_h_clk.clkr,
3134 [SDC3_H_CLK] = &sdc3_h_clk.clkr,
3135 [SDC4_H_CLK] = &sdc4_h_clk.clkr,
3136 [SDC5_H_CLK] = &sdc5_h_clk.clkr,
3137 [ADM0_CLK] = &adm0_clk.clkr,
3138 [ADM0_PBUS_CLK] = &adm0_pbus_clk.clkr,
3139 [PMIC_ARB0_H_CLK] = &pmic_arb0_h_clk.clkr,
3140 [PMIC_ARB1_H_CLK] = &pmic_arb1_h_clk.clkr,
3141 [PMIC_SSBI2_CLK] = &pmic_ssbi2_clk.clkr,
3142 [RPM_MSG_RAM_H_CLK] = &rpm_msg_ram_h_clk.clkr,
3145 static const struct qcom_reset_map gcc_msm8960_resets[] = {
3146 [SFAB_MSS_Q6_SW_RESET] = { 0x2040, 7 },
3147 [SFAB_MSS_Q6_FW_RESET] = { 0x2044, 7 },
3148 [QDSS_STM_RESET] = { 0x2060, 6 },
3149 [AFAB_SMPSS_S_RESET] = { 0x20b8, 2 },
3150 [AFAB_SMPSS_M1_RESET] = { 0x20b8, 1 },
3151 [AFAB_SMPSS_M0_RESET] = { 0x20b8 },
3152 [AFAB_EBI1_CH0_RESET] = { 0x20c0, 7 },
3153 [AFAB_EBI1_CH1_RESET] = { 0x20c4, 7},
3154 [SFAB_ADM0_M0_RESET] = { 0x21e0, 7 },
3155 [SFAB_ADM0_M1_RESET] = { 0x21e4, 7 },
3156 [SFAB_ADM0_M2_RESET] = { 0x21e8, 7 },
3157 [ADM0_C2_RESET] = { 0x220c, 4},
3158 [ADM0_C1_RESET] = { 0x220c, 3},
3159 [ADM0_C0_RESET] = { 0x220c, 2},
3160 [ADM0_PBUS_RESET] = { 0x220c, 1 },
3161 [ADM0_RESET] = { 0x220c },
3162 [QDSS_CLKS_SW_RESET] = { 0x2260, 5 },
3163 [QDSS_POR_RESET] = { 0x2260, 4 },
3164 [QDSS_TSCTR_RESET] = { 0x2260, 3 },
3165 [QDSS_HRESET_RESET] = { 0x2260, 2 },
3166 [QDSS_AXI_RESET] = { 0x2260, 1 },
3167 [QDSS_DBG_RESET] = { 0x2260 },
3168 [PCIE_A_RESET] = { 0x22c0, 7 },
3169 [PCIE_AUX_RESET] = { 0x22c8, 7 },
3170 [PCIE_H_RESET] = { 0x22d0, 7 },
3171 [SFAB_PCIE_M_RESET] = { 0x22d4, 1 },
3172 [SFAB_PCIE_S_RESET] = { 0x22d4 },
3173 [SFAB_MSS_M_RESET] = { 0x2340, 7 },
3174 [SFAB_USB3_M_RESET] = { 0x2360, 7 },
3175 [SFAB_RIVA_M_RESET] = { 0x2380, 7 },
3176 [SFAB_LPASS_RESET] = { 0x23a0, 7 },
3177 [SFAB_AFAB_M_RESET] = { 0x23e0, 7 },
3178 [AFAB_SFAB_M0_RESET] = { 0x2420, 7 },
3179 [AFAB_SFAB_M1_RESET] = { 0x2424, 7 },
3180 [SFAB_SATA_S_RESET] = { 0x2480, 7 },
3181 [SFAB_DFAB_M_RESET] = { 0x2500, 7 },
3182 [DFAB_SFAB_M_RESET] = { 0x2520, 7 },
3183 [DFAB_SWAY0_RESET] = { 0x2540, 7 },
3184 [DFAB_SWAY1_RESET] = { 0x2544, 7 },
3185 [DFAB_ARB0_RESET] = { 0x2560, 7 },
3186 [DFAB_ARB1_RESET] = { 0x2564, 7 },
3187 [PPSS_PROC_RESET] = { 0x2594, 1 },
3188 [PPSS_RESET] = { 0x2594},
3189 [DMA_BAM_RESET] = { 0x25c0, 7 },
3190 [SPS_TIC_H_RESET] = { 0x2600, 7 },
3191 [SLIMBUS_H_RESET] = { 0x2620, 7 },
3192 [SFAB_CFPB_M_RESET] = { 0x2680, 7 },
3193 [SFAB_CFPB_S_RESET] = { 0x26c0, 7 },
3194 [TSIF_H_RESET] = { 0x2700, 7 },
3195 [CE1_H_RESET] = { 0x2720, 7 },
3196 [CE1_CORE_RESET] = { 0x2724, 7 },
3197 [CE1_SLEEP_RESET] = { 0x2728, 7 },
3198 [CE2_H_RESET] = { 0x2740, 7 },
3199 [CE2_CORE_RESET] = { 0x2744, 7 },
3200 [SFAB_SFPB_M_RESET] = { 0x2780, 7 },
3201 [SFAB_SFPB_S_RESET] = { 0x27a0, 7 },
3202 [RPM_PROC_RESET] = { 0x27c0, 7 },
3203 [PMIC_SSBI2_RESET] = { 0x280c, 12 },
3204 [SDC1_RESET] = { 0x2830 },
3205 [SDC2_RESET] = { 0x2850 },
3206 [SDC3_RESET] = { 0x2870 },
3207 [SDC4_RESET] = { 0x2890 },
3208 [SDC5_RESET] = { 0x28b0 },
3209 [DFAB_A2_RESET] = { 0x28c0, 7 },
3210 [USB_HS1_RESET] = { 0x2910 },
3211 [USB_HSIC_RESET] = { 0x2934 },
3212 [USB_FS1_XCVR_RESET] = { 0x2974, 1 },
3213 [USB_FS1_RESET] = { 0x2974 },
3214 [USB_FS2_XCVR_RESET] = { 0x2994, 1 },
3215 [USB_FS2_RESET] = { 0x2994 },
3216 [GSBI1_RESET] = { 0x29dc },
3217 [GSBI2_RESET] = { 0x29fc },
3218 [GSBI3_RESET] = { 0x2a1c },
3219 [GSBI4_RESET] = { 0x2a3c },
3220 [GSBI5_RESET] = { 0x2a5c },
3221 [GSBI6_RESET] = { 0x2a7c },
3222 [GSBI7_RESET] = { 0x2a9c },
3223 [GSBI8_RESET] = { 0x2abc },
3224 [GSBI9_RESET] = { 0x2adc },
3225 [GSBI10_RESET] = { 0x2afc },
3226 [GSBI11_RESET] = { 0x2b1c },
3227 [GSBI12_RESET] = { 0x2b3c },
3228 [SPDM_RESET] = { 0x2b6c },
3229 [TLMM_H_RESET] = { 0x2ba0, 7 },
3230 [SFAB_MSS_S_RESET] = { 0x2c00, 7 },
3231 [MSS_SLP_RESET] = { 0x2c60, 7 },
3232 [MSS_Q6SW_JTAG_RESET] = { 0x2c68, 7 },
3233 [MSS_Q6FW_JTAG_RESET] = { 0x2c6c, 7 },
3234 [MSS_RESET] = { 0x2c64 },
3235 [SATA_H_RESET] = { 0x2c80, 7 },
3236 [SATA_RXOOB_RESE] = { 0x2c8c, 7 },
3237 [SATA_PMALIVE_RESET] = { 0x2c90, 7 },
3238 [SATA_SFAB_M_RESET] = { 0x2c98, 7 },
3239 [TSSC_RESET] = { 0x2ca0, 7 },
3240 [PDM_RESET] = { 0x2cc0, 12 },
3241 [MPM_H_RESET] = { 0x2da0, 7 },
3242 [MPM_RESET] = { 0x2da4 },
3243 [SFAB_SMPSS_S_RESET] = { 0x2e00, 7 },
3244 [PRNG_RESET] = { 0x2e80, 12 },
3245 [RIVA_RESET] = { 0x35e0 },
3248 static struct clk_regmap *gcc_apq8064_clks[] = {
3249 [PLL3] = &pll3.clkr,
3250 [PLL8] = &pll8.clkr,
3251 [PLL8_VOTE] = &pll8_vote,
3252 [PLL14] = &pll14.clkr,
3253 [PLL14_VOTE] = &pll14_vote,
3254 [GSBI1_UART_SRC] = &gsbi1_uart_src.clkr,
3255 [GSBI1_UART_CLK] = &gsbi1_uart_clk.clkr,
3256 [GSBI2_UART_SRC] = &gsbi2_uart_src.clkr,
3257 [GSBI2_UART_CLK] = &gsbi2_uart_clk.clkr,
3258 [GSBI3_UART_SRC] = &gsbi3_uart_src.clkr,
3259 [GSBI3_UART_CLK] = &gsbi3_uart_clk.clkr,
3260 [GSBI4_UART_SRC] = &gsbi4_uart_src.clkr,
3261 [GSBI4_UART_CLK] = &gsbi4_uart_clk.clkr,
3262 [GSBI5_UART_SRC] = &gsbi5_uart_src.clkr,
3263 [GSBI5_UART_CLK] = &gsbi5_uart_clk.clkr,
3264 [GSBI6_UART_SRC] = &gsbi6_uart_src.clkr,
3265 [GSBI6_UART_CLK] = &gsbi6_uart_clk.clkr,
3266 [GSBI7_UART_SRC] = &gsbi7_uart_src.clkr,
3267 [GSBI7_UART_CLK] = &gsbi7_uart_clk.clkr,
3268 [GSBI1_QUP_SRC] = &gsbi1_qup_src.clkr,
3269 [GSBI1_QUP_CLK] = &gsbi1_qup_clk.clkr,
3270 [GSBI2_QUP_SRC] = &gsbi2_qup_src.clkr,
3271 [GSBI2_QUP_CLK] = &gsbi2_qup_clk.clkr,
3272 [GSBI3_QUP_SRC] = &gsbi3_qup_src.clkr,
3273 [GSBI3_QUP_CLK] = &gsbi3_qup_clk.clkr,
3274 [GSBI4_QUP_SRC] = &gsbi4_qup_src.clkr,
3275 [GSBI4_QUP_CLK] = &gsbi4_qup_clk.clkr,
3276 [GSBI5_QUP_SRC] = &gsbi5_qup_src.clkr,
3277 [GSBI5_QUP_CLK] = &gsbi5_qup_clk.clkr,
3278 [GSBI6_QUP_SRC] = &gsbi6_qup_src.clkr,
3279 [GSBI6_QUP_CLK] = &gsbi6_qup_clk.clkr,
3280 [GSBI7_QUP_SRC] = &gsbi7_qup_src.clkr,
3281 [GSBI7_QUP_CLK] = &gsbi7_qup_clk.clkr,
3282 [GP0_SRC] = &gp0_src.clkr,
3283 [GP0_CLK] = &gp0_clk.clkr,
3284 [GP1_SRC] = &gp1_src.clkr,
3285 [GP1_CLK] = &gp1_clk.clkr,
3286 [GP2_SRC] = &gp2_src.clkr,
3287 [GP2_CLK] = &gp2_clk.clkr,
3288 [PMEM_A_CLK] = &pmem_clk.clkr,
3289 [PRNG_SRC] = &prng_src.clkr,
3290 [PRNG_CLK] = &prng_clk.clkr,
3291 [SDC1_SRC] = &sdc1_src.clkr,
3292 [SDC1_CLK] = &sdc1_clk.clkr,
3293 [SDC2_SRC] = &sdc2_src.clkr,
3294 [SDC2_CLK] = &sdc2_clk.clkr,
3295 [SDC3_SRC] = &sdc3_src.clkr,
3296 [SDC3_CLK] = &sdc3_clk.clkr,
3297 [SDC4_SRC] = &sdc4_src.clkr,
3298 [SDC4_CLK] = &sdc4_clk.clkr,
3299 [TSIF_REF_SRC] = &tsif_ref_src.clkr,
3300 [TSIF_REF_CLK] = &tsif_ref_clk.clkr,
3301 [USB_HS1_XCVR_SRC] = &usb_hs1_xcvr_src.clkr,
3302 [USB_HS1_XCVR_CLK] = &usb_hs1_xcvr_clk.clkr,
3303 [USB_HS3_XCVR_SRC] = &usb_hs3_xcvr_src.clkr,
3304 [USB_HS3_XCVR_CLK] = &usb_hs3_xcvr_clk.clkr,
3305 [USB_HS4_XCVR_SRC] = &usb_hs4_xcvr_src.clkr,
3306 [USB_HS4_XCVR_CLK] = &usb_hs4_xcvr_clk.clkr,
3307 [USB_HSIC_XCVR_FS_SRC] = &usb_hsic_xcvr_fs_src.clkr,
3308 [USB_HSIC_XCVR_FS_CLK] = &usb_hsic_xcvr_fs_clk.clkr,
3309 [USB_HSIC_SYSTEM_CLK] = &usb_hsic_system_clk.clkr,
3310 [USB_HSIC_HSIC_CLK] = &usb_hsic_hsic_clk.clkr,
3311 [USB_HSIC_HSIO_CAL_CLK] = &usb_hsic_hsio_cal_clk.clkr,
3312 [USB_FS1_XCVR_FS_SRC] = &usb_fs1_xcvr_fs_src.clkr,
3313 [USB_FS1_XCVR_FS_CLK] = &usb_fs1_xcvr_fs_clk.clkr,
3314 [USB_FS1_SYSTEM_CLK] = &usb_fs1_system_clk.clkr,
3315 [SATA_H_CLK] = &sata_h_clk.clkr,
3316 [SATA_CLK_SRC] = &sata_clk_src.clkr,
3317 [SATA_RXOOB_CLK] = &sata_rxoob_clk.clkr,
3318 [SATA_PMALIVE_CLK] = &sata_pmalive_clk.clkr,
3319 [SATA_PHY_REF_CLK] = &sata_phy_ref_clk.clkr,
3320 [SATA_PHY_CFG_CLK] = &sata_phy_cfg_clk.clkr,
3321 [SATA_A_CLK] = &sata_a_clk.clkr,
3322 [SFAB_SATA_S_H_CLK] = &sfab_sata_s_h_clk.clkr,
3323 [CE3_SRC] = &ce3_src.clkr,
3324 [CE3_CORE_CLK] = &ce3_core_clk.clkr,
3325 [CE3_H_CLK] = &ce3_h_clk.clkr,
3326 [DMA_BAM_H_CLK] = &dma_bam_h_clk.clkr,
3327 [GSBI1_H_CLK] = &gsbi1_h_clk.clkr,
3328 [GSBI2_H_CLK] = &gsbi2_h_clk.clkr,
3329 [GSBI3_H_CLK] = &gsbi3_h_clk.clkr,
3330 [GSBI4_H_CLK] = &gsbi4_h_clk.clkr,
3331 [GSBI5_H_CLK] = &gsbi5_h_clk.clkr,
3332 [GSBI6_H_CLK] = &gsbi6_h_clk.clkr,
3333 [GSBI7_H_CLK] = &gsbi7_h_clk.clkr,
3334 [TSIF_H_CLK] = &tsif_h_clk.clkr,
3335 [USB_FS1_H_CLK] = &usb_fs1_h_clk.clkr,
3336 [USB_HS1_H_CLK] = &usb_hs1_h_clk.clkr,
3337 [USB_HSIC_H_CLK] = &usb_hsic_h_clk.clkr,
3338 [USB_HS3_H_CLK] = &usb_hs3_h_clk.clkr,
3339 [USB_HS4_H_CLK] = &usb_hs4_h_clk.clkr,
3340 [SDC1_H_CLK] = &sdc1_h_clk.clkr,
3341 [SDC2_H_CLK] = &sdc2_h_clk.clkr,
3342 [SDC3_H_CLK] = &sdc3_h_clk.clkr,
3343 [SDC4_H_CLK] = &sdc4_h_clk.clkr,
3344 [ADM0_CLK] = &adm0_clk.clkr,
3345 [ADM0_PBUS_CLK] = &adm0_pbus_clk.clkr,
3346 [PCIE_A_CLK] = &pcie_a_clk.clkr,
3347 [PCIE_PHY_REF_CLK] = &pcie_phy_ref_clk.clkr,
3348 [PCIE_H_CLK] = &pcie_h_clk.clkr,
3349 [PMIC_ARB0_H_CLK] = &pmic_arb0_h_clk.clkr,
3350 [PMIC_ARB1_H_CLK] = &pmic_arb1_h_clk.clkr,
3351 [PMIC_SSBI2_CLK] = &pmic_ssbi2_clk.clkr,
3352 [RPM_MSG_RAM_H_CLK] = &rpm_msg_ram_h_clk.clkr,
3355 static const struct qcom_reset_map gcc_apq8064_resets[] = {
3356 [QDSS_STM_RESET] = { 0x2060, 6 },
3357 [AFAB_SMPSS_S_RESET] = { 0x20b8, 2 },
3358 [AFAB_SMPSS_M1_RESET] = { 0x20b8, 1 },
3359 [AFAB_SMPSS_M0_RESET] = { 0x20b8 },
3360 [AFAB_EBI1_CH0_RESET] = { 0x20c0, 7 },
3361 [AFAB_EBI1_CH1_RESET] = { 0x20c4, 7},
3362 [SFAB_ADM0_M0_RESET] = { 0x21e0, 7 },
3363 [SFAB_ADM0_M1_RESET] = { 0x21e4, 7 },
3364 [SFAB_ADM0_M2_RESET] = { 0x21e8, 7 },
3365 [ADM0_C2_RESET] = { 0x220c, 4},
3366 [ADM0_C1_RESET] = { 0x220c, 3},
3367 [ADM0_C0_RESET] = { 0x220c, 2},
3368 [ADM0_PBUS_RESET] = { 0x220c, 1 },
3369 [ADM0_RESET] = { 0x220c },
3370 [QDSS_CLKS_SW_RESET] = { 0x2260, 5 },
3371 [QDSS_POR_RESET] = { 0x2260, 4 },
3372 [QDSS_TSCTR_RESET] = { 0x2260, 3 },
3373 [QDSS_HRESET_RESET] = { 0x2260, 2 },
3374 [QDSS_AXI_RESET] = { 0x2260, 1 },
3375 [QDSS_DBG_RESET] = { 0x2260 },
3376 [SFAB_PCIE_M_RESET] = { 0x22d8, 1 },
3377 [SFAB_PCIE_S_RESET] = { 0x22d8 },
3378 [PCIE_EXT_PCI_RESET] = { 0x22dc, 6 },
3379 [PCIE_PHY_RESET] = { 0x22dc, 5 },
3380 [PCIE_PCI_RESET] = { 0x22dc, 4 },
3381 [PCIE_POR_RESET] = { 0x22dc, 3 },
3382 [PCIE_HCLK_RESET] = { 0x22dc, 2 },
3383 [PCIE_ACLK_RESET] = { 0x22dc },
3384 [SFAB_USB3_M_RESET] = { 0x2360, 7 },
3385 [SFAB_RIVA_M_RESET] = { 0x2380, 7 },
3386 [SFAB_LPASS_RESET] = { 0x23a0, 7 },
3387 [SFAB_AFAB_M_RESET] = { 0x23e0, 7 },
3388 [AFAB_SFAB_M0_RESET] = { 0x2420, 7 },
3389 [AFAB_SFAB_M1_RESET] = { 0x2424, 7 },
3390 [SFAB_SATA_S_RESET] = { 0x2480, 7 },
3391 [SFAB_DFAB_M_RESET] = { 0x2500, 7 },
3392 [DFAB_SFAB_M_RESET] = { 0x2520, 7 },
3393 [DFAB_SWAY0_RESET] = { 0x2540, 7 },
3394 [DFAB_SWAY1_RESET] = { 0x2544, 7 },
3395 [DFAB_ARB0_RESET] = { 0x2560, 7 },
3396 [DFAB_ARB1_RESET] = { 0x2564, 7 },
3397 [PPSS_PROC_RESET] = { 0x2594, 1 },
3398 [PPSS_RESET] = { 0x2594},
3399 [DMA_BAM_RESET] = { 0x25c0, 7 },
3400 [SPS_TIC_H_RESET] = { 0x2600, 7 },
3401 [SFAB_CFPB_M_RESET] = { 0x2680, 7 },
3402 [SFAB_CFPB_S_RESET] = { 0x26c0, 7 },
3403 [TSIF_H_RESET] = { 0x2700, 7 },
3404 [CE1_H_RESET] = { 0x2720, 7 },
3405 [CE1_CORE_RESET] = { 0x2724, 7 },
3406 [CE1_SLEEP_RESET] = { 0x2728, 7 },
3407 [CE2_H_RESET] = { 0x2740, 7 },
3408 [CE2_CORE_RESET] = { 0x2744, 7 },
3409 [SFAB_SFPB_M_RESET] = { 0x2780, 7 },
3410 [SFAB_SFPB_S_RESET] = { 0x27a0, 7 },
3411 [RPM_PROC_RESET] = { 0x27c0, 7 },
3412 [PMIC_SSBI2_RESET] = { 0x280c, 12 },
3413 [SDC1_RESET] = { 0x2830 },
3414 [SDC2_RESET] = { 0x2850 },
3415 [SDC3_RESET] = { 0x2870 },
3416 [SDC4_RESET] = { 0x2890 },
3417 [USB_HS1_RESET] = { 0x2910 },
3418 [USB_HSIC_RESET] = { 0x2934 },
3419 [USB_FS1_XCVR_RESET] = { 0x2974, 1 },
3420 [USB_FS1_RESET] = { 0x2974 },
3421 [GSBI1_RESET] = { 0x29dc },
3422 [GSBI2_RESET] = { 0x29fc },
3423 [GSBI3_RESET] = { 0x2a1c },
3424 [GSBI4_RESET] = { 0x2a3c },
3425 [GSBI5_RESET] = { 0x2a5c },
3426 [GSBI6_RESET] = { 0x2a7c },
3427 [GSBI7_RESET] = { 0x2a9c },
3428 [SPDM_RESET] = { 0x2b6c },
3429 [TLMM_H_RESET] = { 0x2ba0, 7 },
3430 [SATA_SFAB_M_RESET] = { 0x2c18 },
3431 [SATA_RESET] = { 0x2c1c },
3432 [GSS_SLP_RESET] = { 0x2c60, 7 },
3433 [GSS_RESET] = { 0x2c64 },
3434 [TSSC_RESET] = { 0x2ca0, 7 },
3435 [PDM_RESET] = { 0x2cc0, 12 },
3436 [MPM_H_RESET] = { 0x2da0, 7 },
3437 [MPM_RESET] = { 0x2da4 },
3438 [SFAB_SMPSS_S_RESET] = { 0x2e00, 7 },
3439 [PRNG_RESET] = { 0x2e80, 12 },
3440 [RIVA_RESET] = { 0x35e0 },
3441 [CE3_H_RESET] = { 0x36c4, 7 },
3442 [SFAB_CE3_M_RESET] = { 0x36c8, 1 },
3443 [SFAB_CE3_S_RESET] = { 0x36c8 },
3444 [CE3_RESET] = { 0x36cc, 7 },
3445 [CE3_SLEEP_RESET] = { 0x36d0, 7 },
3446 [USB_HS3_RESET] = { 0x3710 },
3447 [USB_HS4_RESET] = { 0x3730 },
3450 static const struct regmap_config gcc_msm8960_regmap_config = {
3454 .max_register = 0x3660,
3458 static const struct regmap_config gcc_apq8064_regmap_config = {
3462 .max_register = 0x3880,
3466 static const struct qcom_cc_desc gcc_msm8960_desc = {
3467 .config = &gcc_msm8960_regmap_config,
3468 .clks = gcc_msm8960_clks,
3469 .num_clks = ARRAY_SIZE(gcc_msm8960_clks),
3470 .resets = gcc_msm8960_resets,
3471 .num_resets = ARRAY_SIZE(gcc_msm8960_resets),
3474 static const struct qcom_cc_desc gcc_apq8064_desc = {
3475 .config = &gcc_apq8064_regmap_config,
3476 .clks = gcc_apq8064_clks,
3477 .num_clks = ARRAY_SIZE(gcc_apq8064_clks),
3478 .resets = gcc_apq8064_resets,
3479 .num_resets = ARRAY_SIZE(gcc_apq8064_resets),
3482 static const struct of_device_id gcc_msm8960_match_table[] = {
3483 { .compatible = "qcom,gcc-msm8960", .data = &gcc_msm8960_desc },
3484 { .compatible = "qcom,gcc-apq8064", .data = &gcc_apq8064_desc },
3487 MODULE_DEVICE_TABLE(of, gcc_msm8960_match_table);
3489 static int gcc_msm8960_probe(struct platform_device *pdev)
3492 struct device *dev = &pdev->dev;
3493 const struct of_device_id *match;
3495 match = of_match_device(gcc_msm8960_match_table, &pdev->dev);
3499 /* Temporary until RPM clocks supported */
3500 clk = clk_register_fixed_rate(dev, "cxo", NULL, CLK_IS_ROOT, 19200000);
3502 return PTR_ERR(clk);
3504 clk = clk_register_fixed_rate(dev, "pxo", NULL, CLK_IS_ROOT, 27000000);
3506 return PTR_ERR(clk);
3508 return qcom_cc_probe(pdev, match->data);
3511 static int gcc_msm8960_remove(struct platform_device *pdev)
3513 qcom_cc_remove(pdev);
3517 static struct platform_driver gcc_msm8960_driver = {
3518 .probe = gcc_msm8960_probe,
3519 .remove = gcc_msm8960_remove,
3521 .name = "gcc-msm8960",
3522 .of_match_table = gcc_msm8960_match_table,
3526 static int __init gcc_msm8960_init(void)
3528 return platform_driver_register(&gcc_msm8960_driver);
3530 core_initcall(gcc_msm8960_init);
3532 static void __exit gcc_msm8960_exit(void)
3534 platform_driver_unregister(&gcc_msm8960_driver);
3536 module_exit(gcc_msm8960_exit);
3538 MODULE_DESCRIPTION("QCOM GCC MSM8960 Driver");
3539 MODULE_LICENSE("GPL v2");
3540 MODULE_ALIAS("platform:gcc-msm8960");