drivers/clk/qcom/mmcc-msm8960.c

   1 /*
   2  * Copyright (c) 2013, The Linux Foundation. All rights reserved.
   3  *
   4  * This software is licensed under the terms of the GNU General Public
   5  * License version 2, as published by the Free Software Foundation, and
   6  * may be copied, distributed, and modified under those terms.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  */
  13
  14 #include <linux/kernel.h>
  15 #include <linux/bitops.h>
  16 #include <linux/err.h>
  17 #include <linux/delay.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/module.h>
  20 #include <linux/of.h>
  21 #include <linux/of_device.h>
  22 #include <linux/clk.h>
  23 #include <linux/clk-provider.h>
  24 #include <linux/regmap.h>
  25 #include <linux/reset-controller.h>
  26
  27 #include <dt-bindings/clock/qcom,mmcc-msm8960.h>
  28 #include <dt-bindings/reset/qcom,mmcc-msm8960.h>
  29
  30 #include "common.h"
  31 #include "clk-regmap.h"
  32 #include "clk-pll.h"
  33 #include "clk-rcg.h"
  34 #include "clk-branch.h"
  35 #include "reset.h"
  36
  37 enum {
  38         P_PXO,
  39         P_PLL8,
  40         P_PLL2,
  41         P_PLL3,
  42         P_PLL15,
  43         P_HDMI_PLL,
  44 };
  45
  46 #define F_MN(f, s, _m, _n) { .freq = f, .src = s, .m = _m, .n = _n }
  47
  48 static const struct parent_map mmcc_pxo_pll8_pll2_map[] = {
  49         { P_PXO, 0 },
  50         { P_PLL8, 2 },
  51         { P_PLL2, 1 }
  52 };
  53
  54 static const char * const mmcc_pxo_pll8_pll2[] = {
  55         "pxo",
  56         "pll8_vote",
  57         "pll2",
  58 };
  59
  60 static const struct parent_map mmcc_pxo_pll8_pll2_pll3_map[] = {
  61         { P_PXO, 0 },
  62         { P_PLL8, 2 },
  63         { P_PLL2, 1 },
  64         { P_PLL3, 3 }
  65 };
  66
  67 static const char * const mmcc_pxo_pll8_pll2_pll15[] = {
  68         "pxo",
  69         "pll8_vote",
  70         "pll2",
  71         "pll15",
  72 };
  73
  74 static const struct parent_map mmcc_pxo_pll8_pll2_pll15_map[] = {
  75         { P_PXO, 0 },
  76         { P_PLL8, 2 },
  77         { P_PLL2, 1 },
  78         { P_PLL15, 3 }
  79 };
  80
  81 static const char * const mmcc_pxo_pll8_pll2_pll3[] = {
  82         "pxo",
  83         "pll8_vote",
  84         "pll2",
  85         "pll3",
  86 };
  87
  88 static struct clk_pll pll2 = {
  89         .l_reg = 0x320,
  90         .m_reg = 0x324,
  91         .n_reg = 0x328,
  92         .config_reg = 0x32c,
  93         .mode_reg = 0x31c,
  94         .status_reg = 0x334,
  95         .status_bit = 16,
  96         .clkr.hw.init = &(struct clk_init_data){
  97                 .name = "pll2",
  98                 .parent_names = (const char *[]){ "pxo" },
  99                 .num_parents = 1,
 100                 .ops = &clk_pll_ops,
 101         },
 102 };
 103
 104 static struct clk_pll pll15 = {
 105         .l_reg = 0x33c,
 106         .m_reg = 0x340,
 107         .n_reg = 0x344,
 108         .config_reg = 0x348,
 109         .mode_reg = 0x338,
 110         .status_reg = 0x350,
 111         .status_bit = 16,
 112         .clkr.hw.init = &(struct clk_init_data){
 113                 .name = "pll15",
 114                 .parent_names = (const char *[]){ "pxo" },
 115                 .num_parents = 1,
 116                 .ops = &clk_pll_ops,
 117         },
 118 };
 119
 120 static const struct pll_config pll15_config = {
 121         .l = 33,
 122         .m = 1,
 123         .n = 3,
 124         .vco_val = 0x2 << 16,
 125         .vco_mask = 0x3 << 16,
 126         .pre_div_val = 0x0,
 127         .pre_div_mask = BIT(19),
 128         .post_div_val = 0x0,
 129         .post_div_mask = 0x3 << 20,
 130         .mn_ena_mask = BIT(22),
 131         .main_output_mask = BIT(23),
 132 };
 133
 134 static struct freq_tbl clk_tbl_cam[] = {
 135         {   6000000, P_PLL8, 4, 1, 16 },
 136         {   8000000, P_PLL8, 4, 1, 12 },
 137         {  12000000, P_PLL8, 4, 1,  8 },
 138         {  16000000, P_PLL8, 4, 1,  6 },
 139         {  19200000, P_PLL8, 4, 1,  5 },
 140         {  24000000, P_PLL8, 4, 1,  4 },
 141         {  32000000, P_PLL8, 4, 1,  3 },
 142         {  48000000, P_PLL8, 4, 1,  2 },
 143         {  64000000, P_PLL8, 3, 1,  2 },
 144         {  96000000, P_PLL8, 4, 0,  0 },
 145         { 128000000, P_PLL8, 3, 0,  0 },
 146         { }
 147 };
 148
 149 static struct clk_rcg camclk0_src = {
 150         .ns_reg = 0x0148,
 151         .md_reg = 0x0144,
 152         .mn = {
 153                 .mnctr_en_bit = 5,
 154                 .mnctr_reset_bit = 8,
 155                 .reset_in_cc = true,
 156                 .mnctr_mode_shift = 6,
 157                 .n_val_shift = 24,
 158                 .m_val_shift = 8,
 159                 .width = 8,
 160         },
 161         .p = {
 162                 .pre_div_shift = 14,
 163                 .pre_div_width = 2,
 164         },
 165         .s = {
 166                 .src_sel_shift = 0,
 167                 .parent_map = mmcc_pxo_pll8_pll2_map,
 168         },
 169         .freq_tbl = clk_tbl_cam,
 170         .clkr = {
 171                 .enable_reg = 0x0140,
 172                 .enable_mask = BIT(2),
 173                 .hw.init = &(struct clk_init_data){
 174                         .name = "camclk0_src",
 175                         .parent_names = mmcc_pxo_pll8_pll2,
 176                         .num_parents = 3,
 177                         .ops = &clk_rcg_ops,
 178                 },
 179         },
 180 };
 181
 182 static struct clk_branch camclk0_clk = {
 183         .halt_reg = 0x01e8,
 184         .halt_bit = 15,
 185         .clkr = {
 186                 .enable_reg = 0x0140,
 187                 .enable_mask = BIT(0),
 188                 .hw.init = &(struct clk_init_data){
 189                         .name = "camclk0_clk",
 190                         .parent_names = (const char *[]){ "camclk0_src" },
 191                         .num_parents = 1,
 192                         .ops = &clk_branch_ops,
 193                 },
 194         },
 195
 196 };
 197
 198 static struct clk_rcg camclk1_src = {
 199         .ns_reg = 0x015c,
 200         .md_reg = 0x0158,
 201         .mn = {
 202                 .mnctr_en_bit = 5,
 203                 .mnctr_reset_bit = 8,
 204                 .reset_in_cc = true,
 205                 .mnctr_mode_shift = 6,
 206                 .n_val_shift = 24,
 207                 .m_val_shift = 8,
 208                 .width = 8,
 209         },
 210         .p = {
 211                 .pre_div_shift = 14,
 212                 .pre_div_width = 2,
 213         },
 214         .s = {
 215                 .src_sel_shift = 0,
 216                 .parent_map = mmcc_pxo_pll8_pll2_map,
 217         },
 218         .freq_tbl = clk_tbl_cam,
 219         .clkr = {
 220                 .enable_reg = 0x0154,
 221                 .enable_mask = BIT(2),
 222                 .hw.init = &(struct clk_init_data){
 223                         .name = "camclk1_src",
 224                         .parent_names = mmcc_pxo_pll8_pll2,
 225                         .num_parents = 3,
 226                         .ops = &clk_rcg_ops,
 227                 },
 228         },
 229 };
 230
 231 static struct clk_branch camclk1_clk = {
 232         .halt_reg = 0x01e8,
 233         .halt_bit = 16,
 234         .clkr = {
 235                 .enable_reg = 0x0154,
 236                 .enable_mask = BIT(0),
 237                 .hw.init = &(struct clk_init_data){
 238                         .name = "camclk1_clk",
 239                         .parent_names = (const char *[]){ "camclk1_src" },
 240                         .num_parents = 1,
 241                         .ops = &clk_branch_ops,
 242                 },
 243         },
 244
 245 };
 246
 247 static struct clk_rcg camclk2_src = {
 248         .ns_reg = 0x0228,
 249         .md_reg = 0x0224,
 250         .mn = {
 251                 .mnctr_en_bit = 5,
 252                 .mnctr_reset_bit = 8,
 253                 .reset_in_cc = true,
 254                 .mnctr_mode_shift = 6,
 255                 .n_val_shift = 24,
 256                 .m_val_shift = 8,
 257                 .width = 8,
 258         },
 259         .p = {
 260                 .pre_div_shift = 14,
 261                 .pre_div_width = 2,
 262         },
 263         .s = {
 264                 .src_sel_shift = 0,
 265                 .parent_map = mmcc_pxo_pll8_pll2_map,
 266         },
 267         .freq_tbl = clk_tbl_cam,
 268         .clkr = {
 269                 .enable_reg = 0x0220,
 270                 .enable_mask = BIT(2),
 271                 .hw.init = &(struct clk_init_data){
 272                         .name = "camclk2_src",
 273                         .parent_names = mmcc_pxo_pll8_pll2,
 274                         .num_parents = 3,
 275                         .ops = &clk_rcg_ops,
 276                 },
 277         },
 278 };
 279
 280 static struct clk_branch camclk2_clk = {
 281         .halt_reg = 0x01e8,
 282         .halt_bit = 16,
 283         .clkr = {
 284                 .enable_reg = 0x0220,
 285                 .enable_mask = BIT(0),
 286                 .hw.init = &(struct clk_init_data){
 287                         .name = "camclk2_clk",
 288                         .parent_names = (const char *[]){ "camclk2_src" },
 289                         .num_parents = 1,
 290                         .ops = &clk_branch_ops,
 291                 },
 292         },
 293
 294 };
 295
 296 static struct freq_tbl clk_tbl_csi[] = {
 297         {  27000000, P_PXO,  1, 0, 0 },
 298         {  85330000, P_PLL8, 1, 2, 9 },
 299         { 177780000, P_PLL2, 1, 2, 9 },
 300         { }
 301 };
 302
 303 static struct clk_rcg csi0_src = {
 304         .ns_reg = 0x0048,
 305         .md_reg = 0x0044,
 306         .mn = {
 307                 .mnctr_en_bit = 5,
 308                 .mnctr_reset_bit = 7,
 309                 .mnctr_mode_shift = 6,
 310                 .n_val_shift = 24,
 311                 .m_val_shift = 8,
 312                 .width = 8,
 313         },
 314         .p = {
 315                 .pre_div_shift = 14,
 316                 .pre_div_width = 2,
 317         },
 318         .s = {
 319                 .src_sel_shift = 0,
 320                 .parent_map = mmcc_pxo_pll8_pll2_map,
 321         },
 322         .freq_tbl = clk_tbl_csi,
 323         .clkr = {
 324                 .enable_reg = 0x0040,
 325                 .enable_mask = BIT(2),
 326                 .hw.init = &(struct clk_init_data){
 327                         .name = "csi0_src",
 328                         .parent_names = mmcc_pxo_pll8_pll2,
 329                         .num_parents = 3,
 330                         .ops = &clk_rcg_ops,
 331                 },
 332         },
 333 };
 334
 335 static struct clk_branch csi0_clk = {
 336         .halt_reg = 0x01cc,
 337         .halt_bit = 13,
 338         .clkr = {
 339                 .enable_reg = 0x0040,
 340                 .enable_mask = BIT(0),
 341                 .hw.init = &(struct clk_init_data){
 342                         .parent_names = (const char *[]){ "csi0_src" },
 343                         .num_parents = 1,
 344                         .name = "csi0_clk",
 345                         .ops = &clk_branch_ops,
 346                         .flags = CLK_SET_RATE_PARENT,
 347                 },
 348         },
 349 };
 350
 351 static struct clk_branch csi0_phy_clk = {
 352         .halt_reg = 0x01e8,
 353         .halt_bit = 9,
 354         .clkr = {
 355                 .enable_reg = 0x0040,
 356                 .enable_mask = BIT(8),
 357                 .hw.init = &(struct clk_init_data){
 358                         .parent_names = (const char *[]){ "csi0_src" },
 359                         .num_parents = 1,
 360                         .name = "csi0_phy_clk",
 361                         .ops = &clk_branch_ops,
 362                         .flags = CLK_SET_RATE_PARENT,
 363                 },
 364         },
 365 };
 366
 367 static struct clk_rcg csi1_src = {
 368         .ns_reg = 0x0010,
 369         .md_reg = 0x0028,
 370         .mn = {
 371                 .mnctr_en_bit = 5,
 372                 .mnctr_reset_bit = 7,
 373                 .mnctr_mode_shift = 6,
 374                 .n_val_shift = 24,
 375                 .m_val_shift = 8,
 376                 .width = 8,
 377         },
 378         .p = {
 379                 .pre_div_shift = 14,
 380                 .pre_div_width = 2,
 381         },
 382         .s = {
 383                 .src_sel_shift = 0,
 384                 .parent_map = mmcc_pxo_pll8_pll2_map,
 385         },
 386         .freq_tbl = clk_tbl_csi,
 387         .clkr = {
 388                 .enable_reg = 0x0024,
 389                 .enable_mask = BIT(2),
 390                 .hw.init = &(struct clk_init_data){
 391                         .name = "csi1_src",
 392                         .parent_names = mmcc_pxo_pll8_pll2,
 393                         .num_parents = 3,
 394                         .ops = &clk_rcg_ops,
 395                 },
 396         },
 397 };
 398
 399 static struct clk_branch csi1_clk = {
 400         .halt_reg = 0x01cc,
 401         .halt_bit = 14,
 402         .clkr = {
 403                 .enable_reg = 0x0024,
 404                 .enable_mask = BIT(0),
 405                 .hw.init = &(struct clk_init_data){
 406                         .parent_names = (const char *[]){ "csi1_src" },
 407                         .num_parents = 1,
 408                         .name = "csi1_clk",
 409                         .ops = &clk_branch_ops,
 410                         .flags = CLK_SET_RATE_PARENT,
 411                 },
 412         },
 413 };
 414
 415 static struct clk_branch csi1_phy_clk = {
 416         .halt_reg = 0x01e8,
 417         .halt_bit = 10,
 418         .clkr = {
 419                 .enable_reg = 0x0024,
 420                 .enable_mask = BIT(8),
 421                 .hw.init = &(struct clk_init_data){
 422                         .parent_names = (const char *[]){ "csi1_src" },
 423                         .num_parents = 1,
 424                         .name = "csi1_phy_clk",
 425                         .ops = &clk_branch_ops,
 426                         .flags = CLK_SET_RATE_PARENT,
 427                 },
 428         },
 429 };
 430
 431 static struct clk_rcg csi2_src = {
 432         .ns_reg = 0x0234,
 433         .md_reg = 0x022c,
 434         .mn = {
 435                 .mnctr_en_bit = 5,
 436                 .mnctr_reset_bit = 7,
 437                 .mnctr_mode_shift = 6,
 438                 .n_val_shift = 24,
 439                 .m_val_shift = 8,
 440                 .width = 8,
 441         },
 442         .p = {
 443                 .pre_div_shift = 14,
 444                 .pre_div_width = 2,
 445         },
 446         .s = {
 447                 .src_sel_shift = 0,
 448                 .parent_map = mmcc_pxo_pll8_pll2_map,
 449         },
 450         .freq_tbl = clk_tbl_csi,
 451         .clkr = {
 452                 .enable_reg = 0x022c,
 453                 .enable_mask = BIT(2),
 454                 .hw.init = &(struct clk_init_data){
 455                         .name = "csi2_src",
 456                         .parent_names = mmcc_pxo_pll8_pll2,
 457                         .num_parents = 3,
 458                         .ops = &clk_rcg_ops,
 459                 },
 460         },
 461 };
 462
 463 static struct clk_branch csi2_clk = {
 464         .halt_reg = 0x01cc,
 465         .halt_bit = 29,
 466         .clkr = {
 467                 .enable_reg = 0x022c,
 468                 .enable_mask = BIT(0),
 469                 .hw.init = &(struct clk_init_data){
 470                         .parent_names = (const char *[]){ "csi2_src" },
 471                         .num_parents = 1,
 472                         .name = "csi2_clk",
 473                         .ops = &clk_branch_ops,
 474                         .flags = CLK_SET_RATE_PARENT,
 475                 },
 476         },
 477 };
 478
 479 static struct clk_branch csi2_phy_clk = {
 480         .halt_reg = 0x01e8,
 481         .halt_bit = 29,
 482         .clkr = {
 483                 .enable_reg = 0x022c,
 484                 .enable_mask = BIT(8),
 485                 .hw.init = &(struct clk_init_data){
 486                         .parent_names = (const char *[]){ "csi2_src" },
 487                         .num_parents = 1,
 488                         .name = "csi2_phy_clk",
 489                         .ops = &clk_branch_ops,
 490                         .flags = CLK_SET_RATE_PARENT,
 491                 },
 492         },
 493 };
 494
 495 struct clk_pix_rdi {
 496         u32 s_reg;
 497         u32 s_mask;
 498         u32 s2_reg;
 499         u32 s2_mask;
 500         struct clk_regmap clkr;
 501 };
 502
 503 #define to_clk_pix_rdi(_hw) \
 504         container_of(to_clk_regmap(_hw), struct clk_pix_rdi, clkr)
 505
 506 static int pix_rdi_set_parent(struct clk_hw *hw, u8 index)
 507 {
 508         int i;
 509         int ret = 0;
 510         u32 val;
 511         struct clk_pix_rdi *rdi = to_clk_pix_rdi(hw);
 512         int num_parents = clk_hw_get_num_parents(hw);
 513
 514         /*
 515          * These clocks select three inputs via two muxes. One mux selects
 516          * between csi0 and csi1 and the second mux selects between that mux's
 517          * output and csi2. The source and destination selections for each
 518          * mux must be clocking for the switch to succeed so just turn on
 519          * all three sources because it's easier than figuring out what source
 520          * needs to be on at what time.
 521          */
 522         for (i = 0; i < num_parents; i++) {
 523                 struct clk_hw *p = clk_hw_get_parent_by_index(hw, i);
 524                 ret = clk_prepare_enable(p->clk);
 525                 if (ret)
 526                         goto err;
 527         }
 528
 529         if (index == 2)
 530                 val = rdi->s2_mask;
 531         else
 532                 val = 0;
 533         regmap_update_bits(rdi->clkr.regmap, rdi->s2_reg, rdi->s2_mask, val);
 534         /*
 535          * Wait at least 6 cycles of slowest clock
 536          * for the glitch-free MUX to fully switch sources.
 537          */
 538         udelay(1);
 539
 540         if (index == 1)
 541                 val = rdi->s_mask;
 542         else
 543                 val = 0;
 544         regmap_update_bits(rdi->clkr.regmap, rdi->s_reg, rdi->s_mask, val);
 545         /*
 546          * Wait at least 6 cycles of slowest clock
 547          * for the glitch-free MUX to fully switch sources.
 548          */
 549         udelay(1);
 550
 551 err:
 552         for (i--; i >= 0; i--) {
 553                 struct clk_hw *p = clk_hw_get_parent_by_index(hw, i);
 554                 clk_disable_unprepare(p->clk);
 555         }
 556
 557         return ret;
 558 }
 559
 560 static u8 pix_rdi_get_parent(struct clk_hw *hw)
 561 {
 562         u32 val;
 563         struct clk_pix_rdi *rdi = to_clk_pix_rdi(hw);
 564
 565
 566         regmap_read(rdi->clkr.regmap, rdi->s2_reg, &val);
 567         if (val & rdi->s2_mask)
 568                 return 2;
 569
 570         regmap_read(rdi->clkr.regmap, rdi->s_reg, &val);
 571         if (val & rdi->s_mask)
 572                 return 1;
 573
 574         return 0;
 575 }
 576
 577 static const struct clk_ops clk_ops_pix_rdi = {
 578         .enable = clk_enable_regmap,
 579         .disable = clk_disable_regmap,
 580         .set_parent = pix_rdi_set_parent,
 581         .get_parent = pix_rdi_get_parent,
 582         .determine_rate = __clk_mux_determine_rate,
 583 };
 584
 585 static const char * const pix_rdi_parents[] = {
 586         "csi0_clk",
 587         "csi1_clk",
 588         "csi2_clk",
 589 };
 590
 591 static struct clk_pix_rdi csi_pix_clk = {
 592         .s_reg = 0x0058,
 593         .s_mask = BIT(25),
 594         .s2_reg = 0x0238,
 595         .s2_mask = BIT(13),
 596         .clkr = {
 597                 .enable_reg = 0x0058,
 598                 .enable_mask = BIT(26),
 599                 .hw.init = &(struct clk_init_data){
 600                         .name = "csi_pix_clk",
 601                         .parent_names = pix_rdi_parents,
 602                         .num_parents = 3,
 603                         .ops = &clk_ops_pix_rdi,
 604                 },
 605         },
 606 };
 607
 608 static struct clk_pix_rdi csi_pix1_clk = {
 609         .s_reg = 0x0238,
 610         .s_mask = BIT(8),
 611         .s2_reg = 0x0238,
 612         .s2_mask = BIT(9),
 613         .clkr = {
 614                 .enable_reg = 0x0238,
 615                 .enable_mask = BIT(10),
 616                 .hw.init = &(struct clk_init_data){
 617                         .name = "csi_pix1_clk",
 618                         .parent_names = pix_rdi_parents,
 619                         .num_parents = 3,
 620                         .ops = &clk_ops_pix_rdi,
 621                 },
 622         },
 623 };
 624
 625 static struct clk_pix_rdi csi_rdi_clk = {
 626         .s_reg = 0x0058,
 627         .s_mask = BIT(12),
 628         .s2_reg = 0x0238,
 629         .s2_mask = BIT(12),
 630         .clkr = {
 631                 .enable_reg = 0x0058,
 632                 .enable_mask = BIT(13),
 633                 .hw.init = &(struct clk_init_data){
 634                         .name = "csi_rdi_clk",
 635                         .parent_names = pix_rdi_parents,
 636                         .num_parents = 3,
 637                         .ops = &clk_ops_pix_rdi,
 638                 },
 639         },
 640 };
 641
 642 static struct clk_pix_rdi csi_rdi1_clk = {
 643         .s_reg = 0x0238,
 644         .s_mask = BIT(0),
 645         .s2_reg = 0x0238,
 646         .s2_mask = BIT(1),
 647         .clkr = {
 648                 .enable_reg = 0x0238,
 649                 .enable_mask = BIT(2),
 650                 .hw.init = &(struct clk_init_data){
 651                         .name = "csi_rdi1_clk",
 652                         .parent_names = pix_rdi_parents,
 653                         .num_parents = 3,
 654                         .ops = &clk_ops_pix_rdi,
 655                 },
 656         },
 657 };
 658
 659 static struct clk_pix_rdi csi_rdi2_clk = {
 660         .s_reg = 0x0238,
 661         .s_mask = BIT(4),
 662         .s2_reg = 0x0238,
 663         .s2_mask = BIT(5),
 664         .clkr = {
 665                 .enable_reg = 0x0238,
 666                 .enable_mask = BIT(6),
 667                 .hw.init = &(struct clk_init_data){
 668                         .name = "csi_rdi2_clk",
 669                         .parent_names = pix_rdi_parents,
 670                         .num_parents = 3,
 671                         .ops = &clk_ops_pix_rdi,
 672                 },
 673         },
 674 };
 675
 676 static struct freq_tbl clk_tbl_csiphytimer[] = {
 677         {  85330000, P_PLL8, 1, 2, 9 },
 678         { 177780000, P_PLL2, 1, 2, 9 },
 679         { }
 680 };
 681
 682 static struct clk_rcg csiphytimer_src = {
 683         .ns_reg = 0x0168,
 684         .md_reg = 0x0164,
 685         .mn = {
 686                 .mnctr_en_bit = 5,
 687                 .mnctr_reset_bit = 8,
 688                 .reset_in_cc = true,
 689                 .mnctr_mode_shift = 6,
 690                 .n_val_shift = 24,
 691                 .m_val_shift = 8,
 692                 .width = 8,
 693         },
 694         .p = {
 695                 .pre_div_shift = 14,
 696                 .pre_div_width = 2,
 697         },
 698         .s = {
 699                 .src_sel_shift = 0,
 700                 .parent_map = mmcc_pxo_pll8_pll2_map,
 701         },
 702         .freq_tbl = clk_tbl_csiphytimer,
 703         .clkr = {
 704                 .enable_reg = 0x0160,
 705                 .enable_mask = BIT(2),
 706                 .hw.init = &(struct clk_init_data){
 707                         .name = "csiphytimer_src",
 708                         .parent_names = mmcc_pxo_pll8_pll2,
 709                         .num_parents = 3,
 710                         .ops = &clk_rcg_ops,
 711                 },
 712         },
 713 };
 714
 715 static const char * const csixphy_timer_src[] = { "csiphytimer_src" };
 716
 717 static struct clk_branch csiphy0_timer_clk = {
 718         .halt_reg = 0x01e8,
 719         .halt_bit = 17,
 720         .clkr = {
 721                 .enable_reg = 0x0160,
 722                 .enable_mask = BIT(0),
 723                 .hw.init = &(struct clk_init_data){
 724                         .parent_names = csixphy_timer_src,
 725                         .num_parents = 1,
 726                         .name = "csiphy0_timer_clk",
 727                         .ops = &clk_branch_ops,
 728                         .flags = CLK_SET_RATE_PARENT,
 729                 },
 730         },
 731 };
 732
 733 static struct clk_branch csiphy1_timer_clk = {
 734         .halt_reg = 0x01e8,
 735         .halt_bit = 18,
 736         .clkr = {
 737                 .enable_reg = 0x0160,
 738                 .enable_mask = BIT(9),
 739                 .hw.init = &(struct clk_init_data){
 740                         .parent_names = csixphy_timer_src,
 741                         .num_parents = 1,
 742                         .name = "csiphy1_timer_clk",
 743                         .ops = &clk_branch_ops,
 744                         .flags = CLK_SET_RATE_PARENT,
 745                 },
 746         },
 747 };
 748
 749 static struct clk_branch csiphy2_timer_clk = {
 750         .halt_reg = 0x01e8,
 751         .halt_bit = 30,
 752         .clkr = {
 753                 .enable_reg = 0x0160,
 754                 .enable_mask = BIT(11),
 755                 .hw.init = &(struct clk_init_data){
 756                         .parent_names = csixphy_timer_src,
 757                         .num_parents = 1,
 758                         .name = "csiphy2_timer_clk",
 759                         .ops = &clk_branch_ops,
 760                         .flags = CLK_SET_RATE_PARENT,
 761                 },
 762         },
 763 };
 764
 765 static struct freq_tbl clk_tbl_gfx2d[] = {
 766         F_MN( 27000000, P_PXO,  1,  0),
 767         F_MN( 48000000, P_PLL8, 1,  8),
 768         F_MN( 54857000, P_PLL8, 1,  7),
 769         F_MN( 64000000, P_PLL8, 1,  6),
 770         F_MN( 76800000, P_PLL8, 1,  5),
 771         F_MN( 96000000, P_PLL8, 1,  4),
 772         F_MN(128000000, P_PLL8, 1,  3),
 773         F_MN(145455000, P_PLL2, 2, 11),
 774         F_MN(160000000, P_PLL2, 1,  5),
 775         F_MN(177778000, P_PLL2, 2,  9),
 776         F_MN(200000000, P_PLL2, 1,  4),
 777         F_MN(228571000, P_PLL2, 2,  7),
 778         { }
 779 };
 780
 781 static struct clk_dyn_rcg gfx2d0_src = {
 782         .ns_reg[0] = 0x0070,
 783         .ns_reg[1] = 0x0070,
 784         .md_reg[0] = 0x0064,
 785         .md_reg[1] = 0x0068,
 786         .bank_reg = 0x0060,
 787         .mn[0] = {
 788                 .mnctr_en_bit = 8,
 789                 .mnctr_reset_bit = 25,
 790                 .mnctr_mode_shift = 9,
 791                 .n_val_shift = 20,
 792                 .m_val_shift = 4,
 793                 .width = 4,
 794         },
 795         .mn[1] = {
 796                 .mnctr_en_bit = 5,
 797                 .mnctr_reset_bit = 24,
 798                 .mnctr_mode_shift = 6,
 799                 .n_val_shift = 16,
 800                 .m_val_shift = 4,
 801                 .width = 4,
 802         },
 803         .s[0] = {
 804                 .src_sel_shift = 3,
 805                 .parent_map = mmcc_pxo_pll8_pll2_map,
 806         },
 807         .s[1] = {
 808                 .src_sel_shift = 0,
 809                 .parent_map = mmcc_pxo_pll8_pll2_map,
 810         },
 811         .mux_sel_bit = 11,
 812         .freq_tbl = clk_tbl_gfx2d,
 813         .clkr = {
 814                 .enable_reg = 0x0060,
 815                 .enable_mask = BIT(2),
 816                 .hw.init = &(struct clk_init_data){
 817                         .name = "gfx2d0_src",
 818                         .parent_names = mmcc_pxo_pll8_pll2,
 819                         .num_parents = 3,
 820                         .ops = &clk_dyn_rcg_ops,
 821                 },
 822         },
 823 };
 824
 825 static struct clk_branch gfx2d0_clk = {
 826         .halt_reg = 0x01c8,
 827         .halt_bit = 9,
 828         .clkr = {
 829                 .enable_reg = 0x0060,
 830                 .enable_mask = BIT(0),
 831                 .hw.init = &(struct clk_init_data){
 832                         .name = "gfx2d0_clk",
 833                         .parent_names = (const char *[]){ "gfx2d0_src" },
 834                         .num_parents = 1,
 835                         .ops = &clk_branch_ops,
 836                         .flags = CLK_SET_RATE_PARENT,
 837                 },
 838         },
 839 };
 840
 841 static struct clk_dyn_rcg gfx2d1_src = {
 842         .ns_reg[0] = 0x007c,
 843         .ns_reg[1] = 0x007c,
 844         .md_reg[0] = 0x0078,
 845         .md_reg[1] = 0x006c,
 846         .bank_reg = 0x0074,
 847         .mn[0] = {
 848                 .mnctr_en_bit = 8,
 849                 .mnctr_reset_bit = 25,
 850                 .mnctr_mode_shift = 9,
 851                 .n_val_shift = 20,
 852                 .m_val_shift = 4,
 853                 .width = 4,
 854         },
 855         .mn[1] = {
 856                 .mnctr_en_bit = 5,
 857                 .mnctr_reset_bit = 24,
 858                 .mnctr_mode_shift = 6,
 859                 .n_val_shift = 16,
 860                 .m_val_shift = 4,
 861                 .width = 4,
 862         },
 863         .s[0] = {
 864                 .src_sel_shift = 3,
 865                 .parent_map = mmcc_pxo_pll8_pll2_map,
 866         },
 867         .s[1] = {
 868                 .src_sel_shift = 0,
 869                 .parent_map = mmcc_pxo_pll8_pll2_map,
 870         },
 871         .mux_sel_bit = 11,
 872         .freq_tbl = clk_tbl_gfx2d,
 873         .clkr = {
 874                 .enable_reg = 0x0074,
 875                 .enable_mask = BIT(2),
 876                 .hw.init = &(struct clk_init_data){
 877                         .name = "gfx2d1_src",
 878                         .parent_names = mmcc_pxo_pll8_pll2,
 879                         .num_parents = 3,
 880                         .ops = &clk_dyn_rcg_ops,
 881                 },
 882         },
 883 };
 884
 885 static struct clk_branch gfx2d1_clk = {
 886         .halt_reg = 0x01c8,
 887         .halt_bit = 14,
 888         .clkr = {
 889                 .enable_reg = 0x0074,
 890                 .enable_mask = BIT(0),
 891                 .hw.init = &(struct clk_init_data){
 892                         .name = "gfx2d1_clk",
 893                         .parent_names = (const char *[]){ "gfx2d1_src" },
 894                         .num_parents = 1,
 895                         .ops = &clk_branch_ops,
 896                         .flags = CLK_SET_RATE_PARENT,
 897                 },
 898         },
 899 };
 900
 901 static struct freq_tbl clk_tbl_gfx3d[] = {
 902         F_MN( 27000000, P_PXO,  1,  0),
 903         F_MN( 48000000, P_PLL8, 1,  8),
 904         F_MN( 54857000, P_PLL8, 1,  7),
 905         F_MN( 64000000, P_PLL8, 1,  6),
 906         F_MN( 76800000, P_PLL8, 1,  5),
 907         F_MN( 96000000, P_PLL8, 1,  4),
 908         F_MN(128000000, P_PLL8, 1,  3),
 909         F_MN(145455000, P_PLL2, 2, 11),
 910         F_MN(160000000, P_PLL2, 1,  5),
 911         F_MN(177778000, P_PLL2, 2,  9),
 912         F_MN(200000000, P_PLL2, 1,  4),
 913         F_MN(228571000, P_PLL2, 2,  7),
 914         F_MN(266667000, P_PLL2, 1,  3),
 915         F_MN(300000000, P_PLL3, 1,  4),
 916         F_MN(320000000, P_PLL2, 2,  5),
 917         F_MN(400000000, P_PLL2, 1,  2),
 918         { }
 919 };
 920
 921 static struct freq_tbl clk_tbl_gfx3d_8064[] = {
 922         F_MN( 27000000, P_PXO,   0,  0),
 923         F_MN( 48000000, P_PLL8,  1,  8),
 924         F_MN( 54857000, P_PLL8,  1,  7),
 925         F_MN( 64000000, P_PLL8,  1,  6),
 926         F_MN( 76800000, P_PLL8,  1,  5),
 927         F_MN( 96000000, P_PLL8,  1,  4),
 928         F_MN(128000000, P_PLL8,  1,  3),
 929         F_MN(145455000, P_PLL2,  2, 11),
 930         F_MN(160000000, P_PLL2,  1,  5),
 931         F_MN(177778000, P_PLL2,  2,  9),
 932         F_MN(192000000, P_PLL8,  1,  2),
 933         F_MN(200000000, P_PLL2,  1,  4),
 934         F_MN(228571000, P_PLL2,  2,  7),
 935         F_MN(266667000, P_PLL2,  1,  3),
 936         F_MN(320000000, P_PLL2,  2,  5),
 937         F_MN(400000000, P_PLL2,  1,  2),
 938         F_MN(450000000, P_PLL15, 1,  2),
 939         { }
 940 };
 941
 942 static struct clk_dyn_rcg gfx3d_src = {
 943         .ns_reg[0] = 0x008c,
 944         .ns_reg[1] = 0x008c,
 945         .md_reg[0] = 0x0084,
 946         .md_reg[1] = 0x0088,
 947         .bank_reg = 0x0080,
 948         .mn[0] = {
 949                 .mnctr_en_bit = 8,
 950                 .mnctr_reset_bit = 25,
 951                 .mnctr_mode_shift = 9,
 952                 .n_val_shift = 18,
 953                 .m_val_shift = 4,
 954                 .width = 4,
 955         },
 956         .mn[1] = {
 957                 .mnctr_en_bit = 5,
 958                 .mnctr_reset_bit = 24,
 959                 .mnctr_mode_shift = 6,
 960                 .n_val_shift = 14,
 961                 .m_val_shift = 4,
 962                 .width = 4,
 963         },
 964         .s[0] = {
 965                 .src_sel_shift = 3,
 966                 .parent_map = mmcc_pxo_pll8_pll2_pll3_map,
 967         },
 968         .s[1] = {
 969                 .src_sel_shift = 0,
 970                 .parent_map = mmcc_pxo_pll8_pll2_pll3_map,
 971         },
 972         .mux_sel_bit = 11,
 973         .freq_tbl = clk_tbl_gfx3d,
 974         .clkr = {
 975                 .enable_reg = 0x0080,
 976                 .enable_mask = BIT(2),
 977                 .hw.init = &(struct clk_init_data){
 978                         .name = "gfx3d_src",
 979                         .parent_names = mmcc_pxo_pll8_pll2_pll3,
 980                         .num_parents = 4,
 981                         .ops = &clk_dyn_rcg_ops,
 982                 },
 983         },
 984 };
 985
 986 static const struct clk_init_data gfx3d_8064_init = {
 987         .name = "gfx3d_src",
 988         .parent_names = mmcc_pxo_pll8_pll2_pll15,
 989         .num_parents = 4,
 990         .ops = &clk_dyn_rcg_ops,
 991 };
 992
 993 static struct clk_branch gfx3d_clk = {
 994         .halt_reg = 0x01c8,
 995         .halt_bit = 4,
 996         .clkr = {
 997                 .enable_reg = 0x0080,
 998                 .enable_mask = BIT(0),
 999                 .hw.init = &(struct clk_init_data){
1000                         .name = "gfx3d_clk",
1001                         .parent_names = (const char *[]){ "gfx3d_src" },
1002                         .num_parents = 1,
1003                         .ops = &clk_branch_ops,
1004                         .flags = CLK_SET_RATE_PARENT,
1005                 },
1006         },
1007 };
1008
1009 static struct freq_tbl clk_tbl_vcap[] = {
1010         F_MN( 27000000, P_PXO,  0,  0),
1011         F_MN( 54860000, P_PLL8, 1,  7),
1012         F_MN( 64000000, P_PLL8, 1,  6),
1013         F_MN( 76800000, P_PLL8, 1,  5),
1014         F_MN(128000000, P_PLL8, 1,  3),
1015         F_MN(160000000, P_PLL2, 1,  5),
1016         F_MN(200000000, P_PLL2, 1,  4),
1017         { }
1018 };
1019
1020 static struct clk_dyn_rcg vcap_src = {
1021         .ns_reg[0] = 0x021c,
1022         .ns_reg[1] = 0x021c,
1023         .md_reg[0] = 0x01ec,
1024         .md_reg[1] = 0x0218,
1025         .bank_reg = 0x0178,
1026         .mn[0] = {
1027                 .mnctr_en_bit = 8,
1028                 .mnctr_reset_bit = 23,
1029                 .mnctr_mode_shift = 9,
1030                 .n_val_shift = 18,
1031                 .m_val_shift = 4,
1032                 .width = 4,
1033         },
1034         .mn[1] = {
1035                 .mnctr_en_bit = 5,
1036                 .mnctr_reset_bit = 22,
1037                 .mnctr_mode_shift = 6,
1038                 .n_val_shift = 14,
1039                 .m_val_shift = 4,
1040                 .width = 4,
1041         },
1042         .s[0] = {
1043                 .src_sel_shift = 3,
1044                 .parent_map = mmcc_pxo_pll8_pll2_map,
1045         },
1046         .s[1] = {
1047                 .src_sel_shift = 0,
1048                 .parent_map = mmcc_pxo_pll8_pll2_map,
1049         },
1050         .mux_sel_bit = 11,
1051         .freq_tbl = clk_tbl_vcap,
1052         .clkr = {
1053                 .enable_reg = 0x0178,
1054                 .enable_mask = BIT(2),
1055                 .hw.init = &(struct clk_init_data){
1056                         .name = "vcap_src",
1057                         .parent_names = mmcc_pxo_pll8_pll2,
1058                         .num_parents = 3,
1059                         .ops = &clk_dyn_rcg_ops,
1060                 },
1061         },
1062 };
1063
1064 static struct clk_branch vcap_clk = {
1065         .halt_reg = 0x0240,
1066         .halt_bit = 15,
1067         .clkr = {
1068                 .enable_reg = 0x0178,
1069                 .enable_mask = BIT(0),
1070                 .hw.init = &(struct clk_init_data){
1071                         .name = "vcap_clk",
1072                         .parent_names = (const char *[]){ "vcap_src" },
1073                         .num_parents = 1,
1074                         .ops = &clk_branch_ops,
1075                         .flags = CLK_SET_RATE_PARENT,
1076                 },
1077         },
1078 };
1079
1080 static struct clk_branch vcap_npl_clk = {
1081         .halt_reg = 0x0240,
1082         .halt_bit = 25,
1083         .clkr = {
1084                 .enable_reg = 0x0178,
1085                 .enable_mask = BIT(13),
1086                 .hw.init = &(struct clk_init_data){
1087                         .name = "vcap_npl_clk",
1088                         .parent_names = (const char *[]){ "vcap_src" },
1089                         .num_parents = 1,
1090                         .ops = &clk_branch_ops,
1091                         .flags = CLK_SET_RATE_PARENT,
1092                 },
1093         },
1094 };
1095
1096 static struct freq_tbl clk_tbl_ijpeg[] = {
1097         {  27000000, P_PXO,  1, 0,  0 },
1098         {  36570000, P_PLL8, 1, 2, 21 },
1099         {  54860000, P_PLL8, 7, 0,  0 },
1100         {  96000000, P_PLL8, 4, 0,  0 },
1101         { 109710000, P_PLL8, 1, 2,  7 },
1102         { 128000000, P_PLL8, 3, 0,  0 },
1103         { 153600000, P_PLL8, 1, 2,  5 },
1104         { 200000000, P_PLL2, 4, 0,  0 },
1105         { 228571000, P_PLL2, 1, 2,  7 },
1106         { 266667000, P_PLL2, 1, 1,  3 },
1107         { 320000000, P_PLL2, 1, 2,  5 },
1108         { }
1109 };
1110
1111 static struct clk_rcg ijpeg_src = {
1112         .ns_reg = 0x00a0,
1113         .md_reg = 0x009c,
1114         .mn = {
1115                 .mnctr_en_bit = 5,
1116                 .mnctr_reset_bit = 7,
1117                 .mnctr_mode_shift = 6,
1118                 .n_val_shift = 16,
1119                 .m_val_shift = 8,
1120                 .width = 8,
1121         },
1122         .p = {
1123                 .pre_div_shift = 12,
1124                 .pre_div_width = 2,
1125         },
1126         .s = {
1127                 .src_sel_shift = 0,
1128                 .parent_map = mmcc_pxo_pll8_pll2_map,
1129         },
1130         .freq_tbl = clk_tbl_ijpeg,
1131         .clkr = {
1132                 .enable_reg = 0x0098,
1133                 .enable_mask = BIT(2),
1134                 .hw.init = &(struct clk_init_data){
1135                         .name = "ijpeg_src",
1136                         .parent_names = mmcc_pxo_pll8_pll2,
1137                         .num_parents = 3,
1138                         .ops = &clk_rcg_ops,
1139                 },
1140         },
1141 };
1142
1143 static struct clk_branch ijpeg_clk = {
1144         .halt_reg = 0x01c8,
1145         .halt_bit = 24,
1146         .clkr = {
1147                 .enable_reg = 0x0098,
1148                 .enable_mask = BIT(0),
1149                 .hw.init = &(struct clk_init_data){
1150                         .name = "ijpeg_clk",
1151                         .parent_names = (const char *[]){ "ijpeg_src" },
1152                         .num_parents = 1,
1153                         .ops = &clk_branch_ops,
1154                         .flags = CLK_SET_RATE_PARENT,
1155                 },
1156         },
1157 };
1158
1159 static struct freq_tbl clk_tbl_jpegd[] = {
1160         {  64000000, P_PLL8, 6 },
1161         {  76800000, P_PLL8, 5 },
1162         {  96000000, P_PLL8, 4 },
1163         { 160000000, P_PLL2, 5 },
1164         { 200000000, P_PLL2, 4 },
1165         { }
1166 };
1167
1168 static struct clk_rcg jpegd_src = {
1169         .ns_reg = 0x00ac,
1170         .p = {
1171                 .pre_div_shift = 12,
1172                 .pre_div_width = 4,
1173         },
1174         .s = {
1175                 .src_sel_shift = 0,
1176                 .parent_map = mmcc_pxo_pll8_pll2_map,
1177         },
1178         .freq_tbl = clk_tbl_jpegd,
1179         .clkr = {
1180                 .enable_reg = 0x00a4,
1181                 .enable_mask = BIT(2),
1182                 .hw.init = &(struct clk_init_data){
1183                         .name = "jpegd_src",
1184                         .parent_names = mmcc_pxo_pll8_pll2,
1185                         .num_parents = 3,
1186                         .ops = &clk_rcg_ops,
1187                 },
1188         },
1189 };
1190
1191 static struct clk_branch jpegd_clk = {
1192         .halt_reg = 0x01c8,
1193         .halt_bit = 19,
1194         .clkr = {
1195                 .enable_reg = 0x00a4,
1196                 .enable_mask = BIT(0),
1197                 .hw.init = &(struct clk_init_data){
1198                         .name = "jpegd_clk",
1199                         .parent_names = (const char *[]){ "jpegd_src" },
1200                         .num_parents = 1,
1201                         .ops = &clk_branch_ops,
1202                         .flags = CLK_SET_RATE_PARENT,
1203                 },
1204         },
1205 };
1206
1207 static struct freq_tbl clk_tbl_mdp[] = {
1208         {   9600000, P_PLL8, 1, 1, 40 },
1209         {  13710000, P_PLL8, 1, 1, 28 },
1210         {  27000000, P_PXO,  1, 0,  0 },
1211         {  29540000, P_PLL8, 1, 1, 13 },
1212         {  34910000, P_PLL8, 1, 1, 11 },
1213         {  38400000, P_PLL8, 1, 1, 10 },
1214         {  59080000, P_PLL8, 1, 2, 13 },
1215         {  76800000, P_PLL8, 1, 1,  5 },
1216         {  85330000, P_PLL8, 1, 2,  9 },
1217         {  96000000, P_PLL8, 1, 1,  4 },
1218         { 128000000, P_PLL8, 1, 1,  3 },
1219         { 160000000, P_PLL2, 1, 1,  5 },
1220         { 177780000, P_PLL2, 1, 2,  9 },
1221         { 200000000, P_PLL2, 1, 1,  4 },
1222         { 228571000, P_PLL2, 1, 2,  7 },
1223         { 266667000, P_PLL2, 1, 1,  3 },
1224         { }
1225 };
1226
1227 static struct clk_dyn_rcg mdp_src = {
1228         .ns_reg[0] = 0x00d0,
1229         .ns_reg[1] = 0x00d0,
1230         .md_reg[0] = 0x00c4,
1231         .md_reg[1] = 0x00c8,
1232         .bank_reg = 0x00c0,
1233         .mn[0] = {
1234                 .mnctr_en_bit = 8,
1235                 .mnctr_reset_bit = 31,
1236                 .mnctr_mode_shift = 9,
1237                 .n_val_shift = 22,
1238                 .m_val_shift = 8,
1239                 .width = 8,
1240         },
1241         .mn[1] = {
1242                 .mnctr_en_bit = 5,
1243                 .mnctr_reset_bit = 30,
1244                 .mnctr_mode_shift = 6,
1245                 .n_val_shift = 14,
1246                 .m_val_shift = 8,
1247                 .width = 8,
1248         },
1249         .s[0] = {
1250                 .src_sel_shift = 3,
1251                 .parent_map = mmcc_pxo_pll8_pll2_map,
1252         },
1253         .s[1] = {
1254                 .src_sel_shift = 0,
1255                 .parent_map = mmcc_pxo_pll8_pll2_map,
1256         },
1257         .mux_sel_bit = 11,
1258         .freq_tbl = clk_tbl_mdp,
1259         .clkr = {
1260                 .enable_reg = 0x00c0,
1261                 .enable_mask = BIT(2),
1262                 .hw.init = &(struct clk_init_data){
1263                         .name = "mdp_src",
1264                         .parent_names = mmcc_pxo_pll8_pll2,
1265                         .num_parents = 3,
1266                         .ops = &clk_dyn_rcg_ops,
1267                 },
1268         },
1269 };
1270
1271 static struct clk_branch mdp_clk = {
1272         .halt_reg = 0x01d0,
1273         .halt_bit = 10,
1274         .clkr = {
1275                 .enable_reg = 0x00c0,
1276                 .enable_mask = BIT(0),
1277                 .hw.init = &(struct clk_init_data){
1278                         .name = "mdp_clk",
1279                         .parent_names = (const char *[]){ "mdp_src" },
1280                         .num_parents = 1,
1281                         .ops = &clk_branch_ops,
1282                         .flags = CLK_SET_RATE_PARENT,
1283                 },
1284         },
1285 };
1286
1287 static struct clk_branch mdp_lut_clk = {
1288         .halt_reg = 0x01e8,
1289         .halt_bit = 13,
1290         .clkr = {
1291                 .enable_reg = 0x016c,
1292                 .enable_mask = BIT(0),
1293                 .hw.init = &(struct clk_init_data){
1294                         .parent_names = (const char *[]){ "mdp_src" },
1295                         .num_parents = 1,
1296                         .name = "mdp_lut_clk",
1297                         .ops = &clk_branch_ops,
1298                         .flags = CLK_SET_RATE_PARENT,
1299                 },
1300         },
1301 };
1302
1303 static struct clk_branch mdp_vsync_clk = {
1304         .halt_reg = 0x01cc,
1305         .halt_bit = 22,
1306         .clkr = {
1307                 .enable_reg = 0x0058,
1308                 .enable_mask = BIT(6),
1309                 .hw.init = &(struct clk_init_data){
1310                         .name = "mdp_vsync_clk",
1311                         .parent_names = (const char *[]){ "pxo" },
1312                         .num_parents = 1,
1313                         .ops = &clk_branch_ops
1314                 },
1315         },
1316 };
1317
1318 static struct freq_tbl clk_tbl_rot[] = {
1319         {  27000000, P_PXO,   1 },
1320         {  29540000, P_PLL8, 13 },
1321         {  32000000, P_PLL8, 12 },
1322         {  38400000, P_PLL8, 10 },
1323         {  48000000, P_PLL8,  8 },
1324         {  54860000, P_PLL8,  7 },
1325         {  64000000, P_PLL8,  6 },
1326         {  76800000, P_PLL8,  5 },
1327         {  96000000, P_PLL8,  4 },
1328         { 100000000, P_PLL2,  8 },
1329         { 114290000, P_PLL2,  7 },
1330         { 133330000, P_PLL2,  6 },
1331         { 160000000, P_PLL2,  5 },
1332         { 200000000, P_PLL2,  4 },
1333         { }
1334 };
1335
1336 static struct clk_dyn_rcg rot_src = {
1337         .ns_reg[0] = 0x00e8,
1338         .ns_reg[1] = 0x00e8,
1339         .bank_reg = 0x00e8,
1340         .p[0] = {
1341                 .pre_div_shift = 22,
1342                 .pre_div_width = 4,
1343         },
1344         .p[1] = {
1345                 .pre_div_shift = 26,
1346                 .pre_div_width = 4,
1347         },
1348         .s[0] = {
1349                 .src_sel_shift = 16,
1350                 .parent_map = mmcc_pxo_pll8_pll2_map,
1351         },
1352         .s[1] = {
1353                 .src_sel_shift = 19,
1354                 .parent_map = mmcc_pxo_pll8_pll2_map,
1355         },
1356         .mux_sel_bit = 30,
1357         .freq_tbl = clk_tbl_rot,
1358         .clkr = {
1359                 .enable_reg = 0x00e0,
1360                 .enable_mask = BIT(2),
1361                 .hw.init = &(struct clk_init_data){
1362                         .name = "rot_src",
1363                         .parent_names = mmcc_pxo_pll8_pll2,
1364                         .num_parents = 3,
1365                         .ops = &clk_dyn_rcg_ops,
1366                 },
1367         },
1368 };
1369
1370 static struct clk_branch rot_clk = {
1371         .halt_reg = 0x01d0,
1372         .halt_bit = 15,
1373         .clkr = {
1374                 .enable_reg = 0x00e0,
1375                 .enable_mask = BIT(0),
1376                 .hw.init = &(struct clk_init_data){
1377                         .name = "rot_clk",
1378                         .parent_names = (const char *[]){ "rot_src" },
1379                         .num_parents = 1,
1380                         .ops = &clk_branch_ops,
1381                         .flags = CLK_SET_RATE_PARENT,
1382                 },
1383         },
1384 };
1385
1386 static const struct parent_map mmcc_pxo_hdmi_map[] = {
1387         { P_PXO, 0 },
1388         { P_HDMI_PLL, 3 }
1389 };
1390
1391 static const char * const mmcc_pxo_hdmi[] = {
1392         "pxo",
1393         "hdmi_pll",
1394 };
1395
1396 static struct freq_tbl clk_tbl_tv[] = {
1397         {  .src = P_HDMI_PLL, .pre_div = 1 },
1398         { }
1399 };
1400
1401 static struct clk_rcg tv_src = {
1402         .ns_reg = 0x00f4,
1403         .md_reg = 0x00f0,
1404         .mn = {
1405                 .mnctr_en_bit = 5,
1406                 .mnctr_reset_bit = 7,
1407                 .mnctr_mode_shift = 6,
1408                 .n_val_shift = 16,
1409                 .m_val_shift = 8,
1410                 .width = 8,
1411         },
1412         .p = {
1413                 .pre_div_shift = 14,
1414                 .pre_div_width = 2,
1415         },
1416         .s = {
1417                 .src_sel_shift = 0,
1418                 .parent_map = mmcc_pxo_hdmi_map,
1419         },
1420         .freq_tbl = clk_tbl_tv,
1421         .clkr = {
1422                 .enable_reg = 0x00ec,
1423                 .enable_mask = BIT(2),
1424                 .hw.init = &(struct clk_init_data){
1425                         .name = "tv_src",
1426                         .parent_names = mmcc_pxo_hdmi,
1427                         .num_parents = 2,
1428                         .ops = &clk_rcg_bypass_ops,
1429                         .flags = CLK_SET_RATE_PARENT,
1430                 },
1431         },
1432 };
1433
1434 static const char * const tv_src_name[] = { "tv_src" };
1435
1436 static struct clk_branch tv_enc_clk = {
1437         .halt_reg = 0x01d4,
1438         .halt_bit = 9,
1439         .clkr = {
1440                 .enable_reg = 0x00ec,
1441                 .enable_mask = BIT(8),
1442                 .hw.init = &(struct clk_init_data){
1443                         .parent_names = tv_src_name,
1444                         .num_parents = 1,
1445                         .name = "tv_enc_clk",
1446                         .ops = &clk_branch_ops,
1447                         .flags = CLK_SET_RATE_PARENT,
1448                 },
1449         },
1450 };
1451
1452 static struct clk_branch tv_dac_clk = {
1453         .halt_reg = 0x01d4,
1454         .halt_bit = 10,
1455         .clkr = {
1456                 .enable_reg = 0x00ec,
1457                 .enable_mask = BIT(10),
1458                 .hw.init = &(struct clk_init_data){
1459                         .parent_names = tv_src_name,
1460                         .num_parents = 1,
1461                         .name = "tv_dac_clk",
1462                         .ops = &clk_branch_ops,
1463                         .flags = CLK_SET_RATE_PARENT,
1464                 },
1465         },
1466 };
1467
1468 static struct clk_branch mdp_tv_clk = {
1469         .halt_reg = 0x01d4,
1470         .halt_bit = 12,
1471         .clkr = {
1472                 .enable_reg = 0x00ec,
1473                 .enable_mask = BIT(0),
1474                 .hw.init = &(struct clk_init_data){
1475                         .parent_names = tv_src_name,
1476                         .num_parents = 1,
1477                         .name = "mdp_tv_clk",
1478                         .ops = &clk_branch_ops,
1479                         .flags = CLK_SET_RATE_PARENT,
1480                 },
1481         },
1482 };
1483
1484 static struct clk_branch hdmi_tv_clk = {
1485         .halt_reg = 0x01d4,
1486         .halt_bit = 11,
1487         .clkr = {
1488                 .enable_reg = 0x00ec,
1489                 .enable_mask = BIT(12),
1490                 .hw.init = &(struct clk_init_data){
1491                         .parent_names = tv_src_name,
1492                         .num_parents = 1,
1493                         .name = "hdmi_tv_clk",
1494                         .ops = &clk_branch_ops,
1495                         .flags = CLK_SET_RATE_PARENT,
1496                 },
1497         },
1498 };
1499
1500 static struct clk_branch rgb_tv_clk = {
1501         .halt_reg = 0x0240,
1502         .halt_bit = 27,
1503         .clkr = {
1504                 .enable_reg = 0x0124,
1505                 .enable_mask = BIT(14),
1506                 .hw.init = &(struct clk_init_data){
1507                         .parent_names = tv_src_name,
1508                         .num_parents = 1,
1509                         .name = "rgb_tv_clk",
1510                         .ops = &clk_branch_ops,
1511                         .flags = CLK_SET_RATE_PARENT,
1512                 },
1513         },
1514 };
1515
1516 static struct clk_branch npl_tv_clk = {
1517         .halt_reg = 0x0240,
1518         .halt_bit = 26,
1519         .clkr = {
1520                 .enable_reg = 0x0124,
1521                 .enable_mask = BIT(16),
1522                 .hw.init = &(struct clk_init_data){
1523                         .parent_names = tv_src_name,
1524                         .num_parents = 1,
1525                         .name = "npl_tv_clk",
1526                         .ops = &clk_branch_ops,
1527                         .flags = CLK_SET_RATE_PARENT,
1528                 },
1529         },
1530 };
1531
1532 static struct clk_branch hdmi_app_clk = {
1533         .halt_reg = 0x01cc,
1534         .halt_bit = 25,
1535         .clkr = {
1536                 .enable_reg = 0x005c,
1537                 .enable_mask = BIT(11),
1538                 .hw.init = &(struct clk_init_data){
1539                         .parent_names = (const char *[]){ "pxo" },
1540                         .num_parents = 1,
1541                         .name = "hdmi_app_clk",
1542                         .ops = &clk_branch_ops,
1543                 },
1544         },
1545 };
1546
1547 static struct freq_tbl clk_tbl_vcodec[] = {
1548         F_MN( 27000000, P_PXO,  1,  0),
1549         F_MN( 32000000, P_PLL8, 1, 12),
1550         F_MN( 48000000, P_PLL8, 1,  8),
1551         F_MN( 54860000, P_PLL8, 1,  7),
1552         F_MN( 96000000, P_PLL8, 1,  4),
1553         F_MN(133330000, P_PLL2, 1,  6),
1554         F_MN(200000000, P_PLL2, 1,  4),
1555         F_MN(228570000, P_PLL2, 2,  7),
1556         F_MN(266670000, P_PLL2, 1,  3),
1557         { }
1558 };
1559
1560 static struct clk_dyn_rcg vcodec_src = {
1561         .ns_reg[0] = 0x0100,
1562         .ns_reg[1] = 0x0100,
1563         .md_reg[0] = 0x00fc,
1564         .md_reg[1] = 0x0128,
1565         .bank_reg = 0x00f8,
1566         .mn[0] = {
1567                 .mnctr_en_bit = 5,
1568                 .mnctr_reset_bit = 31,
1569                 .mnctr_mode_shift = 6,
1570                 .n_val_shift = 11,
1571                 .m_val_shift = 8,
1572                 .width = 8,
1573         },
1574         .mn[1] = {
1575                 .mnctr_en_bit = 10,
1576                 .mnctr_reset_bit = 30,
1577                 .mnctr_mode_shift = 11,
1578                 .n_val_shift = 19,
1579                 .m_val_shift = 8,
1580                 .width = 8,
1581         },
1582         .s[0] = {
1583                 .src_sel_shift = 27,
1584                 .parent_map = mmcc_pxo_pll8_pll2_map,
1585         },
1586         .s[1] = {
1587                 .src_sel_shift = 0,
1588                 .parent_map = mmcc_pxo_pll8_pll2_map,
1589         },
1590         .mux_sel_bit = 13,
1591         .freq_tbl = clk_tbl_vcodec,
1592         .clkr = {
1593                 .enable_reg = 0x00f8,
1594                 .enable_mask = BIT(2),
1595                 .hw.init = &(struct clk_init_data){
1596                         .name = "vcodec_src",
1597                         .parent_names = mmcc_pxo_pll8_pll2,
1598                         .num_parents = 3,
1599                         .ops = &clk_dyn_rcg_ops,
1600                 },
1601         },
1602 };
1603
1604 static struct clk_branch vcodec_clk = {
1605         .halt_reg = 0x01d0,
1606         .halt_bit = 29,
1607         .clkr = {
1608                 .enable_reg = 0x00f8,
1609                 .enable_mask = BIT(0),
1610                 .hw.init = &(struct clk_init_data){
1611                         .name = "vcodec_clk",
1612                         .parent_names = (const char *[]){ "vcodec_src" },
1613                         .num_parents = 1,
1614                         .ops = &clk_branch_ops,
1615                         .flags = CLK_SET_RATE_PARENT,
1616                 },
1617         },
1618 };
1619
1620 static struct freq_tbl clk_tbl_vpe[] = {
1621         {  27000000, P_PXO,   1 },
1622         {  34909000, P_PLL8, 11 },
1623         {  38400000, P_PLL8, 10 },
1624         {  64000000, P_PLL8,  6 },
1625         {  76800000, P_PLL8,  5 },
1626         {  96000000, P_PLL8,  4 },
1627         { 100000000, P_PLL2,  8 },
1628         { 160000000, P_PLL2,  5 },
1629         { }
1630 };
1631
1632 static struct clk_rcg vpe_src = {
1633         .ns_reg = 0x0118,
1634         .p = {
1635                 .pre_div_shift = 12,
1636                 .pre_div_width = 4,
1637         },
1638         .s = {
1639                 .src_sel_shift = 0,
1640                 .parent_map = mmcc_pxo_pll8_pll2_map,
1641         },
1642         .freq_tbl = clk_tbl_vpe,
1643         .clkr = {
1644                 .enable_reg = 0x0110,
1645                 .enable_mask = BIT(2),
1646                 .hw.init = &(struct clk_init_data){
1647                         .name = "vpe_src",
1648                         .parent_names = mmcc_pxo_pll8_pll2,
1649                         .num_parents = 3,
1650                         .ops = &clk_rcg_ops,
1651                 },
1652         },
1653 };
1654
1655 static struct clk_branch vpe_clk = {
1656         .halt_reg = 0x01c8,
1657         .halt_bit = 28,
1658         .clkr = {
1659                 .enable_reg = 0x0110,
1660                 .enable_mask = BIT(0),
1661                 .hw.init = &(struct clk_init_data){
1662                         .name = "vpe_clk",
1663                         .parent_names = (const char *[]){ "vpe_src" },
1664                         .num_parents = 1,
1665                         .ops = &clk_branch_ops,
1666                         .flags = CLK_SET_RATE_PARENT,
1667                 },
1668         },
1669 };
1670
1671 static struct freq_tbl clk_tbl_vfe[] = {
1672         {  13960000, P_PLL8,  1, 2, 55 },
1673         {  27000000, P_PXO,   1, 0,  0 },
1674         {  36570000, P_PLL8,  1, 2, 21 },
1675         {  38400000, P_PLL8,  2, 1,  5 },
1676         {  45180000, P_PLL8,  1, 2, 17 },
1677         {  48000000, P_PLL8,  2, 1,  4 },
1678         {  54860000, P_PLL8,  1, 1,  7 },
1679         {  64000000, P_PLL8,  2, 1,  3 },
1680         {  76800000, P_PLL8,  1, 1,  5 },
1681         {  96000000, P_PLL8,  2, 1,  2 },
1682         { 109710000, P_PLL8,  1, 2,  7 },
1683         { 128000000, P_PLL8,  1, 1,  3 },
1684         { 153600000, P_PLL8,  1, 2,  5 },
1685         { 200000000, P_PLL2,  2, 1,  2 },
1686         { 228570000, P_PLL2,  1, 2,  7 },
1687         { 266667000, P_PLL2,  1, 1,  3 },
1688         { 320000000, P_PLL2,  1, 2,  5 },
1689         { }
1690 };
1691
1692 static struct clk_rcg vfe_src = {
1693         .ns_reg = 0x0108,
1694         .mn = {
1695                 .mnctr_en_bit = 5,
1696                 .mnctr_reset_bit = 7,
1697                 .mnctr_mode_shift = 6,
1698                 .n_val_shift = 16,
1699                 .m_val_shift = 8,
1700                 .width = 8,
1701         },
1702         .p = {
1703                 .pre_div_shift = 10,
1704                 .pre_div_width = 1,
1705         },
1706         .s = {
1707                 .src_sel_shift = 0,
1708                 .parent_map = mmcc_pxo_pll8_pll2_map,
1709         },
1710         .freq_tbl = clk_tbl_vfe,
1711         .clkr = {
1712                 .enable_reg = 0x0104,
1713                 .enable_mask = BIT(2),
1714                 .hw.init = &(struct clk_init_data){
1715                         .name = "vfe_src",
1716                         .parent_names = mmcc_pxo_pll8_pll2,
1717                         .num_parents = 3,
1718                         .ops = &clk_rcg_ops,
1719                 },
1720         },
1721 };
1722
1723 static struct clk_branch vfe_clk = {
1724         .halt_reg = 0x01cc,
1725         .halt_bit = 6,
1726         .clkr = {
1727                 .enable_reg = 0x0104,
1728                 .enable_mask = BIT(0),
1729                 .hw.init = &(struct clk_init_data){
1730                         .name = "vfe_clk",
1731                         .parent_names = (const char *[]){ "vfe_src" },
1732                         .num_parents = 1,
1733                         .ops = &clk_branch_ops,
1734                         .flags = CLK_SET_RATE_PARENT,
1735                 },
1736         },
1737 };
1738
1739 static struct clk_branch vfe_csi_clk = {
1740         .halt_reg = 0x01cc,
1741         .halt_bit = 8,
1742         .clkr = {
1743                 .enable_reg = 0x0104,
1744                 .enable_mask = BIT(12),
1745                 .hw.init = &(struct clk_init_data){
1746                         .parent_names = (const char *[]){ "vfe_src" },
1747                         .num_parents = 1,
1748                         .name = "vfe_csi_clk",
1749                         .ops = &clk_branch_ops,
1750                         .flags = CLK_SET_RATE_PARENT,
1751                 },
1752         },
1753 };
1754
1755 static struct clk_branch gmem_axi_clk = {
1756         .halt_reg = 0x01d8,
1757         .halt_bit = 6,
1758         .clkr = {
1759                 .enable_reg = 0x0018,
1760                 .enable_mask = BIT(24),
1761                 .hw.init = &(struct clk_init_data){
1762                         .name = "gmem_axi_clk",
1763                         .ops = &clk_branch_ops,
1764                         .flags = CLK_IS_ROOT,
1765                 },
1766         },
1767 };
1768
1769 static struct clk_branch ijpeg_axi_clk = {
1770         .hwcg_reg = 0x0018,
1771         .hwcg_bit = 11,
1772         .halt_reg = 0x01d8,
1773         .halt_bit = 4,
1774         .clkr = {
1775                 .enable_reg = 0x0018,
1776                 .enable_mask = BIT(21),
1777                 .hw.init = &(struct clk_init_data){
1778                         .name = "ijpeg_axi_clk",
1779                         .ops = &clk_branch_ops,
1780                         .flags = CLK_IS_ROOT,
1781                 },
1782         },
1783 };
1784
1785 static struct clk_branch mmss_imem_axi_clk = {
1786         .hwcg_reg = 0x0018,
1787         .hwcg_bit = 15,
1788         .halt_reg = 0x01d8,
1789         .halt_bit = 7,
1790         .clkr = {
1791                 .enable_reg = 0x0018,
1792                 .enable_mask = BIT(22),
1793                 .hw.init = &(struct clk_init_data){
1794                         .name = "mmss_imem_axi_clk",
1795                         .ops = &clk_branch_ops,
1796                         .flags = CLK_IS_ROOT,
1797                 },
1798         },
1799 };
1800
1801 static struct clk_branch jpegd_axi_clk = {
1802         .halt_reg = 0x01d8,
1803         .halt_bit = 5,
1804         .clkr = {
1805                 .enable_reg = 0x0018,
1806                 .enable_mask = BIT(25),
1807                 .hw.init = &(struct clk_init_data){
1808                         .name = "jpegd_axi_clk",
1809                         .ops = &clk_branch_ops,
1810                         .flags = CLK_IS_ROOT,
1811                 },
1812         },
1813 };
1814
1815 static struct clk_branch vcodec_axi_b_clk = {
1816         .hwcg_reg = 0x0114,
1817         .hwcg_bit = 22,
1818         .halt_reg = 0x01e8,
1819         .halt_bit = 25,
1820         .clkr = {
1821                 .enable_reg = 0x0114,
1822                 .enable_mask = BIT(23),
1823                 .hw.init = &(struct clk_init_data){
1824                         .name = "vcodec_axi_b_clk",
1825                         .ops = &clk_branch_ops,
1826                         .flags = CLK_IS_ROOT,
1827                 },
1828         },
1829 };
1830
1831 static struct clk_branch vcodec_axi_a_clk = {
1832         .hwcg_reg = 0x0114,
1833         .hwcg_bit = 24,
1834         .halt_reg = 0x01e8,
1835         .halt_bit = 26,
1836         .clkr = {
1837                 .enable_reg = 0x0114,
1838                 .enable_mask = BIT(25),
1839                 .hw.init = &(struct clk_init_data){
1840                         .name = "vcodec_axi_a_clk",
1841                         .ops = &clk_branch_ops,
1842                         .flags = CLK_IS_ROOT,
1843                 },
1844         },
1845 };
1846
1847 static struct clk_branch vcodec_axi_clk = {
1848         .hwcg_reg = 0x0018,
1849         .hwcg_bit = 13,
1850         .halt_reg = 0x01d8,
1851         .halt_bit = 3,
1852         .clkr = {
1853                 .enable_reg = 0x0018,
1854                 .enable_mask = BIT(19),
1855                 .hw.init = &(struct clk_init_data){
1856                         .name = "vcodec_axi_clk",
1857                         .ops = &clk_branch_ops,
1858                         .flags = CLK_IS_ROOT,
1859                 },
1860         },
1861 };
1862
1863 static struct clk_branch vfe_axi_clk = {
1864         .halt_reg = 0x01d8,
1865         .halt_bit = 0,
1866         .clkr = {
1867                 .enable_reg = 0x0018,
1868                 .enable_mask = BIT(18),
1869                 .hw.init = &(struct clk_init_data){
1870                         .name = "vfe_axi_clk",
1871                         .ops = &clk_branch_ops,
1872                         .flags = CLK_IS_ROOT,
1873                 },
1874         },
1875 };
1876
1877 static struct clk_branch mdp_axi_clk = {
1878         .hwcg_reg = 0x0018,
1879         .hwcg_bit = 16,
1880         .halt_reg = 0x01d8,
1881         .halt_bit = 8,
1882         .clkr = {
1883                 .enable_reg = 0x0018,
1884                 .enable_mask = BIT(23),
1885                 .hw.init = &(struct clk_init_data){
1886                         .name = "mdp_axi_clk",
1887                         .ops = &clk_branch_ops,
1888                         .flags = CLK_IS_ROOT,
1889                 },
1890         },
1891 };
1892
1893 static struct clk_branch rot_axi_clk = {
1894         .hwcg_reg = 0x0020,
1895         .hwcg_bit = 25,
1896         .halt_reg = 0x01d8,
1897         .halt_bit = 2,
1898         .clkr = {
1899                 .enable_reg = 0x0020,
1900                 .enable_mask = BIT(24),
1901                 .hw.init = &(struct clk_init_data){
1902                         .name = "rot_axi_clk",
1903                         .ops = &clk_branch_ops,
1904                         .flags = CLK_IS_ROOT,
1905                 },
1906         },
1907 };
1908
1909 static struct clk_branch vcap_axi_clk = {
1910         .halt_reg = 0x0240,
1911         .halt_bit = 20,
1912         .hwcg_reg = 0x0244,
1913         .hwcg_bit = 11,
1914         .clkr = {
1915                 .enable_reg = 0x0244,
1916                 .enable_mask = BIT(12),
1917                 .hw.init = &(struct clk_init_data){
1918                         .name = "vcap_axi_clk",
1919                         .ops = &clk_branch_ops,
1920                         .flags = CLK_IS_ROOT,
1921                 },
1922         },
1923 };
1924
1925 static struct clk_branch vpe_axi_clk = {
1926         .hwcg_reg = 0x0020,
1927         .hwcg_bit = 27,
1928         .halt_reg = 0x01d8,
1929         .halt_bit = 1,
1930         .clkr = {
1931                 .enable_reg = 0x0020,
1932                 .enable_mask = BIT(26),
1933                 .hw.init = &(struct clk_init_data){
1934                         .name = "vpe_axi_clk",
1935                         .ops = &clk_branch_ops,
1936                         .flags = CLK_IS_ROOT,
1937                 },
1938         },
1939 };
1940
1941 static struct clk_branch gfx3d_axi_clk = {
1942         .hwcg_reg = 0x0244,
1943         .hwcg_bit = 24,
1944         .halt_reg = 0x0240,
1945         .halt_bit = 30,
1946         .clkr = {
1947                 .enable_reg = 0x0244,
1948                 .enable_mask = BIT(25),
1949                 .hw.init = &(struct clk_init_data){
1950                         .name = "gfx3d_axi_clk",
1951                         .ops = &clk_branch_ops,
1952                         .flags = CLK_IS_ROOT,
1953                 },
1954         },
1955 };
1956
1957 static struct clk_branch amp_ahb_clk = {
1958         .halt_reg = 0x01dc,
1959         .halt_bit = 18,
1960         .clkr = {
1961                 .enable_reg = 0x0008,
1962                 .enable_mask = BIT(24),
1963                 .hw.init = &(struct clk_init_data){
1964                         .name = "amp_ahb_clk",
1965                         .ops = &clk_branch_ops,
1966                         .flags = CLK_IS_ROOT,
1967                 },
1968         },
1969 };
1970
1971 static struct clk_branch csi_ahb_clk = {
1972         .halt_reg = 0x01dc,
1973         .halt_bit = 16,
1974         .clkr = {
1975                 .enable_reg = 0x0008,
1976                 .enable_mask = BIT(7),
1977                 .hw.init = &(struct clk_init_data){
1978                         .name = "csi_ahb_clk",
1979                         .ops = &clk_branch_ops,
1980                         .flags = CLK_IS_ROOT
1981                 },
1982         },
1983 };
1984
1985 static struct clk_branch dsi_m_ahb_clk = {
1986         .halt_reg = 0x01dc,
1987         .halt_bit = 19,
1988         .clkr = {
1989                 .enable_reg = 0x0008,
1990                 .enable_mask = BIT(9),
1991                 .hw.init = &(struct clk_init_data){
1992                         .name = "dsi_m_ahb_clk",
1993                         .ops = &clk_branch_ops,
1994                         .flags = CLK_IS_ROOT,
1995                 },
1996         },
1997 };
1998
1999 static struct clk_branch dsi_s_ahb_clk = {
2000         .hwcg_reg = 0x0038,
2001         .hwcg_bit = 20,
2002         .halt_reg = 0x01dc,
2003         .halt_bit = 21,
2004         .clkr = {
2005                 .enable_reg = 0x0008,
2006                 .enable_mask = BIT(18),
2007                 .hw.init = &(struct clk_init_data){
2008                         .name = "dsi_s_ahb_clk",
2009                         .ops = &clk_branch_ops,
2010                         .flags = CLK_IS_ROOT,
2011                 },
2012         },
2013 };
2014
2015 static struct clk_branch dsi2_m_ahb_clk = {
2016         .halt_reg = 0x01d8,
2017         .halt_bit = 18,
2018         .clkr = {
2019                 .enable_reg = 0x0008,
2020                 .enable_mask = BIT(17),
2021                 .hw.init = &(struct clk_init_data){
2022                         .name = "dsi2_m_ahb_clk",
2023                         .ops = &clk_branch_ops,
2024                         .flags = CLK_IS_ROOT
2025                 },
2026         },
2027 };
2028
2029 static struct clk_branch dsi2_s_ahb_clk = {
2030         .hwcg_reg = 0x0038,
2031         .hwcg_bit = 15,
2032         .halt_reg = 0x01dc,
2033         .halt_bit = 20,
2034         .clkr = {
2035                 .enable_reg = 0x0008,
2036                 .enable_mask = BIT(22),
2037                 .hw.init = &(struct clk_init_data){
2038                         .name = "dsi2_s_ahb_clk",
2039                         .ops = &clk_branch_ops,
2040                         .flags = CLK_IS_ROOT,
2041                 },
2042         },
2043 };
2044
2045 static struct clk_branch gfx2d0_ahb_clk = {
2046         .hwcg_reg = 0x0038,
2047         .hwcg_bit = 28,
2048         .halt_reg = 0x01dc,
2049         .halt_bit = 2,
2050         .clkr = {
2051                 .enable_reg = 0x0008,
2052                 .enable_mask = BIT(19),
2053                 .hw.init = &(struct clk_init_data){
2054                         .name = "gfx2d0_ahb_clk",
2055                         .ops = &clk_branch_ops,
2056                         .flags = CLK_IS_ROOT,
2057                 },
2058         },
2059 };
2060
2061 static struct clk_branch gfx2d1_ahb_clk = {
2062         .hwcg_reg = 0x0038,
2063         .hwcg_bit = 29,
2064         .halt_reg = 0x01dc,
2065         .halt_bit = 3,
2066         .clkr = {
2067                 .enable_reg = 0x0008,
2068                 .enable_mask = BIT(2),
2069                 .hw.init = &(struct clk_init_data){
2070                         .name = "gfx2d1_ahb_clk",
2071                         .ops = &clk_branch_ops,
2072                         .flags = CLK_IS_ROOT,
2073                 },
2074         },
2075 };
2076
2077 static struct clk_branch gfx3d_ahb_clk = {
2078         .hwcg_reg = 0x0038,
2079         .hwcg_bit = 27,
2080         .halt_reg = 0x01dc,
2081         .halt_bit = 4,
2082         .clkr = {
2083                 .enable_reg = 0x0008,
2084                 .enable_mask = BIT(3),
2085                 .hw.init = &(struct clk_init_data){
2086                         .name = "gfx3d_ahb_clk",
2087                         .ops = &clk_branch_ops,
2088                         .flags = CLK_IS_ROOT,
2089                 },
2090         },
2091 };
2092
2093 static struct clk_branch hdmi_m_ahb_clk = {
2094         .hwcg_reg = 0x0038,
2095         .hwcg_bit = 21,
2096         .halt_reg = 0x01dc,
2097         .halt_bit = 5,
2098         .clkr = {
2099                 .enable_reg = 0x0008,
2100                 .enable_mask = BIT(14),
2101                 .hw.init = &(struct clk_init_data){
2102                         .name = "hdmi_m_ahb_clk",
2103                         .ops = &clk_branch_ops,
2104                         .flags = CLK_IS_ROOT,
2105                 },
2106         },
2107 };
2108
2109 static struct clk_branch hdmi_s_ahb_clk = {
2110         .hwcg_reg = 0x0038,
2111         .hwcg_bit = 22,
2112         .halt_reg = 0x01dc,
2113         .halt_bit = 6,
2114         .clkr = {
2115                 .enable_reg = 0x0008,
2116                 .enable_mask = BIT(4),
2117                 .hw.init = &(struct clk_init_data){
2118                         .name = "hdmi_s_ahb_clk",
2119                         .ops = &clk_branch_ops,
2120                         .flags = CLK_IS_ROOT,
2121                 },
2122         },
2123 };
2124
2125 static struct clk_branch ijpeg_ahb_clk = {
2126         .halt_reg = 0x01dc,
2127         .halt_bit = 9,
2128         .clkr = {
2129                 .enable_reg = 0x0008,
2130                 .enable_mask = BIT(5),
2131                 .hw.init = &(struct clk_init_data){
2132                         .name = "ijpeg_ahb_clk",
2133                         .ops = &clk_branch_ops,
2134                         .flags = CLK_IS_ROOT
2135                 },
2136         },
2137 };
2138
2139 static struct clk_branch mmss_imem_ahb_clk = {
2140         .hwcg_reg = 0x0038,
2141         .hwcg_bit = 12,
2142         .halt_reg = 0x01dc,
2143         .halt_bit = 10,
2144         .clkr = {
2145                 .enable_reg = 0x0008,
2146                 .enable_mask = BIT(6),
2147                 .hw.init = &(struct clk_init_data){
2148                         .name = "mmss_imem_ahb_clk",
2149                         .ops = &clk_branch_ops,
2150                         .flags = CLK_IS_ROOT
2151                 },
2152         },
2153 };
2154
2155 static struct clk_branch jpegd_ahb_clk = {
2156         .halt_reg = 0x01dc,
2157         .halt_bit = 7,
2158         .clkr = {
2159                 .enable_reg = 0x0008,
2160                 .enable_mask = BIT(21),
2161                 .hw.init = &(struct clk_init_data){
2162                         .name = "jpegd_ahb_clk",
2163                         .ops = &clk_branch_ops,
2164                         .flags = CLK_IS_ROOT,
2165                 },
2166         },
2167 };
2168
2169 static struct clk_branch mdp_ahb_clk = {
2170         .halt_reg = 0x01dc,
2171         .halt_bit = 11,
2172         .clkr = {
2173                 .enable_reg = 0x0008,
2174                 .enable_mask = BIT(10),
2175                 .hw.init = &(struct clk_init_data){
2176                         .name = "mdp_ahb_clk",
2177                         .ops = &clk_branch_ops,
2178                         .flags = CLK_IS_ROOT,
2179                 },
2180         },
2181 };
2182
2183 static struct clk_branch rot_ahb_clk = {
2184         .halt_reg = 0x01dc,
2185         .halt_bit = 13,
2186         .clkr = {
2187                 .enable_reg = 0x0008,
2188                 .enable_mask = BIT(12),
2189                 .hw.init = &(struct clk_init_data){
2190                         .name = "rot_ahb_clk",
2191                         .ops = &clk_branch_ops,
2192                         .flags = CLK_IS_ROOT
2193                 },
2194         },
2195 };
2196
2197 static struct clk_branch smmu_ahb_clk = {
2198         .hwcg_reg = 0x0008,
2199         .hwcg_bit = 26,
2200         .halt_reg = 0x01dc,
2201         .halt_bit = 22,
2202         .clkr = {
2203                 .enable_reg = 0x0008,
2204                 .enable_mask = BIT(15),
2205                 .hw.init = &(struct clk_init_data){
2206                         .name = "smmu_ahb_clk",
2207                         .ops = &clk_branch_ops,
2208                         .flags = CLK_IS_ROOT,
2209                 },
2210         },
2211 };
2212
2213 static struct clk_branch tv_enc_ahb_clk = {
2214         .halt_reg = 0x01dc,
2215         .halt_bit = 23,
2216         .clkr = {
2217                 .enable_reg = 0x0008,
2218                 .enable_mask = BIT(25),
2219                 .hw.init = &(struct clk_init_data){
2220                         .name = "tv_enc_ahb_clk",
2221                         .ops = &clk_branch_ops,
2222                         .flags = CLK_IS_ROOT,
2223                 },
2224         },
2225 };
2226
2227 static struct clk_branch vcap_ahb_clk = {
2228         .halt_reg = 0x0240,
2229         .halt_bit = 23,
2230         .clkr = {
2231                 .enable_reg = 0x0248,
2232                 .enable_mask = BIT(1),
2233                 .hw.init = &(struct clk_init_data){
2234                         .name = "vcap_ahb_clk",
2235                         .ops = &clk_branch_ops,
2236                         .flags = CLK_IS_ROOT,
2237                 },
2238         },
2239 };
2240
2241 static struct clk_branch vcodec_ahb_clk = {
2242         .hwcg_reg = 0x0038,
2243         .hwcg_bit = 26,
2244         .halt_reg = 0x01dc,
2245         .halt_bit = 12,
2246         .clkr = {
2247                 .enable_reg = 0x0008,
2248                 .enable_mask = BIT(11),
2249                 .hw.init = &(struct clk_init_data){
2250                         .name = "vcodec_ahb_clk",
2251                         .ops = &clk_branch_ops,
2252                         .flags = CLK_IS_ROOT,
2253                 },
2254         },
2255 };
2256
2257 static struct clk_branch vfe_ahb_clk = {
2258         .halt_reg = 0x01dc,
2259         .halt_bit = 14,
2260         .clkr = {
2261                 .enable_reg = 0x0008,
2262                 .enable_mask = BIT(13),
2263                 .hw.init = &(struct clk_init_data){
2264                         .name = "vfe_ahb_clk",
2265                         .ops = &clk_branch_ops,
2266                         .flags = CLK_IS_ROOT,
2267                 },
2268         },
2269 };
2270
2271 static struct clk_branch vpe_ahb_clk = {
2272         .halt_reg = 0x01dc,
2273         .halt_bit = 15,
2274         .clkr = {
2275                 .enable_reg = 0x0008,
2276                 .enable_mask = BIT(16),
2277                 .hw.init = &(struct clk_init_data){
2278                         .name = "vpe_ahb_clk",
2279                         .ops = &clk_branch_ops,
2280                         .flags = CLK_IS_ROOT,
2281                 },
2282         },
2283 };
2284
2285 static struct clk_regmap *mmcc_msm8960_clks[] = {
2286         [TV_ENC_AHB_CLK] = &tv_enc_ahb_clk.clkr,
2287         [AMP_AHB_CLK] = &amp_ahb_clk.clkr,
2288         [DSI2_S_AHB_CLK] = &dsi2_s_ahb_clk.clkr,
2289         [JPEGD_AHB_CLK] = &jpegd_ahb_clk.clkr,
2290         [GFX2D0_AHB_CLK] = &gfx2d0_ahb_clk.clkr,
2291         [DSI_S_AHB_CLK] = &dsi_s_ahb_clk.clkr,
2292         [DSI2_M_AHB_CLK] = &dsi2_m_ahb_clk.clkr,
2293         [VPE_AHB_CLK] = &vpe_ahb_clk.clkr,
2294         [SMMU_AHB_CLK] = &smmu_ahb_clk.clkr,
2295         [HDMI_M_AHB_CLK] = &hdmi_m_ahb_clk.clkr,
2296         [VFE_AHB_CLK] = &vfe_ahb_clk.clkr,
2297         [ROT_AHB_CLK] = &rot_ahb_clk.clkr,
2298         [VCODEC_AHB_CLK] = &vcodec_ahb_clk.clkr,
2299         [MDP_AHB_CLK] = &mdp_ahb_clk.clkr,
2300         [DSI_M_AHB_CLK] = &dsi_m_ahb_clk.clkr,
2301         [CSI_AHB_CLK] = &csi_ahb_clk.clkr,
2302         [MMSS_IMEM_AHB_CLK] = &mmss_imem_ahb_clk.clkr,
2303         [IJPEG_AHB_CLK] = &ijpeg_ahb_clk.clkr,
2304         [HDMI_S_AHB_CLK] = &hdmi_s_ahb_clk.clkr,
2305         [GFX3D_AHB_CLK] = &gfx3d_ahb_clk.clkr,
2306         [GFX2D1_AHB_CLK] = &gfx2d1_ahb_clk.clkr,
2307         [JPEGD_AXI_CLK] = &jpegd_axi_clk.clkr,
2308         [GMEM_AXI_CLK] = &gmem_axi_clk.clkr,
2309         [MDP_AXI_CLK] = &mdp_axi_clk.clkr,
2310         [MMSS_IMEM_AXI_CLK] = &mmss_imem_axi_clk.clkr,
2311         [IJPEG_AXI_CLK] = &ijpeg_axi_clk.clkr,
2312         [GFX3D_AXI_CLK] = &gfx3d_axi_clk.clkr,
2313         [VCODEC_AXI_CLK] = &vcodec_axi_clk.clkr,
2314         [VFE_AXI_CLK] = &vfe_axi_clk.clkr,
2315         [VPE_AXI_CLK] = &vpe_axi_clk.clkr,
2316         [ROT_AXI_CLK] = &rot_axi_clk.clkr,
2317         [VCODEC_AXI_A_CLK] = &vcodec_axi_a_clk.clkr,
2318         [VCODEC_AXI_B_CLK] = &vcodec_axi_b_clk.clkr,
2319         [CSI0_SRC] = &csi0_src.clkr,
2320         [CSI0_CLK] = &csi0_clk.clkr,
2321         [CSI0_PHY_CLK] = &csi0_phy_clk.clkr,
2322         [CSI1_SRC] = &csi1_src.clkr,
2323         [CSI1_CLK] = &csi1_clk.clkr,
2324         [CSI1_PHY_CLK] = &csi1_phy_clk.clkr,
2325         [CSI2_SRC] = &csi2_src.clkr,
2326         [CSI2_CLK] = &csi2_clk.clkr,
2327         [CSI2_PHY_CLK] = &csi2_phy_clk.clkr,
2328         [CSI_PIX_CLK] = &csi_pix_clk.clkr,
2329         [CSI_RDI_CLK] = &csi_rdi_clk.clkr,
2330         [MDP_VSYNC_CLK] = &mdp_vsync_clk.clkr,
2331         [HDMI_APP_CLK] = &hdmi_app_clk.clkr,
2332         [CSI_PIX1_CLK] = &csi_pix1_clk.clkr,
2333         [CSI_RDI2_CLK] = &csi_rdi2_clk.clkr,
2334         [CSI_RDI1_CLK] = &csi_rdi1_clk.clkr,
2335         [GFX2D0_SRC] = &gfx2d0_src.clkr,
2336         [GFX2D0_CLK] = &gfx2d0_clk.clkr,
2337         [GFX2D1_SRC] = &gfx2d1_src.clkr,
2338         [GFX2D1_CLK] = &gfx2d1_clk.clkr,
2339         [GFX3D_SRC] = &gfx3d_src.clkr,
2340         [GFX3D_CLK] = &gfx3d_clk.clkr,
2341         [IJPEG_SRC] = &ijpeg_src.clkr,
2342         [IJPEG_CLK] = &ijpeg_clk.clkr,
2343         [JPEGD_SRC] = &jpegd_src.clkr,
2344         [JPEGD_CLK] = &jpegd_clk.clkr,
2345         [MDP_SRC] = &mdp_src.clkr,
2346         [MDP_CLK] = &mdp_clk.clkr,
2347         [MDP_LUT_CLK] = &mdp_lut_clk.clkr,
2348         [ROT_SRC] = &rot_src.clkr,
2349         [ROT_CLK] = &rot_clk.clkr,
2350         [TV_ENC_CLK] = &tv_enc_clk.clkr,
2351         [TV_DAC_CLK] = &tv_dac_clk.clkr,
2352         [HDMI_TV_CLK] = &hdmi_tv_clk.clkr,
2353         [MDP_TV_CLK] = &mdp_tv_clk.clkr,
2354         [TV_SRC] = &tv_src.clkr,
2355         [VCODEC_SRC] = &vcodec_src.clkr,
2356         [VCODEC_CLK] = &vcodec_clk.clkr,
2357         [VFE_SRC] = &vfe_src.clkr,
2358         [VFE_CLK] = &vfe_clk.clkr,
2359         [VFE_CSI_CLK] = &vfe_csi_clk.clkr,
2360         [VPE_SRC] = &vpe_src.clkr,
2361         [VPE_CLK] = &vpe_clk.clkr,
2362         [CAMCLK0_SRC] = &camclk0_src.clkr,
2363         [CAMCLK0_CLK] = &camclk0_clk.clkr,
2364         [CAMCLK1_SRC] = &camclk1_src.clkr,
2365         [CAMCLK1_CLK] = &camclk1_clk.clkr,
2366         [CAMCLK2_SRC] = &camclk2_src.clkr,
2367         [CAMCLK2_CLK] = &camclk2_clk.clkr,
2368         [CSIPHYTIMER_SRC] = &csiphytimer_src.clkr,
2369         [CSIPHY2_TIMER_CLK] = &csiphy2_timer_clk.clkr,
2370         [CSIPHY1_TIMER_CLK] = &csiphy1_timer_clk.clkr,
2371         [CSIPHY0_TIMER_CLK] = &csiphy0_timer_clk.clkr,
2372         [PLL2] = &pll2.clkr,
2373 };
2374
2375 static const struct qcom_reset_map mmcc_msm8960_resets[] = {
2376         [VPE_AXI_RESET] = { 0x0208, 15 },
2377         [IJPEG_AXI_RESET] = { 0x0208, 14 },
2378         [MPD_AXI_RESET] = { 0x0208, 13 },
2379         [VFE_AXI_RESET] = { 0x0208, 9 },
2380         [SP_AXI_RESET] = { 0x0208, 8 },
2381         [VCODEC_AXI_RESET] = { 0x0208, 7 },
2382         [ROT_AXI_RESET] = { 0x0208, 6 },
2383         [VCODEC_AXI_A_RESET] = { 0x0208, 5 },
2384         [VCODEC_AXI_B_RESET] = { 0x0208, 4 },
2385         [FAB_S3_AXI_RESET] = { 0x0208, 3 },
2386         [FAB_S2_AXI_RESET] = { 0x0208, 2 },
2387         [FAB_S1_AXI_RESET] = { 0x0208, 1 },
2388         [FAB_S0_AXI_RESET] = { 0x0208 },
2389         [SMMU_GFX3D_ABH_RESET] = { 0x020c, 31 },
2390         [SMMU_VPE_AHB_RESET] = { 0x020c, 30 },
2391         [SMMU_VFE_AHB_RESET] = { 0x020c, 29 },
2392         [SMMU_ROT_AHB_RESET] = { 0x020c, 28 },
2393         [SMMU_VCODEC_B_AHB_RESET] = { 0x020c, 27 },
2394         [SMMU_VCODEC_A_AHB_RESET] = { 0x020c, 26 },
2395         [SMMU_MDP1_AHB_RESET] = { 0x020c, 25 },
2396         [SMMU_MDP0_AHB_RESET] = { 0x020c, 24 },
2397         [SMMU_JPEGD_AHB_RESET] = { 0x020c, 23 },
2398         [SMMU_IJPEG_AHB_RESET] = { 0x020c, 22 },
2399         [SMMU_GFX2D0_AHB_RESET] = { 0x020c, 21 },
2400         [SMMU_GFX2D1_AHB_RESET] = { 0x020c, 20 },
2401         [APU_AHB_RESET] = { 0x020c, 18 },
2402         [CSI_AHB_RESET] = { 0x020c, 17 },
2403         [TV_ENC_AHB_RESET] = { 0x020c, 15 },
2404         [VPE_AHB_RESET] = { 0x020c, 14 },
2405         [FABRIC_AHB_RESET] = { 0x020c, 13 },
2406         [GFX2D0_AHB_RESET] = { 0x020c, 12 },
2407         [GFX2D1_AHB_RESET] = { 0x020c, 11 },
2408         [GFX3D_AHB_RESET] = { 0x020c, 10 },
2409         [HDMI_AHB_RESET] = { 0x020c, 9 },
2410         [MSSS_IMEM_AHB_RESET] = { 0x020c, 8 },
2411         [IJPEG_AHB_RESET] = { 0x020c, 7 },
2412         [DSI_M_AHB_RESET] = { 0x020c, 6 },
2413         [DSI_S_AHB_RESET] = { 0x020c, 5 },
2414         [JPEGD_AHB_RESET] = { 0x020c, 4 },
2415         [MDP_AHB_RESET] = { 0x020c, 3 },
2416         [ROT_AHB_RESET] = { 0x020c, 2 },
2417         [VCODEC_AHB_RESET] = { 0x020c, 1 },
2418         [VFE_AHB_RESET] = { 0x020c, 0 },
2419         [DSI2_M_AHB_RESET] = { 0x0210, 31 },
2420         [DSI2_S_AHB_RESET] = { 0x0210, 30 },
2421         [CSIPHY2_RESET] = { 0x0210, 29 },
2422         [CSI_PIX1_RESET] = { 0x0210, 28 },
2423         [CSIPHY0_RESET] = { 0x0210, 27 },
2424         [CSIPHY1_RESET] = { 0x0210, 26 },
2425         [DSI2_RESET] = { 0x0210, 25 },
2426         [VFE_CSI_RESET] = { 0x0210, 24 },
2427         [MDP_RESET] = { 0x0210, 21 },
2428         [AMP_RESET] = { 0x0210, 20 },
2429         [JPEGD_RESET] = { 0x0210, 19 },
2430         [CSI1_RESET] = { 0x0210, 18 },
2431         [VPE_RESET] = { 0x0210, 17 },
2432         [MMSS_FABRIC_RESET] = { 0x0210, 16 },
2433         [VFE_RESET] = { 0x0210, 15 },
2434         [GFX2D0_RESET] = { 0x0210, 14 },
2435         [GFX2D1_RESET] = { 0x0210, 13 },
2436         [GFX3D_RESET] = { 0x0210, 12 },
2437         [HDMI_RESET] = { 0x0210, 11 },
2438         [MMSS_IMEM_RESET] = { 0x0210, 10 },
2439         [IJPEG_RESET] = { 0x0210, 9 },
2440         [CSI0_RESET] = { 0x0210, 8 },
2441         [DSI_RESET] = { 0x0210, 7 },
2442         [VCODEC_RESET] = { 0x0210, 6 },
2443         [MDP_TV_RESET] = { 0x0210, 4 },
2444         [MDP_VSYNC_RESET] = { 0x0210, 3 },
2445         [ROT_RESET] = { 0x0210, 2 },
2446         [TV_HDMI_RESET] = { 0x0210, 1 },
2447         [TV_ENC_RESET] = { 0x0210 },
2448         [CSI2_RESET] = { 0x0214, 2 },
2449         [CSI_RDI1_RESET] = { 0x0214, 1 },
2450         [CSI_RDI2_RESET] = { 0x0214 },
2451 };
2452
2453 static struct clk_regmap *mmcc_apq8064_clks[] = {
2454         [AMP_AHB_CLK] = &amp_ahb_clk.clkr,
2455         [DSI2_S_AHB_CLK] = &dsi2_s_ahb_clk.clkr,
2456         [JPEGD_AHB_CLK] = &jpegd_ahb_clk.clkr,
2457         [DSI_S_AHB_CLK] = &dsi_s_ahb_clk.clkr,
2458         [DSI2_M_AHB_CLK] = &dsi2_m_ahb_clk.clkr,
2459         [VPE_AHB_CLK] = &vpe_ahb_clk.clkr,
2460         [SMMU_AHB_CLK] = &smmu_ahb_clk.clkr,
2461         [HDMI_M_AHB_CLK] = &hdmi_m_ahb_clk.clkr,
2462         [VFE_AHB_CLK] = &vfe_ahb_clk.clkr,
2463         [ROT_AHB_CLK] = &rot_ahb_clk.clkr,
2464         [VCODEC_AHB_CLK] = &vcodec_ahb_clk.clkr,
2465         [MDP_AHB_CLK] = &mdp_ahb_clk.clkr,
2466         [DSI_M_AHB_CLK] = &dsi_m_ahb_clk.clkr,
2467         [CSI_AHB_CLK] = &csi_ahb_clk.clkr,
2468         [MMSS_IMEM_AHB_CLK] = &mmss_imem_ahb_clk.clkr,
2469         [IJPEG_AHB_CLK] = &ijpeg_ahb_clk.clkr,
2470         [HDMI_S_AHB_CLK] = &hdmi_s_ahb_clk.clkr,
2471         [GFX3D_AHB_CLK] = &gfx3d_ahb_clk.clkr,
2472         [JPEGD_AXI_CLK] = &jpegd_axi_clk.clkr,
2473         [GMEM_AXI_CLK] = &gmem_axi_clk.clkr,
2474         [MDP_AXI_CLK] = &mdp_axi_clk.clkr,
2475         [MMSS_IMEM_AXI_CLK] = &mmss_imem_axi_clk.clkr,
2476         [IJPEG_AXI_CLK] = &ijpeg_axi_clk.clkr,
2477         [GFX3D_AXI_CLK] = &gfx3d_axi_clk.clkr,
2478         [VCODEC_AXI_CLK] = &vcodec_axi_clk.clkr,
2479         [VFE_AXI_CLK] = &vfe_axi_clk.clkr,
2480         [VPE_AXI_CLK] = &vpe_axi_clk.clkr,
2481         [ROT_AXI_CLK] = &rot_axi_clk.clkr,
2482         [VCODEC_AXI_A_CLK] = &vcodec_axi_a_clk.clkr,
2483         [VCODEC_AXI_B_CLK] = &vcodec_axi_b_clk.clkr,
2484         [CSI0_SRC] = &csi0_src.clkr,
2485         [CSI0_CLK] = &csi0_clk.clkr,
2486         [CSI0_PHY_CLK] = &csi0_phy_clk.clkr,
2487         [CSI1_SRC] = &csi1_src.clkr,
2488         [CSI1_CLK] = &csi1_clk.clkr,
2489         [CSI1_PHY_CLK] = &csi1_phy_clk.clkr,
2490         [CSI2_SRC] = &csi2_src.clkr,
2491         [CSI2_CLK] = &csi2_clk.clkr,
2492         [CSI2_PHY_CLK] = &csi2_phy_clk.clkr,
2493         [CSI_PIX_CLK] = &csi_pix_clk.clkr,
2494         [CSI_RDI_CLK] = &csi_rdi_clk.clkr,
2495         [MDP_VSYNC_CLK] = &mdp_vsync_clk.clkr,
2496         [HDMI_APP_CLK] = &hdmi_app_clk.clkr,
2497         [CSI_PIX1_CLK] = &csi_pix1_clk.clkr,
2498         [CSI_RDI2_CLK] = &csi_rdi2_clk.clkr,
2499         [CSI_RDI1_CLK] = &csi_rdi1_clk.clkr,
2500         [GFX3D_SRC] = &gfx3d_src.clkr,
2501         [GFX3D_CLK] = &gfx3d_clk.clkr,
2502         [IJPEG_SRC] = &ijpeg_src.clkr,
2503         [IJPEG_CLK] = &ijpeg_clk.clkr,
2504         [JPEGD_SRC] = &jpegd_src.clkr,
2505         [JPEGD_CLK] = &jpegd_clk.clkr,
2506         [MDP_SRC] = &mdp_src.clkr,
2507         [MDP_CLK] = &mdp_clk.clkr,
2508         [MDP_LUT_CLK] = &mdp_lut_clk.clkr,
2509         [ROT_SRC] = &rot_src.clkr,
2510         [ROT_CLK] = &rot_clk.clkr,
2511         [TV_DAC_CLK] = &tv_dac_clk.clkr,
2512         [HDMI_TV_CLK] = &hdmi_tv_clk.clkr,
2513         [MDP_TV_CLK] = &mdp_tv_clk.clkr,
2514         [TV_SRC] = &tv_src.clkr,
2515         [VCODEC_SRC] = &vcodec_src.clkr,
2516         [VCODEC_CLK] = &vcodec_clk.clkr,
2517         [VFE_SRC] = &vfe_src.clkr,
2518         [VFE_CLK] = &vfe_clk.clkr,
2519         [VFE_CSI_CLK] = &vfe_csi_clk.clkr,
2520         [VPE_SRC] = &vpe_src.clkr,
2521         [VPE_CLK] = &vpe_clk.clkr,
2522         [CAMCLK0_SRC] = &camclk0_src.clkr,
2523         [CAMCLK0_CLK] = &camclk0_clk.clkr,
2524         [CAMCLK1_SRC] = &camclk1_src.clkr,
2525         [CAMCLK1_CLK] = &camclk1_clk.clkr,
2526         [CAMCLK2_SRC] = &camclk2_src.clkr,
2527         [CAMCLK2_CLK] = &camclk2_clk.clkr,
2528         [CSIPHYTIMER_SRC] = &csiphytimer_src.clkr,
2529         [CSIPHY2_TIMER_CLK] = &csiphy2_timer_clk.clkr,
2530         [CSIPHY1_TIMER_CLK] = &csiphy1_timer_clk.clkr,
2531         [CSIPHY0_TIMER_CLK] = &csiphy0_timer_clk.clkr,
2532         [PLL2] = &pll2.clkr,
2533         [RGB_TV_CLK] = &rgb_tv_clk.clkr,
2534         [NPL_TV_CLK] = &npl_tv_clk.clkr,
2535         [VCAP_AHB_CLK] = &vcap_ahb_clk.clkr,
2536         [VCAP_AXI_CLK] = &vcap_axi_clk.clkr,
2537         [VCAP_SRC] = &vcap_src.clkr,
2538         [VCAP_CLK] = &vcap_clk.clkr,
2539         [VCAP_NPL_CLK] = &vcap_npl_clk.clkr,
2540         [PLL15] = &pll15.clkr,
2541 };
2542
2543 static const struct qcom_reset_map mmcc_apq8064_resets[] = {
2544         [GFX3D_AXI_RESET] = { 0x0208, 17 },
2545         [VCAP_AXI_RESET] = { 0x0208, 16 },
2546         [VPE_AXI_RESET] = { 0x0208, 15 },
2547         [IJPEG_AXI_RESET] = { 0x0208, 14 },
2548         [MPD_AXI_RESET] = { 0x0208, 13 },
2549         [VFE_AXI_RESET] = { 0x0208, 9 },
2550         [SP_AXI_RESET] = { 0x0208, 8 },
2551         [VCODEC_AXI_RESET] = { 0x0208, 7 },
2552         [ROT_AXI_RESET] = { 0x0208, 6 },
2553         [VCODEC_AXI_A_RESET] = { 0x0208, 5 },
2554         [VCODEC_AXI_B_RESET] = { 0x0208, 4 },
2555         [FAB_S3_AXI_RESET] = { 0x0208, 3 },
2556         [FAB_S2_AXI_RESET] = { 0x0208, 2 },
2557         [FAB_S1_AXI_RESET] = { 0x0208, 1 },
2558         [FAB_S0_AXI_RESET] = { 0x0208 },
2559         [SMMU_GFX3D_ABH_RESET] = { 0x020c, 31 },
2560         [SMMU_VPE_AHB_RESET] = { 0x020c, 30 },
2561         [SMMU_VFE_AHB_RESET] = { 0x020c, 29 },
2562         [SMMU_ROT_AHB_RESET] = { 0x020c, 28 },
2563         [SMMU_VCODEC_B_AHB_RESET] = { 0x020c, 27 },
2564         [SMMU_VCODEC_A_AHB_RESET] = { 0x020c, 26 },
2565         [SMMU_MDP1_AHB_RESET] = { 0x020c, 25 },
2566         [SMMU_MDP0_AHB_RESET] = { 0x020c, 24 },
2567         [SMMU_JPEGD_AHB_RESET] = { 0x020c, 23 },
2568         [SMMU_IJPEG_AHB_RESET] = { 0x020c, 22 },
2569         [APU_AHB_RESET] = { 0x020c, 18 },
2570         [CSI_AHB_RESET] = { 0x020c, 17 },
2571         [TV_ENC_AHB_RESET] = { 0x020c, 15 },
2572         [VPE_AHB_RESET] = { 0x020c, 14 },
2573         [FABRIC_AHB_RESET] = { 0x020c, 13 },
2574         [GFX3D_AHB_RESET] = { 0x020c, 10 },
2575         [HDMI_AHB_RESET] = { 0x020c, 9 },
2576         [MSSS_IMEM_AHB_RESET] = { 0x020c, 8 },
2577         [IJPEG_AHB_RESET] = { 0x020c, 7 },
2578         [DSI_M_AHB_RESET] = { 0x020c, 6 },
2579         [DSI_S_AHB_RESET] = { 0x020c, 5 },
2580         [JPEGD_AHB_RESET] = { 0x020c, 4 },
2581         [MDP_AHB_RESET] = { 0x020c, 3 },
2582         [ROT_AHB_RESET] = { 0x020c, 2 },
2583         [VCODEC_AHB_RESET] = { 0x020c, 1 },
2584         [VFE_AHB_RESET] = { 0x020c, 0 },
2585         [SMMU_VCAP_AHB_RESET] = { 0x0200, 3 },
2586         [VCAP_AHB_RESET] = { 0x0200, 2 },
2587         [DSI2_M_AHB_RESET] = { 0x0200, 1 },
2588         [DSI2_S_AHB_RESET] = { 0x0200, 0 },
2589         [CSIPHY2_RESET] = { 0x0210, 31 },
2590         [CSI_PIX1_RESET] = { 0x0210, 30 },
2591         [CSIPHY0_RESET] = { 0x0210, 29 },
2592         [CSIPHY1_RESET] = { 0x0210, 28 },
2593         [CSI_RDI_RESET] = { 0x0210, 27 },
2594         [CSI_PIX_RESET] = { 0x0210, 26 },
2595         [DSI2_RESET] = { 0x0210, 25 },
2596         [VFE_CSI_RESET] = { 0x0210, 24 },
2597         [MDP_RESET] = { 0x0210, 21 },
2598         [AMP_RESET] = { 0x0210, 20 },
2599         [JPEGD_RESET] = { 0x0210, 19 },
2600         [CSI1_RESET] = { 0x0210, 18 },
2601         [VPE_RESET] = { 0x0210, 17 },
2602         [MMSS_FABRIC_RESET] = { 0x0210, 16 },
2603         [VFE_RESET] = { 0x0210, 15 },
2604         [GFX3D_RESET] = { 0x0210, 12 },
2605         [HDMI_RESET] = { 0x0210, 11 },
2606         [MMSS_IMEM_RESET] = { 0x0210, 10 },
2607         [IJPEG_RESET] = { 0x0210, 9 },
2608         [CSI0_RESET] = { 0x0210, 8 },
2609         [DSI_RESET] = { 0x0210, 7 },
2610         [VCODEC_RESET] = { 0x0210, 6 },
2611         [MDP_TV_RESET] = { 0x0210, 4 },
2612         [MDP_VSYNC_RESET] = { 0x0210, 3 },
2613         [ROT_RESET] = { 0x0210, 2 },
2614         [TV_HDMI_RESET] = { 0x0210, 1 },
2615         [VCAP_NPL_RESET] = { 0x0214, 4 },
2616         [VCAP_RESET] = { 0x0214, 3 },
2617         [CSI2_RESET] = { 0x0214, 2 },
2618         [CSI_RDI1_RESET] = { 0x0214, 1 },
2619         [CSI_RDI2_RESET] = { 0x0214 },
2620 };
2621
2622 static const struct regmap_config mmcc_msm8960_regmap_config = {
2623         .reg_bits       = 32,
2624         .reg_stride     = 4,
2625         .val_bits       = 32,
2626         .max_register   = 0x334,
2627         .fast_io        = true,
2628 };
2629
2630 static const struct regmap_config mmcc_apq8064_regmap_config = {
2631         .reg_bits       = 32,
2632         .reg_stride     = 4,
2633         .val_bits       = 32,
2634         .max_register   = 0x350,
2635         .fast_io        = true,
2636 };
2637
2638 static const struct qcom_cc_desc mmcc_msm8960_desc = {
2639         .config = &mmcc_msm8960_regmap_config,
2640         .clks = mmcc_msm8960_clks,
2641         .num_clks = ARRAY_SIZE(mmcc_msm8960_clks),
2642         .resets = mmcc_msm8960_resets,
2643         .num_resets = ARRAY_SIZE(mmcc_msm8960_resets),
2644 };
2645
2646 static const struct qcom_cc_desc mmcc_apq8064_desc = {
2647         .config = &mmcc_apq8064_regmap_config,
2648         .clks = mmcc_apq8064_clks,
2649         .num_clks = ARRAY_SIZE(mmcc_apq8064_clks),
2650         .resets = mmcc_apq8064_resets,
2651         .num_resets = ARRAY_SIZE(mmcc_apq8064_resets),
2652 };
2653
2654 static const struct of_device_id mmcc_msm8960_match_table[] = {
2655         { .compatible = "qcom,mmcc-msm8960", .data = &mmcc_msm8960_desc },
2656         { .compatible = "qcom,mmcc-apq8064", .data = &mmcc_apq8064_desc },
2657         { }
2658 };
2659 MODULE_DEVICE_TABLE(of, mmcc_msm8960_match_table);
2660
2661 static int mmcc_msm8960_probe(struct platform_device *pdev)
2662 {
2663         const struct of_device_id *match;
2664         struct regmap *regmap;
2665         bool is_8064;
2666         struct device *dev = &pdev->dev;
2667
2668         match = of_match_device(mmcc_msm8960_match_table, dev);
2669         if (!match)
2670                 return -EINVAL;
2671
2672         is_8064 = of_device_is_compatible(dev->of_node, "qcom,mmcc-apq8064");
2673         if (is_8064) {
2674                 gfx3d_src.freq_tbl = clk_tbl_gfx3d_8064;
2675                 gfx3d_src.clkr.hw.init = &gfx3d_8064_init;
2676                 gfx3d_src.s[0].parent_map = mmcc_pxo_pll8_pll2_pll15_map;
2677                 gfx3d_src.s[1].parent_map = mmcc_pxo_pll8_pll2_pll15_map;
2678         }
2679
2680         regmap = qcom_cc_map(pdev, match->data);
2681         if (IS_ERR(regmap))
2682                 return PTR_ERR(regmap);
2683
2684         clk_pll_configure_sr(&pll15, regmap, &pll15_config, false);
2685
2686         return qcom_cc_really_probe(pdev, match->data, regmap);
2687 }
2688
2689 static int mmcc_msm8960_remove(struct platform_device *pdev)
2690 {
2691         qcom_cc_remove(pdev);
2692         return 0;
2693 }
2694
2695 static struct platform_driver mmcc_msm8960_driver = {
2696         .probe          = mmcc_msm8960_probe,
2697         .remove         = mmcc_msm8960_remove,
2698         .driver         = {
2699                 .name   = "mmcc-msm8960",
2700                 .of_match_table = mmcc_msm8960_match_table,
2701         },
2702 };
2703
2704 module_platform_driver(mmcc_msm8960_driver);
2705
2706 MODULE_DESCRIPTION("QCOM MMCC MSM8960 Driver");
2707 MODULE_LICENSE("GPL v2");
2708 MODULE_ALIAS("platform:mmcc-msm8960");