2 * Copyright (c) 2013, The Linux Foundation. All rights reserved.
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
14 #include <linux/kernel.h>
15 #include <linux/bitops.h>
16 #include <linux/err.h>
17 #include <linux/delay.h>
18 #include <linux/platform_device.h>
19 #include <linux/module.h>
21 #include <linux/of_device.h>
22 #include <linux/clk-provider.h>
23 #include <linux/regmap.h>
24 #include <linux/reset-controller.h>
26 #include <dt-bindings/clock/qcom,mmcc-msm8960.h>
27 #include <dt-bindings/reset/qcom,mmcc-msm8960.h>
30 #include "clk-regmap.h"
33 #include "clk-branch.h"
41 static u8 mmcc_pxo_pll8_pll2_map[] = {
47 static const char *mmcc_pxo_pll8_pll2[] = {
53 static u8 mmcc_pxo_pll8_pll2_pll3_map[] = {
60 static const char *mmcc_pxo_pll8_pll2_pll3[] = {
67 static struct clk_pll pll2 = {
75 .clkr.hw.init = &(struct clk_init_data){
77 .parent_names = (const char *[]){ "pxo" },
83 static struct freq_tbl clk_tbl_cam[] = {
84 { 6000000, P_PLL8, 4, 1, 16 },
85 { 8000000, P_PLL8, 4, 1, 12 },
86 { 12000000, P_PLL8, 4, 1, 8 },
87 { 16000000, P_PLL8, 4, 1, 6 },
88 { 19200000, P_PLL8, 4, 1, 5 },
89 { 24000000, P_PLL8, 4, 1, 4 },
90 { 32000000, P_PLL8, 4, 1, 3 },
91 { 48000000, P_PLL8, 4, 1, 2 },
92 { 64000000, P_PLL8, 3, 1, 2 },
93 { 96000000, P_PLL8, 4, 0, 0 },
94 { 128000000, P_PLL8, 3, 0, 0 },
98 static struct clk_rcg camclk0_src = {
103 .mnctr_reset_bit = 8,
105 .mnctr_mode_shift = 6,
116 .parent_map = mmcc_pxo_pll8_pll2_map,
118 .freq_tbl = clk_tbl_cam,
120 .enable_reg = 0x0140,
121 .enable_mask = BIT(2),
122 .hw.init = &(struct clk_init_data){
123 .name = "camclk0_src",
124 .parent_names = mmcc_pxo_pll8_pll2,
131 static struct clk_branch camclk0_clk = {
135 .enable_reg = 0x0140,
136 .enable_mask = BIT(0),
137 .hw.init = &(struct clk_init_data){
138 .name = "camclk0_clk",
139 .parent_names = (const char *[]){ "camclk0_src" },
141 .ops = &clk_branch_ops,
147 static struct clk_rcg camclk1_src = {
152 .mnctr_reset_bit = 8,
154 .mnctr_mode_shift = 6,
165 .parent_map = mmcc_pxo_pll8_pll2_map,
167 .freq_tbl = clk_tbl_cam,
169 .enable_reg = 0x0154,
170 .enable_mask = BIT(2),
171 .hw.init = &(struct clk_init_data){
172 .name = "camclk1_src",
173 .parent_names = mmcc_pxo_pll8_pll2,
180 static struct clk_branch camclk1_clk = {
184 .enable_reg = 0x0154,
185 .enable_mask = BIT(0),
186 .hw.init = &(struct clk_init_data){
187 .name = "camclk1_clk",
188 .parent_names = (const char *[]){ "camclk1_src" },
190 .ops = &clk_branch_ops,
196 static struct clk_rcg camclk2_src = {
201 .mnctr_reset_bit = 8,
203 .mnctr_mode_shift = 6,
214 .parent_map = mmcc_pxo_pll8_pll2_map,
216 .freq_tbl = clk_tbl_cam,
218 .enable_reg = 0x0220,
219 .enable_mask = BIT(2),
220 .hw.init = &(struct clk_init_data){
221 .name = "camclk2_src",
222 .parent_names = mmcc_pxo_pll8_pll2,
229 static struct clk_branch camclk2_clk = {
233 .enable_reg = 0x0220,
234 .enable_mask = BIT(0),
235 .hw.init = &(struct clk_init_data){
236 .name = "camclk2_clk",
237 .parent_names = (const char *[]){ "camclk2_src" },
239 .ops = &clk_branch_ops,
245 static struct freq_tbl clk_tbl_csi[] = {
246 { 27000000, P_PXO, 1, 0, 0 },
247 { 85330000, P_PLL8, 1, 2, 9 },
248 { 177780000, P_PLL2, 1, 2, 9 },
252 static struct clk_rcg csi0_src = {
257 .mnctr_reset_bit = 7,
258 .mnctr_mode_shift = 6,
269 .parent_map = mmcc_pxo_pll8_pll2_map,
271 .freq_tbl = clk_tbl_csi,
273 .enable_reg = 0x0040,
274 .enable_mask = BIT(2),
275 .hw.init = &(struct clk_init_data){
277 .parent_names = mmcc_pxo_pll8_pll2,
284 static struct clk_branch csi0_clk = {
288 .enable_reg = 0x0040,
289 .enable_mask = BIT(0),
290 .hw.init = &(struct clk_init_data){
291 .parent_names = (const char *[]){ "csi0_src" },
294 .ops = &clk_branch_ops,
295 .flags = CLK_SET_RATE_PARENT,
300 static struct clk_branch csi0_phy_clk = {
304 .enable_reg = 0x0040,
305 .enable_mask = BIT(8),
306 .hw.init = &(struct clk_init_data){
307 .parent_names = (const char *[]){ "csi0_src" },
309 .name = "csi0_phy_clk",
310 .ops = &clk_branch_ops,
311 .flags = CLK_SET_RATE_PARENT,
316 static struct clk_rcg csi1_src = {
321 .mnctr_reset_bit = 7,
322 .mnctr_mode_shift = 6,
333 .parent_map = mmcc_pxo_pll8_pll2_map,
335 .freq_tbl = clk_tbl_csi,
337 .enable_reg = 0x0024,
338 .enable_mask = BIT(2),
339 .hw.init = &(struct clk_init_data){
341 .parent_names = mmcc_pxo_pll8_pll2,
348 static struct clk_branch csi1_clk = {
352 .enable_reg = 0x0024,
353 .enable_mask = BIT(0),
354 .hw.init = &(struct clk_init_data){
355 .parent_names = (const char *[]){ "csi1_src" },
358 .ops = &clk_branch_ops,
359 .flags = CLK_SET_RATE_PARENT,
364 static struct clk_branch csi1_phy_clk = {
368 .enable_reg = 0x0024,
369 .enable_mask = BIT(8),
370 .hw.init = &(struct clk_init_data){
371 .parent_names = (const char *[]){ "csi1_src" },
373 .name = "csi1_phy_clk",
374 .ops = &clk_branch_ops,
375 .flags = CLK_SET_RATE_PARENT,
380 static struct clk_rcg csi2_src = {
385 .mnctr_reset_bit = 7,
386 .mnctr_mode_shift = 6,
397 .parent_map = mmcc_pxo_pll8_pll2_map,
399 .freq_tbl = clk_tbl_csi,
401 .enable_reg = 0x022c,
402 .enable_mask = BIT(2),
403 .hw.init = &(struct clk_init_data){
405 .parent_names = mmcc_pxo_pll8_pll2,
412 static struct clk_branch csi2_clk = {
416 .enable_reg = 0x022c,
417 .enable_mask = BIT(0),
418 .hw.init = &(struct clk_init_data){
419 .parent_names = (const char *[]){ "csi2_src" },
422 .ops = &clk_branch_ops,
423 .flags = CLK_SET_RATE_PARENT,
428 static struct clk_branch csi2_phy_clk = {
432 .enable_reg = 0x022c,
433 .enable_mask = BIT(8),
434 .hw.init = &(struct clk_init_data){
435 .parent_names = (const char *[]){ "csi2_src" },
437 .name = "csi2_phy_clk",
438 .ops = &clk_branch_ops,
439 .flags = CLK_SET_RATE_PARENT,
449 struct clk_regmap clkr;
452 #define to_clk_pix_rdi(_hw) \
453 container_of(to_clk_regmap(_hw), struct clk_pix_rdi, clkr)
455 static int pix_rdi_set_parent(struct clk_hw *hw, u8 index)
460 struct clk_pix_rdi *rdi = to_clk_pix_rdi(hw);
461 struct clk *clk = hw->clk;
462 int num_parents = __clk_get_num_parents(hw->clk);
465 * These clocks select three inputs via two muxes. One mux selects
466 * between csi0 and csi1 and the second mux selects between that mux's
467 * output and csi2. The source and destination selections for each
468 * mux must be clocking for the switch to succeed so just turn on
469 * all three sources because it's easier than figuring out what source
470 * needs to be on at what time.
472 for (i = 0; i < num_parents; i++) {
473 ret = clk_prepare_enable(clk_get_parent_by_index(clk, i));
482 regmap_update_bits(rdi->clkr.regmap, rdi->s2_reg, rdi->s2_mask, val);
484 * Wait at least 6 cycles of slowest clock
485 * for the glitch-free MUX to fully switch sources.
493 regmap_update_bits(rdi->clkr.regmap, rdi->s_reg, rdi->s_mask, val);
495 * Wait at least 6 cycles of slowest clock
496 * for the glitch-free MUX to fully switch sources.
501 for (i--; i >= 0; i--)
502 clk_disable_unprepare(clk_get_parent_by_index(clk, i));
507 static u8 pix_rdi_get_parent(struct clk_hw *hw)
510 struct clk_pix_rdi *rdi = to_clk_pix_rdi(hw);
513 regmap_read(rdi->clkr.regmap, rdi->s2_reg, &val);
514 if (val & rdi->s2_mask)
517 regmap_read(rdi->clkr.regmap, rdi->s_reg, &val);
518 if (val & rdi->s_mask)
524 static const struct clk_ops clk_ops_pix_rdi = {
525 .enable = clk_enable_regmap,
526 .disable = clk_disable_regmap,
527 .set_parent = pix_rdi_set_parent,
528 .get_parent = pix_rdi_get_parent,
529 .determine_rate = __clk_mux_determine_rate,
532 static const char *pix_rdi_parents[] = {
538 static struct clk_pix_rdi csi_pix_clk = {
544 .enable_reg = 0x0058,
545 .enable_mask = BIT(26),
546 .hw.init = &(struct clk_init_data){
547 .name = "csi_pix_clk",
548 .parent_names = pix_rdi_parents,
550 .ops = &clk_ops_pix_rdi,
555 static struct clk_pix_rdi csi_pix1_clk = {
561 .enable_reg = 0x0238,
562 .enable_mask = BIT(10),
563 .hw.init = &(struct clk_init_data){
564 .name = "csi_pix1_clk",
565 .parent_names = pix_rdi_parents,
567 .ops = &clk_ops_pix_rdi,
572 static struct clk_pix_rdi csi_rdi_clk = {
578 .enable_reg = 0x0058,
579 .enable_mask = BIT(13),
580 .hw.init = &(struct clk_init_data){
581 .name = "csi_rdi_clk",
582 .parent_names = pix_rdi_parents,
584 .ops = &clk_ops_pix_rdi,
589 static struct clk_pix_rdi csi_rdi1_clk = {
595 .enable_reg = 0x0238,
596 .enable_mask = BIT(2),
597 .hw.init = &(struct clk_init_data){
598 .name = "csi_rdi1_clk",
599 .parent_names = pix_rdi_parents,
601 .ops = &clk_ops_pix_rdi,
606 static struct clk_pix_rdi csi_rdi2_clk = {
612 .enable_reg = 0x0238,
613 .enable_mask = BIT(6),
614 .hw.init = &(struct clk_init_data){
615 .name = "csi_rdi2_clk",
616 .parent_names = pix_rdi_parents,
618 .ops = &clk_ops_pix_rdi,
623 static struct freq_tbl clk_tbl_csiphytimer[] = {
624 { 85330000, P_PLL8, 1, 2, 9 },
625 { 177780000, P_PLL2, 1, 2, 9 },
629 static struct clk_rcg csiphytimer_src = {
634 .mnctr_reset_bit = 8,
636 .mnctr_mode_shift = 6,
647 .parent_map = mmcc_pxo_pll8_pll2_map,
649 .freq_tbl = clk_tbl_csiphytimer,
651 .enable_reg = 0x0160,
652 .enable_mask = BIT(2),
653 .hw.init = &(struct clk_init_data){
654 .name = "csiphytimer_src",
655 .parent_names = mmcc_pxo_pll8_pll2,
662 static const char *csixphy_timer_src[] = { "csiphytimer_src" };
664 static struct clk_branch csiphy0_timer_clk = {
668 .enable_reg = 0x0160,
669 .enable_mask = BIT(0),
670 .hw.init = &(struct clk_init_data){
671 .parent_names = csixphy_timer_src,
673 .name = "csiphy0_timer_clk",
674 .ops = &clk_branch_ops,
675 .flags = CLK_SET_RATE_PARENT,
680 static struct clk_branch csiphy1_timer_clk = {
684 .enable_reg = 0x0160,
685 .enable_mask = BIT(9),
686 .hw.init = &(struct clk_init_data){
687 .parent_names = csixphy_timer_src,
689 .name = "csiphy1_timer_clk",
690 .ops = &clk_branch_ops,
691 .flags = CLK_SET_RATE_PARENT,
696 static struct clk_branch csiphy2_timer_clk = {
700 .enable_reg = 0x0160,
701 .enable_mask = BIT(11),
702 .hw.init = &(struct clk_init_data){
703 .parent_names = csixphy_timer_src,
705 .name = "csiphy2_timer_clk",
706 .ops = &clk_branch_ops,
707 .flags = CLK_SET_RATE_PARENT,
712 static struct freq_tbl clk_tbl_gfx2d[] = {
713 { 27000000, P_PXO, 1, 0 },
714 { 48000000, P_PLL8, 1, 8 },
715 { 54857000, P_PLL8, 1, 7 },
716 { 64000000, P_PLL8, 1, 6 },
717 { 76800000, P_PLL8, 1, 5 },
718 { 96000000, P_PLL8, 1, 4 },
719 { 128000000, P_PLL8, 1, 3 },
720 { 145455000, P_PLL2, 2, 11 },
721 { 160000000, P_PLL2, 1, 5 },
722 { 177778000, P_PLL2, 2, 9 },
723 { 200000000, P_PLL2, 1, 4 },
724 { 228571000, P_PLL2, 2, 7 },
728 static struct clk_dyn_rcg gfx2d0_src = {
734 .mnctr_reset_bit = 25,
735 .mnctr_mode_shift = 9,
742 .mnctr_reset_bit = 24,
743 .mnctr_mode_shift = 6,
750 .parent_map = mmcc_pxo_pll8_pll2_map,
754 .parent_map = mmcc_pxo_pll8_pll2_map,
757 .freq_tbl = clk_tbl_gfx2d,
759 .enable_reg = 0x0060,
760 .enable_mask = BIT(2),
761 .hw.init = &(struct clk_init_data){
762 .name = "gfx2d0_src",
763 .parent_names = mmcc_pxo_pll8_pll2,
765 .ops = &clk_dyn_rcg_ops,
770 static struct clk_branch gfx2d0_clk = {
774 .enable_reg = 0x0060,
775 .enable_mask = BIT(0),
776 .hw.init = &(struct clk_init_data){
777 .name = "gfx2d0_clk",
778 .parent_names = (const char *[]){ "gfx2d0_src" },
780 .ops = &clk_branch_ops,
781 .flags = CLK_SET_RATE_PARENT,
786 static struct clk_dyn_rcg gfx2d1_src = {
792 .mnctr_reset_bit = 25,
793 .mnctr_mode_shift = 9,
800 .mnctr_reset_bit = 24,
801 .mnctr_mode_shift = 6,
808 .parent_map = mmcc_pxo_pll8_pll2_map,
812 .parent_map = mmcc_pxo_pll8_pll2_map,
815 .freq_tbl = clk_tbl_gfx2d,
817 .enable_reg = 0x0074,
818 .enable_mask = BIT(2),
819 .hw.init = &(struct clk_init_data){
820 .name = "gfx2d1_src",
821 .parent_names = mmcc_pxo_pll8_pll2,
823 .ops = &clk_dyn_rcg_ops,
828 static struct clk_branch gfx2d1_clk = {
832 .enable_reg = 0x0074,
833 .enable_mask = BIT(0),
834 .hw.init = &(struct clk_init_data){
835 .name = "gfx2d1_clk",
836 .parent_names = (const char *[]){ "gfx2d1_src" },
838 .ops = &clk_branch_ops,
839 .flags = CLK_SET_RATE_PARENT,
844 static struct freq_tbl clk_tbl_gfx3d[] = {
845 { 27000000, P_PXO, 1, 0 },
846 { 48000000, P_PLL8, 1, 8 },
847 { 54857000, P_PLL8, 1, 7 },
848 { 64000000, P_PLL8, 1, 6 },
849 { 76800000, P_PLL8, 1, 5 },
850 { 96000000, P_PLL8, 1, 4 },
851 { 128000000, P_PLL8, 1, 3 },
852 { 145455000, P_PLL2, 2, 11 },
853 { 160000000, P_PLL2, 1, 5 },
854 { 177778000, P_PLL2, 2, 9 },
855 { 200000000, P_PLL2, 1, 4 },
856 { 228571000, P_PLL2, 2, 7 },
857 { 266667000, P_PLL2, 1, 3 },
858 { 300000000, P_PLL3, 1, 4 },
859 { 320000000, P_PLL2, 2, 5 },
860 { 400000000, P_PLL2, 1, 2 },
864 static struct clk_dyn_rcg gfx3d_src = {
870 .mnctr_reset_bit = 25,
871 .mnctr_mode_shift = 9,
878 .mnctr_reset_bit = 24,
879 .mnctr_mode_shift = 6,
886 .parent_map = mmcc_pxo_pll8_pll2_pll3_map,
890 .parent_map = mmcc_pxo_pll8_pll2_pll3_map,
893 .freq_tbl = clk_tbl_gfx3d,
895 .enable_reg = 0x0080,
896 .enable_mask = BIT(2),
897 .hw.init = &(struct clk_init_data){
899 .parent_names = mmcc_pxo_pll8_pll2_pll3,
901 .ops = &clk_dyn_rcg_ops,
906 static struct clk_branch gfx3d_clk = {
910 .enable_reg = 0x0080,
911 .enable_mask = BIT(0),
912 .hw.init = &(struct clk_init_data){
914 .parent_names = (const char *[]){ "gfx3d_src" },
916 .ops = &clk_branch_ops,
917 .flags = CLK_SET_RATE_PARENT,
922 static struct freq_tbl clk_tbl_ijpeg[] = {
923 { 27000000, P_PXO, 1, 0, 0 },
924 { 36570000, P_PLL8, 1, 2, 21 },
925 { 54860000, P_PLL8, 7, 0, 0 },
926 { 96000000, P_PLL8, 4, 0, 0 },
927 { 109710000, P_PLL8, 1, 2, 7 },
928 { 128000000, P_PLL8, 3, 0, 0 },
929 { 153600000, P_PLL8, 1, 2, 5 },
930 { 200000000, P_PLL2, 4, 0, 0 },
931 { 228571000, P_PLL2, 1, 2, 7 },
932 { 266667000, P_PLL2, 1, 1, 3 },
933 { 320000000, P_PLL2, 1, 2, 5 },
937 static struct clk_rcg ijpeg_src = {
942 .mnctr_reset_bit = 7,
943 .mnctr_mode_shift = 6,
954 .parent_map = mmcc_pxo_pll8_pll2_map,
956 .freq_tbl = clk_tbl_ijpeg,
958 .enable_reg = 0x0098,
959 .enable_mask = BIT(2),
960 .hw.init = &(struct clk_init_data){
962 .parent_names = mmcc_pxo_pll8_pll2,
969 static struct clk_branch ijpeg_clk = {
973 .enable_reg = 0x0098,
974 .enable_mask = BIT(0),
975 .hw.init = &(struct clk_init_data){
977 .parent_names = (const char *[]){ "ijpeg_src" },
979 .ops = &clk_branch_ops,
980 .flags = CLK_SET_RATE_PARENT,
985 static struct freq_tbl clk_tbl_jpegd[] = {
986 { 64000000, P_PLL8, 6 },
987 { 76800000, P_PLL8, 5 },
988 { 96000000, P_PLL8, 4 },
989 { 160000000, P_PLL2, 5 },
990 { 200000000, P_PLL2, 4 },
994 static struct clk_rcg jpegd_src = {
1002 .parent_map = mmcc_pxo_pll8_pll2_map,
1004 .freq_tbl = clk_tbl_jpegd,
1006 .enable_reg = 0x00a4,
1007 .enable_mask = BIT(2),
1008 .hw.init = &(struct clk_init_data){
1009 .name = "jpegd_src",
1010 .parent_names = mmcc_pxo_pll8_pll2,
1012 .ops = &clk_rcg_ops,
1017 static struct clk_branch jpegd_clk = {
1021 .enable_reg = 0x00a4,
1022 .enable_mask = BIT(0),
1023 .hw.init = &(struct clk_init_data){
1024 .name = "jpegd_clk",
1025 .parent_names = (const char *[]){ "jpegd_src" },
1027 .ops = &clk_branch_ops,
1028 .flags = CLK_SET_RATE_PARENT,
1033 static struct freq_tbl clk_tbl_mdp[] = {
1034 { 9600000, P_PLL8, 1, 1, 40 },
1035 { 13710000, P_PLL8, 1, 1, 28 },
1036 { 27000000, P_PXO, 1, 0, 0 },
1037 { 29540000, P_PLL8, 1, 1, 13 },
1038 { 34910000, P_PLL8, 1, 1, 11 },
1039 { 38400000, P_PLL8, 1, 1, 10 },
1040 { 59080000, P_PLL8, 1, 2, 13 },
1041 { 76800000, P_PLL8, 1, 1, 5 },
1042 { 85330000, P_PLL8, 1, 2, 9 },
1043 { 96000000, P_PLL8, 1, 1, 4 },
1044 { 128000000, P_PLL8, 1, 1, 3 },
1045 { 160000000, P_PLL2, 1, 1, 5 },
1046 { 177780000, P_PLL2, 1, 2, 9 },
1047 { 200000000, P_PLL2, 1, 1, 4 },
1048 { 228571000, P_PLL2, 1, 2, 7 },
1049 { 266667000, P_PLL2, 1, 1, 3 },
1053 static struct clk_dyn_rcg mdp_src = {
1055 .md_reg[0] = 0x00c4,
1056 .md_reg[1] = 0x00c8,
1059 .mnctr_reset_bit = 31,
1060 .mnctr_mode_shift = 9,
1067 .mnctr_reset_bit = 30,
1068 .mnctr_mode_shift = 6,
1075 .parent_map = mmcc_pxo_pll8_pll2_map,
1079 .parent_map = mmcc_pxo_pll8_pll2_map,
1082 .freq_tbl = clk_tbl_mdp,
1084 .enable_reg = 0x00c0,
1085 .enable_mask = BIT(2),
1086 .hw.init = &(struct clk_init_data){
1088 .parent_names = mmcc_pxo_pll8_pll2,
1090 .ops = &clk_dyn_rcg_ops,
1095 static struct clk_branch mdp_clk = {
1099 .enable_reg = 0x00c0,
1100 .enable_mask = BIT(0),
1101 .hw.init = &(struct clk_init_data){
1103 .parent_names = (const char *[]){ "mdp_src" },
1105 .ops = &clk_branch_ops,
1106 .flags = CLK_SET_RATE_PARENT,
1111 static struct clk_branch mdp_lut_clk = {
1115 .enable_reg = 0x016c,
1116 .enable_mask = BIT(0),
1117 .hw.init = &(struct clk_init_data){
1118 .parent_names = (const char *[]){ "mdp_clk" },
1120 .name = "mdp_lut_clk",
1121 .ops = &clk_branch_ops,
1122 .flags = CLK_SET_RATE_PARENT,
1127 static struct clk_branch mdp_vsync_clk = {
1131 .enable_reg = 0x0058,
1132 .enable_mask = BIT(6),
1133 .hw.init = &(struct clk_init_data){
1134 .name = "mdp_vsync_clk",
1135 .parent_names = (const char *[]){ "pxo" },
1137 .ops = &clk_branch_ops
1142 static struct freq_tbl clk_tbl_rot[] = {
1143 { 27000000, P_PXO, 1 },
1144 { 29540000, P_PLL8, 13 },
1145 { 32000000, P_PLL8, 12 },
1146 { 38400000, P_PLL8, 10 },
1147 { 48000000, P_PLL8, 8 },
1148 { 54860000, P_PLL8, 7 },
1149 { 64000000, P_PLL8, 6 },
1150 { 76800000, P_PLL8, 5 },
1151 { 96000000, P_PLL8, 4 },
1152 { 100000000, P_PLL2, 8 },
1153 { 114290000, P_PLL2, 7 },
1154 { 133330000, P_PLL2, 6 },
1155 { 160000000, P_PLL2, 5 },
1156 { 200000000, P_PLL2, 4 },
1160 static struct clk_dyn_rcg rot_src = {
1163 .pre_div_shift = 22,
1167 .pre_div_shift = 26,
1171 .src_sel_shift = 16,
1172 .parent_map = mmcc_pxo_pll8_pll2_map,
1175 .src_sel_shift = 19,
1176 .parent_map = mmcc_pxo_pll8_pll2_map,
1179 .freq_tbl = clk_tbl_rot,
1181 .enable_reg = 0x00e0,
1182 .enable_mask = BIT(2),
1183 .hw.init = &(struct clk_init_data){
1185 .parent_names = mmcc_pxo_pll8_pll2,
1187 .ops = &clk_dyn_rcg_ops,
1192 static struct clk_branch rot_clk = {
1196 .enable_reg = 0x00e0,
1197 .enable_mask = BIT(0),
1198 .hw.init = &(struct clk_init_data){
1200 .parent_names = (const char *[]){ "rot_src" },
1202 .ops = &clk_branch_ops,
1203 .flags = CLK_SET_RATE_PARENT,
1208 #define P_HDMI_PLL 1
1210 static u8 mmcc_pxo_hdmi_map[] = {
1215 static const char *mmcc_pxo_hdmi[] = {
1220 static struct freq_tbl clk_tbl_tv[] = {
1221 { 25200000, P_HDMI_PLL, 1, 0, 0 },
1222 { 27000000, P_HDMI_PLL, 1, 0, 0 },
1223 { 27030000, P_HDMI_PLL, 1, 0, 0 },
1224 { 74250000, P_HDMI_PLL, 1, 0, 0 },
1225 { 108000000, P_HDMI_PLL, 1, 0, 0 },
1226 { 148500000, P_HDMI_PLL, 1, 0, 0 },
1230 static struct clk_rcg tv_src = {
1235 .mnctr_reset_bit = 7,
1236 .mnctr_mode_shift = 6,
1242 .pre_div_shift = 14,
1247 .parent_map = mmcc_pxo_hdmi_map,
1249 .freq_tbl = clk_tbl_tv,
1251 .enable_reg = 0x00ec,
1252 .enable_mask = BIT(2),
1253 .hw.init = &(struct clk_init_data){
1255 .parent_names = mmcc_pxo_hdmi,
1257 .ops = &clk_rcg_ops,
1258 .flags = CLK_SET_RATE_PARENT,
1263 static const char *tv_src_name[] = { "tv_src" };
1265 static struct clk_branch tv_enc_clk = {
1269 .enable_reg = 0x00ec,
1270 .enable_mask = BIT(8),
1271 .hw.init = &(struct clk_init_data){
1272 .parent_names = tv_src_name,
1274 .name = "tv_enc_clk",
1275 .ops = &clk_branch_ops,
1276 .flags = CLK_SET_RATE_PARENT,
1281 static struct clk_branch tv_dac_clk = {
1285 .enable_reg = 0x00ec,
1286 .enable_mask = BIT(10),
1287 .hw.init = &(struct clk_init_data){
1288 .parent_names = tv_src_name,
1290 .name = "tv_dac_clk",
1291 .ops = &clk_branch_ops,
1292 .flags = CLK_SET_RATE_PARENT,
1297 static struct clk_branch mdp_tv_clk = {
1301 .enable_reg = 0x00ec,
1302 .enable_mask = BIT(0),
1303 .hw.init = &(struct clk_init_data){
1304 .parent_names = tv_src_name,
1306 .name = "mdp_tv_clk",
1307 .ops = &clk_branch_ops,
1308 .flags = CLK_SET_RATE_PARENT,
1313 static struct clk_branch hdmi_tv_clk = {
1317 .enable_reg = 0x00ec,
1318 .enable_mask = BIT(12),
1319 .hw.init = &(struct clk_init_data){
1320 .parent_names = tv_src_name,
1322 .name = "hdmi_tv_clk",
1323 .ops = &clk_branch_ops,
1324 .flags = CLK_SET_RATE_PARENT,
1329 static struct clk_branch hdmi_app_clk = {
1333 .enable_reg = 0x005c,
1334 .enable_mask = BIT(11),
1335 .hw.init = &(struct clk_init_data){
1336 .parent_names = (const char *[]){ "pxo" },
1338 .name = "hdmi_app_clk",
1339 .ops = &clk_branch_ops,
1344 static struct freq_tbl clk_tbl_vcodec[] = {
1345 { 27000000, P_PXO, 1, 0 },
1346 { 32000000, P_PLL8, 1, 12 },
1347 { 48000000, P_PLL8, 1, 8 },
1348 { 54860000, P_PLL8, 1, 7 },
1349 { 96000000, P_PLL8, 1, 4 },
1350 { 133330000, P_PLL2, 1, 6 },
1351 { 200000000, P_PLL2, 1, 4 },
1352 { 228570000, P_PLL2, 2, 7 },
1353 { 266670000, P_PLL2, 1, 3 },
1357 static struct clk_dyn_rcg vcodec_src = {
1359 .md_reg[0] = 0x00fc,
1360 .md_reg[1] = 0x0128,
1363 .mnctr_reset_bit = 31,
1364 .mnctr_mode_shift = 6,
1371 .mnctr_reset_bit = 30,
1372 .mnctr_mode_shift = 11,
1378 .src_sel_shift = 27,
1379 .parent_map = mmcc_pxo_pll8_pll2_map,
1383 .parent_map = mmcc_pxo_pll8_pll2_map,
1386 .freq_tbl = clk_tbl_vcodec,
1388 .enable_reg = 0x00f8,
1389 .enable_mask = BIT(2),
1390 .hw.init = &(struct clk_init_data){
1391 .name = "vcodec_src",
1392 .parent_names = mmcc_pxo_pll8_pll2,
1394 .ops = &clk_dyn_rcg_ops,
1399 static struct clk_branch vcodec_clk = {
1403 .enable_reg = 0x00f8,
1404 .enable_mask = BIT(0),
1405 .hw.init = &(struct clk_init_data){
1406 .name = "vcodec_clk",
1407 .parent_names = (const char *[]){ "vcodec_src" },
1409 .ops = &clk_branch_ops,
1410 .flags = CLK_SET_RATE_PARENT,
1415 static struct freq_tbl clk_tbl_vpe[] = {
1416 { 27000000, P_PXO, 1 },
1417 { 34909000, P_PLL8, 11 },
1418 { 38400000, P_PLL8, 10 },
1419 { 64000000, P_PLL8, 6 },
1420 { 76800000, P_PLL8, 5 },
1421 { 96000000, P_PLL8, 4 },
1422 { 100000000, P_PLL2, 8 },
1423 { 160000000, P_PLL2, 5 },
1427 static struct clk_rcg vpe_src = {
1430 .pre_div_shift = 12,
1435 .parent_map = mmcc_pxo_pll8_pll2_map,
1437 .freq_tbl = clk_tbl_vpe,
1439 .enable_reg = 0x0110,
1440 .enable_mask = BIT(2),
1441 .hw.init = &(struct clk_init_data){
1443 .parent_names = mmcc_pxo_pll8_pll2,
1445 .ops = &clk_rcg_ops,
1450 static struct clk_branch vpe_clk = {
1454 .enable_reg = 0x0110,
1455 .enable_mask = BIT(0),
1456 .hw.init = &(struct clk_init_data){
1458 .parent_names = (const char *[]){ "vpe_src" },
1460 .ops = &clk_branch_ops,
1461 .flags = CLK_SET_RATE_PARENT,
1466 static struct freq_tbl clk_tbl_vfe[] = {
1467 { 13960000, P_PLL8, 1, 2, 55 },
1468 { 27000000, P_PXO, 1, 0, 0 },
1469 { 36570000, P_PLL8, 1, 2, 21 },
1470 { 38400000, P_PLL8, 2, 1, 5 },
1471 { 45180000, P_PLL8, 1, 2, 17 },
1472 { 48000000, P_PLL8, 2, 1, 4 },
1473 { 54860000, P_PLL8, 1, 1, 7 },
1474 { 64000000, P_PLL8, 2, 1, 3 },
1475 { 76800000, P_PLL8, 1, 1, 5 },
1476 { 96000000, P_PLL8, 2, 1, 2 },
1477 { 109710000, P_PLL8, 1, 2, 7 },
1478 { 128000000, P_PLL8, 1, 1, 3 },
1479 { 153600000, P_PLL8, 1, 2, 5 },
1480 { 200000000, P_PLL2, 2, 1, 2 },
1481 { 228570000, P_PLL2, 1, 2, 7 },
1482 { 266667000, P_PLL2, 1, 1, 3 },
1483 { 320000000, P_PLL2, 1, 2, 5 },
1487 static struct clk_rcg vfe_src = {
1491 .mnctr_reset_bit = 7,
1492 .mnctr_mode_shift = 6,
1498 .pre_div_shift = 10,
1503 .parent_map = mmcc_pxo_pll8_pll2_map,
1505 .freq_tbl = clk_tbl_vfe,
1507 .enable_reg = 0x0104,
1508 .enable_mask = BIT(2),
1509 .hw.init = &(struct clk_init_data){
1511 .parent_names = mmcc_pxo_pll8_pll2,
1513 .ops = &clk_rcg_ops,
1518 static struct clk_branch vfe_clk = {
1522 .enable_reg = 0x0104,
1523 .enable_mask = BIT(0),
1524 .hw.init = &(struct clk_init_data){
1526 .parent_names = (const char *[]){ "vfe_src" },
1528 .ops = &clk_branch_ops,
1529 .flags = CLK_SET_RATE_PARENT,
1534 static struct clk_branch vfe_csi_clk = {
1538 .enable_reg = 0x0104,
1539 .enable_mask = BIT(12),
1540 .hw.init = &(struct clk_init_data){
1541 .parent_names = (const char *[]){ "vfe_src" },
1543 .name = "vfe_csi_clk",
1544 .ops = &clk_branch_ops,
1545 .flags = CLK_SET_RATE_PARENT,
1550 static struct clk_branch gmem_axi_clk = {
1554 .enable_reg = 0x0018,
1555 .enable_mask = BIT(24),
1556 .hw.init = &(struct clk_init_data){
1557 .name = "gmem_axi_clk",
1558 .ops = &clk_branch_ops,
1559 .flags = CLK_IS_ROOT,
1564 static struct clk_branch ijpeg_axi_clk = {
1570 .enable_reg = 0x0018,
1571 .enable_mask = BIT(21),
1572 .hw.init = &(struct clk_init_data){
1573 .name = "ijpeg_axi_clk",
1574 .ops = &clk_branch_ops,
1575 .flags = CLK_IS_ROOT,
1580 static struct clk_branch mmss_imem_axi_clk = {
1586 .enable_reg = 0x0018,
1587 .enable_mask = BIT(22),
1588 .hw.init = &(struct clk_init_data){
1589 .name = "mmss_imem_axi_clk",
1590 .ops = &clk_branch_ops,
1591 .flags = CLK_IS_ROOT,
1596 static struct clk_branch jpegd_axi_clk = {
1600 .enable_reg = 0x0018,
1601 .enable_mask = BIT(25),
1602 .hw.init = &(struct clk_init_data){
1603 .name = "jpegd_axi_clk",
1604 .ops = &clk_branch_ops,
1605 .flags = CLK_IS_ROOT,
1610 static struct clk_branch vcodec_axi_b_clk = {
1616 .enable_reg = 0x0114,
1617 .enable_mask = BIT(23),
1618 .hw.init = &(struct clk_init_data){
1619 .name = "vcodec_axi_b_clk",
1620 .ops = &clk_branch_ops,
1621 .flags = CLK_IS_ROOT,
1626 static struct clk_branch vcodec_axi_a_clk = {
1632 .enable_reg = 0x0114,
1633 .enable_mask = BIT(25),
1634 .hw.init = &(struct clk_init_data){
1635 .name = "vcodec_axi_a_clk",
1636 .ops = &clk_branch_ops,
1637 .flags = CLK_IS_ROOT,
1642 static struct clk_branch vcodec_axi_clk = {
1648 .enable_reg = 0x0018,
1649 .enable_mask = BIT(19),
1650 .hw.init = &(struct clk_init_data){
1651 .name = "vcodec_axi_clk",
1652 .ops = &clk_branch_ops,
1653 .flags = CLK_IS_ROOT,
1658 static struct clk_branch vfe_axi_clk = {
1662 .enable_reg = 0x0018,
1663 .enable_mask = BIT(18),
1664 .hw.init = &(struct clk_init_data){
1665 .name = "vfe_axi_clk",
1666 .ops = &clk_branch_ops,
1667 .flags = CLK_IS_ROOT,
1672 static struct clk_branch mdp_axi_clk = {
1678 .enable_reg = 0x0018,
1679 .enable_mask = BIT(23),
1680 .hw.init = &(struct clk_init_data){
1681 .name = "mdp_axi_clk",
1682 .ops = &clk_branch_ops,
1683 .flags = CLK_IS_ROOT,
1688 static struct clk_branch rot_axi_clk = {
1694 .enable_reg = 0x0020,
1695 .enable_mask = BIT(24),
1696 .hw.init = &(struct clk_init_data){
1697 .name = "rot_axi_clk",
1698 .ops = &clk_branch_ops,
1699 .flags = CLK_IS_ROOT,
1704 static struct clk_branch vpe_axi_clk = {
1710 .enable_reg = 0x0020,
1711 .enable_mask = BIT(26),
1712 .hw.init = &(struct clk_init_data){
1713 .name = "vpe_axi_clk",
1714 .ops = &clk_branch_ops,
1715 .flags = CLK_IS_ROOT,
1720 static struct clk_branch gfx3d_axi_clk = {
1726 .enable_reg = 0x0244,
1727 .enable_mask = BIT(25),
1728 .hw.init = &(struct clk_init_data){
1729 .name = "gfx3d_axi_clk",
1730 .ops = &clk_branch_ops,
1731 .flags = CLK_IS_ROOT,
1736 static struct clk_branch amp_ahb_clk = {
1740 .enable_reg = 0x0008,
1741 .enable_mask = BIT(24),
1742 .hw.init = &(struct clk_init_data){
1743 .name = "amp_ahb_clk",
1744 .ops = &clk_branch_ops,
1745 .flags = CLK_IS_ROOT,
1750 static struct clk_branch csi_ahb_clk = {
1754 .enable_reg = 0x0008,
1755 .enable_mask = BIT(7),
1756 .hw.init = &(struct clk_init_data){
1757 .name = "csi_ahb_clk",
1758 .ops = &clk_branch_ops,
1759 .flags = CLK_IS_ROOT
1764 static struct clk_branch dsi_m_ahb_clk = {
1768 .enable_reg = 0x0008,
1769 .enable_mask = BIT(9),
1770 .hw.init = &(struct clk_init_data){
1771 .name = "dsi_m_ahb_clk",
1772 .ops = &clk_branch_ops,
1773 .flags = CLK_IS_ROOT,
1778 static struct clk_branch dsi_s_ahb_clk = {
1784 .enable_reg = 0x0008,
1785 .enable_mask = BIT(18),
1786 .hw.init = &(struct clk_init_data){
1787 .name = "dsi_s_ahb_clk",
1788 .ops = &clk_branch_ops,
1789 .flags = CLK_IS_ROOT,
1794 static struct clk_branch dsi2_m_ahb_clk = {
1798 .enable_reg = 0x0008,
1799 .enable_mask = BIT(17),
1800 .hw.init = &(struct clk_init_data){
1801 .name = "dsi2_m_ahb_clk",
1802 .ops = &clk_branch_ops,
1803 .flags = CLK_IS_ROOT
1808 static struct clk_branch dsi2_s_ahb_clk = {
1814 .enable_reg = 0x0008,
1815 .enable_mask = BIT(22),
1816 .hw.init = &(struct clk_init_data){
1817 .name = "dsi2_s_ahb_clk",
1818 .ops = &clk_branch_ops,
1819 .flags = CLK_IS_ROOT,
1824 static struct clk_branch gfx2d0_ahb_clk = {
1830 .enable_reg = 0x0008,
1831 .enable_mask = BIT(19),
1832 .hw.init = &(struct clk_init_data){
1833 .name = "gfx2d0_ahb_clk",
1834 .ops = &clk_branch_ops,
1835 .flags = CLK_IS_ROOT,
1840 static struct clk_branch gfx2d1_ahb_clk = {
1846 .enable_reg = 0x0008,
1847 .enable_mask = BIT(2),
1848 .hw.init = &(struct clk_init_data){
1849 .name = "gfx2d1_ahb_clk",
1850 .ops = &clk_branch_ops,
1851 .flags = CLK_IS_ROOT,
1856 static struct clk_branch gfx3d_ahb_clk = {
1862 .enable_reg = 0x0008,
1863 .enable_mask = BIT(3),
1864 .hw.init = &(struct clk_init_data){
1865 .name = "gfx3d_ahb_clk",
1866 .ops = &clk_branch_ops,
1867 .flags = CLK_IS_ROOT,
1872 static struct clk_branch hdmi_m_ahb_clk = {
1878 .enable_reg = 0x0008,
1879 .enable_mask = BIT(14),
1880 .hw.init = &(struct clk_init_data){
1881 .name = "hdmi_m_ahb_clk",
1882 .ops = &clk_branch_ops,
1883 .flags = CLK_IS_ROOT,
1888 static struct clk_branch hdmi_s_ahb_clk = {
1894 .enable_reg = 0x0008,
1895 .enable_mask = BIT(4),
1896 .hw.init = &(struct clk_init_data){
1897 .name = "hdmi_s_ahb_clk",
1898 .ops = &clk_branch_ops,
1899 .flags = CLK_IS_ROOT,
1904 static struct clk_branch ijpeg_ahb_clk = {
1908 .enable_reg = 0x0008,
1909 .enable_mask = BIT(5),
1910 .hw.init = &(struct clk_init_data){
1911 .name = "ijpeg_ahb_clk",
1912 .ops = &clk_branch_ops,
1913 .flags = CLK_IS_ROOT
1918 static struct clk_branch mmss_imem_ahb_clk = {
1924 .enable_reg = 0x0008,
1925 .enable_mask = BIT(6),
1926 .hw.init = &(struct clk_init_data){
1927 .name = "mmss_imem_ahb_clk",
1928 .ops = &clk_branch_ops,
1929 .flags = CLK_IS_ROOT
1934 static struct clk_branch jpegd_ahb_clk = {
1938 .enable_reg = 0x0008,
1939 .enable_mask = BIT(21),
1940 .hw.init = &(struct clk_init_data){
1941 .name = "jpegd_ahb_clk",
1942 .ops = &clk_branch_ops,
1943 .flags = CLK_IS_ROOT,
1948 static struct clk_branch mdp_ahb_clk = {
1952 .enable_reg = 0x0008,
1953 .enable_mask = BIT(10),
1954 .hw.init = &(struct clk_init_data){
1955 .name = "mdp_ahb_clk",
1956 .ops = &clk_branch_ops,
1957 .flags = CLK_IS_ROOT,
1962 static struct clk_branch rot_ahb_clk = {
1966 .enable_reg = 0x0008,
1967 .enable_mask = BIT(12),
1968 .hw.init = &(struct clk_init_data){
1969 .name = "rot_ahb_clk",
1970 .ops = &clk_branch_ops,
1971 .flags = CLK_IS_ROOT
1976 static struct clk_branch smmu_ahb_clk = {
1982 .enable_reg = 0x0008,
1983 .enable_mask = BIT(15),
1984 .hw.init = &(struct clk_init_data){
1985 .name = "smmu_ahb_clk",
1986 .ops = &clk_branch_ops,
1987 .flags = CLK_IS_ROOT,
1992 static struct clk_branch tv_enc_ahb_clk = {
1996 .enable_reg = 0x0008,
1997 .enable_mask = BIT(25),
1998 .hw.init = &(struct clk_init_data){
1999 .name = "tv_enc_ahb_clk",
2000 .ops = &clk_branch_ops,
2001 .flags = CLK_IS_ROOT,
2006 static struct clk_branch vcodec_ahb_clk = {
2012 .enable_reg = 0x0008,
2013 .enable_mask = BIT(11),
2014 .hw.init = &(struct clk_init_data){
2015 .name = "vcodec_ahb_clk",
2016 .ops = &clk_branch_ops,
2017 .flags = CLK_IS_ROOT,
2022 static struct clk_branch vfe_ahb_clk = {
2026 .enable_reg = 0x0008,
2027 .enable_mask = BIT(13),
2028 .hw.init = &(struct clk_init_data){
2029 .name = "vfe_ahb_clk",
2030 .ops = &clk_branch_ops,
2031 .flags = CLK_IS_ROOT,
2036 static struct clk_branch vpe_ahb_clk = {
2040 .enable_reg = 0x0008,
2041 .enable_mask = BIT(16),
2042 .hw.init = &(struct clk_init_data){
2043 .name = "vpe_ahb_clk",
2044 .ops = &clk_branch_ops,
2045 .flags = CLK_IS_ROOT,
2050 static struct clk_regmap *mmcc_msm8960_clks[] = {
2051 [TV_ENC_AHB_CLK] = &tv_enc_ahb_clk.clkr,
2052 [AMP_AHB_CLK] = &_ahb_clk.clkr,
2053 [DSI2_S_AHB_CLK] = &dsi2_s_ahb_clk.clkr,
2054 [JPEGD_AHB_CLK] = &jpegd_ahb_clk.clkr,
2055 [GFX2D0_AHB_CLK] = &gfx2d0_ahb_clk.clkr,
2056 [DSI_S_AHB_CLK] = &dsi_s_ahb_clk.clkr,
2057 [DSI2_M_AHB_CLK] = &dsi2_m_ahb_clk.clkr,
2058 [VPE_AHB_CLK] = &vpe_ahb_clk.clkr,
2059 [SMMU_AHB_CLK] = &smmu_ahb_clk.clkr,
2060 [HDMI_M_AHB_CLK] = &hdmi_m_ahb_clk.clkr,
2061 [VFE_AHB_CLK] = &vfe_ahb_clk.clkr,
2062 [ROT_AHB_CLK] = &rot_ahb_clk.clkr,
2063 [VCODEC_AHB_CLK] = &vcodec_ahb_clk.clkr,
2064 [MDP_AHB_CLK] = &mdp_ahb_clk.clkr,
2065 [DSI_M_AHB_CLK] = &dsi_m_ahb_clk.clkr,
2066 [CSI_AHB_CLK] = &csi_ahb_clk.clkr,
2067 [MMSS_IMEM_AHB_CLK] = &mmss_imem_ahb_clk.clkr,
2068 [IJPEG_AHB_CLK] = &ijpeg_ahb_clk.clkr,
2069 [HDMI_S_AHB_CLK] = &hdmi_s_ahb_clk.clkr,
2070 [GFX3D_AHB_CLK] = &gfx3d_ahb_clk.clkr,
2071 [GFX2D1_AHB_CLK] = &gfx2d1_ahb_clk.clkr,
2072 [JPEGD_AXI_CLK] = &jpegd_axi_clk.clkr,
2073 [GMEM_AXI_CLK] = &gmem_axi_clk.clkr,
2074 [MDP_AXI_CLK] = &mdp_axi_clk.clkr,
2075 [MMSS_IMEM_AXI_CLK] = &mmss_imem_axi_clk.clkr,
2076 [IJPEG_AXI_CLK] = &ijpeg_axi_clk.clkr,
2077 [GFX3D_AXI_CLK] = &gfx3d_axi_clk.clkr,
2078 [VCODEC_AXI_CLK] = &vcodec_axi_clk.clkr,
2079 [VFE_AXI_CLK] = &vfe_axi_clk.clkr,
2080 [VPE_AXI_CLK] = &vpe_axi_clk.clkr,
2081 [ROT_AXI_CLK] = &rot_axi_clk.clkr,
2082 [VCODEC_AXI_A_CLK] = &vcodec_axi_a_clk.clkr,
2083 [VCODEC_AXI_B_CLK] = &vcodec_axi_b_clk.clkr,
2084 [CSI0_SRC] = &csi0_src.clkr,
2085 [CSI0_CLK] = &csi0_clk.clkr,
2086 [CSI0_PHY_CLK] = &csi0_phy_clk.clkr,
2087 [CSI1_SRC] = &csi1_src.clkr,
2088 [CSI1_CLK] = &csi1_clk.clkr,
2089 [CSI1_PHY_CLK] = &csi1_phy_clk.clkr,
2090 [CSI2_SRC] = &csi2_src.clkr,
2091 [CSI2_CLK] = &csi2_clk.clkr,
2092 [CSI2_PHY_CLK] = &csi2_phy_clk.clkr,
2093 [CSI_PIX_CLK] = &csi_pix_clk.clkr,
2094 [CSI_RDI_CLK] = &csi_rdi_clk.clkr,
2095 [MDP_VSYNC_CLK] = &mdp_vsync_clk.clkr,
2096 [HDMI_APP_CLK] = &hdmi_app_clk.clkr,
2097 [CSI_PIX1_CLK] = &csi_pix1_clk.clkr,
2098 [CSI_RDI2_CLK] = &csi_rdi2_clk.clkr,
2099 [CSI_RDI1_CLK] = &csi_rdi1_clk.clkr,
2100 [GFX2D0_SRC] = &gfx2d0_src.clkr,
2101 [GFX2D0_CLK] = &gfx2d0_clk.clkr,
2102 [GFX2D1_SRC] = &gfx2d1_src.clkr,
2103 [GFX2D1_CLK] = &gfx2d1_clk.clkr,
2104 [GFX3D_SRC] = &gfx3d_src.clkr,
2105 [GFX3D_CLK] = &gfx3d_clk.clkr,
2106 [IJPEG_SRC] = &ijpeg_src.clkr,
2107 [IJPEG_CLK] = &ijpeg_clk.clkr,
2108 [JPEGD_SRC] = &jpegd_src.clkr,
2109 [JPEGD_CLK] = &jpegd_clk.clkr,
2110 [MDP_SRC] = &mdp_src.clkr,
2111 [MDP_CLK] = &mdp_clk.clkr,
2112 [MDP_LUT_CLK] = &mdp_lut_clk.clkr,
2113 [ROT_SRC] = &rot_src.clkr,
2114 [ROT_CLK] = &rot_clk.clkr,
2115 [TV_ENC_CLK] = &tv_enc_clk.clkr,
2116 [TV_DAC_CLK] = &tv_dac_clk.clkr,
2117 [HDMI_TV_CLK] = &hdmi_tv_clk.clkr,
2118 [MDP_TV_CLK] = &mdp_tv_clk.clkr,
2119 [TV_SRC] = &tv_src.clkr,
2120 [VCODEC_SRC] = &vcodec_src.clkr,
2121 [VCODEC_CLK] = &vcodec_clk.clkr,
2122 [VFE_SRC] = &vfe_src.clkr,
2123 [VFE_CLK] = &vfe_clk.clkr,
2124 [VFE_CSI_CLK] = &vfe_csi_clk.clkr,
2125 [VPE_SRC] = &vpe_src.clkr,
2126 [VPE_CLK] = &vpe_clk.clkr,
2127 [CAMCLK0_SRC] = &camclk0_src.clkr,
2128 [CAMCLK0_CLK] = &camclk0_clk.clkr,
2129 [CAMCLK1_SRC] = &camclk1_src.clkr,
2130 [CAMCLK1_CLK] = &camclk1_clk.clkr,
2131 [CAMCLK2_SRC] = &camclk2_src.clkr,
2132 [CAMCLK2_CLK] = &camclk2_clk.clkr,
2133 [CSIPHYTIMER_SRC] = &csiphytimer_src.clkr,
2134 [CSIPHY2_TIMER_CLK] = &csiphy2_timer_clk.clkr,
2135 [CSIPHY1_TIMER_CLK] = &csiphy1_timer_clk.clkr,
2136 [CSIPHY0_TIMER_CLK] = &csiphy0_timer_clk.clkr,
2137 [PLL2] = &pll2.clkr,
2140 static const struct qcom_reset_map mmcc_msm8960_resets[] = {
2141 [VPE_AXI_RESET] = { 0x0208, 15 },
2142 [IJPEG_AXI_RESET] = { 0x0208, 14 },
2143 [MPD_AXI_RESET] = { 0x0208, 13 },
2144 [VFE_AXI_RESET] = { 0x0208, 9 },
2145 [SP_AXI_RESET] = { 0x0208, 8 },
2146 [VCODEC_AXI_RESET] = { 0x0208, 7 },
2147 [ROT_AXI_RESET] = { 0x0208, 6 },
2148 [VCODEC_AXI_A_RESET] = { 0x0208, 5 },
2149 [VCODEC_AXI_B_RESET] = { 0x0208, 4 },
2150 [FAB_S3_AXI_RESET] = { 0x0208, 3 },
2151 [FAB_S2_AXI_RESET] = { 0x0208, 2 },
2152 [FAB_S1_AXI_RESET] = { 0x0208, 1 },
2153 [FAB_S0_AXI_RESET] = { 0x0208 },
2154 [SMMU_GFX3D_ABH_RESET] = { 0x020c, 31 },
2155 [SMMU_VPE_AHB_RESET] = { 0x020c, 30 },
2156 [SMMU_VFE_AHB_RESET] = { 0x020c, 29 },
2157 [SMMU_ROT_AHB_RESET] = { 0x020c, 28 },
2158 [SMMU_VCODEC_B_AHB_RESET] = { 0x020c, 27 },
2159 [SMMU_VCODEC_A_AHB_RESET] = { 0x020c, 26 },
2160 [SMMU_MDP1_AHB_RESET] = { 0x020c, 25 },
2161 [SMMU_MDP0_AHB_RESET] = { 0x020c, 24 },
2162 [SMMU_JPEGD_AHB_RESET] = { 0x020c, 23 },
2163 [SMMU_IJPEG_AHB_RESET] = { 0x020c, 22 },
2164 [SMMU_GFX2D0_AHB_RESET] = { 0x020c, 21 },
2165 [SMMU_GFX2D1_AHB_RESET] = { 0x020c, 20 },
2166 [APU_AHB_RESET] = { 0x020c, 18 },
2167 [CSI_AHB_RESET] = { 0x020c, 17 },
2168 [TV_ENC_AHB_RESET] = { 0x020c, 15 },
2169 [VPE_AHB_RESET] = { 0x020c, 14 },
2170 [FABRIC_AHB_RESET] = { 0x020c, 13 },
2171 [GFX2D0_AHB_RESET] = { 0x020c, 12 },
2172 [GFX2D1_AHB_RESET] = { 0x020c, 11 },
2173 [GFX3D_AHB_RESET] = { 0x020c, 10 },
2174 [HDMI_AHB_RESET] = { 0x020c, 9 },
2175 [MSSS_IMEM_AHB_RESET] = { 0x020c, 8 },
2176 [IJPEG_AHB_RESET] = { 0x020c, 7 },
2177 [DSI_M_AHB_RESET] = { 0x020c, 6 },
2178 [DSI_S_AHB_RESET] = { 0x020c, 5 },
2179 [JPEGD_AHB_RESET] = { 0x020c, 4 },
2180 [MDP_AHB_RESET] = { 0x020c, 3 },
2181 [ROT_AHB_RESET] = { 0x020c, 2 },
2182 [VCODEC_AHB_RESET] = { 0x020c, 1 },
2183 [VFE_AHB_RESET] = { 0x020c, 0 },
2184 [DSI2_M_AHB_RESET] = { 0x0210, 31 },
2185 [DSI2_S_AHB_RESET] = { 0x0210, 30 },
2186 [CSIPHY2_RESET] = { 0x0210, 29 },
2187 [CSI_PIX1_RESET] = { 0x0210, 28 },
2188 [CSIPHY0_RESET] = { 0x0210, 27 },
2189 [CSIPHY1_RESET] = { 0x0210, 26 },
2190 [DSI2_RESET] = { 0x0210, 25 },
2191 [VFE_CSI_RESET] = { 0x0210, 24 },
2192 [MDP_RESET] = { 0x0210, 21 },
2193 [AMP_RESET] = { 0x0210, 20 },
2194 [JPEGD_RESET] = { 0x0210, 19 },
2195 [CSI1_RESET] = { 0x0210, 18 },
2196 [VPE_RESET] = { 0x0210, 17 },
2197 [MMSS_FABRIC_RESET] = { 0x0210, 16 },
2198 [VFE_RESET] = { 0x0210, 15 },
2199 [GFX2D0_RESET] = { 0x0210, 14 },
2200 [GFX2D1_RESET] = { 0x0210, 13 },
2201 [GFX3D_RESET] = { 0x0210, 12 },
2202 [HDMI_RESET] = { 0x0210, 11 },
2203 [MMSS_IMEM_RESET] = { 0x0210, 10 },
2204 [IJPEG_RESET] = { 0x0210, 9 },
2205 [CSI0_RESET] = { 0x0210, 8 },
2206 [DSI_RESET] = { 0x0210, 7 },
2207 [VCODEC_RESET] = { 0x0210, 6 },
2208 [MDP_TV_RESET] = { 0x0210, 4 },
2209 [MDP_VSYNC_RESET] = { 0x0210, 3 },
2210 [ROT_RESET] = { 0x0210, 2 },
2211 [TV_HDMI_RESET] = { 0x0210, 1 },
2212 [TV_ENC_RESET] = { 0x0210 },
2213 [CSI2_RESET] = { 0x0214, 2 },
2214 [CSI_RDI1_RESET] = { 0x0214, 1 },
2215 [CSI_RDI2_RESET] = { 0x0214 },
2218 static const struct regmap_config mmcc_msm8960_regmap_config = {
2222 .max_register = 0x334,
2226 static const struct qcom_cc_desc mmcc_msm8960_desc = {
2227 .config = &mmcc_msm8960_regmap_config,
2228 .clks = mmcc_msm8960_clks,
2229 .num_clks = ARRAY_SIZE(mmcc_msm8960_clks),
2230 .resets = mmcc_msm8960_resets,
2231 .num_resets = ARRAY_SIZE(mmcc_msm8960_resets),
2234 static const struct of_device_id mmcc_msm8960_match_table[] = {
2235 { .compatible = "qcom,mmcc-msm8960" },
2238 MODULE_DEVICE_TABLE(of, mmcc_msm8960_match_table);
2240 static int mmcc_msm8960_probe(struct platform_device *pdev)
2242 return qcom_cc_probe(pdev, &mmcc_msm8960_desc);
2245 static int mmcc_msm8960_remove(struct platform_device *pdev)
2247 qcom_cc_remove(pdev);
2251 static struct platform_driver mmcc_msm8960_driver = {
2252 .probe = mmcc_msm8960_probe,
2253 .remove = mmcc_msm8960_remove,
2255 .name = "mmcc-msm8960",
2256 .owner = THIS_MODULE,
2257 .of_match_table = mmcc_msm8960_match_table,
2261 module_platform_driver(mmcc_msm8960_driver);
2263 MODULE_DESCRIPTION("QCOM MMCC MSM8960 Driver");
2264 MODULE_LICENSE("GPL v2");
2265 MODULE_ALIAS("platform:mmcc-msm8960");