2 * Copyright (c) 2013, The Linux Foundation. All rights reserved.
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
14 #include <linux/kernel.h>
15 #include <linux/bitops.h>
16 #include <linux/err.h>
17 #include <linux/delay.h>
18 #include <linux/platform_device.h>
19 #include <linux/module.h>
21 #include <linux/of_device.h>
22 #include <linux/clk-provider.h>
23 #include <linux/regmap.h>
24 #include <linux/reset-controller.h>
26 #include <dt-bindings/clock/qcom,mmcc-msm8960.h>
27 #include <dt-bindings/reset/qcom,mmcc-msm8960.h>
30 #include "clk-regmap.h"
33 #include "clk-branch.h"
42 #define F_MN(f, s, _m, _n) { .freq = f, .src = s, .m = _m, .n = _n }
44 static u8 mmcc_pxo_pll8_pll2_map[] = {
50 static const char *mmcc_pxo_pll8_pll2[] = {
56 static u8 mmcc_pxo_pll8_pll2_pll3_map[] = {
63 static const char *mmcc_pxo_pll8_pll2_pll15[] = {
70 static u8 mmcc_pxo_pll8_pll2_pll15_map[] = {
77 static const char *mmcc_pxo_pll8_pll2_pll3[] = {
84 static struct clk_pll pll2 = {
92 .clkr.hw.init = &(struct clk_init_data){
94 .parent_names = (const char *[]){ "pxo" },
100 static struct clk_pll pll15 = {
108 .clkr.hw.init = &(struct clk_init_data){
110 .parent_names = (const char *[]){ "pxo" },
116 static const struct pll_config pll15_config = {
120 .vco_val = 0x2 << 16,
121 .vco_mask = 0x3 << 16,
123 .pre_div_mask = BIT(19),
125 .post_div_mask = 0x3 << 20,
126 .mn_ena_mask = BIT(22),
127 .main_output_mask = BIT(23),
130 static struct freq_tbl clk_tbl_cam[] = {
131 { 6000000, P_PLL8, 4, 1, 16 },
132 { 8000000, P_PLL8, 4, 1, 12 },
133 { 12000000, P_PLL8, 4, 1, 8 },
134 { 16000000, P_PLL8, 4, 1, 6 },
135 { 19200000, P_PLL8, 4, 1, 5 },
136 { 24000000, P_PLL8, 4, 1, 4 },
137 { 32000000, P_PLL8, 4, 1, 3 },
138 { 48000000, P_PLL8, 4, 1, 2 },
139 { 64000000, P_PLL8, 3, 1, 2 },
140 { 96000000, P_PLL8, 4, 0, 0 },
141 { 128000000, P_PLL8, 3, 0, 0 },
145 static struct clk_rcg camclk0_src = {
150 .mnctr_reset_bit = 8,
152 .mnctr_mode_shift = 6,
163 .parent_map = mmcc_pxo_pll8_pll2_map,
165 .freq_tbl = clk_tbl_cam,
167 .enable_reg = 0x0140,
168 .enable_mask = BIT(2),
169 .hw.init = &(struct clk_init_data){
170 .name = "camclk0_src",
171 .parent_names = mmcc_pxo_pll8_pll2,
178 static struct clk_branch camclk0_clk = {
182 .enable_reg = 0x0140,
183 .enable_mask = BIT(0),
184 .hw.init = &(struct clk_init_data){
185 .name = "camclk0_clk",
186 .parent_names = (const char *[]){ "camclk0_src" },
188 .ops = &clk_branch_ops,
194 static struct clk_rcg camclk1_src = {
199 .mnctr_reset_bit = 8,
201 .mnctr_mode_shift = 6,
212 .parent_map = mmcc_pxo_pll8_pll2_map,
214 .freq_tbl = clk_tbl_cam,
216 .enable_reg = 0x0154,
217 .enable_mask = BIT(2),
218 .hw.init = &(struct clk_init_data){
219 .name = "camclk1_src",
220 .parent_names = mmcc_pxo_pll8_pll2,
227 static struct clk_branch camclk1_clk = {
231 .enable_reg = 0x0154,
232 .enable_mask = BIT(0),
233 .hw.init = &(struct clk_init_data){
234 .name = "camclk1_clk",
235 .parent_names = (const char *[]){ "camclk1_src" },
237 .ops = &clk_branch_ops,
243 static struct clk_rcg camclk2_src = {
248 .mnctr_reset_bit = 8,
250 .mnctr_mode_shift = 6,
261 .parent_map = mmcc_pxo_pll8_pll2_map,
263 .freq_tbl = clk_tbl_cam,
265 .enable_reg = 0x0220,
266 .enable_mask = BIT(2),
267 .hw.init = &(struct clk_init_data){
268 .name = "camclk2_src",
269 .parent_names = mmcc_pxo_pll8_pll2,
276 static struct clk_branch camclk2_clk = {
280 .enable_reg = 0x0220,
281 .enable_mask = BIT(0),
282 .hw.init = &(struct clk_init_data){
283 .name = "camclk2_clk",
284 .parent_names = (const char *[]){ "camclk2_src" },
286 .ops = &clk_branch_ops,
292 static struct freq_tbl clk_tbl_csi[] = {
293 { 27000000, P_PXO, 1, 0, 0 },
294 { 85330000, P_PLL8, 1, 2, 9 },
295 { 177780000, P_PLL2, 1, 2, 9 },
299 static struct clk_rcg csi0_src = {
304 .mnctr_reset_bit = 7,
305 .mnctr_mode_shift = 6,
316 .parent_map = mmcc_pxo_pll8_pll2_map,
318 .freq_tbl = clk_tbl_csi,
320 .enable_reg = 0x0040,
321 .enable_mask = BIT(2),
322 .hw.init = &(struct clk_init_data){
324 .parent_names = mmcc_pxo_pll8_pll2,
331 static struct clk_branch csi0_clk = {
335 .enable_reg = 0x0040,
336 .enable_mask = BIT(0),
337 .hw.init = &(struct clk_init_data){
338 .parent_names = (const char *[]){ "csi0_src" },
341 .ops = &clk_branch_ops,
342 .flags = CLK_SET_RATE_PARENT,
347 static struct clk_branch csi0_phy_clk = {
351 .enable_reg = 0x0040,
352 .enable_mask = BIT(8),
353 .hw.init = &(struct clk_init_data){
354 .parent_names = (const char *[]){ "csi0_src" },
356 .name = "csi0_phy_clk",
357 .ops = &clk_branch_ops,
358 .flags = CLK_SET_RATE_PARENT,
363 static struct clk_rcg csi1_src = {
368 .mnctr_reset_bit = 7,
369 .mnctr_mode_shift = 6,
380 .parent_map = mmcc_pxo_pll8_pll2_map,
382 .freq_tbl = clk_tbl_csi,
384 .enable_reg = 0x0024,
385 .enable_mask = BIT(2),
386 .hw.init = &(struct clk_init_data){
388 .parent_names = mmcc_pxo_pll8_pll2,
395 static struct clk_branch csi1_clk = {
399 .enable_reg = 0x0024,
400 .enable_mask = BIT(0),
401 .hw.init = &(struct clk_init_data){
402 .parent_names = (const char *[]){ "csi1_src" },
405 .ops = &clk_branch_ops,
406 .flags = CLK_SET_RATE_PARENT,
411 static struct clk_branch csi1_phy_clk = {
415 .enable_reg = 0x0024,
416 .enable_mask = BIT(8),
417 .hw.init = &(struct clk_init_data){
418 .parent_names = (const char *[]){ "csi1_src" },
420 .name = "csi1_phy_clk",
421 .ops = &clk_branch_ops,
422 .flags = CLK_SET_RATE_PARENT,
427 static struct clk_rcg csi2_src = {
432 .mnctr_reset_bit = 7,
433 .mnctr_mode_shift = 6,
444 .parent_map = mmcc_pxo_pll8_pll2_map,
446 .freq_tbl = clk_tbl_csi,
448 .enable_reg = 0x022c,
449 .enable_mask = BIT(2),
450 .hw.init = &(struct clk_init_data){
452 .parent_names = mmcc_pxo_pll8_pll2,
459 static struct clk_branch csi2_clk = {
463 .enable_reg = 0x022c,
464 .enable_mask = BIT(0),
465 .hw.init = &(struct clk_init_data){
466 .parent_names = (const char *[]){ "csi2_src" },
469 .ops = &clk_branch_ops,
470 .flags = CLK_SET_RATE_PARENT,
475 static struct clk_branch csi2_phy_clk = {
479 .enable_reg = 0x022c,
480 .enable_mask = BIT(8),
481 .hw.init = &(struct clk_init_data){
482 .parent_names = (const char *[]){ "csi2_src" },
484 .name = "csi2_phy_clk",
485 .ops = &clk_branch_ops,
486 .flags = CLK_SET_RATE_PARENT,
496 struct clk_regmap clkr;
499 #define to_clk_pix_rdi(_hw) \
500 container_of(to_clk_regmap(_hw), struct clk_pix_rdi, clkr)
502 static int pix_rdi_set_parent(struct clk_hw *hw, u8 index)
507 struct clk_pix_rdi *rdi = to_clk_pix_rdi(hw);
508 struct clk *clk = hw->clk;
509 int num_parents = __clk_get_num_parents(hw->clk);
512 * These clocks select three inputs via two muxes. One mux selects
513 * between csi0 and csi1 and the second mux selects between that mux's
514 * output and csi2. The source and destination selections for each
515 * mux must be clocking for the switch to succeed so just turn on
516 * all three sources because it's easier than figuring out what source
517 * needs to be on at what time.
519 for (i = 0; i < num_parents; i++) {
520 ret = clk_prepare_enable(clk_get_parent_by_index(clk, i));
529 regmap_update_bits(rdi->clkr.regmap, rdi->s2_reg, rdi->s2_mask, val);
531 * Wait at least 6 cycles of slowest clock
532 * for the glitch-free MUX to fully switch sources.
540 regmap_update_bits(rdi->clkr.regmap, rdi->s_reg, rdi->s_mask, val);
542 * Wait at least 6 cycles of slowest clock
543 * for the glitch-free MUX to fully switch sources.
548 for (i--; i >= 0; i--)
549 clk_disable_unprepare(clk_get_parent_by_index(clk, i));
554 static u8 pix_rdi_get_parent(struct clk_hw *hw)
557 struct clk_pix_rdi *rdi = to_clk_pix_rdi(hw);
560 regmap_read(rdi->clkr.regmap, rdi->s2_reg, &val);
561 if (val & rdi->s2_mask)
564 regmap_read(rdi->clkr.regmap, rdi->s_reg, &val);
565 if (val & rdi->s_mask)
571 static const struct clk_ops clk_ops_pix_rdi = {
572 .enable = clk_enable_regmap,
573 .disable = clk_disable_regmap,
574 .set_parent = pix_rdi_set_parent,
575 .get_parent = pix_rdi_get_parent,
576 .determine_rate = __clk_mux_determine_rate,
579 static const char *pix_rdi_parents[] = {
585 static struct clk_pix_rdi csi_pix_clk = {
591 .enable_reg = 0x0058,
592 .enable_mask = BIT(26),
593 .hw.init = &(struct clk_init_data){
594 .name = "csi_pix_clk",
595 .parent_names = pix_rdi_parents,
597 .ops = &clk_ops_pix_rdi,
602 static struct clk_pix_rdi csi_pix1_clk = {
608 .enable_reg = 0x0238,
609 .enable_mask = BIT(10),
610 .hw.init = &(struct clk_init_data){
611 .name = "csi_pix1_clk",
612 .parent_names = pix_rdi_parents,
614 .ops = &clk_ops_pix_rdi,
619 static struct clk_pix_rdi csi_rdi_clk = {
625 .enable_reg = 0x0058,
626 .enable_mask = BIT(13),
627 .hw.init = &(struct clk_init_data){
628 .name = "csi_rdi_clk",
629 .parent_names = pix_rdi_parents,
631 .ops = &clk_ops_pix_rdi,
636 static struct clk_pix_rdi csi_rdi1_clk = {
642 .enable_reg = 0x0238,
643 .enable_mask = BIT(2),
644 .hw.init = &(struct clk_init_data){
645 .name = "csi_rdi1_clk",
646 .parent_names = pix_rdi_parents,
648 .ops = &clk_ops_pix_rdi,
653 static struct clk_pix_rdi csi_rdi2_clk = {
659 .enable_reg = 0x0238,
660 .enable_mask = BIT(6),
661 .hw.init = &(struct clk_init_data){
662 .name = "csi_rdi2_clk",
663 .parent_names = pix_rdi_parents,
665 .ops = &clk_ops_pix_rdi,
670 static struct freq_tbl clk_tbl_csiphytimer[] = {
671 { 85330000, P_PLL8, 1, 2, 9 },
672 { 177780000, P_PLL2, 1, 2, 9 },
676 static struct clk_rcg csiphytimer_src = {
681 .mnctr_reset_bit = 8,
683 .mnctr_mode_shift = 6,
694 .parent_map = mmcc_pxo_pll8_pll2_map,
696 .freq_tbl = clk_tbl_csiphytimer,
698 .enable_reg = 0x0160,
699 .enable_mask = BIT(2),
700 .hw.init = &(struct clk_init_data){
701 .name = "csiphytimer_src",
702 .parent_names = mmcc_pxo_pll8_pll2,
709 static const char *csixphy_timer_src[] = { "csiphytimer_src" };
711 static struct clk_branch csiphy0_timer_clk = {
715 .enable_reg = 0x0160,
716 .enable_mask = BIT(0),
717 .hw.init = &(struct clk_init_data){
718 .parent_names = csixphy_timer_src,
720 .name = "csiphy0_timer_clk",
721 .ops = &clk_branch_ops,
722 .flags = CLK_SET_RATE_PARENT,
727 static struct clk_branch csiphy1_timer_clk = {
731 .enable_reg = 0x0160,
732 .enable_mask = BIT(9),
733 .hw.init = &(struct clk_init_data){
734 .parent_names = csixphy_timer_src,
736 .name = "csiphy1_timer_clk",
737 .ops = &clk_branch_ops,
738 .flags = CLK_SET_RATE_PARENT,
743 static struct clk_branch csiphy2_timer_clk = {
747 .enable_reg = 0x0160,
748 .enable_mask = BIT(11),
749 .hw.init = &(struct clk_init_data){
750 .parent_names = csixphy_timer_src,
752 .name = "csiphy2_timer_clk",
753 .ops = &clk_branch_ops,
754 .flags = CLK_SET_RATE_PARENT,
759 static struct freq_tbl clk_tbl_gfx2d[] = {
760 F_MN( 27000000, P_PXO, 1, 0),
761 F_MN( 48000000, P_PLL8, 1, 8),
762 F_MN( 54857000, P_PLL8, 1, 7),
763 F_MN( 64000000, P_PLL8, 1, 6),
764 F_MN( 76800000, P_PLL8, 1, 5),
765 F_MN( 96000000, P_PLL8, 1, 4),
766 F_MN(128000000, P_PLL8, 1, 3),
767 F_MN(145455000, P_PLL2, 2, 11),
768 F_MN(160000000, P_PLL2, 1, 5),
769 F_MN(177778000, P_PLL2, 2, 9),
770 F_MN(200000000, P_PLL2, 1, 4),
771 F_MN(228571000, P_PLL2, 2, 7),
775 static struct clk_dyn_rcg gfx2d0_src = {
783 .mnctr_reset_bit = 25,
784 .mnctr_mode_shift = 9,
791 .mnctr_reset_bit = 24,
792 .mnctr_mode_shift = 6,
799 .parent_map = mmcc_pxo_pll8_pll2_map,
803 .parent_map = mmcc_pxo_pll8_pll2_map,
806 .freq_tbl = clk_tbl_gfx2d,
808 .enable_reg = 0x0060,
809 .enable_mask = BIT(2),
810 .hw.init = &(struct clk_init_data){
811 .name = "gfx2d0_src",
812 .parent_names = mmcc_pxo_pll8_pll2,
814 .ops = &clk_dyn_rcg_ops,
819 static struct clk_branch gfx2d0_clk = {
823 .enable_reg = 0x0060,
824 .enable_mask = BIT(0),
825 .hw.init = &(struct clk_init_data){
826 .name = "gfx2d0_clk",
827 .parent_names = (const char *[]){ "gfx2d0_src" },
829 .ops = &clk_branch_ops,
830 .flags = CLK_SET_RATE_PARENT,
835 static struct clk_dyn_rcg gfx2d1_src = {
843 .mnctr_reset_bit = 25,
844 .mnctr_mode_shift = 9,
851 .mnctr_reset_bit = 24,
852 .mnctr_mode_shift = 6,
859 .parent_map = mmcc_pxo_pll8_pll2_map,
863 .parent_map = mmcc_pxo_pll8_pll2_map,
866 .freq_tbl = clk_tbl_gfx2d,
868 .enable_reg = 0x0074,
869 .enable_mask = BIT(2),
870 .hw.init = &(struct clk_init_data){
871 .name = "gfx2d1_src",
872 .parent_names = mmcc_pxo_pll8_pll2,
874 .ops = &clk_dyn_rcg_ops,
879 static struct clk_branch gfx2d1_clk = {
883 .enable_reg = 0x0074,
884 .enable_mask = BIT(0),
885 .hw.init = &(struct clk_init_data){
886 .name = "gfx2d1_clk",
887 .parent_names = (const char *[]){ "gfx2d1_src" },
889 .ops = &clk_branch_ops,
890 .flags = CLK_SET_RATE_PARENT,
895 static struct freq_tbl clk_tbl_gfx3d[] = {
896 F_MN( 27000000, P_PXO, 1, 0),
897 F_MN( 48000000, P_PLL8, 1, 8),
898 F_MN( 54857000, P_PLL8, 1, 7),
899 F_MN( 64000000, P_PLL8, 1, 6),
900 F_MN( 76800000, P_PLL8, 1, 5),
901 F_MN( 96000000, P_PLL8, 1, 4),
902 F_MN(128000000, P_PLL8, 1, 3),
903 F_MN(145455000, P_PLL2, 2, 11),
904 F_MN(160000000, P_PLL2, 1, 5),
905 F_MN(177778000, P_PLL2, 2, 9),
906 F_MN(200000000, P_PLL2, 1, 4),
907 F_MN(228571000, P_PLL2, 2, 7),
908 F_MN(266667000, P_PLL2, 1, 3),
909 F_MN(300000000, P_PLL3, 1, 4),
910 F_MN(320000000, P_PLL2, 2, 5),
911 F_MN(400000000, P_PLL2, 1, 2),
915 static struct freq_tbl clk_tbl_gfx3d_8064[] = {
916 F_MN( 27000000, P_PXO, 0, 0),
917 F_MN( 48000000, P_PLL8, 1, 8),
918 F_MN( 54857000, P_PLL8, 1, 7),
919 F_MN( 64000000, P_PLL8, 1, 6),
920 F_MN( 76800000, P_PLL8, 1, 5),
921 F_MN( 96000000, P_PLL8, 1, 4),
922 F_MN(128000000, P_PLL8, 1, 3),
923 F_MN(145455000, P_PLL2, 2, 11),
924 F_MN(160000000, P_PLL2, 1, 5),
925 F_MN(177778000, P_PLL2, 2, 9),
926 F_MN(192000000, P_PLL8, 1, 2),
927 F_MN(200000000, P_PLL2, 1, 4),
928 F_MN(228571000, P_PLL2, 2, 7),
929 F_MN(266667000, P_PLL2, 1, 3),
930 F_MN(320000000, P_PLL2, 2, 5),
931 F_MN(400000000, P_PLL2, 1, 2),
932 F_MN(450000000, P_PLL15, 1, 2),
936 static struct clk_dyn_rcg gfx3d_src = {
944 .mnctr_reset_bit = 25,
945 .mnctr_mode_shift = 9,
952 .mnctr_reset_bit = 24,
953 .mnctr_mode_shift = 6,
960 .parent_map = mmcc_pxo_pll8_pll2_pll3_map,
964 .parent_map = mmcc_pxo_pll8_pll2_pll3_map,
967 .freq_tbl = clk_tbl_gfx3d,
969 .enable_reg = 0x0080,
970 .enable_mask = BIT(2),
971 .hw.init = &(struct clk_init_data){
973 .parent_names = mmcc_pxo_pll8_pll2_pll3,
975 .ops = &clk_dyn_rcg_ops,
980 static const struct clk_init_data gfx3d_8064_init = {
982 .parent_names = mmcc_pxo_pll8_pll2_pll15,
984 .ops = &clk_dyn_rcg_ops,
987 static struct clk_branch gfx3d_clk = {
991 .enable_reg = 0x0080,
992 .enable_mask = BIT(0),
993 .hw.init = &(struct clk_init_data){
995 .parent_names = (const char *[]){ "gfx3d_src" },
997 .ops = &clk_branch_ops,
998 .flags = CLK_SET_RATE_PARENT,
1003 static struct freq_tbl clk_tbl_vcap[] = {
1004 F_MN( 27000000, P_PXO, 0, 0),
1005 F_MN( 54860000, P_PLL8, 1, 7),
1006 F_MN( 64000000, P_PLL8, 1, 6),
1007 F_MN( 76800000, P_PLL8, 1, 5),
1008 F_MN(128000000, P_PLL8, 1, 3),
1009 F_MN(160000000, P_PLL2, 1, 5),
1010 F_MN(200000000, P_PLL2, 1, 4),
1014 static struct clk_dyn_rcg vcap_src = {
1015 .ns_reg[0] = 0x021c,
1016 .ns_reg[1] = 0x021c,
1017 .md_reg[0] = 0x01ec,
1018 .md_reg[1] = 0x0218,
1022 .mnctr_reset_bit = 23,
1023 .mnctr_mode_shift = 9,
1030 .mnctr_reset_bit = 22,
1031 .mnctr_mode_shift = 6,
1038 .parent_map = mmcc_pxo_pll8_pll2_map,
1042 .parent_map = mmcc_pxo_pll8_pll2_map,
1045 .freq_tbl = clk_tbl_vcap,
1047 .enable_reg = 0x0178,
1048 .enable_mask = BIT(2),
1049 .hw.init = &(struct clk_init_data){
1051 .parent_names = mmcc_pxo_pll8_pll2,
1053 .ops = &clk_dyn_rcg_ops,
1058 static struct clk_branch vcap_clk = {
1062 .enable_reg = 0x0178,
1063 .enable_mask = BIT(0),
1064 .hw.init = &(struct clk_init_data){
1066 .parent_names = (const char *[]){ "vcap_src" },
1068 .ops = &clk_branch_ops,
1069 .flags = CLK_SET_RATE_PARENT,
1074 static struct clk_branch vcap_npl_clk = {
1078 .enable_reg = 0x0178,
1079 .enable_mask = BIT(13),
1080 .hw.init = &(struct clk_init_data){
1081 .name = "vcap_npl_clk",
1082 .parent_names = (const char *[]){ "vcap_src" },
1084 .ops = &clk_branch_ops,
1085 .flags = CLK_SET_RATE_PARENT,
1090 static struct freq_tbl clk_tbl_ijpeg[] = {
1091 { 27000000, P_PXO, 1, 0, 0 },
1092 { 36570000, P_PLL8, 1, 2, 21 },
1093 { 54860000, P_PLL8, 7, 0, 0 },
1094 { 96000000, P_PLL8, 4, 0, 0 },
1095 { 109710000, P_PLL8, 1, 2, 7 },
1096 { 128000000, P_PLL8, 3, 0, 0 },
1097 { 153600000, P_PLL8, 1, 2, 5 },
1098 { 200000000, P_PLL2, 4, 0, 0 },
1099 { 228571000, P_PLL2, 1, 2, 7 },
1100 { 266667000, P_PLL2, 1, 1, 3 },
1101 { 320000000, P_PLL2, 1, 2, 5 },
1105 static struct clk_rcg ijpeg_src = {
1110 .mnctr_reset_bit = 7,
1111 .mnctr_mode_shift = 6,
1117 .pre_div_shift = 12,
1122 .parent_map = mmcc_pxo_pll8_pll2_map,
1124 .freq_tbl = clk_tbl_ijpeg,
1126 .enable_reg = 0x0098,
1127 .enable_mask = BIT(2),
1128 .hw.init = &(struct clk_init_data){
1129 .name = "ijpeg_src",
1130 .parent_names = mmcc_pxo_pll8_pll2,
1132 .ops = &clk_rcg_ops,
1137 static struct clk_branch ijpeg_clk = {
1141 .enable_reg = 0x0098,
1142 .enable_mask = BIT(0),
1143 .hw.init = &(struct clk_init_data){
1144 .name = "ijpeg_clk",
1145 .parent_names = (const char *[]){ "ijpeg_src" },
1147 .ops = &clk_branch_ops,
1148 .flags = CLK_SET_RATE_PARENT,
1153 static struct freq_tbl clk_tbl_jpegd[] = {
1154 { 64000000, P_PLL8, 6 },
1155 { 76800000, P_PLL8, 5 },
1156 { 96000000, P_PLL8, 4 },
1157 { 160000000, P_PLL2, 5 },
1158 { 200000000, P_PLL2, 4 },
1162 static struct clk_rcg jpegd_src = {
1165 .pre_div_shift = 12,
1170 .parent_map = mmcc_pxo_pll8_pll2_map,
1172 .freq_tbl = clk_tbl_jpegd,
1174 .enable_reg = 0x00a4,
1175 .enable_mask = BIT(2),
1176 .hw.init = &(struct clk_init_data){
1177 .name = "jpegd_src",
1178 .parent_names = mmcc_pxo_pll8_pll2,
1180 .ops = &clk_rcg_ops,
1185 static struct clk_branch jpegd_clk = {
1189 .enable_reg = 0x00a4,
1190 .enable_mask = BIT(0),
1191 .hw.init = &(struct clk_init_data){
1192 .name = "jpegd_clk",
1193 .parent_names = (const char *[]){ "jpegd_src" },
1195 .ops = &clk_branch_ops,
1196 .flags = CLK_SET_RATE_PARENT,
1201 static struct freq_tbl clk_tbl_mdp[] = {
1202 { 9600000, P_PLL8, 1, 1, 40 },
1203 { 13710000, P_PLL8, 1, 1, 28 },
1204 { 27000000, P_PXO, 1, 0, 0 },
1205 { 29540000, P_PLL8, 1, 1, 13 },
1206 { 34910000, P_PLL8, 1, 1, 11 },
1207 { 38400000, P_PLL8, 1, 1, 10 },
1208 { 59080000, P_PLL8, 1, 2, 13 },
1209 { 76800000, P_PLL8, 1, 1, 5 },
1210 { 85330000, P_PLL8, 1, 2, 9 },
1211 { 96000000, P_PLL8, 1, 1, 4 },
1212 { 128000000, P_PLL8, 1, 1, 3 },
1213 { 160000000, P_PLL2, 1, 1, 5 },
1214 { 177780000, P_PLL2, 1, 2, 9 },
1215 { 200000000, P_PLL2, 1, 1, 4 },
1216 { 228571000, P_PLL2, 1, 2, 7 },
1217 { 266667000, P_PLL2, 1, 1, 3 },
1221 static struct clk_dyn_rcg mdp_src = {
1222 .ns_reg[0] = 0x00d0,
1223 .ns_reg[1] = 0x00d0,
1224 .md_reg[0] = 0x00c4,
1225 .md_reg[1] = 0x00c8,
1229 .mnctr_reset_bit = 31,
1230 .mnctr_mode_shift = 9,
1237 .mnctr_reset_bit = 30,
1238 .mnctr_mode_shift = 6,
1245 .parent_map = mmcc_pxo_pll8_pll2_map,
1249 .parent_map = mmcc_pxo_pll8_pll2_map,
1252 .freq_tbl = clk_tbl_mdp,
1254 .enable_reg = 0x00c0,
1255 .enable_mask = BIT(2),
1256 .hw.init = &(struct clk_init_data){
1258 .parent_names = mmcc_pxo_pll8_pll2,
1260 .ops = &clk_dyn_rcg_ops,
1265 static struct clk_branch mdp_clk = {
1269 .enable_reg = 0x00c0,
1270 .enable_mask = BIT(0),
1271 .hw.init = &(struct clk_init_data){
1273 .parent_names = (const char *[]){ "mdp_src" },
1275 .ops = &clk_branch_ops,
1276 .flags = CLK_SET_RATE_PARENT,
1281 static struct clk_branch mdp_lut_clk = {
1285 .enable_reg = 0x016c,
1286 .enable_mask = BIT(0),
1287 .hw.init = &(struct clk_init_data){
1288 .parent_names = (const char *[]){ "mdp_src" },
1290 .name = "mdp_lut_clk",
1291 .ops = &clk_branch_ops,
1292 .flags = CLK_SET_RATE_PARENT,
1297 static struct clk_branch mdp_vsync_clk = {
1301 .enable_reg = 0x0058,
1302 .enable_mask = BIT(6),
1303 .hw.init = &(struct clk_init_data){
1304 .name = "mdp_vsync_clk",
1305 .parent_names = (const char *[]){ "pxo" },
1307 .ops = &clk_branch_ops
1312 static struct freq_tbl clk_tbl_rot[] = {
1313 { 27000000, P_PXO, 1 },
1314 { 29540000, P_PLL8, 13 },
1315 { 32000000, P_PLL8, 12 },
1316 { 38400000, P_PLL8, 10 },
1317 { 48000000, P_PLL8, 8 },
1318 { 54860000, P_PLL8, 7 },
1319 { 64000000, P_PLL8, 6 },
1320 { 76800000, P_PLL8, 5 },
1321 { 96000000, P_PLL8, 4 },
1322 { 100000000, P_PLL2, 8 },
1323 { 114290000, P_PLL2, 7 },
1324 { 133330000, P_PLL2, 6 },
1325 { 160000000, P_PLL2, 5 },
1326 { 200000000, P_PLL2, 4 },
1330 static struct clk_dyn_rcg rot_src = {
1331 .ns_reg[0] = 0x00e8,
1332 .ns_reg[1] = 0x00e8,
1335 .pre_div_shift = 22,
1339 .pre_div_shift = 26,
1343 .src_sel_shift = 16,
1344 .parent_map = mmcc_pxo_pll8_pll2_map,
1347 .src_sel_shift = 19,
1348 .parent_map = mmcc_pxo_pll8_pll2_map,
1351 .freq_tbl = clk_tbl_rot,
1353 .enable_reg = 0x00e0,
1354 .enable_mask = BIT(2),
1355 .hw.init = &(struct clk_init_data){
1357 .parent_names = mmcc_pxo_pll8_pll2,
1359 .ops = &clk_dyn_rcg_ops,
1364 static struct clk_branch rot_clk = {
1368 .enable_reg = 0x00e0,
1369 .enable_mask = BIT(0),
1370 .hw.init = &(struct clk_init_data){
1372 .parent_names = (const char *[]){ "rot_src" },
1374 .ops = &clk_branch_ops,
1375 .flags = CLK_SET_RATE_PARENT,
1380 #define P_HDMI_PLL 1
1382 static u8 mmcc_pxo_hdmi_map[] = {
1387 static const char *mmcc_pxo_hdmi[] = {
1392 static struct freq_tbl clk_tbl_tv[] = {
1393 { .src = P_HDMI_PLL, .pre_div = 1 },
1397 static struct clk_rcg tv_src = {
1402 .mnctr_reset_bit = 7,
1403 .mnctr_mode_shift = 6,
1409 .pre_div_shift = 14,
1414 .parent_map = mmcc_pxo_hdmi_map,
1416 .freq_tbl = clk_tbl_tv,
1418 .enable_reg = 0x00ec,
1419 .enable_mask = BIT(2),
1420 .hw.init = &(struct clk_init_data){
1422 .parent_names = mmcc_pxo_hdmi,
1424 .ops = &clk_rcg_bypass_ops,
1425 .flags = CLK_SET_RATE_PARENT,
1430 static const char *tv_src_name[] = { "tv_src" };
1432 static struct clk_branch tv_enc_clk = {
1436 .enable_reg = 0x00ec,
1437 .enable_mask = BIT(8),
1438 .hw.init = &(struct clk_init_data){
1439 .parent_names = tv_src_name,
1441 .name = "tv_enc_clk",
1442 .ops = &clk_branch_ops,
1443 .flags = CLK_SET_RATE_PARENT,
1448 static struct clk_branch tv_dac_clk = {
1452 .enable_reg = 0x00ec,
1453 .enable_mask = BIT(10),
1454 .hw.init = &(struct clk_init_data){
1455 .parent_names = tv_src_name,
1457 .name = "tv_dac_clk",
1458 .ops = &clk_branch_ops,
1459 .flags = CLK_SET_RATE_PARENT,
1464 static struct clk_branch mdp_tv_clk = {
1468 .enable_reg = 0x00ec,
1469 .enable_mask = BIT(0),
1470 .hw.init = &(struct clk_init_data){
1471 .parent_names = tv_src_name,
1473 .name = "mdp_tv_clk",
1474 .ops = &clk_branch_ops,
1475 .flags = CLK_SET_RATE_PARENT,
1480 static struct clk_branch hdmi_tv_clk = {
1484 .enable_reg = 0x00ec,
1485 .enable_mask = BIT(12),
1486 .hw.init = &(struct clk_init_data){
1487 .parent_names = tv_src_name,
1489 .name = "hdmi_tv_clk",
1490 .ops = &clk_branch_ops,
1491 .flags = CLK_SET_RATE_PARENT,
1496 static struct clk_branch rgb_tv_clk = {
1500 .enable_reg = 0x0124,
1501 .enable_mask = BIT(14),
1502 .hw.init = &(struct clk_init_data){
1503 .parent_names = tv_src_name,
1505 .name = "rgb_tv_clk",
1506 .ops = &clk_branch_ops,
1507 .flags = CLK_SET_RATE_PARENT,
1512 static struct clk_branch npl_tv_clk = {
1516 .enable_reg = 0x0124,
1517 .enable_mask = BIT(16),
1518 .hw.init = &(struct clk_init_data){
1519 .parent_names = tv_src_name,
1521 .name = "npl_tv_clk",
1522 .ops = &clk_branch_ops,
1523 .flags = CLK_SET_RATE_PARENT,
1528 static struct clk_branch hdmi_app_clk = {
1532 .enable_reg = 0x005c,
1533 .enable_mask = BIT(11),
1534 .hw.init = &(struct clk_init_data){
1535 .parent_names = (const char *[]){ "pxo" },
1537 .name = "hdmi_app_clk",
1538 .ops = &clk_branch_ops,
1543 static struct freq_tbl clk_tbl_vcodec[] = {
1544 F_MN( 27000000, P_PXO, 1, 0),
1545 F_MN( 32000000, P_PLL8, 1, 12),
1546 F_MN( 48000000, P_PLL8, 1, 8),
1547 F_MN( 54860000, P_PLL8, 1, 7),
1548 F_MN( 96000000, P_PLL8, 1, 4),
1549 F_MN(133330000, P_PLL2, 1, 6),
1550 F_MN(200000000, P_PLL2, 1, 4),
1551 F_MN(228570000, P_PLL2, 2, 7),
1552 F_MN(266670000, P_PLL2, 1, 3),
1556 static struct clk_dyn_rcg vcodec_src = {
1557 .ns_reg[0] = 0x0100,
1558 .ns_reg[1] = 0x0100,
1559 .md_reg[0] = 0x00fc,
1560 .md_reg[1] = 0x0128,
1564 .mnctr_reset_bit = 31,
1565 .mnctr_mode_shift = 6,
1572 .mnctr_reset_bit = 30,
1573 .mnctr_mode_shift = 11,
1579 .src_sel_shift = 27,
1580 .parent_map = mmcc_pxo_pll8_pll2_map,
1584 .parent_map = mmcc_pxo_pll8_pll2_map,
1587 .freq_tbl = clk_tbl_vcodec,
1589 .enable_reg = 0x00f8,
1590 .enable_mask = BIT(2),
1591 .hw.init = &(struct clk_init_data){
1592 .name = "vcodec_src",
1593 .parent_names = mmcc_pxo_pll8_pll2,
1595 .ops = &clk_dyn_rcg_ops,
1600 static struct clk_branch vcodec_clk = {
1604 .enable_reg = 0x00f8,
1605 .enable_mask = BIT(0),
1606 .hw.init = &(struct clk_init_data){
1607 .name = "vcodec_clk",
1608 .parent_names = (const char *[]){ "vcodec_src" },
1610 .ops = &clk_branch_ops,
1611 .flags = CLK_SET_RATE_PARENT,
1616 static struct freq_tbl clk_tbl_vpe[] = {
1617 { 27000000, P_PXO, 1 },
1618 { 34909000, P_PLL8, 11 },
1619 { 38400000, P_PLL8, 10 },
1620 { 64000000, P_PLL8, 6 },
1621 { 76800000, P_PLL8, 5 },
1622 { 96000000, P_PLL8, 4 },
1623 { 100000000, P_PLL2, 8 },
1624 { 160000000, P_PLL2, 5 },
1628 static struct clk_rcg vpe_src = {
1631 .pre_div_shift = 12,
1636 .parent_map = mmcc_pxo_pll8_pll2_map,
1638 .freq_tbl = clk_tbl_vpe,
1640 .enable_reg = 0x0110,
1641 .enable_mask = BIT(2),
1642 .hw.init = &(struct clk_init_data){
1644 .parent_names = mmcc_pxo_pll8_pll2,
1646 .ops = &clk_rcg_ops,
1651 static struct clk_branch vpe_clk = {
1655 .enable_reg = 0x0110,
1656 .enable_mask = BIT(0),
1657 .hw.init = &(struct clk_init_data){
1659 .parent_names = (const char *[]){ "vpe_src" },
1661 .ops = &clk_branch_ops,
1662 .flags = CLK_SET_RATE_PARENT,
1667 static struct freq_tbl clk_tbl_vfe[] = {
1668 { 13960000, P_PLL8, 1, 2, 55 },
1669 { 27000000, P_PXO, 1, 0, 0 },
1670 { 36570000, P_PLL8, 1, 2, 21 },
1671 { 38400000, P_PLL8, 2, 1, 5 },
1672 { 45180000, P_PLL8, 1, 2, 17 },
1673 { 48000000, P_PLL8, 2, 1, 4 },
1674 { 54860000, P_PLL8, 1, 1, 7 },
1675 { 64000000, P_PLL8, 2, 1, 3 },
1676 { 76800000, P_PLL8, 1, 1, 5 },
1677 { 96000000, P_PLL8, 2, 1, 2 },
1678 { 109710000, P_PLL8, 1, 2, 7 },
1679 { 128000000, P_PLL8, 1, 1, 3 },
1680 { 153600000, P_PLL8, 1, 2, 5 },
1681 { 200000000, P_PLL2, 2, 1, 2 },
1682 { 228570000, P_PLL2, 1, 2, 7 },
1683 { 266667000, P_PLL2, 1, 1, 3 },
1684 { 320000000, P_PLL2, 1, 2, 5 },
1688 static struct clk_rcg vfe_src = {
1692 .mnctr_reset_bit = 7,
1693 .mnctr_mode_shift = 6,
1699 .pre_div_shift = 10,
1704 .parent_map = mmcc_pxo_pll8_pll2_map,
1706 .freq_tbl = clk_tbl_vfe,
1708 .enable_reg = 0x0104,
1709 .enable_mask = BIT(2),
1710 .hw.init = &(struct clk_init_data){
1712 .parent_names = mmcc_pxo_pll8_pll2,
1714 .ops = &clk_rcg_ops,
1719 static struct clk_branch vfe_clk = {
1723 .enable_reg = 0x0104,
1724 .enable_mask = BIT(0),
1725 .hw.init = &(struct clk_init_data){
1727 .parent_names = (const char *[]){ "vfe_src" },
1729 .ops = &clk_branch_ops,
1730 .flags = CLK_SET_RATE_PARENT,
1735 static struct clk_branch vfe_csi_clk = {
1739 .enable_reg = 0x0104,
1740 .enable_mask = BIT(12),
1741 .hw.init = &(struct clk_init_data){
1742 .parent_names = (const char *[]){ "vfe_src" },
1744 .name = "vfe_csi_clk",
1745 .ops = &clk_branch_ops,
1746 .flags = CLK_SET_RATE_PARENT,
1751 static struct clk_branch gmem_axi_clk = {
1755 .enable_reg = 0x0018,
1756 .enable_mask = BIT(24),
1757 .hw.init = &(struct clk_init_data){
1758 .name = "gmem_axi_clk",
1759 .ops = &clk_branch_ops,
1760 .flags = CLK_IS_ROOT,
1765 static struct clk_branch ijpeg_axi_clk = {
1771 .enable_reg = 0x0018,
1772 .enable_mask = BIT(21),
1773 .hw.init = &(struct clk_init_data){
1774 .name = "ijpeg_axi_clk",
1775 .ops = &clk_branch_ops,
1776 .flags = CLK_IS_ROOT,
1781 static struct clk_branch mmss_imem_axi_clk = {
1787 .enable_reg = 0x0018,
1788 .enable_mask = BIT(22),
1789 .hw.init = &(struct clk_init_data){
1790 .name = "mmss_imem_axi_clk",
1791 .ops = &clk_branch_ops,
1792 .flags = CLK_IS_ROOT,
1797 static struct clk_branch jpegd_axi_clk = {
1801 .enable_reg = 0x0018,
1802 .enable_mask = BIT(25),
1803 .hw.init = &(struct clk_init_data){
1804 .name = "jpegd_axi_clk",
1805 .ops = &clk_branch_ops,
1806 .flags = CLK_IS_ROOT,
1811 static struct clk_branch vcodec_axi_b_clk = {
1817 .enable_reg = 0x0114,
1818 .enable_mask = BIT(23),
1819 .hw.init = &(struct clk_init_data){
1820 .name = "vcodec_axi_b_clk",
1821 .ops = &clk_branch_ops,
1822 .flags = CLK_IS_ROOT,
1827 static struct clk_branch vcodec_axi_a_clk = {
1833 .enable_reg = 0x0114,
1834 .enable_mask = BIT(25),
1835 .hw.init = &(struct clk_init_data){
1836 .name = "vcodec_axi_a_clk",
1837 .ops = &clk_branch_ops,
1838 .flags = CLK_IS_ROOT,
1843 static struct clk_branch vcodec_axi_clk = {
1849 .enable_reg = 0x0018,
1850 .enable_mask = BIT(19),
1851 .hw.init = &(struct clk_init_data){
1852 .name = "vcodec_axi_clk",
1853 .ops = &clk_branch_ops,
1854 .flags = CLK_IS_ROOT,
1859 static struct clk_branch vfe_axi_clk = {
1863 .enable_reg = 0x0018,
1864 .enable_mask = BIT(18),
1865 .hw.init = &(struct clk_init_data){
1866 .name = "vfe_axi_clk",
1867 .ops = &clk_branch_ops,
1868 .flags = CLK_IS_ROOT,
1873 static struct clk_branch mdp_axi_clk = {
1879 .enable_reg = 0x0018,
1880 .enable_mask = BIT(23),
1881 .hw.init = &(struct clk_init_data){
1882 .name = "mdp_axi_clk",
1883 .ops = &clk_branch_ops,
1884 .flags = CLK_IS_ROOT,
1889 static struct clk_branch rot_axi_clk = {
1895 .enable_reg = 0x0020,
1896 .enable_mask = BIT(24),
1897 .hw.init = &(struct clk_init_data){
1898 .name = "rot_axi_clk",
1899 .ops = &clk_branch_ops,
1900 .flags = CLK_IS_ROOT,
1905 static struct clk_branch vcap_axi_clk = {
1911 .enable_reg = 0x0244,
1912 .enable_mask = BIT(12),
1913 .hw.init = &(struct clk_init_data){
1914 .name = "vcap_axi_clk",
1915 .ops = &clk_branch_ops,
1916 .flags = CLK_IS_ROOT,
1921 static struct clk_branch vpe_axi_clk = {
1927 .enable_reg = 0x0020,
1928 .enable_mask = BIT(26),
1929 .hw.init = &(struct clk_init_data){
1930 .name = "vpe_axi_clk",
1931 .ops = &clk_branch_ops,
1932 .flags = CLK_IS_ROOT,
1937 static struct clk_branch gfx3d_axi_clk = {
1943 .enable_reg = 0x0244,
1944 .enable_mask = BIT(25),
1945 .hw.init = &(struct clk_init_data){
1946 .name = "gfx3d_axi_clk",
1947 .ops = &clk_branch_ops,
1948 .flags = CLK_IS_ROOT,
1953 static struct clk_branch amp_ahb_clk = {
1957 .enable_reg = 0x0008,
1958 .enable_mask = BIT(24),
1959 .hw.init = &(struct clk_init_data){
1960 .name = "amp_ahb_clk",
1961 .ops = &clk_branch_ops,
1962 .flags = CLK_IS_ROOT,
1967 static struct clk_branch csi_ahb_clk = {
1971 .enable_reg = 0x0008,
1972 .enable_mask = BIT(7),
1973 .hw.init = &(struct clk_init_data){
1974 .name = "csi_ahb_clk",
1975 .ops = &clk_branch_ops,
1976 .flags = CLK_IS_ROOT
1981 static struct clk_branch dsi_m_ahb_clk = {
1985 .enable_reg = 0x0008,
1986 .enable_mask = BIT(9),
1987 .hw.init = &(struct clk_init_data){
1988 .name = "dsi_m_ahb_clk",
1989 .ops = &clk_branch_ops,
1990 .flags = CLK_IS_ROOT,
1995 static struct clk_branch dsi_s_ahb_clk = {
2001 .enable_reg = 0x0008,
2002 .enable_mask = BIT(18),
2003 .hw.init = &(struct clk_init_data){
2004 .name = "dsi_s_ahb_clk",
2005 .ops = &clk_branch_ops,
2006 .flags = CLK_IS_ROOT,
2011 static struct clk_branch dsi2_m_ahb_clk = {
2015 .enable_reg = 0x0008,
2016 .enable_mask = BIT(17),
2017 .hw.init = &(struct clk_init_data){
2018 .name = "dsi2_m_ahb_clk",
2019 .ops = &clk_branch_ops,
2020 .flags = CLK_IS_ROOT
2025 static struct clk_branch dsi2_s_ahb_clk = {
2031 .enable_reg = 0x0008,
2032 .enable_mask = BIT(22),
2033 .hw.init = &(struct clk_init_data){
2034 .name = "dsi2_s_ahb_clk",
2035 .ops = &clk_branch_ops,
2036 .flags = CLK_IS_ROOT,
2041 static struct clk_branch gfx2d0_ahb_clk = {
2047 .enable_reg = 0x0008,
2048 .enable_mask = BIT(19),
2049 .hw.init = &(struct clk_init_data){
2050 .name = "gfx2d0_ahb_clk",
2051 .ops = &clk_branch_ops,
2052 .flags = CLK_IS_ROOT,
2057 static struct clk_branch gfx2d1_ahb_clk = {
2063 .enable_reg = 0x0008,
2064 .enable_mask = BIT(2),
2065 .hw.init = &(struct clk_init_data){
2066 .name = "gfx2d1_ahb_clk",
2067 .ops = &clk_branch_ops,
2068 .flags = CLK_IS_ROOT,
2073 static struct clk_branch gfx3d_ahb_clk = {
2079 .enable_reg = 0x0008,
2080 .enable_mask = BIT(3),
2081 .hw.init = &(struct clk_init_data){
2082 .name = "gfx3d_ahb_clk",
2083 .ops = &clk_branch_ops,
2084 .flags = CLK_IS_ROOT,
2089 static struct clk_branch hdmi_m_ahb_clk = {
2095 .enable_reg = 0x0008,
2096 .enable_mask = BIT(14),
2097 .hw.init = &(struct clk_init_data){
2098 .name = "hdmi_m_ahb_clk",
2099 .ops = &clk_branch_ops,
2100 .flags = CLK_IS_ROOT,
2105 static struct clk_branch hdmi_s_ahb_clk = {
2111 .enable_reg = 0x0008,
2112 .enable_mask = BIT(4),
2113 .hw.init = &(struct clk_init_data){
2114 .name = "hdmi_s_ahb_clk",
2115 .ops = &clk_branch_ops,
2116 .flags = CLK_IS_ROOT,
2121 static struct clk_branch ijpeg_ahb_clk = {
2125 .enable_reg = 0x0008,
2126 .enable_mask = BIT(5),
2127 .hw.init = &(struct clk_init_data){
2128 .name = "ijpeg_ahb_clk",
2129 .ops = &clk_branch_ops,
2130 .flags = CLK_IS_ROOT
2135 static struct clk_branch mmss_imem_ahb_clk = {
2141 .enable_reg = 0x0008,
2142 .enable_mask = BIT(6),
2143 .hw.init = &(struct clk_init_data){
2144 .name = "mmss_imem_ahb_clk",
2145 .ops = &clk_branch_ops,
2146 .flags = CLK_IS_ROOT
2151 static struct clk_branch jpegd_ahb_clk = {
2155 .enable_reg = 0x0008,
2156 .enable_mask = BIT(21),
2157 .hw.init = &(struct clk_init_data){
2158 .name = "jpegd_ahb_clk",
2159 .ops = &clk_branch_ops,
2160 .flags = CLK_IS_ROOT,
2165 static struct clk_branch mdp_ahb_clk = {
2169 .enable_reg = 0x0008,
2170 .enable_mask = BIT(10),
2171 .hw.init = &(struct clk_init_data){
2172 .name = "mdp_ahb_clk",
2173 .ops = &clk_branch_ops,
2174 .flags = CLK_IS_ROOT,
2179 static struct clk_branch rot_ahb_clk = {
2183 .enable_reg = 0x0008,
2184 .enable_mask = BIT(12),
2185 .hw.init = &(struct clk_init_data){
2186 .name = "rot_ahb_clk",
2187 .ops = &clk_branch_ops,
2188 .flags = CLK_IS_ROOT
2193 static struct clk_branch smmu_ahb_clk = {
2199 .enable_reg = 0x0008,
2200 .enable_mask = BIT(15),
2201 .hw.init = &(struct clk_init_data){
2202 .name = "smmu_ahb_clk",
2203 .ops = &clk_branch_ops,
2204 .flags = CLK_IS_ROOT,
2209 static struct clk_branch tv_enc_ahb_clk = {
2213 .enable_reg = 0x0008,
2214 .enable_mask = BIT(25),
2215 .hw.init = &(struct clk_init_data){
2216 .name = "tv_enc_ahb_clk",
2217 .ops = &clk_branch_ops,
2218 .flags = CLK_IS_ROOT,
2223 static struct clk_branch vcap_ahb_clk = {
2227 .enable_reg = 0x0248,
2228 .enable_mask = BIT(1),
2229 .hw.init = &(struct clk_init_data){
2230 .name = "vcap_ahb_clk",
2231 .ops = &clk_branch_ops,
2232 .flags = CLK_IS_ROOT,
2237 static struct clk_branch vcodec_ahb_clk = {
2243 .enable_reg = 0x0008,
2244 .enable_mask = BIT(11),
2245 .hw.init = &(struct clk_init_data){
2246 .name = "vcodec_ahb_clk",
2247 .ops = &clk_branch_ops,
2248 .flags = CLK_IS_ROOT,
2253 static struct clk_branch vfe_ahb_clk = {
2257 .enable_reg = 0x0008,
2258 .enable_mask = BIT(13),
2259 .hw.init = &(struct clk_init_data){
2260 .name = "vfe_ahb_clk",
2261 .ops = &clk_branch_ops,
2262 .flags = CLK_IS_ROOT,
2267 static struct clk_branch vpe_ahb_clk = {
2271 .enable_reg = 0x0008,
2272 .enable_mask = BIT(16),
2273 .hw.init = &(struct clk_init_data){
2274 .name = "vpe_ahb_clk",
2275 .ops = &clk_branch_ops,
2276 .flags = CLK_IS_ROOT,
2281 static struct clk_regmap *mmcc_msm8960_clks[] = {
2282 [TV_ENC_AHB_CLK] = &tv_enc_ahb_clk.clkr,
2283 [AMP_AHB_CLK] = &_ahb_clk.clkr,
2284 [DSI2_S_AHB_CLK] = &dsi2_s_ahb_clk.clkr,
2285 [JPEGD_AHB_CLK] = &jpegd_ahb_clk.clkr,
2286 [GFX2D0_AHB_CLK] = &gfx2d0_ahb_clk.clkr,
2287 [DSI_S_AHB_CLK] = &dsi_s_ahb_clk.clkr,
2288 [DSI2_M_AHB_CLK] = &dsi2_m_ahb_clk.clkr,
2289 [VPE_AHB_CLK] = &vpe_ahb_clk.clkr,
2290 [SMMU_AHB_CLK] = &smmu_ahb_clk.clkr,
2291 [HDMI_M_AHB_CLK] = &hdmi_m_ahb_clk.clkr,
2292 [VFE_AHB_CLK] = &vfe_ahb_clk.clkr,
2293 [ROT_AHB_CLK] = &rot_ahb_clk.clkr,
2294 [VCODEC_AHB_CLK] = &vcodec_ahb_clk.clkr,
2295 [MDP_AHB_CLK] = &mdp_ahb_clk.clkr,
2296 [DSI_M_AHB_CLK] = &dsi_m_ahb_clk.clkr,
2297 [CSI_AHB_CLK] = &csi_ahb_clk.clkr,
2298 [MMSS_IMEM_AHB_CLK] = &mmss_imem_ahb_clk.clkr,
2299 [IJPEG_AHB_CLK] = &ijpeg_ahb_clk.clkr,
2300 [HDMI_S_AHB_CLK] = &hdmi_s_ahb_clk.clkr,
2301 [GFX3D_AHB_CLK] = &gfx3d_ahb_clk.clkr,
2302 [GFX2D1_AHB_CLK] = &gfx2d1_ahb_clk.clkr,
2303 [JPEGD_AXI_CLK] = &jpegd_axi_clk.clkr,
2304 [GMEM_AXI_CLK] = &gmem_axi_clk.clkr,
2305 [MDP_AXI_CLK] = &mdp_axi_clk.clkr,
2306 [MMSS_IMEM_AXI_CLK] = &mmss_imem_axi_clk.clkr,
2307 [IJPEG_AXI_CLK] = &ijpeg_axi_clk.clkr,
2308 [GFX3D_AXI_CLK] = &gfx3d_axi_clk.clkr,
2309 [VCODEC_AXI_CLK] = &vcodec_axi_clk.clkr,
2310 [VFE_AXI_CLK] = &vfe_axi_clk.clkr,
2311 [VPE_AXI_CLK] = &vpe_axi_clk.clkr,
2312 [ROT_AXI_CLK] = &rot_axi_clk.clkr,
2313 [VCODEC_AXI_A_CLK] = &vcodec_axi_a_clk.clkr,
2314 [VCODEC_AXI_B_CLK] = &vcodec_axi_b_clk.clkr,
2315 [CSI0_SRC] = &csi0_src.clkr,
2316 [CSI0_CLK] = &csi0_clk.clkr,
2317 [CSI0_PHY_CLK] = &csi0_phy_clk.clkr,
2318 [CSI1_SRC] = &csi1_src.clkr,
2319 [CSI1_CLK] = &csi1_clk.clkr,
2320 [CSI1_PHY_CLK] = &csi1_phy_clk.clkr,
2321 [CSI2_SRC] = &csi2_src.clkr,
2322 [CSI2_CLK] = &csi2_clk.clkr,
2323 [CSI2_PHY_CLK] = &csi2_phy_clk.clkr,
2324 [CSI_PIX_CLK] = &csi_pix_clk.clkr,
2325 [CSI_RDI_CLK] = &csi_rdi_clk.clkr,
2326 [MDP_VSYNC_CLK] = &mdp_vsync_clk.clkr,
2327 [HDMI_APP_CLK] = &hdmi_app_clk.clkr,
2328 [CSI_PIX1_CLK] = &csi_pix1_clk.clkr,
2329 [CSI_RDI2_CLK] = &csi_rdi2_clk.clkr,
2330 [CSI_RDI1_CLK] = &csi_rdi1_clk.clkr,
2331 [GFX2D0_SRC] = &gfx2d0_src.clkr,
2332 [GFX2D0_CLK] = &gfx2d0_clk.clkr,
2333 [GFX2D1_SRC] = &gfx2d1_src.clkr,
2334 [GFX2D1_CLK] = &gfx2d1_clk.clkr,
2335 [GFX3D_SRC] = &gfx3d_src.clkr,
2336 [GFX3D_CLK] = &gfx3d_clk.clkr,
2337 [IJPEG_SRC] = &ijpeg_src.clkr,
2338 [IJPEG_CLK] = &ijpeg_clk.clkr,
2339 [JPEGD_SRC] = &jpegd_src.clkr,
2340 [JPEGD_CLK] = &jpegd_clk.clkr,
2341 [MDP_SRC] = &mdp_src.clkr,
2342 [MDP_CLK] = &mdp_clk.clkr,
2343 [MDP_LUT_CLK] = &mdp_lut_clk.clkr,
2344 [ROT_SRC] = &rot_src.clkr,
2345 [ROT_CLK] = &rot_clk.clkr,
2346 [TV_ENC_CLK] = &tv_enc_clk.clkr,
2347 [TV_DAC_CLK] = &tv_dac_clk.clkr,
2348 [HDMI_TV_CLK] = &hdmi_tv_clk.clkr,
2349 [MDP_TV_CLK] = &mdp_tv_clk.clkr,
2350 [TV_SRC] = &tv_src.clkr,
2351 [VCODEC_SRC] = &vcodec_src.clkr,
2352 [VCODEC_CLK] = &vcodec_clk.clkr,
2353 [VFE_SRC] = &vfe_src.clkr,
2354 [VFE_CLK] = &vfe_clk.clkr,
2355 [VFE_CSI_CLK] = &vfe_csi_clk.clkr,
2356 [VPE_SRC] = &vpe_src.clkr,
2357 [VPE_CLK] = &vpe_clk.clkr,
2358 [CAMCLK0_SRC] = &camclk0_src.clkr,
2359 [CAMCLK0_CLK] = &camclk0_clk.clkr,
2360 [CAMCLK1_SRC] = &camclk1_src.clkr,
2361 [CAMCLK1_CLK] = &camclk1_clk.clkr,
2362 [CAMCLK2_SRC] = &camclk2_src.clkr,
2363 [CAMCLK2_CLK] = &camclk2_clk.clkr,
2364 [CSIPHYTIMER_SRC] = &csiphytimer_src.clkr,
2365 [CSIPHY2_TIMER_CLK] = &csiphy2_timer_clk.clkr,
2366 [CSIPHY1_TIMER_CLK] = &csiphy1_timer_clk.clkr,
2367 [CSIPHY0_TIMER_CLK] = &csiphy0_timer_clk.clkr,
2368 [PLL2] = &pll2.clkr,
2371 static const struct qcom_reset_map mmcc_msm8960_resets[] = {
2372 [VPE_AXI_RESET] = { 0x0208, 15 },
2373 [IJPEG_AXI_RESET] = { 0x0208, 14 },
2374 [MPD_AXI_RESET] = { 0x0208, 13 },
2375 [VFE_AXI_RESET] = { 0x0208, 9 },
2376 [SP_AXI_RESET] = { 0x0208, 8 },
2377 [VCODEC_AXI_RESET] = { 0x0208, 7 },
2378 [ROT_AXI_RESET] = { 0x0208, 6 },
2379 [VCODEC_AXI_A_RESET] = { 0x0208, 5 },
2380 [VCODEC_AXI_B_RESET] = { 0x0208, 4 },
2381 [FAB_S3_AXI_RESET] = { 0x0208, 3 },
2382 [FAB_S2_AXI_RESET] = { 0x0208, 2 },
2383 [FAB_S1_AXI_RESET] = { 0x0208, 1 },
2384 [FAB_S0_AXI_RESET] = { 0x0208 },
2385 [SMMU_GFX3D_ABH_RESET] = { 0x020c, 31 },
2386 [SMMU_VPE_AHB_RESET] = { 0x020c, 30 },
2387 [SMMU_VFE_AHB_RESET] = { 0x020c, 29 },
2388 [SMMU_ROT_AHB_RESET] = { 0x020c, 28 },
2389 [SMMU_VCODEC_B_AHB_RESET] = { 0x020c, 27 },
2390 [SMMU_VCODEC_A_AHB_RESET] = { 0x020c, 26 },
2391 [SMMU_MDP1_AHB_RESET] = { 0x020c, 25 },
2392 [SMMU_MDP0_AHB_RESET] = { 0x020c, 24 },
2393 [SMMU_JPEGD_AHB_RESET] = { 0x020c, 23 },
2394 [SMMU_IJPEG_AHB_RESET] = { 0x020c, 22 },
2395 [SMMU_GFX2D0_AHB_RESET] = { 0x020c, 21 },
2396 [SMMU_GFX2D1_AHB_RESET] = { 0x020c, 20 },
2397 [APU_AHB_RESET] = { 0x020c, 18 },
2398 [CSI_AHB_RESET] = { 0x020c, 17 },
2399 [TV_ENC_AHB_RESET] = { 0x020c, 15 },
2400 [VPE_AHB_RESET] = { 0x020c, 14 },
2401 [FABRIC_AHB_RESET] = { 0x020c, 13 },
2402 [GFX2D0_AHB_RESET] = { 0x020c, 12 },
2403 [GFX2D1_AHB_RESET] = { 0x020c, 11 },
2404 [GFX3D_AHB_RESET] = { 0x020c, 10 },
2405 [HDMI_AHB_RESET] = { 0x020c, 9 },
2406 [MSSS_IMEM_AHB_RESET] = { 0x020c, 8 },
2407 [IJPEG_AHB_RESET] = { 0x020c, 7 },
2408 [DSI_M_AHB_RESET] = { 0x020c, 6 },
2409 [DSI_S_AHB_RESET] = { 0x020c, 5 },
2410 [JPEGD_AHB_RESET] = { 0x020c, 4 },
2411 [MDP_AHB_RESET] = { 0x020c, 3 },
2412 [ROT_AHB_RESET] = { 0x020c, 2 },
2413 [VCODEC_AHB_RESET] = { 0x020c, 1 },
2414 [VFE_AHB_RESET] = { 0x020c, 0 },
2415 [DSI2_M_AHB_RESET] = { 0x0210, 31 },
2416 [DSI2_S_AHB_RESET] = { 0x0210, 30 },
2417 [CSIPHY2_RESET] = { 0x0210, 29 },
2418 [CSI_PIX1_RESET] = { 0x0210, 28 },
2419 [CSIPHY0_RESET] = { 0x0210, 27 },
2420 [CSIPHY1_RESET] = { 0x0210, 26 },
2421 [DSI2_RESET] = { 0x0210, 25 },
2422 [VFE_CSI_RESET] = { 0x0210, 24 },
2423 [MDP_RESET] = { 0x0210, 21 },
2424 [AMP_RESET] = { 0x0210, 20 },
2425 [JPEGD_RESET] = { 0x0210, 19 },
2426 [CSI1_RESET] = { 0x0210, 18 },
2427 [VPE_RESET] = { 0x0210, 17 },
2428 [MMSS_FABRIC_RESET] = { 0x0210, 16 },
2429 [VFE_RESET] = { 0x0210, 15 },
2430 [GFX2D0_RESET] = { 0x0210, 14 },
2431 [GFX2D1_RESET] = { 0x0210, 13 },
2432 [GFX3D_RESET] = { 0x0210, 12 },
2433 [HDMI_RESET] = { 0x0210, 11 },
2434 [MMSS_IMEM_RESET] = { 0x0210, 10 },
2435 [IJPEG_RESET] = { 0x0210, 9 },
2436 [CSI0_RESET] = { 0x0210, 8 },
2437 [DSI_RESET] = { 0x0210, 7 },
2438 [VCODEC_RESET] = { 0x0210, 6 },
2439 [MDP_TV_RESET] = { 0x0210, 4 },
2440 [MDP_VSYNC_RESET] = { 0x0210, 3 },
2441 [ROT_RESET] = { 0x0210, 2 },
2442 [TV_HDMI_RESET] = { 0x0210, 1 },
2443 [TV_ENC_RESET] = { 0x0210 },
2444 [CSI2_RESET] = { 0x0214, 2 },
2445 [CSI_RDI1_RESET] = { 0x0214, 1 },
2446 [CSI_RDI2_RESET] = { 0x0214 },
2449 static struct clk_regmap *mmcc_apq8064_clks[] = {
2450 [AMP_AHB_CLK] = &_ahb_clk.clkr,
2451 [DSI2_S_AHB_CLK] = &dsi2_s_ahb_clk.clkr,
2452 [JPEGD_AHB_CLK] = &jpegd_ahb_clk.clkr,
2453 [DSI_S_AHB_CLK] = &dsi_s_ahb_clk.clkr,
2454 [DSI2_M_AHB_CLK] = &dsi2_m_ahb_clk.clkr,
2455 [VPE_AHB_CLK] = &vpe_ahb_clk.clkr,
2456 [SMMU_AHB_CLK] = &smmu_ahb_clk.clkr,
2457 [HDMI_M_AHB_CLK] = &hdmi_m_ahb_clk.clkr,
2458 [VFE_AHB_CLK] = &vfe_ahb_clk.clkr,
2459 [ROT_AHB_CLK] = &rot_ahb_clk.clkr,
2460 [VCODEC_AHB_CLK] = &vcodec_ahb_clk.clkr,
2461 [MDP_AHB_CLK] = &mdp_ahb_clk.clkr,
2462 [DSI_M_AHB_CLK] = &dsi_m_ahb_clk.clkr,
2463 [CSI_AHB_CLK] = &csi_ahb_clk.clkr,
2464 [MMSS_IMEM_AHB_CLK] = &mmss_imem_ahb_clk.clkr,
2465 [IJPEG_AHB_CLK] = &ijpeg_ahb_clk.clkr,
2466 [HDMI_S_AHB_CLK] = &hdmi_s_ahb_clk.clkr,
2467 [GFX3D_AHB_CLK] = &gfx3d_ahb_clk.clkr,
2468 [JPEGD_AXI_CLK] = &jpegd_axi_clk.clkr,
2469 [GMEM_AXI_CLK] = &gmem_axi_clk.clkr,
2470 [MDP_AXI_CLK] = &mdp_axi_clk.clkr,
2471 [MMSS_IMEM_AXI_CLK] = &mmss_imem_axi_clk.clkr,
2472 [IJPEG_AXI_CLK] = &ijpeg_axi_clk.clkr,
2473 [GFX3D_AXI_CLK] = &gfx3d_axi_clk.clkr,
2474 [VCODEC_AXI_CLK] = &vcodec_axi_clk.clkr,
2475 [VFE_AXI_CLK] = &vfe_axi_clk.clkr,
2476 [VPE_AXI_CLK] = &vpe_axi_clk.clkr,
2477 [ROT_AXI_CLK] = &rot_axi_clk.clkr,
2478 [VCODEC_AXI_A_CLK] = &vcodec_axi_a_clk.clkr,
2479 [VCODEC_AXI_B_CLK] = &vcodec_axi_b_clk.clkr,
2480 [CSI0_SRC] = &csi0_src.clkr,
2481 [CSI0_CLK] = &csi0_clk.clkr,
2482 [CSI0_PHY_CLK] = &csi0_phy_clk.clkr,
2483 [CSI1_SRC] = &csi1_src.clkr,
2484 [CSI1_CLK] = &csi1_clk.clkr,
2485 [CSI1_PHY_CLK] = &csi1_phy_clk.clkr,
2486 [CSI2_SRC] = &csi2_src.clkr,
2487 [CSI2_CLK] = &csi2_clk.clkr,
2488 [CSI2_PHY_CLK] = &csi2_phy_clk.clkr,
2489 [CSI_PIX_CLK] = &csi_pix_clk.clkr,
2490 [CSI_RDI_CLK] = &csi_rdi_clk.clkr,
2491 [MDP_VSYNC_CLK] = &mdp_vsync_clk.clkr,
2492 [HDMI_APP_CLK] = &hdmi_app_clk.clkr,
2493 [CSI_PIX1_CLK] = &csi_pix1_clk.clkr,
2494 [CSI_RDI2_CLK] = &csi_rdi2_clk.clkr,
2495 [CSI_RDI1_CLK] = &csi_rdi1_clk.clkr,
2496 [GFX3D_SRC] = &gfx3d_src.clkr,
2497 [GFX3D_CLK] = &gfx3d_clk.clkr,
2498 [IJPEG_SRC] = &ijpeg_src.clkr,
2499 [IJPEG_CLK] = &ijpeg_clk.clkr,
2500 [JPEGD_SRC] = &jpegd_src.clkr,
2501 [JPEGD_CLK] = &jpegd_clk.clkr,
2502 [MDP_SRC] = &mdp_src.clkr,
2503 [MDP_CLK] = &mdp_clk.clkr,
2504 [MDP_LUT_CLK] = &mdp_lut_clk.clkr,
2505 [ROT_SRC] = &rot_src.clkr,
2506 [ROT_CLK] = &rot_clk.clkr,
2507 [TV_DAC_CLK] = &tv_dac_clk.clkr,
2508 [HDMI_TV_CLK] = &hdmi_tv_clk.clkr,
2509 [MDP_TV_CLK] = &mdp_tv_clk.clkr,
2510 [TV_SRC] = &tv_src.clkr,
2511 [VCODEC_SRC] = &vcodec_src.clkr,
2512 [VCODEC_CLK] = &vcodec_clk.clkr,
2513 [VFE_SRC] = &vfe_src.clkr,
2514 [VFE_CLK] = &vfe_clk.clkr,
2515 [VFE_CSI_CLK] = &vfe_csi_clk.clkr,
2516 [VPE_SRC] = &vpe_src.clkr,
2517 [VPE_CLK] = &vpe_clk.clkr,
2518 [CAMCLK0_SRC] = &camclk0_src.clkr,
2519 [CAMCLK0_CLK] = &camclk0_clk.clkr,
2520 [CAMCLK1_SRC] = &camclk1_src.clkr,
2521 [CAMCLK1_CLK] = &camclk1_clk.clkr,
2522 [CAMCLK2_SRC] = &camclk2_src.clkr,
2523 [CAMCLK2_CLK] = &camclk2_clk.clkr,
2524 [CSIPHYTIMER_SRC] = &csiphytimer_src.clkr,
2525 [CSIPHY2_TIMER_CLK] = &csiphy2_timer_clk.clkr,
2526 [CSIPHY1_TIMER_CLK] = &csiphy1_timer_clk.clkr,
2527 [CSIPHY0_TIMER_CLK] = &csiphy0_timer_clk.clkr,
2528 [PLL2] = &pll2.clkr,
2529 [RGB_TV_CLK] = &rgb_tv_clk.clkr,
2530 [NPL_TV_CLK] = &npl_tv_clk.clkr,
2531 [VCAP_AHB_CLK] = &vcap_ahb_clk.clkr,
2532 [VCAP_AXI_CLK] = &vcap_axi_clk.clkr,
2533 [VCAP_SRC] = &vcap_src.clkr,
2534 [VCAP_CLK] = &vcap_clk.clkr,
2535 [VCAP_NPL_CLK] = &vcap_npl_clk.clkr,
2536 [PLL15] = &pll15.clkr,
2539 static const struct qcom_reset_map mmcc_apq8064_resets[] = {
2540 [GFX3D_AXI_RESET] = { 0x0208, 17 },
2541 [VCAP_AXI_RESET] = { 0x0208, 16 },
2542 [VPE_AXI_RESET] = { 0x0208, 15 },
2543 [IJPEG_AXI_RESET] = { 0x0208, 14 },
2544 [MPD_AXI_RESET] = { 0x0208, 13 },
2545 [VFE_AXI_RESET] = { 0x0208, 9 },
2546 [SP_AXI_RESET] = { 0x0208, 8 },
2547 [VCODEC_AXI_RESET] = { 0x0208, 7 },
2548 [ROT_AXI_RESET] = { 0x0208, 6 },
2549 [VCODEC_AXI_A_RESET] = { 0x0208, 5 },
2550 [VCODEC_AXI_B_RESET] = { 0x0208, 4 },
2551 [FAB_S3_AXI_RESET] = { 0x0208, 3 },
2552 [FAB_S2_AXI_RESET] = { 0x0208, 2 },
2553 [FAB_S1_AXI_RESET] = { 0x0208, 1 },
2554 [FAB_S0_AXI_RESET] = { 0x0208 },
2555 [SMMU_GFX3D_ABH_RESET] = { 0x020c, 31 },
2556 [SMMU_VPE_AHB_RESET] = { 0x020c, 30 },
2557 [SMMU_VFE_AHB_RESET] = { 0x020c, 29 },
2558 [SMMU_ROT_AHB_RESET] = { 0x020c, 28 },
2559 [SMMU_VCODEC_B_AHB_RESET] = { 0x020c, 27 },
2560 [SMMU_VCODEC_A_AHB_RESET] = { 0x020c, 26 },
2561 [SMMU_MDP1_AHB_RESET] = { 0x020c, 25 },
2562 [SMMU_MDP0_AHB_RESET] = { 0x020c, 24 },
2563 [SMMU_JPEGD_AHB_RESET] = { 0x020c, 23 },
2564 [SMMU_IJPEG_AHB_RESET] = { 0x020c, 22 },
2565 [APU_AHB_RESET] = { 0x020c, 18 },
2566 [CSI_AHB_RESET] = { 0x020c, 17 },
2567 [TV_ENC_AHB_RESET] = { 0x020c, 15 },
2568 [VPE_AHB_RESET] = { 0x020c, 14 },
2569 [FABRIC_AHB_RESET] = { 0x020c, 13 },
2570 [GFX3D_AHB_RESET] = { 0x020c, 10 },
2571 [HDMI_AHB_RESET] = { 0x020c, 9 },
2572 [MSSS_IMEM_AHB_RESET] = { 0x020c, 8 },
2573 [IJPEG_AHB_RESET] = { 0x020c, 7 },
2574 [DSI_M_AHB_RESET] = { 0x020c, 6 },
2575 [DSI_S_AHB_RESET] = { 0x020c, 5 },
2576 [JPEGD_AHB_RESET] = { 0x020c, 4 },
2577 [MDP_AHB_RESET] = { 0x020c, 3 },
2578 [ROT_AHB_RESET] = { 0x020c, 2 },
2579 [VCODEC_AHB_RESET] = { 0x020c, 1 },
2580 [VFE_AHB_RESET] = { 0x020c, 0 },
2581 [SMMU_VCAP_AHB_RESET] = { 0x0200, 3 },
2582 [VCAP_AHB_RESET] = { 0x0200, 2 },
2583 [DSI2_M_AHB_RESET] = { 0x0200, 1 },
2584 [DSI2_S_AHB_RESET] = { 0x0200, 0 },
2585 [CSIPHY2_RESET] = { 0x0210, 31 },
2586 [CSI_PIX1_RESET] = { 0x0210, 30 },
2587 [CSIPHY0_RESET] = { 0x0210, 29 },
2588 [CSIPHY1_RESET] = { 0x0210, 28 },
2589 [CSI_RDI_RESET] = { 0x0210, 27 },
2590 [CSI_PIX_RESET] = { 0x0210, 26 },
2591 [DSI2_RESET] = { 0x0210, 25 },
2592 [VFE_CSI_RESET] = { 0x0210, 24 },
2593 [MDP_RESET] = { 0x0210, 21 },
2594 [AMP_RESET] = { 0x0210, 20 },
2595 [JPEGD_RESET] = { 0x0210, 19 },
2596 [CSI1_RESET] = { 0x0210, 18 },
2597 [VPE_RESET] = { 0x0210, 17 },
2598 [MMSS_FABRIC_RESET] = { 0x0210, 16 },
2599 [VFE_RESET] = { 0x0210, 15 },
2600 [GFX3D_RESET] = { 0x0210, 12 },
2601 [HDMI_RESET] = { 0x0210, 11 },
2602 [MMSS_IMEM_RESET] = { 0x0210, 10 },
2603 [IJPEG_RESET] = { 0x0210, 9 },
2604 [CSI0_RESET] = { 0x0210, 8 },
2605 [DSI_RESET] = { 0x0210, 7 },
2606 [VCODEC_RESET] = { 0x0210, 6 },
2607 [MDP_TV_RESET] = { 0x0210, 4 },
2608 [MDP_VSYNC_RESET] = { 0x0210, 3 },
2609 [ROT_RESET] = { 0x0210, 2 },
2610 [TV_HDMI_RESET] = { 0x0210, 1 },
2611 [VCAP_NPL_RESET] = { 0x0214, 4 },
2612 [VCAP_RESET] = { 0x0214, 3 },
2613 [CSI2_RESET] = { 0x0214, 2 },
2614 [CSI_RDI1_RESET] = { 0x0214, 1 },
2615 [CSI_RDI2_RESET] = { 0x0214 },
2618 static const struct regmap_config mmcc_msm8960_regmap_config = {
2622 .max_register = 0x334,
2626 static const struct regmap_config mmcc_apq8064_regmap_config = {
2630 .max_register = 0x350,
2634 static const struct qcom_cc_desc mmcc_msm8960_desc = {
2635 .config = &mmcc_msm8960_regmap_config,
2636 .clks = mmcc_msm8960_clks,
2637 .num_clks = ARRAY_SIZE(mmcc_msm8960_clks),
2638 .resets = mmcc_msm8960_resets,
2639 .num_resets = ARRAY_SIZE(mmcc_msm8960_resets),
2642 static const struct qcom_cc_desc mmcc_apq8064_desc = {
2643 .config = &mmcc_apq8064_regmap_config,
2644 .clks = mmcc_apq8064_clks,
2645 .num_clks = ARRAY_SIZE(mmcc_apq8064_clks),
2646 .resets = mmcc_apq8064_resets,
2647 .num_resets = ARRAY_SIZE(mmcc_apq8064_resets),
2650 static const struct of_device_id mmcc_msm8960_match_table[] = {
2651 { .compatible = "qcom,mmcc-msm8960", .data = &mmcc_msm8960_desc },
2652 { .compatible = "qcom,mmcc-apq8064", .data = &mmcc_apq8064_desc },
2655 MODULE_DEVICE_TABLE(of, mmcc_msm8960_match_table);
2657 static int mmcc_msm8960_probe(struct platform_device *pdev)
2659 const struct of_device_id *match;
2660 struct regmap *regmap;
2662 struct device *dev = &pdev->dev;
2664 match = of_match_device(mmcc_msm8960_match_table, dev);
2668 is_8064 = of_device_is_compatible(dev->of_node, "qcom,mmcc-apq8064");
2670 gfx3d_src.freq_tbl = clk_tbl_gfx3d_8064;
2671 gfx3d_src.clkr.hw.init = &gfx3d_8064_init;
2672 gfx3d_src.s[0].parent_map = mmcc_pxo_pll8_pll2_pll15_map;
2673 gfx3d_src.s[1].parent_map = mmcc_pxo_pll8_pll2_pll15_map;
2676 regmap = qcom_cc_map(pdev, match->data);
2678 return PTR_ERR(regmap);
2680 clk_pll_configure_sr(&pll15, regmap, &pll15_config, false);
2682 return qcom_cc_really_probe(pdev, match->data, regmap);
2685 static int mmcc_msm8960_remove(struct platform_device *pdev)
2687 qcom_cc_remove(pdev);
2691 static struct platform_driver mmcc_msm8960_driver = {
2692 .probe = mmcc_msm8960_probe,
2693 .remove = mmcc_msm8960_remove,
2695 .name = "mmcc-msm8960",
2696 .of_match_table = mmcc_msm8960_match_table,
2700 module_platform_driver(mmcc_msm8960_driver);
2702 MODULE_DESCRIPTION("QCOM MMCC MSM8960 Driver");
2703 MODULE_LICENSE("GPL v2");
2704 MODULE_ALIAS("platform:mmcc-msm8960");