2 * Copyright (c) 2013, The Linux Foundation. All rights reserved.
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
14 #include <linux/kernel.h>
15 #include <linux/bitops.h>
16 #include <linux/err.h>
17 #include <linux/platform_device.h>
18 #include <linux/module.h>
20 #include <linux/of_device.h>
21 #include <linux/clk-provider.h>
22 #include <linux/regmap.h>
23 #include <linux/reset-controller.h>
25 #include <dt-bindings/clock/qcom,mmcc-msm8974.h>
26 #include <dt-bindings/reset/qcom,mmcc-msm8974.h>
29 #include "clk-regmap.h"
32 #include "clk-branch.h"
44 #define P_DSI0PLL_BYTE 4
48 #define P_DSI1PLL_BYTE 5
50 static const u8 mmcc_xo_mmpll0_mmpll1_gpll0_map[] = {
57 static const char *mmcc_xo_mmpll0_mmpll1_gpll0[] = {
64 static const u8 mmcc_xo_mmpll0_dsi_hdmi_gpll0_map[] = {
73 static const char *mmcc_xo_mmpll0_dsi_hdmi_gpll0[] = {
82 static const u8 mmcc_xo_mmpll0_1_2_gpll0_map[] = {
90 static const char *mmcc_xo_mmpll0_1_2_gpll0[] = {
98 static const u8 mmcc_xo_mmpll0_1_3_gpll0_map[] = {
106 static const char *mmcc_xo_mmpll0_1_3_gpll0[] = {
114 static const u8 mmcc_xo_mmpll0_1_gpll1_0_map[] = {
122 static const char *mmcc_xo_mmpll0_1_gpll1_0[] = {
130 static const u8 mmcc_xo_dsi_hdmi_edp_map[] = {
139 static const char *mmcc_xo_dsi_hdmi_edp[] = {
148 static const u8 mmcc_xo_dsi_hdmi_edp_gpll0_map[] = {
157 static const char *mmcc_xo_dsi_hdmi_edp_gpll0[] = {
166 static const u8 mmcc_xo_dsibyte_hdmi_edp_gpll0_map[] = {
171 [P_DSI0PLL_BYTE] = 1,
172 [P_DSI1PLL_BYTE] = 2,
175 static const char *mmcc_xo_dsibyte_hdmi_edp_gpll0[] = {
184 #define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
186 static struct clk_pll mmpll0 = {
190 .config_reg = 0x0014,
192 .status_reg = 0x001c,
194 .clkr.hw.init = &(struct clk_init_data){
196 .parent_names = (const char *[]){ "xo" },
202 static struct clk_regmap mmpll0_vote = {
203 .enable_reg = 0x0100,
204 .enable_mask = BIT(0),
205 .hw.init = &(struct clk_init_data){
206 .name = "mmpll0_vote",
207 .parent_names = (const char *[]){ "mmpll0" },
209 .ops = &clk_pll_vote_ops,
213 static struct clk_pll mmpll1 = {
217 .config_reg = 0x0050,
219 .status_reg = 0x005c,
221 .clkr.hw.init = &(struct clk_init_data){
223 .parent_names = (const char *[]){ "xo" },
229 static struct clk_regmap mmpll1_vote = {
230 .enable_reg = 0x0100,
231 .enable_mask = BIT(1),
232 .hw.init = &(struct clk_init_data){
233 .name = "mmpll1_vote",
234 .parent_names = (const char *[]){ "mmpll1" },
236 .ops = &clk_pll_vote_ops,
240 static struct clk_pll mmpll2 = {
244 .config_reg = 0x4110,
246 .status_reg = 0x411c,
247 .clkr.hw.init = &(struct clk_init_data){
249 .parent_names = (const char *[]){ "xo" },
255 static struct clk_pll mmpll3 = {
259 .config_reg = 0x0090,
261 .status_reg = 0x009c,
263 .clkr.hw.init = &(struct clk_init_data){
265 .parent_names = (const char *[]){ "xo" },
271 static struct clk_rcg2 mmss_ahb_clk_src = {
274 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
275 .clkr.hw.init = &(struct clk_init_data){
276 .name = "mmss_ahb_clk_src",
277 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
279 .ops = &clk_rcg2_ops,
283 static struct freq_tbl ftbl_mmss_axi_clk[] = {
284 F( 19200000, P_XO, 1, 0, 0),
285 F( 37500000, P_GPLL0, 16, 0, 0),
286 F( 50000000, P_GPLL0, 12, 0, 0),
287 F( 75000000, P_GPLL0, 8, 0, 0),
288 F(100000000, P_GPLL0, 6, 0, 0),
289 F(150000000, P_GPLL0, 4, 0, 0),
290 F(291750000, P_MMPLL1, 4, 0, 0),
291 F(400000000, P_MMPLL0, 2, 0, 0),
292 F(466800000, P_MMPLL1, 2.5, 0, 0),
295 static struct clk_rcg2 mmss_axi_clk_src = {
298 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
299 .freq_tbl = ftbl_mmss_axi_clk,
300 .clkr.hw.init = &(struct clk_init_data){
301 .name = "mmss_axi_clk_src",
302 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
304 .ops = &clk_rcg2_ops,
308 static struct freq_tbl ftbl_ocmemnoc_clk[] = {
309 F( 19200000, P_XO, 1, 0, 0),
310 F( 37500000, P_GPLL0, 16, 0, 0),
311 F( 50000000, P_GPLL0, 12, 0, 0),
312 F( 75000000, P_GPLL0, 8, 0, 0),
313 F(100000000, P_GPLL0, 6, 0, 0),
314 F(150000000, P_GPLL0, 4, 0, 0),
315 F(291750000, P_MMPLL1, 4, 0, 0),
316 F(400000000, P_MMPLL0, 2, 0, 0),
319 static struct clk_rcg2 ocmemnoc_clk_src = {
322 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
323 .freq_tbl = ftbl_ocmemnoc_clk,
324 .clkr.hw.init = &(struct clk_init_data){
325 .name = "ocmemnoc_clk_src",
326 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
328 .ops = &clk_rcg2_ops,
332 static struct freq_tbl ftbl_camss_csi0_3_clk[] = {
333 F(100000000, P_GPLL0, 6, 0, 0),
334 F(200000000, P_MMPLL0, 4, 0, 0),
338 static struct clk_rcg2 csi0_clk_src = {
341 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
342 .freq_tbl = ftbl_camss_csi0_3_clk,
343 .clkr.hw.init = &(struct clk_init_data){
344 .name = "csi0_clk_src",
345 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
347 .ops = &clk_rcg2_ops,
351 static struct clk_rcg2 csi1_clk_src = {
354 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
355 .freq_tbl = ftbl_camss_csi0_3_clk,
356 .clkr.hw.init = &(struct clk_init_data){
357 .name = "csi1_clk_src",
358 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
360 .ops = &clk_rcg2_ops,
364 static struct clk_rcg2 csi2_clk_src = {
367 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
368 .freq_tbl = ftbl_camss_csi0_3_clk,
369 .clkr.hw.init = &(struct clk_init_data){
370 .name = "csi2_clk_src",
371 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
373 .ops = &clk_rcg2_ops,
377 static struct clk_rcg2 csi3_clk_src = {
380 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
381 .freq_tbl = ftbl_camss_csi0_3_clk,
382 .clkr.hw.init = &(struct clk_init_data){
383 .name = "csi3_clk_src",
384 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
386 .ops = &clk_rcg2_ops,
390 static struct freq_tbl ftbl_camss_vfe_vfe0_1_clk[] = {
391 F(37500000, P_GPLL0, 16, 0, 0),
392 F(50000000, P_GPLL0, 12, 0, 0),
393 F(60000000, P_GPLL0, 10, 0, 0),
394 F(80000000, P_GPLL0, 7.5, 0, 0),
395 F(100000000, P_GPLL0, 6, 0, 0),
396 F(109090000, P_GPLL0, 5.5, 0, 0),
397 F(133330000, P_GPLL0, 4.5, 0, 0),
398 F(200000000, P_GPLL0, 3, 0, 0),
399 F(228570000, P_MMPLL0, 3.5, 0, 0),
400 F(266670000, P_MMPLL0, 3, 0, 0),
401 F(320000000, P_MMPLL0, 2.5, 0, 0),
402 F(400000000, P_MMPLL0, 2, 0, 0),
403 F(465000000, P_MMPLL3, 2, 0, 0),
407 static struct clk_rcg2 vfe0_clk_src = {
410 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
411 .freq_tbl = ftbl_camss_vfe_vfe0_1_clk,
412 .clkr.hw.init = &(struct clk_init_data){
413 .name = "vfe0_clk_src",
414 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
416 .ops = &clk_rcg2_ops,
420 static struct clk_rcg2 vfe1_clk_src = {
423 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
424 .freq_tbl = ftbl_camss_vfe_vfe0_1_clk,
425 .clkr.hw.init = &(struct clk_init_data){
426 .name = "vfe1_clk_src",
427 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
429 .ops = &clk_rcg2_ops,
433 static struct freq_tbl ftbl_mdss_mdp_clk[] = {
434 F(37500000, P_GPLL0, 16, 0, 0),
435 F(60000000, P_GPLL0, 10, 0, 0),
436 F(75000000, P_GPLL0, 8, 0, 0),
437 F(85710000, P_GPLL0, 7, 0, 0),
438 F(100000000, P_GPLL0, 6, 0, 0),
439 F(133330000, P_MMPLL0, 6, 0, 0),
440 F(160000000, P_MMPLL0, 5, 0, 0),
441 F(200000000, P_MMPLL0, 4, 0, 0),
442 F(228570000, P_MMPLL0, 3.5, 0, 0),
443 F(240000000, P_GPLL0, 2.5, 0, 0),
444 F(266670000, P_MMPLL0, 3, 0, 0),
445 F(320000000, P_MMPLL0, 2.5, 0, 0),
449 static struct clk_rcg2 mdp_clk_src = {
452 .parent_map = mmcc_xo_mmpll0_dsi_hdmi_gpll0_map,
453 .freq_tbl = ftbl_mdss_mdp_clk,
454 .clkr.hw.init = &(struct clk_init_data){
455 .name = "mdp_clk_src",
456 .parent_names = mmcc_xo_mmpll0_dsi_hdmi_gpll0,
458 .ops = &clk_rcg2_ops,
462 static struct clk_rcg2 gfx3d_clk_src = {
465 .parent_map = mmcc_xo_mmpll0_1_2_gpll0_map,
466 .clkr.hw.init = &(struct clk_init_data){
467 .name = "gfx3d_clk_src",
468 .parent_names = mmcc_xo_mmpll0_1_2_gpll0,
470 .ops = &clk_rcg2_ops,
474 static struct freq_tbl ftbl_camss_jpeg_jpeg0_2_clk[] = {
475 F(75000000, P_GPLL0, 8, 0, 0),
476 F(133330000, P_GPLL0, 4.5, 0, 0),
477 F(200000000, P_GPLL0, 3, 0, 0),
478 F(228570000, P_MMPLL0, 3.5, 0, 0),
479 F(266670000, P_MMPLL0, 3, 0, 0),
480 F(320000000, P_MMPLL0, 2.5, 0, 0),
484 static struct clk_rcg2 jpeg0_clk_src = {
487 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
488 .freq_tbl = ftbl_camss_jpeg_jpeg0_2_clk,
489 .clkr.hw.init = &(struct clk_init_data){
490 .name = "jpeg0_clk_src",
491 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
493 .ops = &clk_rcg2_ops,
497 static struct clk_rcg2 jpeg1_clk_src = {
500 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
501 .freq_tbl = ftbl_camss_jpeg_jpeg0_2_clk,
502 .clkr.hw.init = &(struct clk_init_data){
503 .name = "jpeg1_clk_src",
504 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
506 .ops = &clk_rcg2_ops,
510 static struct clk_rcg2 jpeg2_clk_src = {
513 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
514 .freq_tbl = ftbl_camss_jpeg_jpeg0_2_clk,
515 .clkr.hw.init = &(struct clk_init_data){
516 .name = "jpeg2_clk_src",
517 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
519 .ops = &clk_rcg2_ops,
523 static struct freq_tbl pixel_freq_tbl[] = {
524 { .src = P_DSI0PLL },
528 static struct clk_rcg2 pclk0_clk_src = {
532 .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
533 .freq_tbl = pixel_freq_tbl,
534 .clkr.hw.init = &(struct clk_init_data){
535 .name = "pclk0_clk_src",
536 .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
538 .ops = &clk_pixel_ops,
539 .flags = CLK_SET_RATE_PARENT,
543 static struct clk_rcg2 pclk1_clk_src = {
547 .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
548 .freq_tbl = pixel_freq_tbl,
549 .clkr.hw.init = &(struct clk_init_data){
550 .name = "pclk1_clk_src",
551 .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
553 .ops = &clk_pixel_ops,
554 .flags = CLK_SET_RATE_PARENT,
558 static struct freq_tbl ftbl_venus0_vcodec0_clk[] = {
559 F(50000000, P_GPLL0, 12, 0, 0),
560 F(100000000, P_GPLL0, 6, 0, 0),
561 F(133330000, P_MMPLL0, 6, 0, 0),
562 F(200000000, P_MMPLL0, 4, 0, 0),
563 F(266670000, P_MMPLL0, 3, 0, 0),
564 F(465000000, P_MMPLL3, 2, 0, 0),
568 static struct clk_rcg2 vcodec0_clk_src = {
572 .parent_map = mmcc_xo_mmpll0_1_3_gpll0_map,
573 .freq_tbl = ftbl_venus0_vcodec0_clk,
574 .clkr.hw.init = &(struct clk_init_data){
575 .name = "vcodec0_clk_src",
576 .parent_names = mmcc_xo_mmpll0_1_3_gpll0,
578 .ops = &clk_rcg2_ops,
582 static struct freq_tbl ftbl_camss_cci_cci_clk[] = {
583 F(19200000, P_XO, 1, 0, 0),
587 static struct clk_rcg2 cci_clk_src = {
590 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
591 .freq_tbl = ftbl_camss_cci_cci_clk,
592 .clkr.hw.init = &(struct clk_init_data){
593 .name = "cci_clk_src",
594 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
596 .ops = &clk_rcg2_ops,
600 static struct freq_tbl ftbl_camss_gp0_1_clk[] = {
601 F(10000, P_XO, 16, 1, 120),
602 F(24000, P_XO, 16, 1, 50),
603 F(6000000, P_GPLL0, 10, 1, 10),
604 F(12000000, P_GPLL0, 10, 1, 5),
605 F(13000000, P_GPLL0, 4, 13, 150),
606 F(24000000, P_GPLL0, 5, 1, 5),
610 static struct clk_rcg2 camss_gp0_clk_src = {
614 .parent_map = mmcc_xo_mmpll0_1_gpll1_0_map,
615 .freq_tbl = ftbl_camss_gp0_1_clk,
616 .clkr.hw.init = &(struct clk_init_data){
617 .name = "camss_gp0_clk_src",
618 .parent_names = mmcc_xo_mmpll0_1_gpll1_0,
620 .ops = &clk_rcg2_ops,
624 static struct clk_rcg2 camss_gp1_clk_src = {
628 .parent_map = mmcc_xo_mmpll0_1_gpll1_0_map,
629 .freq_tbl = ftbl_camss_gp0_1_clk,
630 .clkr.hw.init = &(struct clk_init_data){
631 .name = "camss_gp1_clk_src",
632 .parent_names = mmcc_xo_mmpll0_1_gpll1_0,
634 .ops = &clk_rcg2_ops,
638 static struct freq_tbl ftbl_camss_mclk0_3_clk[] = {
639 F(4800000, P_XO, 4, 0, 0),
640 F(6000000, P_GPLL0, 10, 1, 10),
641 F(8000000, P_GPLL0, 15, 1, 5),
642 F(9600000, P_XO, 2, 0, 0),
643 F(16000000, P_GPLL0, 12.5, 1, 3),
644 F(19200000, P_XO, 1, 0, 0),
645 F(24000000, P_GPLL0, 5, 1, 5),
646 F(32000000, P_MMPLL0, 5, 1, 5),
647 F(48000000, P_GPLL0, 12.5, 0, 0),
648 F(64000000, P_MMPLL0, 12.5, 0, 0),
649 F(66670000, P_GPLL0, 9, 0, 0),
653 static struct clk_rcg2 mclk0_clk_src = {
656 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
657 .freq_tbl = ftbl_camss_mclk0_3_clk,
658 .clkr.hw.init = &(struct clk_init_data){
659 .name = "mclk0_clk_src",
660 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
662 .ops = &clk_rcg2_ops,
666 static struct clk_rcg2 mclk1_clk_src = {
669 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
670 .freq_tbl = ftbl_camss_mclk0_3_clk,
671 .clkr.hw.init = &(struct clk_init_data){
672 .name = "mclk1_clk_src",
673 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
675 .ops = &clk_rcg2_ops,
679 static struct clk_rcg2 mclk2_clk_src = {
682 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
683 .freq_tbl = ftbl_camss_mclk0_3_clk,
684 .clkr.hw.init = &(struct clk_init_data){
685 .name = "mclk2_clk_src",
686 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
688 .ops = &clk_rcg2_ops,
692 static struct clk_rcg2 mclk3_clk_src = {
695 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
696 .freq_tbl = ftbl_camss_mclk0_3_clk,
697 .clkr.hw.init = &(struct clk_init_data){
698 .name = "mclk3_clk_src",
699 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
701 .ops = &clk_rcg2_ops,
705 static struct freq_tbl ftbl_camss_phy0_2_csi0_2phytimer_clk[] = {
706 F(100000000, P_GPLL0, 6, 0, 0),
707 F(200000000, P_MMPLL0, 4, 0, 0),
711 static struct clk_rcg2 csi0phytimer_clk_src = {
714 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
715 .freq_tbl = ftbl_camss_phy0_2_csi0_2phytimer_clk,
716 .clkr.hw.init = &(struct clk_init_data){
717 .name = "csi0phytimer_clk_src",
718 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
720 .ops = &clk_rcg2_ops,
724 static struct clk_rcg2 csi1phytimer_clk_src = {
727 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
728 .freq_tbl = ftbl_camss_phy0_2_csi0_2phytimer_clk,
729 .clkr.hw.init = &(struct clk_init_data){
730 .name = "csi1phytimer_clk_src",
731 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
733 .ops = &clk_rcg2_ops,
737 static struct clk_rcg2 csi2phytimer_clk_src = {
740 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
741 .freq_tbl = ftbl_camss_phy0_2_csi0_2phytimer_clk,
742 .clkr.hw.init = &(struct clk_init_data){
743 .name = "csi2phytimer_clk_src",
744 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
746 .ops = &clk_rcg2_ops,
750 static struct freq_tbl ftbl_camss_vfe_cpp_clk[] = {
751 F(133330000, P_GPLL0, 4.5, 0, 0),
752 F(266670000, P_MMPLL0, 3, 0, 0),
753 F(320000000, P_MMPLL0, 2.5, 0, 0),
754 F(400000000, P_MMPLL0, 2, 0, 0),
755 F(465000000, P_MMPLL3, 2, 0, 0),
759 static struct clk_rcg2 cpp_clk_src = {
762 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
763 .freq_tbl = ftbl_camss_vfe_cpp_clk,
764 .clkr.hw.init = &(struct clk_init_data){
765 .name = "cpp_clk_src",
766 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
768 .ops = &clk_rcg2_ops,
772 static struct freq_tbl byte_freq_tbl[] = {
773 { .src = P_DSI0PLL_BYTE },
777 static struct clk_rcg2 byte0_clk_src = {
780 .parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map,
781 .freq_tbl = byte_freq_tbl,
782 .clkr.hw.init = &(struct clk_init_data){
783 .name = "byte0_clk_src",
784 .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0,
786 .ops = &clk_byte_ops,
787 .flags = CLK_SET_RATE_PARENT,
791 static struct clk_rcg2 byte1_clk_src = {
794 .parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map,
795 .freq_tbl = byte_freq_tbl,
796 .clkr.hw.init = &(struct clk_init_data){
797 .name = "byte1_clk_src",
798 .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0,
800 .ops = &clk_byte_ops,
801 .flags = CLK_SET_RATE_PARENT,
805 static struct freq_tbl ftbl_mdss_edpaux_clk[] = {
806 F(19200000, P_XO, 1, 0, 0),
810 static struct clk_rcg2 edpaux_clk_src = {
813 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
814 .freq_tbl = ftbl_mdss_edpaux_clk,
815 .clkr.hw.init = &(struct clk_init_data){
816 .name = "edpaux_clk_src",
817 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
819 .ops = &clk_rcg2_ops,
823 static struct freq_tbl ftbl_mdss_edplink_clk[] = {
824 F(135000000, P_EDPLINK, 2, 0, 0),
825 F(270000000, P_EDPLINK, 11, 0, 0),
829 static struct clk_rcg2 edplink_clk_src = {
832 .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
833 .freq_tbl = ftbl_mdss_edplink_clk,
834 .clkr.hw.init = &(struct clk_init_data){
835 .name = "edplink_clk_src",
836 .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
838 .ops = &clk_rcg2_ops,
839 .flags = CLK_SET_RATE_PARENT,
843 static struct freq_tbl edp_pixel_freq_tbl[] = {
848 static struct clk_rcg2 edppixel_clk_src = {
852 .parent_map = mmcc_xo_dsi_hdmi_edp_map,
853 .freq_tbl = edp_pixel_freq_tbl,
854 .clkr.hw.init = &(struct clk_init_data){
855 .name = "edppixel_clk_src",
856 .parent_names = mmcc_xo_dsi_hdmi_edp,
858 .ops = &clk_edp_pixel_ops,
862 static struct freq_tbl ftbl_mdss_esc0_1_clk[] = {
863 F(19200000, P_XO, 1, 0, 0),
867 static struct clk_rcg2 esc0_clk_src = {
870 .parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map,
871 .freq_tbl = ftbl_mdss_esc0_1_clk,
872 .clkr.hw.init = &(struct clk_init_data){
873 .name = "esc0_clk_src",
874 .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0,
876 .ops = &clk_rcg2_ops,
880 static struct clk_rcg2 esc1_clk_src = {
883 .parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map,
884 .freq_tbl = ftbl_mdss_esc0_1_clk,
885 .clkr.hw.init = &(struct clk_init_data){
886 .name = "esc1_clk_src",
887 .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0,
889 .ops = &clk_rcg2_ops,
893 static struct freq_tbl extpclk_freq_tbl[] = {
894 { .src = P_HDMIPLL },
898 static struct clk_rcg2 extpclk_clk_src = {
901 .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
902 .freq_tbl = extpclk_freq_tbl,
903 .clkr.hw.init = &(struct clk_init_data){
904 .name = "extpclk_clk_src",
905 .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
907 .ops = &clk_byte_ops,
908 .flags = CLK_SET_RATE_PARENT,
912 static struct freq_tbl ftbl_mdss_hdmi_clk[] = {
913 F(19200000, P_XO, 1, 0, 0),
917 static struct clk_rcg2 hdmi_clk_src = {
920 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
921 .freq_tbl = ftbl_mdss_hdmi_clk,
922 .clkr.hw.init = &(struct clk_init_data){
923 .name = "hdmi_clk_src",
924 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
926 .ops = &clk_rcg2_ops,
930 static struct freq_tbl ftbl_mdss_vsync_clk[] = {
931 F(19200000, P_XO, 1, 0, 0),
935 static struct clk_rcg2 vsync_clk_src = {
938 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
939 .freq_tbl = ftbl_mdss_vsync_clk,
940 .clkr.hw.init = &(struct clk_init_data){
941 .name = "vsync_clk_src",
942 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
944 .ops = &clk_rcg2_ops,
948 static struct clk_branch camss_cci_cci_ahb_clk = {
951 .enable_reg = 0x3348,
952 .enable_mask = BIT(0),
953 .hw.init = &(struct clk_init_data){
954 .name = "camss_cci_cci_ahb_clk",
955 .parent_names = (const char *[]){
959 .ops = &clk_branch2_ops,
964 static struct clk_branch camss_cci_cci_clk = {
967 .enable_reg = 0x3344,
968 .enable_mask = BIT(0),
969 .hw.init = &(struct clk_init_data){
970 .name = "camss_cci_cci_clk",
971 .parent_names = (const char *[]){
975 .flags = CLK_SET_RATE_PARENT,
976 .ops = &clk_branch2_ops,
981 static struct clk_branch camss_csi0_ahb_clk = {
984 .enable_reg = 0x30bc,
985 .enable_mask = BIT(0),
986 .hw.init = &(struct clk_init_data){
987 .name = "camss_csi0_ahb_clk",
988 .parent_names = (const char *[]){
992 .ops = &clk_branch2_ops,
997 static struct clk_branch camss_csi0_clk = {
1000 .enable_reg = 0x30b4,
1001 .enable_mask = BIT(0),
1002 .hw.init = &(struct clk_init_data){
1003 .name = "camss_csi0_clk",
1004 .parent_names = (const char *[]){
1008 .flags = CLK_SET_RATE_PARENT,
1009 .ops = &clk_branch2_ops,
1014 static struct clk_branch camss_csi0phy_clk = {
1017 .enable_reg = 0x30c4,
1018 .enable_mask = BIT(0),
1019 .hw.init = &(struct clk_init_data){
1020 .name = "camss_csi0phy_clk",
1021 .parent_names = (const char *[]){
1025 .flags = CLK_SET_RATE_PARENT,
1026 .ops = &clk_branch2_ops,
1031 static struct clk_branch camss_csi0pix_clk = {
1034 .enable_reg = 0x30e4,
1035 .enable_mask = BIT(0),
1036 .hw.init = &(struct clk_init_data){
1037 .name = "camss_csi0pix_clk",
1038 .parent_names = (const char *[]){
1042 .flags = CLK_SET_RATE_PARENT,
1043 .ops = &clk_branch2_ops,
1048 static struct clk_branch camss_csi0rdi_clk = {
1051 .enable_reg = 0x30d4,
1052 .enable_mask = BIT(0),
1053 .hw.init = &(struct clk_init_data){
1054 .name = "camss_csi0rdi_clk",
1055 .parent_names = (const char *[]){
1059 .flags = CLK_SET_RATE_PARENT,
1060 .ops = &clk_branch2_ops,
1065 static struct clk_branch camss_csi1_ahb_clk = {
1068 .enable_reg = 0x3128,
1069 .enable_mask = BIT(0),
1070 .hw.init = &(struct clk_init_data){
1071 .name = "camss_csi1_ahb_clk",
1072 .parent_names = (const char *[]){
1076 .ops = &clk_branch2_ops,
1081 static struct clk_branch camss_csi1_clk = {
1084 .enable_reg = 0x3124,
1085 .enable_mask = BIT(0),
1086 .hw.init = &(struct clk_init_data){
1087 .name = "camss_csi1_clk",
1088 .parent_names = (const char *[]){
1092 .flags = CLK_SET_RATE_PARENT,
1093 .ops = &clk_branch2_ops,
1098 static struct clk_branch camss_csi1phy_clk = {
1101 .enable_reg = 0x3134,
1102 .enable_mask = BIT(0),
1103 .hw.init = &(struct clk_init_data){
1104 .name = "camss_csi1phy_clk",
1105 .parent_names = (const char *[]){
1109 .flags = CLK_SET_RATE_PARENT,
1110 .ops = &clk_branch2_ops,
1115 static struct clk_branch camss_csi1pix_clk = {
1118 .enable_reg = 0x3154,
1119 .enable_mask = BIT(0),
1120 .hw.init = &(struct clk_init_data){
1121 .name = "camss_csi1pix_clk",
1122 .parent_names = (const char *[]){
1126 .flags = CLK_SET_RATE_PARENT,
1127 .ops = &clk_branch2_ops,
1132 static struct clk_branch camss_csi1rdi_clk = {
1135 .enable_reg = 0x3144,
1136 .enable_mask = BIT(0),
1137 .hw.init = &(struct clk_init_data){
1138 .name = "camss_csi1rdi_clk",
1139 .parent_names = (const char *[]){
1143 .flags = CLK_SET_RATE_PARENT,
1144 .ops = &clk_branch2_ops,
1149 static struct clk_branch camss_csi2_ahb_clk = {
1152 .enable_reg = 0x3188,
1153 .enable_mask = BIT(0),
1154 .hw.init = &(struct clk_init_data){
1155 .name = "camss_csi2_ahb_clk",
1156 .parent_names = (const char *[]){
1160 .ops = &clk_branch2_ops,
1165 static struct clk_branch camss_csi2_clk = {
1168 .enable_reg = 0x3184,
1169 .enable_mask = BIT(0),
1170 .hw.init = &(struct clk_init_data){
1171 .name = "camss_csi2_clk",
1172 .parent_names = (const char *[]){
1176 .flags = CLK_SET_RATE_PARENT,
1177 .ops = &clk_branch2_ops,
1182 static struct clk_branch camss_csi2phy_clk = {
1185 .enable_reg = 0x3194,
1186 .enable_mask = BIT(0),
1187 .hw.init = &(struct clk_init_data){
1188 .name = "camss_csi2phy_clk",
1189 .parent_names = (const char *[]){
1193 .flags = CLK_SET_RATE_PARENT,
1194 .ops = &clk_branch2_ops,
1199 static struct clk_branch camss_csi2pix_clk = {
1202 .enable_reg = 0x31b4,
1203 .enable_mask = BIT(0),
1204 .hw.init = &(struct clk_init_data){
1205 .name = "camss_csi2pix_clk",
1206 .parent_names = (const char *[]){
1210 .flags = CLK_SET_RATE_PARENT,
1211 .ops = &clk_branch2_ops,
1216 static struct clk_branch camss_csi2rdi_clk = {
1219 .enable_reg = 0x31a4,
1220 .enable_mask = BIT(0),
1221 .hw.init = &(struct clk_init_data){
1222 .name = "camss_csi2rdi_clk",
1223 .parent_names = (const char *[]){
1227 .flags = CLK_SET_RATE_PARENT,
1228 .ops = &clk_branch2_ops,
1233 static struct clk_branch camss_csi3_ahb_clk = {
1236 .enable_reg = 0x31e8,
1237 .enable_mask = BIT(0),
1238 .hw.init = &(struct clk_init_data){
1239 .name = "camss_csi3_ahb_clk",
1240 .parent_names = (const char *[]){
1244 .ops = &clk_branch2_ops,
1249 static struct clk_branch camss_csi3_clk = {
1252 .enable_reg = 0x31e4,
1253 .enable_mask = BIT(0),
1254 .hw.init = &(struct clk_init_data){
1255 .name = "camss_csi3_clk",
1256 .parent_names = (const char *[]){
1260 .flags = CLK_SET_RATE_PARENT,
1261 .ops = &clk_branch2_ops,
1266 static struct clk_branch camss_csi3phy_clk = {
1269 .enable_reg = 0x31f4,
1270 .enable_mask = BIT(0),
1271 .hw.init = &(struct clk_init_data){
1272 .name = "camss_csi3phy_clk",
1273 .parent_names = (const char *[]){
1277 .flags = CLK_SET_RATE_PARENT,
1278 .ops = &clk_branch2_ops,
1283 static struct clk_branch camss_csi3pix_clk = {
1286 .enable_reg = 0x3214,
1287 .enable_mask = BIT(0),
1288 .hw.init = &(struct clk_init_data){
1289 .name = "camss_csi3pix_clk",
1290 .parent_names = (const char *[]){
1294 .flags = CLK_SET_RATE_PARENT,
1295 .ops = &clk_branch2_ops,
1300 static struct clk_branch camss_csi3rdi_clk = {
1303 .enable_reg = 0x3204,
1304 .enable_mask = BIT(0),
1305 .hw.init = &(struct clk_init_data){
1306 .name = "camss_csi3rdi_clk",
1307 .parent_names = (const char *[]){
1311 .flags = CLK_SET_RATE_PARENT,
1312 .ops = &clk_branch2_ops,
1317 static struct clk_branch camss_csi_vfe0_clk = {
1320 .enable_reg = 0x3704,
1321 .enable_mask = BIT(0),
1322 .hw.init = &(struct clk_init_data){
1323 .name = "camss_csi_vfe0_clk",
1324 .parent_names = (const char *[]){
1328 .flags = CLK_SET_RATE_PARENT,
1329 .ops = &clk_branch2_ops,
1334 static struct clk_branch camss_csi_vfe1_clk = {
1337 .enable_reg = 0x3714,
1338 .enable_mask = BIT(0),
1339 .hw.init = &(struct clk_init_data){
1340 .name = "camss_csi_vfe1_clk",
1341 .parent_names = (const char *[]){
1345 .flags = CLK_SET_RATE_PARENT,
1346 .ops = &clk_branch2_ops,
1351 static struct clk_branch camss_gp0_clk = {
1354 .enable_reg = 0x3444,
1355 .enable_mask = BIT(0),
1356 .hw.init = &(struct clk_init_data){
1357 .name = "camss_gp0_clk",
1358 .parent_names = (const char *[]){
1359 "camss_gp0_clk_src",
1362 .flags = CLK_SET_RATE_PARENT,
1363 .ops = &clk_branch2_ops,
1368 static struct clk_branch camss_gp1_clk = {
1371 .enable_reg = 0x3474,
1372 .enable_mask = BIT(0),
1373 .hw.init = &(struct clk_init_data){
1374 .name = "camss_gp1_clk",
1375 .parent_names = (const char *[]){
1376 "camss_gp1_clk_src",
1379 .flags = CLK_SET_RATE_PARENT,
1380 .ops = &clk_branch2_ops,
1385 static struct clk_branch camss_ispif_ahb_clk = {
1388 .enable_reg = 0x3224,
1389 .enable_mask = BIT(0),
1390 .hw.init = &(struct clk_init_data){
1391 .name = "camss_ispif_ahb_clk",
1392 .parent_names = (const char *[]){
1396 .ops = &clk_branch2_ops,
1401 static struct clk_branch camss_jpeg_jpeg0_clk = {
1404 .enable_reg = 0x35a8,
1405 .enable_mask = BIT(0),
1406 .hw.init = &(struct clk_init_data){
1407 .name = "camss_jpeg_jpeg0_clk",
1408 .parent_names = (const char *[]){
1412 .flags = CLK_SET_RATE_PARENT,
1413 .ops = &clk_branch2_ops,
1418 static struct clk_branch camss_jpeg_jpeg1_clk = {
1421 .enable_reg = 0x35ac,
1422 .enable_mask = BIT(0),
1423 .hw.init = &(struct clk_init_data){
1424 .name = "camss_jpeg_jpeg1_clk",
1425 .parent_names = (const char *[]){
1429 .flags = CLK_SET_RATE_PARENT,
1430 .ops = &clk_branch2_ops,
1435 static struct clk_branch camss_jpeg_jpeg2_clk = {
1438 .enable_reg = 0x35b0,
1439 .enable_mask = BIT(0),
1440 .hw.init = &(struct clk_init_data){
1441 .name = "camss_jpeg_jpeg2_clk",
1442 .parent_names = (const char *[]){
1446 .flags = CLK_SET_RATE_PARENT,
1447 .ops = &clk_branch2_ops,
1452 static struct clk_branch camss_jpeg_jpeg_ahb_clk = {
1455 .enable_reg = 0x35b4,
1456 .enable_mask = BIT(0),
1457 .hw.init = &(struct clk_init_data){
1458 .name = "camss_jpeg_jpeg_ahb_clk",
1459 .parent_names = (const char *[]){
1463 .ops = &clk_branch2_ops,
1468 static struct clk_branch camss_jpeg_jpeg_axi_clk = {
1471 .enable_reg = 0x35b8,
1472 .enable_mask = BIT(0),
1473 .hw.init = &(struct clk_init_data){
1474 .name = "camss_jpeg_jpeg_axi_clk",
1475 .parent_names = (const char *[]){
1479 .ops = &clk_branch2_ops,
1484 static struct clk_branch camss_jpeg_jpeg_ocmemnoc_clk = {
1487 .enable_reg = 0x35bc,
1488 .enable_mask = BIT(0),
1489 .hw.init = &(struct clk_init_data){
1490 .name = "camss_jpeg_jpeg_ocmemnoc_clk",
1491 .parent_names = (const char *[]){
1495 .flags = CLK_SET_RATE_PARENT,
1496 .ops = &clk_branch2_ops,
1501 static struct clk_branch camss_mclk0_clk = {
1504 .enable_reg = 0x3384,
1505 .enable_mask = BIT(0),
1506 .hw.init = &(struct clk_init_data){
1507 .name = "camss_mclk0_clk",
1508 .parent_names = (const char *[]){
1512 .flags = CLK_SET_RATE_PARENT,
1513 .ops = &clk_branch2_ops,
1518 static struct clk_branch camss_mclk1_clk = {
1521 .enable_reg = 0x33b4,
1522 .enable_mask = BIT(0),
1523 .hw.init = &(struct clk_init_data){
1524 .name = "camss_mclk1_clk",
1525 .parent_names = (const char *[]){
1529 .flags = CLK_SET_RATE_PARENT,
1530 .ops = &clk_branch2_ops,
1535 static struct clk_branch camss_mclk2_clk = {
1538 .enable_reg = 0x33e4,
1539 .enable_mask = BIT(0),
1540 .hw.init = &(struct clk_init_data){
1541 .name = "camss_mclk2_clk",
1542 .parent_names = (const char *[]){
1546 .flags = CLK_SET_RATE_PARENT,
1547 .ops = &clk_branch2_ops,
1552 static struct clk_branch camss_mclk3_clk = {
1555 .enable_reg = 0x3414,
1556 .enable_mask = BIT(0),
1557 .hw.init = &(struct clk_init_data){
1558 .name = "camss_mclk3_clk",
1559 .parent_names = (const char *[]){
1563 .flags = CLK_SET_RATE_PARENT,
1564 .ops = &clk_branch2_ops,
1569 static struct clk_branch camss_micro_ahb_clk = {
1572 .enable_reg = 0x3494,
1573 .enable_mask = BIT(0),
1574 .hw.init = &(struct clk_init_data){
1575 .name = "camss_micro_ahb_clk",
1576 .parent_names = (const char *[]){
1580 .ops = &clk_branch2_ops,
1585 static struct clk_branch camss_phy0_csi0phytimer_clk = {
1588 .enable_reg = 0x3024,
1589 .enable_mask = BIT(0),
1590 .hw.init = &(struct clk_init_data){
1591 .name = "camss_phy0_csi0phytimer_clk",
1592 .parent_names = (const char *[]){
1593 "csi0phytimer_clk_src",
1596 .flags = CLK_SET_RATE_PARENT,
1597 .ops = &clk_branch2_ops,
1602 static struct clk_branch camss_phy1_csi1phytimer_clk = {
1605 .enable_reg = 0x3054,
1606 .enable_mask = BIT(0),
1607 .hw.init = &(struct clk_init_data){
1608 .name = "camss_phy1_csi1phytimer_clk",
1609 .parent_names = (const char *[]){
1610 "csi1phytimer_clk_src",
1613 .flags = CLK_SET_RATE_PARENT,
1614 .ops = &clk_branch2_ops,
1619 static struct clk_branch camss_phy2_csi2phytimer_clk = {
1622 .enable_reg = 0x3084,
1623 .enable_mask = BIT(0),
1624 .hw.init = &(struct clk_init_data){
1625 .name = "camss_phy2_csi2phytimer_clk",
1626 .parent_names = (const char *[]){
1627 "csi2phytimer_clk_src",
1630 .flags = CLK_SET_RATE_PARENT,
1631 .ops = &clk_branch2_ops,
1636 static struct clk_branch camss_top_ahb_clk = {
1639 .enable_reg = 0x3484,
1640 .enable_mask = BIT(0),
1641 .hw.init = &(struct clk_init_data){
1642 .name = "camss_top_ahb_clk",
1643 .parent_names = (const char *[]){
1647 .ops = &clk_branch2_ops,
1652 static struct clk_branch camss_vfe_cpp_ahb_clk = {
1655 .enable_reg = 0x36b4,
1656 .enable_mask = BIT(0),
1657 .hw.init = &(struct clk_init_data){
1658 .name = "camss_vfe_cpp_ahb_clk",
1659 .parent_names = (const char *[]){
1663 .ops = &clk_branch2_ops,
1668 static struct clk_branch camss_vfe_cpp_clk = {
1671 .enable_reg = 0x36b0,
1672 .enable_mask = BIT(0),
1673 .hw.init = &(struct clk_init_data){
1674 .name = "camss_vfe_cpp_clk",
1675 .parent_names = (const char *[]){
1679 .flags = CLK_SET_RATE_PARENT,
1680 .ops = &clk_branch2_ops,
1685 static struct clk_branch camss_vfe_vfe0_clk = {
1688 .enable_reg = 0x36a8,
1689 .enable_mask = BIT(0),
1690 .hw.init = &(struct clk_init_data){
1691 .name = "camss_vfe_vfe0_clk",
1692 .parent_names = (const char *[]){
1696 .flags = CLK_SET_RATE_PARENT,
1697 .ops = &clk_branch2_ops,
1702 static struct clk_branch camss_vfe_vfe1_clk = {
1705 .enable_reg = 0x36ac,
1706 .enable_mask = BIT(0),
1707 .hw.init = &(struct clk_init_data){
1708 .name = "camss_vfe_vfe1_clk",
1709 .parent_names = (const char *[]){
1713 .flags = CLK_SET_RATE_PARENT,
1714 .ops = &clk_branch2_ops,
1719 static struct clk_branch camss_vfe_vfe_ahb_clk = {
1722 .enable_reg = 0x36b8,
1723 .enable_mask = BIT(0),
1724 .hw.init = &(struct clk_init_data){
1725 .name = "camss_vfe_vfe_ahb_clk",
1726 .parent_names = (const char *[]){
1730 .ops = &clk_branch2_ops,
1735 static struct clk_branch camss_vfe_vfe_axi_clk = {
1738 .enable_reg = 0x36bc,
1739 .enable_mask = BIT(0),
1740 .hw.init = &(struct clk_init_data){
1741 .name = "camss_vfe_vfe_axi_clk",
1742 .parent_names = (const char *[]){
1746 .ops = &clk_branch2_ops,
1751 static struct clk_branch camss_vfe_vfe_ocmemnoc_clk = {
1754 .enable_reg = 0x36c0,
1755 .enable_mask = BIT(0),
1756 .hw.init = &(struct clk_init_data){
1757 .name = "camss_vfe_vfe_ocmemnoc_clk",
1758 .parent_names = (const char *[]){
1762 .flags = CLK_SET_RATE_PARENT,
1763 .ops = &clk_branch2_ops,
1768 static struct clk_branch mdss_ahb_clk = {
1771 .enable_reg = 0x2308,
1772 .enable_mask = BIT(0),
1773 .hw.init = &(struct clk_init_data){
1774 .name = "mdss_ahb_clk",
1775 .parent_names = (const char *[]){
1779 .ops = &clk_branch2_ops,
1784 static struct clk_branch mdss_axi_clk = {
1787 .enable_reg = 0x2310,
1788 .enable_mask = BIT(0),
1789 .hw.init = &(struct clk_init_data){
1790 .name = "mdss_axi_clk",
1791 .parent_names = (const char *[]){
1795 .flags = CLK_SET_RATE_PARENT,
1796 .ops = &clk_branch2_ops,
1801 static struct clk_branch mdss_byte0_clk = {
1804 .enable_reg = 0x233c,
1805 .enable_mask = BIT(0),
1806 .hw.init = &(struct clk_init_data){
1807 .name = "mdss_byte0_clk",
1808 .parent_names = (const char *[]){
1812 .flags = CLK_SET_RATE_PARENT,
1813 .ops = &clk_branch2_ops,
1818 static struct clk_branch mdss_byte1_clk = {
1821 .enable_reg = 0x2340,
1822 .enable_mask = BIT(0),
1823 .hw.init = &(struct clk_init_data){
1824 .name = "mdss_byte1_clk",
1825 .parent_names = (const char *[]){
1829 .flags = CLK_SET_RATE_PARENT,
1830 .ops = &clk_branch2_ops,
1835 static struct clk_branch mdss_edpaux_clk = {
1838 .enable_reg = 0x2334,
1839 .enable_mask = BIT(0),
1840 .hw.init = &(struct clk_init_data){
1841 .name = "mdss_edpaux_clk",
1842 .parent_names = (const char *[]){
1846 .flags = CLK_SET_RATE_PARENT,
1847 .ops = &clk_branch2_ops,
1852 static struct clk_branch mdss_edplink_clk = {
1855 .enable_reg = 0x2330,
1856 .enable_mask = BIT(0),
1857 .hw.init = &(struct clk_init_data){
1858 .name = "mdss_edplink_clk",
1859 .parent_names = (const char *[]){
1863 .flags = CLK_SET_RATE_PARENT,
1864 .ops = &clk_branch2_ops,
1869 static struct clk_branch mdss_edppixel_clk = {
1872 .enable_reg = 0x232c,
1873 .enable_mask = BIT(0),
1874 .hw.init = &(struct clk_init_data){
1875 .name = "mdss_edppixel_clk",
1876 .parent_names = (const char *[]){
1880 .flags = CLK_SET_RATE_PARENT,
1881 .ops = &clk_branch2_ops,
1886 static struct clk_branch mdss_esc0_clk = {
1889 .enable_reg = 0x2344,
1890 .enable_mask = BIT(0),
1891 .hw.init = &(struct clk_init_data){
1892 .name = "mdss_esc0_clk",
1893 .parent_names = (const char *[]){
1897 .flags = CLK_SET_RATE_PARENT,
1898 .ops = &clk_branch2_ops,
1903 static struct clk_branch mdss_esc1_clk = {
1906 .enable_reg = 0x2348,
1907 .enable_mask = BIT(0),
1908 .hw.init = &(struct clk_init_data){
1909 .name = "mdss_esc1_clk",
1910 .parent_names = (const char *[]){
1914 .flags = CLK_SET_RATE_PARENT,
1915 .ops = &clk_branch2_ops,
1920 static struct clk_branch mdss_extpclk_clk = {
1923 .enable_reg = 0x2324,
1924 .enable_mask = BIT(0),
1925 .hw.init = &(struct clk_init_data){
1926 .name = "mdss_extpclk_clk",
1927 .parent_names = (const char *[]){
1931 .flags = CLK_SET_RATE_PARENT,
1932 .ops = &clk_branch2_ops,
1937 static struct clk_branch mdss_hdmi_ahb_clk = {
1940 .enable_reg = 0x230c,
1941 .enable_mask = BIT(0),
1942 .hw.init = &(struct clk_init_data){
1943 .name = "mdss_hdmi_ahb_clk",
1944 .parent_names = (const char *[]){
1948 .ops = &clk_branch2_ops,
1953 static struct clk_branch mdss_hdmi_clk = {
1956 .enable_reg = 0x2338,
1957 .enable_mask = BIT(0),
1958 .hw.init = &(struct clk_init_data){
1959 .name = "mdss_hdmi_clk",
1960 .parent_names = (const char *[]){
1964 .flags = CLK_SET_RATE_PARENT,
1965 .ops = &clk_branch2_ops,
1970 static struct clk_branch mdss_mdp_clk = {
1973 .enable_reg = 0x231c,
1974 .enable_mask = BIT(0),
1975 .hw.init = &(struct clk_init_data){
1976 .name = "mdss_mdp_clk",
1977 .parent_names = (const char *[]){
1981 .flags = CLK_SET_RATE_PARENT,
1982 .ops = &clk_branch2_ops,
1987 static struct clk_branch mdss_mdp_lut_clk = {
1990 .enable_reg = 0x2320,
1991 .enable_mask = BIT(0),
1992 .hw.init = &(struct clk_init_data){
1993 .name = "mdss_mdp_lut_clk",
1994 .parent_names = (const char *[]){
1998 .flags = CLK_SET_RATE_PARENT,
1999 .ops = &clk_branch2_ops,
2004 static struct clk_branch mdss_pclk0_clk = {
2007 .enable_reg = 0x2314,
2008 .enable_mask = BIT(0),
2009 .hw.init = &(struct clk_init_data){
2010 .name = "mdss_pclk0_clk",
2011 .parent_names = (const char *[]){
2015 .flags = CLK_SET_RATE_PARENT,
2016 .ops = &clk_branch2_ops,
2021 static struct clk_branch mdss_pclk1_clk = {
2024 .enable_reg = 0x2318,
2025 .enable_mask = BIT(0),
2026 .hw.init = &(struct clk_init_data){
2027 .name = "mdss_pclk1_clk",
2028 .parent_names = (const char *[]){
2032 .flags = CLK_SET_RATE_PARENT,
2033 .ops = &clk_branch2_ops,
2038 static struct clk_branch mdss_vsync_clk = {
2041 .enable_reg = 0x2328,
2042 .enable_mask = BIT(0),
2043 .hw.init = &(struct clk_init_data){
2044 .name = "mdss_vsync_clk",
2045 .parent_names = (const char *[]){
2049 .flags = CLK_SET_RATE_PARENT,
2050 .ops = &clk_branch2_ops,
2055 static struct clk_branch mmss_misc_ahb_clk = {
2058 .enable_reg = 0x502c,
2059 .enable_mask = BIT(0),
2060 .hw.init = &(struct clk_init_data){
2061 .name = "mmss_misc_ahb_clk",
2062 .parent_names = (const char *[]){
2066 .ops = &clk_branch2_ops,
2071 static struct clk_branch mmss_mmssnoc_ahb_clk = {
2074 .enable_reg = 0x5024,
2075 .enable_mask = BIT(0),
2076 .hw.init = &(struct clk_init_data){
2077 .name = "mmss_mmssnoc_ahb_clk",
2078 .parent_names = (const char *[]){
2082 .ops = &clk_branch2_ops,
2083 .flags = CLK_IGNORE_UNUSED,
2088 static struct clk_branch mmss_mmssnoc_bto_ahb_clk = {
2091 .enable_reg = 0x5028,
2092 .enable_mask = BIT(0),
2093 .hw.init = &(struct clk_init_data){
2094 .name = "mmss_mmssnoc_bto_ahb_clk",
2095 .parent_names = (const char *[]){
2099 .ops = &clk_branch2_ops,
2100 .flags = CLK_IGNORE_UNUSED,
2105 static struct clk_branch mmss_mmssnoc_axi_clk = {
2108 .enable_reg = 0x506c,
2109 .enable_mask = BIT(0),
2110 .hw.init = &(struct clk_init_data){
2111 .name = "mmss_mmssnoc_axi_clk",
2112 .parent_names = (const char *[]){
2116 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2117 .ops = &clk_branch2_ops,
2122 static struct clk_branch mmss_s0_axi_clk = {
2125 .enable_reg = 0x5064,
2126 .enable_mask = BIT(0),
2127 .hw.init = &(struct clk_init_data){
2128 .name = "mmss_s0_axi_clk",
2129 .parent_names = (const char *[]){
2133 .ops = &clk_branch2_ops,
2134 .flags = CLK_IGNORE_UNUSED,
2139 static struct clk_branch ocmemcx_ahb_clk = {
2142 .enable_reg = 0x405c,
2143 .enable_mask = BIT(0),
2144 .hw.init = &(struct clk_init_data){
2145 .name = "ocmemcx_ahb_clk",
2146 .parent_names = (const char *[]){
2150 .ops = &clk_branch2_ops,
2155 static struct clk_branch ocmemcx_ocmemnoc_clk = {
2158 .enable_reg = 0x4058,
2159 .enable_mask = BIT(0),
2160 .hw.init = &(struct clk_init_data){
2161 .name = "ocmemcx_ocmemnoc_clk",
2162 .parent_names = (const char *[]){
2166 .flags = CLK_SET_RATE_PARENT,
2167 .ops = &clk_branch2_ops,
2172 static struct clk_branch oxili_ocmemgx_clk = {
2175 .enable_reg = 0x402c,
2176 .enable_mask = BIT(0),
2177 .hw.init = &(struct clk_init_data){
2178 .name = "oxili_ocmemgx_clk",
2179 .parent_names = (const char *[]){
2183 .flags = CLK_SET_RATE_PARENT,
2184 .ops = &clk_branch2_ops,
2189 static struct clk_branch ocmemnoc_clk = {
2192 .enable_reg = 0x50b4,
2193 .enable_mask = BIT(0),
2194 .hw.init = &(struct clk_init_data){
2195 .name = "ocmemnoc_clk",
2196 .parent_names = (const char *[]){
2200 .flags = CLK_SET_RATE_PARENT,
2201 .ops = &clk_branch2_ops,
2206 static struct clk_branch oxili_gfx3d_clk = {
2209 .enable_reg = 0x4028,
2210 .enable_mask = BIT(0),
2211 .hw.init = &(struct clk_init_data){
2212 .name = "oxili_gfx3d_clk",
2213 .parent_names = (const char *[]){
2217 .flags = CLK_SET_RATE_PARENT,
2218 .ops = &clk_branch2_ops,
2223 static struct clk_branch oxilicx_ahb_clk = {
2226 .enable_reg = 0x403c,
2227 .enable_mask = BIT(0),
2228 .hw.init = &(struct clk_init_data){
2229 .name = "oxilicx_ahb_clk",
2230 .parent_names = (const char *[]){
2234 .ops = &clk_branch2_ops,
2239 static struct clk_branch oxilicx_axi_clk = {
2242 .enable_reg = 0x4038,
2243 .enable_mask = BIT(0),
2244 .hw.init = &(struct clk_init_data){
2245 .name = "oxilicx_axi_clk",
2246 .parent_names = (const char *[]){
2250 .ops = &clk_branch2_ops,
2255 static struct clk_branch venus0_ahb_clk = {
2258 .enable_reg = 0x1030,
2259 .enable_mask = BIT(0),
2260 .hw.init = &(struct clk_init_data){
2261 .name = "venus0_ahb_clk",
2262 .parent_names = (const char *[]){
2266 .ops = &clk_branch2_ops,
2271 static struct clk_branch venus0_axi_clk = {
2274 .enable_reg = 0x1034,
2275 .enable_mask = BIT(0),
2276 .hw.init = &(struct clk_init_data){
2277 .name = "venus0_axi_clk",
2278 .parent_names = (const char *[]){
2282 .ops = &clk_branch2_ops,
2287 static struct clk_branch venus0_ocmemnoc_clk = {
2290 .enable_reg = 0x1038,
2291 .enable_mask = BIT(0),
2292 .hw.init = &(struct clk_init_data){
2293 .name = "venus0_ocmemnoc_clk",
2294 .parent_names = (const char *[]){
2298 .flags = CLK_SET_RATE_PARENT,
2299 .ops = &clk_branch2_ops,
2304 static struct clk_branch venus0_vcodec0_clk = {
2307 .enable_reg = 0x1028,
2308 .enable_mask = BIT(0),
2309 .hw.init = &(struct clk_init_data){
2310 .name = "venus0_vcodec0_clk",
2311 .parent_names = (const char *[]){
2315 .flags = CLK_SET_RATE_PARENT,
2316 .ops = &clk_branch2_ops,
2321 static const struct pll_config mmpll1_config = {
2326 .vco_mask = 0x3 << 20,
2328 .pre_div_mask = 0x7 << 12,
2329 .post_div_val = 0x0,
2330 .post_div_mask = 0x3 << 8,
2331 .mn_ena_mask = BIT(24),
2332 .main_output_mask = BIT(0),
2335 static struct pll_config mmpll3_config = {
2340 .vco_mask = 0x3 << 20,
2342 .pre_div_mask = 0x7 << 12,
2343 .post_div_val = 0x0,
2344 .post_div_mask = 0x3 << 8,
2345 .mn_ena_mask = BIT(24),
2346 .main_output_mask = BIT(0),
2347 .aux_output_mask = BIT(1),
2350 static struct clk_regmap *mmcc_msm8974_clocks[] = {
2351 [MMSS_AHB_CLK_SRC] = &mmss_ahb_clk_src.clkr,
2352 [MMSS_AXI_CLK_SRC] = &mmss_axi_clk_src.clkr,
2353 [OCMEMNOC_CLK_SRC] = &ocmemnoc_clk_src.clkr,
2354 [MMPLL0] = &mmpll0.clkr,
2355 [MMPLL0_VOTE] = &mmpll0_vote,
2356 [MMPLL1] = &mmpll1.clkr,
2357 [MMPLL1_VOTE] = &mmpll1_vote,
2358 [MMPLL2] = &mmpll2.clkr,
2359 [MMPLL3] = &mmpll3.clkr,
2360 [CSI0_CLK_SRC] = &csi0_clk_src.clkr,
2361 [CSI1_CLK_SRC] = &csi1_clk_src.clkr,
2362 [CSI2_CLK_SRC] = &csi2_clk_src.clkr,
2363 [CSI3_CLK_SRC] = &csi3_clk_src.clkr,
2364 [VFE0_CLK_SRC] = &vfe0_clk_src.clkr,
2365 [VFE1_CLK_SRC] = &vfe1_clk_src.clkr,
2366 [MDP_CLK_SRC] = &mdp_clk_src.clkr,
2367 [GFX3D_CLK_SRC] = &gfx3d_clk_src.clkr,
2368 [JPEG0_CLK_SRC] = &jpeg0_clk_src.clkr,
2369 [JPEG1_CLK_SRC] = &jpeg1_clk_src.clkr,
2370 [JPEG2_CLK_SRC] = &jpeg2_clk_src.clkr,
2371 [PCLK0_CLK_SRC] = &pclk0_clk_src.clkr,
2372 [PCLK1_CLK_SRC] = &pclk1_clk_src.clkr,
2373 [VCODEC0_CLK_SRC] = &vcodec0_clk_src.clkr,
2374 [CCI_CLK_SRC] = &cci_clk_src.clkr,
2375 [CAMSS_GP0_CLK_SRC] = &camss_gp0_clk_src.clkr,
2376 [CAMSS_GP1_CLK_SRC] = &camss_gp1_clk_src.clkr,
2377 [MCLK0_CLK_SRC] = &mclk0_clk_src.clkr,
2378 [MCLK1_CLK_SRC] = &mclk1_clk_src.clkr,
2379 [MCLK2_CLK_SRC] = &mclk2_clk_src.clkr,
2380 [MCLK3_CLK_SRC] = &mclk3_clk_src.clkr,
2381 [CSI0PHYTIMER_CLK_SRC] = &csi0phytimer_clk_src.clkr,
2382 [CSI1PHYTIMER_CLK_SRC] = &csi1phytimer_clk_src.clkr,
2383 [CSI2PHYTIMER_CLK_SRC] = &csi2phytimer_clk_src.clkr,
2384 [CPP_CLK_SRC] = &cpp_clk_src.clkr,
2385 [BYTE0_CLK_SRC] = &byte0_clk_src.clkr,
2386 [BYTE1_CLK_SRC] = &byte1_clk_src.clkr,
2387 [EDPAUX_CLK_SRC] = &edpaux_clk_src.clkr,
2388 [EDPLINK_CLK_SRC] = &edplink_clk_src.clkr,
2389 [EDPPIXEL_CLK_SRC] = &edppixel_clk_src.clkr,
2390 [ESC0_CLK_SRC] = &esc0_clk_src.clkr,
2391 [ESC1_CLK_SRC] = &esc1_clk_src.clkr,
2392 [EXTPCLK_CLK_SRC] = &extpclk_clk_src.clkr,
2393 [HDMI_CLK_SRC] = &hdmi_clk_src.clkr,
2394 [VSYNC_CLK_SRC] = &vsync_clk_src.clkr,
2395 [CAMSS_CCI_CCI_AHB_CLK] = &camss_cci_cci_ahb_clk.clkr,
2396 [CAMSS_CCI_CCI_CLK] = &camss_cci_cci_clk.clkr,
2397 [CAMSS_CSI0_AHB_CLK] = &camss_csi0_ahb_clk.clkr,
2398 [CAMSS_CSI0_CLK] = &camss_csi0_clk.clkr,
2399 [CAMSS_CSI0PHY_CLK] = &camss_csi0phy_clk.clkr,
2400 [CAMSS_CSI0PIX_CLK] = &camss_csi0pix_clk.clkr,
2401 [CAMSS_CSI0RDI_CLK] = &camss_csi0rdi_clk.clkr,
2402 [CAMSS_CSI1_AHB_CLK] = &camss_csi1_ahb_clk.clkr,
2403 [CAMSS_CSI1_CLK] = &camss_csi1_clk.clkr,
2404 [CAMSS_CSI1PHY_CLK] = &camss_csi1phy_clk.clkr,
2405 [CAMSS_CSI1PIX_CLK] = &camss_csi1pix_clk.clkr,
2406 [CAMSS_CSI1RDI_CLK] = &camss_csi1rdi_clk.clkr,
2407 [CAMSS_CSI2_AHB_CLK] = &camss_csi2_ahb_clk.clkr,
2408 [CAMSS_CSI2_CLK] = &camss_csi2_clk.clkr,
2409 [CAMSS_CSI2PHY_CLK] = &camss_csi2phy_clk.clkr,
2410 [CAMSS_CSI2PIX_CLK] = &camss_csi2pix_clk.clkr,
2411 [CAMSS_CSI2RDI_CLK] = &camss_csi2rdi_clk.clkr,
2412 [CAMSS_CSI3_AHB_CLK] = &camss_csi3_ahb_clk.clkr,
2413 [CAMSS_CSI3_CLK] = &camss_csi3_clk.clkr,
2414 [CAMSS_CSI3PHY_CLK] = &camss_csi3phy_clk.clkr,
2415 [CAMSS_CSI3PIX_CLK] = &camss_csi3pix_clk.clkr,
2416 [CAMSS_CSI3RDI_CLK] = &camss_csi3rdi_clk.clkr,
2417 [CAMSS_CSI_VFE0_CLK] = &camss_csi_vfe0_clk.clkr,
2418 [CAMSS_CSI_VFE1_CLK] = &camss_csi_vfe1_clk.clkr,
2419 [CAMSS_GP0_CLK] = &camss_gp0_clk.clkr,
2420 [CAMSS_GP1_CLK] = &camss_gp1_clk.clkr,
2421 [CAMSS_ISPIF_AHB_CLK] = &camss_ispif_ahb_clk.clkr,
2422 [CAMSS_JPEG_JPEG0_CLK] = &camss_jpeg_jpeg0_clk.clkr,
2423 [CAMSS_JPEG_JPEG1_CLK] = &camss_jpeg_jpeg1_clk.clkr,
2424 [CAMSS_JPEG_JPEG2_CLK] = &camss_jpeg_jpeg2_clk.clkr,
2425 [CAMSS_JPEG_JPEG_AHB_CLK] = &camss_jpeg_jpeg_ahb_clk.clkr,
2426 [CAMSS_JPEG_JPEG_AXI_CLK] = &camss_jpeg_jpeg_axi_clk.clkr,
2427 [CAMSS_JPEG_JPEG_OCMEMNOC_CLK] = &camss_jpeg_jpeg_ocmemnoc_clk.clkr,
2428 [CAMSS_MCLK0_CLK] = &camss_mclk0_clk.clkr,
2429 [CAMSS_MCLK1_CLK] = &camss_mclk1_clk.clkr,
2430 [CAMSS_MCLK2_CLK] = &camss_mclk2_clk.clkr,
2431 [CAMSS_MCLK3_CLK] = &camss_mclk3_clk.clkr,
2432 [CAMSS_MICRO_AHB_CLK] = &camss_micro_ahb_clk.clkr,
2433 [CAMSS_PHY0_CSI0PHYTIMER_CLK] = &camss_phy0_csi0phytimer_clk.clkr,
2434 [CAMSS_PHY1_CSI1PHYTIMER_CLK] = &camss_phy1_csi1phytimer_clk.clkr,
2435 [CAMSS_PHY2_CSI2PHYTIMER_CLK] = &camss_phy2_csi2phytimer_clk.clkr,
2436 [CAMSS_TOP_AHB_CLK] = &camss_top_ahb_clk.clkr,
2437 [CAMSS_VFE_CPP_AHB_CLK] = &camss_vfe_cpp_ahb_clk.clkr,
2438 [CAMSS_VFE_CPP_CLK] = &camss_vfe_cpp_clk.clkr,
2439 [CAMSS_VFE_VFE0_CLK] = &camss_vfe_vfe0_clk.clkr,
2440 [CAMSS_VFE_VFE1_CLK] = &camss_vfe_vfe1_clk.clkr,
2441 [CAMSS_VFE_VFE_AHB_CLK] = &camss_vfe_vfe_ahb_clk.clkr,
2442 [CAMSS_VFE_VFE_AXI_CLK] = &camss_vfe_vfe_axi_clk.clkr,
2443 [CAMSS_VFE_VFE_OCMEMNOC_CLK] = &camss_vfe_vfe_ocmemnoc_clk.clkr,
2444 [MDSS_AHB_CLK] = &mdss_ahb_clk.clkr,
2445 [MDSS_AXI_CLK] = &mdss_axi_clk.clkr,
2446 [MDSS_BYTE0_CLK] = &mdss_byte0_clk.clkr,
2447 [MDSS_BYTE1_CLK] = &mdss_byte1_clk.clkr,
2448 [MDSS_EDPAUX_CLK] = &mdss_edpaux_clk.clkr,
2449 [MDSS_EDPLINK_CLK] = &mdss_edplink_clk.clkr,
2450 [MDSS_EDPPIXEL_CLK] = &mdss_edppixel_clk.clkr,
2451 [MDSS_ESC0_CLK] = &mdss_esc0_clk.clkr,
2452 [MDSS_ESC1_CLK] = &mdss_esc1_clk.clkr,
2453 [MDSS_EXTPCLK_CLK] = &mdss_extpclk_clk.clkr,
2454 [MDSS_HDMI_AHB_CLK] = &mdss_hdmi_ahb_clk.clkr,
2455 [MDSS_HDMI_CLK] = &mdss_hdmi_clk.clkr,
2456 [MDSS_MDP_CLK] = &mdss_mdp_clk.clkr,
2457 [MDSS_MDP_LUT_CLK] = &mdss_mdp_lut_clk.clkr,
2458 [MDSS_PCLK0_CLK] = &mdss_pclk0_clk.clkr,
2459 [MDSS_PCLK1_CLK] = &mdss_pclk1_clk.clkr,
2460 [MDSS_VSYNC_CLK] = &mdss_vsync_clk.clkr,
2461 [MMSS_MISC_AHB_CLK] = &mmss_misc_ahb_clk.clkr,
2462 [MMSS_MMSSNOC_AHB_CLK] = &mmss_mmssnoc_ahb_clk.clkr,
2463 [MMSS_MMSSNOC_BTO_AHB_CLK] = &mmss_mmssnoc_bto_ahb_clk.clkr,
2464 [MMSS_MMSSNOC_AXI_CLK] = &mmss_mmssnoc_axi_clk.clkr,
2465 [MMSS_S0_AXI_CLK] = &mmss_s0_axi_clk.clkr,
2466 [OCMEMCX_AHB_CLK] = &ocmemcx_ahb_clk.clkr,
2467 [OCMEMCX_OCMEMNOC_CLK] = &ocmemcx_ocmemnoc_clk.clkr,
2468 [OXILI_OCMEMGX_CLK] = &oxili_ocmemgx_clk.clkr,
2469 [OCMEMNOC_CLK] = &ocmemnoc_clk.clkr,
2470 [OXILI_GFX3D_CLK] = &oxili_gfx3d_clk.clkr,
2471 [OXILICX_AHB_CLK] = &oxilicx_ahb_clk.clkr,
2472 [OXILICX_AXI_CLK] = &oxilicx_axi_clk.clkr,
2473 [VENUS0_AHB_CLK] = &venus0_ahb_clk.clkr,
2474 [VENUS0_AXI_CLK] = &venus0_axi_clk.clkr,
2475 [VENUS0_OCMEMNOC_CLK] = &venus0_ocmemnoc_clk.clkr,
2476 [VENUS0_VCODEC0_CLK] = &venus0_vcodec0_clk.clkr,
2479 static const struct qcom_reset_map mmcc_msm8974_resets[] = {
2480 [SPDM_RESET] = { 0x0200 },
2481 [SPDM_RM_RESET] = { 0x0300 },
2482 [VENUS0_RESET] = { 0x1020 },
2483 [MDSS_RESET] = { 0x2300 },
2484 [CAMSS_PHY0_RESET] = { 0x3020 },
2485 [CAMSS_PHY1_RESET] = { 0x3050 },
2486 [CAMSS_PHY2_RESET] = { 0x3080 },
2487 [CAMSS_CSI0_RESET] = { 0x30b0 },
2488 [CAMSS_CSI0PHY_RESET] = { 0x30c0 },
2489 [CAMSS_CSI0RDI_RESET] = { 0x30d0 },
2490 [CAMSS_CSI0PIX_RESET] = { 0x30e0 },
2491 [CAMSS_CSI1_RESET] = { 0x3120 },
2492 [CAMSS_CSI1PHY_RESET] = { 0x3130 },
2493 [CAMSS_CSI1RDI_RESET] = { 0x3140 },
2494 [CAMSS_CSI1PIX_RESET] = { 0x3150 },
2495 [CAMSS_CSI2_RESET] = { 0x3180 },
2496 [CAMSS_CSI2PHY_RESET] = { 0x3190 },
2497 [CAMSS_CSI2RDI_RESET] = { 0x31a0 },
2498 [CAMSS_CSI2PIX_RESET] = { 0x31b0 },
2499 [CAMSS_CSI3_RESET] = { 0x31e0 },
2500 [CAMSS_CSI3PHY_RESET] = { 0x31f0 },
2501 [CAMSS_CSI3RDI_RESET] = { 0x3200 },
2502 [CAMSS_CSI3PIX_RESET] = { 0x3210 },
2503 [CAMSS_ISPIF_RESET] = { 0x3220 },
2504 [CAMSS_CCI_RESET] = { 0x3340 },
2505 [CAMSS_MCLK0_RESET] = { 0x3380 },
2506 [CAMSS_MCLK1_RESET] = { 0x33b0 },
2507 [CAMSS_MCLK2_RESET] = { 0x33e0 },
2508 [CAMSS_MCLK3_RESET] = { 0x3410 },
2509 [CAMSS_GP0_RESET] = { 0x3440 },
2510 [CAMSS_GP1_RESET] = { 0x3470 },
2511 [CAMSS_TOP_RESET] = { 0x3480 },
2512 [CAMSS_MICRO_RESET] = { 0x3490 },
2513 [CAMSS_JPEG_RESET] = { 0x35a0 },
2514 [CAMSS_VFE_RESET] = { 0x36a0 },
2515 [CAMSS_CSI_VFE0_RESET] = { 0x3700 },
2516 [CAMSS_CSI_VFE1_RESET] = { 0x3710 },
2517 [OXILI_RESET] = { 0x4020 },
2518 [OXILICX_RESET] = { 0x4030 },
2519 [OCMEMCX_RESET] = { 0x4050 },
2520 [MMSS_RBCRP_RESET] = { 0x4080 },
2521 [MMSSNOCAHB_RESET] = { 0x5020 },
2522 [MMSSNOCAXI_RESET] = { 0x5060 },
2523 [OCMEMNOC_RESET] = { 0x50b0 },
2526 static const struct regmap_config mmcc_msm8974_regmap_config = {
2530 .max_register = 0x5104,
2534 static const struct qcom_cc_desc mmcc_msm8974_desc = {
2535 .config = &mmcc_msm8974_regmap_config,
2536 .clks = mmcc_msm8974_clocks,
2537 .num_clks = ARRAY_SIZE(mmcc_msm8974_clocks),
2538 .resets = mmcc_msm8974_resets,
2539 .num_resets = ARRAY_SIZE(mmcc_msm8974_resets),
2542 static const struct of_device_id mmcc_msm8974_match_table[] = {
2543 { .compatible = "qcom,mmcc-msm8974" },
2546 MODULE_DEVICE_TABLE(of, mmcc_msm8974_match_table);
2548 static int mmcc_msm8974_probe(struct platform_device *pdev)
2550 struct regmap *regmap;
2552 regmap = qcom_cc_map(pdev, &mmcc_msm8974_desc);
2554 return PTR_ERR(regmap);
2556 clk_pll_configure_sr_hpm_lp(&mmpll1, regmap, &mmpll1_config, true);
2557 clk_pll_configure_sr_hpm_lp(&mmpll3, regmap, &mmpll3_config, false);
2559 return qcom_cc_really_probe(pdev, &mmcc_msm8974_desc, regmap);
2562 static int mmcc_msm8974_remove(struct platform_device *pdev)
2564 qcom_cc_remove(pdev);
2568 static struct platform_driver mmcc_msm8974_driver = {
2569 .probe = mmcc_msm8974_probe,
2570 .remove = mmcc_msm8974_remove,
2572 .name = "mmcc-msm8974",
2573 .of_match_table = mmcc_msm8974_match_table,
2576 module_platform_driver(mmcc_msm8974_driver);
2578 MODULE_DESCRIPTION("QCOM MMCC MSM8974 Driver");
2579 MODULE_LICENSE("GPL v2");
2580 MODULE_ALIAS("platform:mmcc-msm8974");