2 * Copyright (C) 2013 ROCKCHIP, Inc.
3 * Author: chenxing <chenxing@rock-chips.com>
4 * Dai Kelin <dkl@rock-chips.com>
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
17 #include <linux/clk-provider.h>
18 #include <linux/clkdev.h>
20 #include <linux/of_address.h>
21 #include <linux/clk-private.h>
28 static void __iomem *rk_cru_base;
29 static void __iomem *rk_grf_base;
31 u32 cru_readl(u32 offset)
33 return readl_relaxed(rk_cru_base + (offset));
36 void cru_writel(u32 val, u32 offset)
38 writel_relaxed(val, rk_cru_base + (offset));
42 u32 grf_readl(u32 offset)
44 return readl_relaxed(rk_grf_base + (offset));
47 struct rkclk_muxinfo {
49 struct device_node *np;
52 const char **parent_names;
56 struct rkclk_divinfo {
58 struct device_node *np;
59 struct clk_divider *div;
61 const char *parent_name;
65 struct rkclk_fracinfo {
67 struct device_node *np;
68 struct clk_divider *frac;
70 const char *parent_name;
74 struct rkclk_gateinfo {
76 struct device_node *np;
77 struct clk_gate *gate;
78 const char *parent_name;
82 struct rkclk_pllinfo {
84 struct device_node *np;
86 const char *parent_name;
90 struct rkclk_fixed_rate_info {
92 struct device_node *np;
93 struct clk_fixed_rate *fixed_rate;
94 const char *parent_name;
97 struct rkclk_fixed_factor_info {
99 struct device_node *np;
100 struct clk_fixed_factor *fixed_factor;
101 const char *parent_name;
104 struct rkclk_pd_info {
105 const char *clk_name;
106 struct device_node *np;
108 const char *parent_name;
113 const char *clk_name;
114 //struct device_node *np;
117 struct rkclk_muxinfo *mux_info;
118 struct rkclk_divinfo *div_info;
119 struct rkclk_fracinfo *frac_info;
120 struct rkclk_pllinfo *pll_info;
121 struct rkclk_gateinfo *gate_info;
122 struct rkclk_fixed_rate_info *fixed_rate_info;
123 struct rkclk_fixed_factor_info *fixed_factor_info;
124 struct rkclk_pd_info *pd_info;
125 struct list_head node;
128 static DEFINE_SPINLOCK(clk_lock);
131 #define RKCLK_PLL_TYPE (1 << 0)
132 #define RKCLK_MUX_TYPE (1 << 1)
133 #define RKCLK_DIV_TYPE (1 << 2)
134 #define RKCLK_FRAC_TYPE (1 << 3)
135 #define RKCLK_GATE_TYPE (1 << 4)
136 #define RKCLK_FIXED_RATE_TYPE (1 << 5)
137 #define RKCLK_FIXED_FACTOR_TYPE (1 << 6)
138 #define RKCLK_PD_TYPE (1 << 7)
141 static int rkclk_init_muxinfo(struct device_node *np, void __iomem *addr)
143 struct rkclk_muxinfo *muxinfo = NULL;
144 struct clk_mux *mux = NULL;
149 struct rkclk *rkclk = NULL;
152 muxinfo = kzalloc(sizeof(struct rkclk_muxinfo), GFP_KERNEL);
158 muxinfo->mux = kzalloc(sizeof(struct clk_mux), GFP_KERNEL);
165 ret = of_property_read_string(np, "clock-output-names",
172 cnt = of_count_phandle_with_args(np, "clocks", "#clock-cells");
177 clk_debug("%s: parent cnt = %d\n", __func__, cnt);
178 muxinfo->parent_num = (u8)cnt;
181 muxinfo->parent_names = kzalloc(cnt * sizeof(char *), GFP_KERNEL);
182 for (i = 0; i < cnt ; i++) {
183 muxinfo->parent_names[i] = of_clk_get_parent_name(np, i);
188 ret = of_property_read_u32_index(np, "rockchip,bits", 0, &shift);
192 mux->shift = (u8)shift;
195 ret = of_property_read_u32_index(np, "rockchip,bits", 1, &width);
198 mux->mask = (1 << width) - 1;
200 mux->flags = CLK_MUX_HIWORD_MASK;
202 ret = of_property_read_u32(np, "rockchip,clkops-idx",
203 &muxinfo->clkops_idx);
205 muxinfo->clkops_idx = CLKOPS_TABLE_END;
209 ret = of_property_read_u32(np, "rockchip,flags", &flags);
216 list_for_each_entry(rkclk, &rk_clks, node) {
217 if (strcmp(muxinfo->clk_name, rkclk->clk_name) == 0) {
218 if (rkclk->mux_info != NULL) {
219 clk_err("%s %d:\n", __func__, __LINE__);
220 clk_err("This clk(%s) has been used,"
221 "will be overwrited here!\n",
224 clk_debug("%s: find match %s\n", __func__,
227 rkclk->mux_info = muxinfo;
228 rkclk->clk_type |= RKCLK_MUX_TYPE;
229 rkclk->flags |= flags;
235 rkclk = kzalloc(sizeof(struct rkclk), GFP_KERNEL);
240 rkclk->clk_name = muxinfo->clk_name;
241 rkclk->mux_info = muxinfo;
242 rkclk->clk_type = RKCLK_MUX_TYPE;
243 rkclk->flags = flags;
244 clk_debug("%s: creat %s\n", __func__, rkclk->clk_name);
245 list_add_tail(&rkclk->node, &rk_clks);
250 clk_err("%s error, ret = %d\n", __func__, ret);
263 static int rkclk_init_divinfo(struct device_node *np, void __iomem *addr)
265 int cnt = 0, i = 0, ret = 0;
266 struct rkclk *rkclk = NULL;
270 struct rkclk_divinfo *divinfo = NULL;
271 struct clk_divider *div = NULL;
272 struct clk_div_table *table;
273 u32 table_val, table_div;
276 divinfo = kzalloc(sizeof(struct rkclk_divinfo), GFP_KERNEL);
282 divinfo->div = kzalloc(sizeof(struct clk_divider), GFP_KERNEL);
289 ret = of_property_read_string(np, "clock-output-names",
294 divinfo->parent_name = of_clk_get_parent_name(np, 0);
298 ret = of_property_read_u32(np, "rockchip,clkops-idx",
299 &divinfo->clkops_idx);
301 divinfo->clkops_idx = CLKOPS_TABLE_END;
305 ret = of_property_read_u32(np, "rockchip,flags", &flags);
311 ret = of_property_read_u32(np, "rockchip,div-type", &divinfo->div_type);
315 switch (divinfo->div_type) {
316 case CLK_DIVIDER_PLUS_ONE:
317 case CLK_DIVIDER_ONE_BASED:
318 case CLK_DIVIDER_POWER_OF_TWO:
320 case CLK_DIVIDER_USER_DEFINE:
321 of_get_property(np, "rockchip,div-relations", &cnt);
327 table = kzalloc(cnt * sizeof(struct clk_div_table),
333 for (i = 0; i < cnt; i++) {
334 ret = of_property_read_u32_index(np,
335 "rockchip,div-relations", i * 2,
339 ret = of_property_read_u32_index(np,
340 "rockchip,div-relations",
341 i * 2 + 1, &table_div);
344 table[i].val = (unsigned int)table_val;
345 table[i].div = (unsigned int)table_div;
346 clk_debug("\tGet div table %d: val=%d, div=%d\n",
347 i, table_val, table_div);
352 clk_err("%s: %s: unknown rockchip,div-type\n", __func__,
359 ret = of_property_read_u32_index(np, "rockchip,bits", 0, &shift);
362 ret = of_property_read_u32_index(np, "rockchip,bits", 1, &width);
365 div->shift = (u8)shift;
366 div->width = (u8)width;
367 div->flags = CLK_DIVIDER_HIWORD_MASK | divinfo->div_type;
370 list_for_each_entry(rkclk, &rk_clks, node) {
371 if (strcmp(divinfo->clk_name, rkclk->clk_name) == 0) {
372 if (rkclk->div_info != NULL) {
373 clk_err("%s %d:\n", __func__, __LINE__);
374 clk_err("This clk(%s) has been used,"
375 "will be overwrited here!\n",
378 clk_debug("%s: find match %s\n", __func__,
381 rkclk->div_info = divinfo;
382 rkclk->clk_type |= RKCLK_DIV_TYPE;
383 rkclk->flags |= flags;
389 rkclk = kzalloc(sizeof(struct rkclk), GFP_KERNEL);
394 rkclk->clk_name = divinfo->clk_name;
395 rkclk->div_info = divinfo;
396 rkclk->clk_type = RKCLK_DIV_TYPE;
397 rkclk->flags = flags;
398 clk_debug("%s: creat %s\n", __func__, rkclk->clk_name);
399 list_add_tail(&rkclk->node, &rk_clks);
404 clk_err("%s error, ret = %d\n", __func__, ret);
419 static int rkclk_init_fracinfo(struct device_node *np, void __iomem *addr)
421 struct rkclk *rkclk = NULL;
424 struct rkclk_fracinfo *fracinfo = NULL;
425 struct clk_divider *frac = NULL;
426 u32 shift, width, flags;
429 fracinfo = kzalloc(sizeof(struct rkclk_fracinfo), GFP_KERNEL);
435 fracinfo->frac = kzalloc(sizeof(struct clk_divider), GFP_KERNEL);
436 if (!fracinfo->frac) {
440 frac = fracinfo->frac;
442 ret = of_property_read_string(np, "clock-output-names",
443 &fracinfo->clk_name);
447 fracinfo->parent_name = of_clk_get_parent_name(np, 0);
450 ret = of_property_read_u32(np, "rockchip,clkops-idx",
451 &fracinfo->clkops_idx);
453 fracinfo->clkops_idx = CLKOPS_TABLE_END;
454 clk_err("frac node without specified ops!\n");
459 ret = of_property_read_u32(np, "rockchip,flags", &flags);
461 clk_debug("if not specified, frac use CLK_SET_RATE_PARENT flag "
463 flags = CLK_SET_RATE_PARENT;
468 ret = of_property_read_u32_index(np, "rockchip,bits", 0, &shift);
471 ret = of_property_read_u32_index(np, "rockchip,bits", 1, &width);
474 frac->shift = (u8)shift;
475 frac->width = (u8)width;
479 list_for_each_entry(rkclk, &rk_clks, node) {
480 if (strcmp(fracinfo->clk_name, rkclk->clk_name) == 0) {
481 if (rkclk->frac_info != NULL) {
482 clk_err("%s %d:\n", __func__, __LINE__);
483 clk_err("This clk(%s) has been used,"
484 "will be overwrited here!\n",
487 clk_debug("%s: find match %s\n", __func__,
490 rkclk->frac_info = fracinfo;
491 rkclk->clk_type |= RKCLK_FRAC_TYPE;
492 rkclk->flags |= flags;
498 rkclk = kzalloc(sizeof(struct rkclk), GFP_KERNEL);
503 rkclk->clk_name = fracinfo->clk_name;
504 rkclk->frac_info = fracinfo;
505 rkclk->clk_type = RKCLK_FRAC_TYPE;
506 rkclk->flags = flags;
507 clk_debug("%s: creat %s\n", __func__, rkclk->clk_name);
508 list_add_tail(&rkclk->node, &rk_clks);
513 clk_err("%s error, ret = %d\n", __func__, ret);
516 kfree(fracinfo->frac);
526 static int __init rkclk_init_selcon(struct device_node *np)
528 struct device_node *node_con, *node;
529 void __iomem *reg = 0;
533 for_each_available_child_of_node(np, node_con) {
534 reg = of_iomap(node_con, 0);
536 clk_debug("%s: reg = 0x%x\n", __func__, (u32)reg);
538 for_each_available_child_of_node(node_con, node) {
540 if (of_device_is_compatible(node,
541 "rockchip,rk3188-div-con"))
542 ret = rkclk_init_divinfo(node, reg);
544 else if (of_device_is_compatible(node,
545 "rockchip,rk3188-mux-con"))
546 ret = rkclk_init_muxinfo(node, reg);
548 else if (of_device_is_compatible(node,
549 "rockchip,rk3188-frac-con"))
550 ret = rkclk_init_fracinfo(node, reg);
552 else if (of_device_is_compatible(node,
553 "rockchip,rk3188-inv-con"))
554 clk_debug("INV clk\n");
557 clk_err("%s: unknown controller type\n",
567 static int __init rkclk_init_gatecon(struct device_node *np)
569 struct device_node *node;
570 const char *clk_name;
574 struct rkclk_gateinfo *gateinfo;
578 struct clk_gate *gate = NULL;
581 for_each_available_child_of_node(np, node) {
582 cnt = of_property_count_strings(node, "clock-output-names");
584 clk_err("%s: error in clock-output-names %d\n",
590 clk_debug("%s: nothing to do\n", __func__);
594 reg = of_iomap(node, 0);
596 clk_debug("%s: reg = 0x%x\n", __func__, (u32)reg);
598 for (i = 0; i < cnt; i++) {
599 ret = of_property_read_string_index(node,
600 "clock-output-names", i, &clk_name);
604 /* ignore empty slots */
605 if (!strcmp("reserved", clk_name)) {
606 clk_debug("do nothing for reserved clk\n");
610 gateinfo = kzalloc(sizeof(struct rkclk_gateinfo),
617 gateinfo->gate = kzalloc(sizeof(struct clk_gate),
619 if (!gateinfo->gate) {
623 gate = gateinfo->gate;
625 gateinfo->clk_name = clk_name;
626 gateinfo->parent_name = of_clk_get_parent_name(node, i);
630 gate->bit_idx = (i % 16);
631 gate->flags = CLK_GATE_HIWORD_MASK |
632 CLK_GATE_SET_TO_DISABLE;
635 list_for_each_entry(rkclk, &rk_clks, node) {
636 if (strcmp(clk_name, rkclk->clk_name) == 0) {
637 if (rkclk->gate_info != NULL) {
638 clk_err("%s %d:\n", __func__,
640 clk_err("This clk(%s) has been used,"
641 "will be overwrited here!\n",
644 clk_debug("%s: find match %s\n",
645 __func__, rkclk->clk_name);
647 rkclk->gate_info = gateinfo;
648 rkclk->clk_type |= RKCLK_GATE_TYPE;
653 rkclk = kzalloc(sizeof(struct rkclk), GFP_KERNEL);
658 rkclk->clk_name = gateinfo->clk_name;
659 rkclk->gate_info = gateinfo;
660 rkclk->clk_type = RKCLK_GATE_TYPE;
661 clk_debug("%s: creat %s\n", __func__,
663 list_add_tail(&rkclk->node, &rk_clks);
668 clk_err("%s error, ret = %d\n", __func__, ret);
671 kfree(gateinfo->gate);
684 static int __init rkclk_init_pllcon(struct device_node *np)
686 struct device_node *node = NULL;
687 struct rkclk_pllinfo *pllinfo = NULL;
688 struct clk_pll *pll = NULL;
691 struct rkclk *rkclk = NULL;
693 u32 mode_shift, status_shift;
696 for_each_available_child_of_node(np, node) {
697 pllinfo = kzalloc(sizeof(struct rkclk_pllinfo), GFP_KERNEL);
703 pllinfo->pll = kzalloc(sizeof(struct clk_pll), GFP_KERNEL);
712 ret = of_property_read_string_index(node, "clock-output-names",
713 0, &pllinfo->clk_name);
717 pllinfo->parent_name = of_clk_get_parent_name(node, 0);
719 ret = of_property_read_u32(np, "rockchip,flags", &flags);
725 ret = of_property_read_u32_index(node, "reg", 0, &pll->reg);
727 clk_err("%s: can not get reg addr info\n", __func__);
731 ret = of_property_read_u32_index(node, "reg", 1, &pll->width);
733 clk_err("%s: can not get reg length info\n", __func__);
737 ret = of_property_read_u32_index(node, "mode-reg", 0,
740 clk_err("%s: can not get mode_reg offset\n", __func__);
744 ret = of_property_read_u32_index(node, "mode-reg", 1,
747 clk_err("%s: can not get mode_reg shift\n", __func__);
750 pll->mode_shift = (u8)mode_shift;
753 ret = of_property_read_u32_index(node, "status-reg", 0,
754 &pll->status_offset);
756 clk_err("%s: can not get status_reg offset\n", __func__);
760 ret = of_property_read_u32_index(node, "status-reg", 1,
763 clk_err("%s: can not get status_reg shift\n", __func__);
766 pll->status_shift= (u8)status_shift;
769 ret = of_property_read_u32(node, "rockchip,pll-type", &pll->flags);
771 clk_err("%s: can not get pll-type\n", __func__);
775 clk_debug("%s: pllname=%s, parent=%s, flags=0x%x\n",
776 __func__, pllinfo->clk_name,
777 pllinfo->parent_name, flags);
779 clk_debug("\t\taddr=0x%x, len=0x%x, mode:offset=0x%x, shift=0x%x,"
780 " status:offset=0x%x, shift=0x%x, pll->flags=0x%x\n",
781 (u32)pll->reg, pll->width,
782 pll->mode_offset, pll->mode_shift,
783 pll->status_offset, pll->status_shift,
787 list_for_each_entry(rkclk, &rk_clks, node) {
788 if (strcmp(pllinfo->clk_name, rkclk->clk_name) == 0) {
789 if (rkclk->pll_info != NULL) {
790 clk_err("%s %d:\n", __func__, __LINE__);
791 clk_err("This clk(%s) has been used,"
792 "will be overwrited here!\n",
795 clk_debug("%s: find match %s\n", __func__,
798 rkclk->pll_info = pllinfo;
799 rkclk->clk_type |= RKCLK_PLL_TYPE;
800 rkclk->flags |= flags;
806 rkclk = kzalloc(sizeof(struct rkclk), GFP_KERNEL);
811 rkclk->clk_name = pllinfo->clk_name;
812 rkclk->pll_info = pllinfo;
813 rkclk->clk_type = RKCLK_PLL_TYPE;
814 rkclk->flags = flags;
815 list_add_tail(&rkclk->node, &rk_clks);
821 clk_err("%s error, ret = %d\n", __func__, ret);
834 static int __init rkclk_init_fixed_rate(struct device_node *np)
836 struct device_node *node = NULL;
837 struct rkclk_fixed_rate_info *fixed_rate_info = NULL;
838 struct clk_fixed_rate *fixed_rate = NULL;
842 struct rkclk *rkclk = NULL;
845 for_each_available_child_of_node(np, node) {
846 fixed_rate_info = kzalloc(sizeof(struct rkclk_fixed_rate_info),
848 if (!fixed_rate_info) {
853 fixed_rate_info->fixed_rate = kzalloc(sizeof(struct clk_fixed_rate),
855 if (!fixed_rate_info->fixed_rate) {
859 fixed_rate = fixed_rate_info->fixed_rate;
861 fixed_rate_info->np = node;
863 ret = of_property_read_string_index(node, "clock-output-names",
864 0, &fixed_rate_info->clk_name);
868 fixed_rate_info->parent_name = of_clk_get_parent_name(node, 0);
870 ret = of_property_read_u32(node, "clock-frequency", &rate);
872 clk_err("%s: can not get clock-frequency\n", __func__);
875 fixed_rate->fixed_rate = (unsigned long)rate;
878 list_for_each_entry(rkclk, &rk_clks, node) {
879 if (strcmp(fixed_rate_info->clk_name, rkclk->clk_name) == 0) {
880 if (rkclk->fixed_rate_info != NULL) {
881 clk_err("%s %d:\n", __func__, __LINE__);
882 clk_err("This clk(%s) has been used,"
883 "will be overwrited here!\n",
886 clk_debug("%s: find match %s\n", __func__,
889 rkclk->fixed_rate_info = fixed_rate_info;
890 rkclk->clk_type |= RKCLK_FIXED_RATE_TYPE;
891 rkclk->flags |= CLK_IS_ROOT;
897 rkclk = kzalloc(sizeof(struct rkclk), GFP_KERNEL);
902 rkclk->clk_name = fixed_rate_info->clk_name;
903 rkclk->fixed_rate_info = fixed_rate_info;
904 rkclk->clk_type = RKCLK_FIXED_RATE_TYPE;
905 rkclk->flags = CLK_IS_ROOT;
906 clk_debug("%s: creat %s\n", __func__, rkclk->clk_name);
907 list_add_tail(&rkclk->node, &rk_clks);
913 clk_err("%s error, ret = %d\n", __func__, ret);
914 if (fixed_rate_info) {
915 if (fixed_rate_info->fixed_rate)
916 kfree(fixed_rate_info->fixed_rate);
917 kfree(fixed_rate_info);
926 static int __init rkclk_init_fixed_factor(struct device_node *np)
928 struct device_node *node = NULL;
929 struct rkclk_fixed_factor_info *fixed_factor_info = NULL;
930 struct clk_fixed_factor *fixed_factor = NULL;
931 u32 flags, mult, div;
934 struct rkclk *rkclk = NULL;
937 for_each_available_child_of_node(np, node) {
938 fixed_factor_info = kzalloc(sizeof(struct rkclk_fixed_factor_info),
940 if (!fixed_factor_info) {
945 fixed_factor_info->fixed_factor = kzalloc(sizeof(struct clk_fixed_factor),
947 if (!fixed_factor_info->fixed_factor) {
951 fixed_factor = fixed_factor_info->fixed_factor;
953 fixed_factor_info->np = node;
955 ret = of_property_read_string_index(node, "clock-output-names",
956 0, &fixed_factor_info->clk_name);
960 fixed_factor_info->parent_name = of_clk_get_parent_name(node, 0);
962 ret = of_property_read_u32(node, "rockchip,flags", &flags);
968 ret = of_property_read_u32(node, "clock-mult", &mult);
970 clk_err("%s: can not get mult\n", __func__);
973 fixed_factor->mult = (unsigned int)mult;
975 ret = of_property_read_u32(node, "clock-div", &div);
977 clk_err("%s: can not get div\n", __func__);
980 fixed_factor->div = (unsigned int)div;
984 list_for_each_entry(rkclk, &rk_clks, node) {
985 if (strcmp(fixed_factor_info->clk_name, rkclk->clk_name) == 0) {
986 if (rkclk->fixed_factor_info != NULL) {
987 clk_err("%s %d:\n", __func__, __LINE__);
988 clk_err("This clk(%s) has been used,"
989 "will be overwrited here!\n",
992 clk_debug("%s: find match %s\n", __func__,
995 rkclk->fixed_factor_info = fixed_factor_info;
996 rkclk->clk_type |= RKCLK_FIXED_FACTOR_TYPE;
997 rkclk->flags |= flags;
1003 rkclk = kzalloc(sizeof(struct rkclk), GFP_KERNEL);
1008 rkclk->clk_name = fixed_factor_info->clk_name;
1009 rkclk->fixed_factor_info = fixed_factor_info;
1010 rkclk->clk_type = RKCLK_FIXED_FACTOR_TYPE;
1011 rkclk->flags = flags;
1012 clk_debug("%s: creat %s\n", __func__, rkclk->clk_name);
1013 list_add_tail(&rkclk->node, &rk_clks);
1019 clk_err("%s error, ret = %d\n", __func__, ret);
1020 if (fixed_factor_info) {
1021 if (fixed_factor_info->fixed_factor)
1022 kfree(fixed_factor_info->fixed_factor);
1023 kfree(fixed_factor_info);
1032 static int __init rkclk_init_regcon(struct device_node *np)
1034 struct device_node *node;
1035 const char *compatible;
1039 for_each_available_child_of_node(np, node) {
1041 of_property_read_string(node, "compatible", &compatible);
1043 if (strcmp(compatible, "rockchip,rk-pll-cons") == 0) {
1044 ret = rkclk_init_pllcon(node);
1046 clk_err("%s: init pll cons err\n", __func__);
1049 } else if (strcmp(compatible, "rockchip,rk-sel-cons") == 0) {
1050 ret = rkclk_init_selcon(node);
1052 clk_err("%s: init sel cons err\n", __func__);
1055 } else if (strcmp(compatible, "rockchip,rk-gate-cons") == 0) {
1056 ret = rkclk_init_gatecon(node);
1058 clk_err("%s: init gate cons err\n", __func__);
1062 clk_err("%s: unknown\n", __func__);
1071 static int __init rkclk_init_special_regs(struct device_node *np)
1073 struct device_node *node;
1074 const char *compatible;
1075 void __iomem *reg = 0;
1079 for_each_available_child_of_node(np, node) {
1081 of_property_read_string(node, "compatible", &compatible);
1082 if (strcmp(compatible, "rockchip,rk3188-mux-con") == 0) {
1083 reg = of_iomap(node, 0);
1084 ret = rkclk_init_muxinfo(node, reg);
1086 clk_err("%s: init mux con err\n", __func__);
1096 static int __init rkclk_init_pd(struct device_node *np)
1098 struct device_node *node = NULL;
1099 struct rkclk_pd_info *pd_info = NULL;
1100 struct clk_pd *pd = NULL;
1103 struct rkclk *rkclk = NULL;
1106 for_each_available_child_of_node(np, node) {
1107 pd_info = kzalloc(sizeof(struct rkclk_pd_info), GFP_KERNEL);
1113 pd_info->pd = kzalloc(sizeof(struct clk_pd), GFP_KERNEL);
1122 ret = of_property_read_string_index(node, "clock-output-names",
1123 0, &pd_info->clk_name);
1127 pd_info->parent_name = of_clk_get_parent_name(node, 0);
1129 ret = of_property_read_u32(node, "rockchip,pd-id", &pd->id);
1131 clk_err("%s: can not get pd-id\n", __func__);
1136 list_for_each_entry(rkclk, &rk_clks, node) {
1137 if (strcmp(pd_info->clk_name, rkclk->clk_name) == 0) {
1138 clk_err("%s %d:\n", __func__, __LINE__);
1139 clk_err("This clk (%s) has been used, error!\n",
1146 rkclk = kzalloc(sizeof(struct rkclk), GFP_KERNEL);
1151 rkclk->clk_name = pd_info->clk_name;
1152 rkclk->pd_info = pd_info;
1153 rkclk->clk_type = RKCLK_PD_TYPE;
1155 clk_debug("%s: creat %s\n", __func__, rkclk->clk_name);
1156 list_add_tail(&rkclk->node, &rk_clks);
1162 clk_err("%s error, ret = %d\n", __func__, ret);
1175 static int rkclk_register(struct rkclk *rkclk)
1177 struct clk *clk = NULL;
1178 struct clk_mux *mux = NULL;
1179 struct clk_divider *div = NULL;
1180 struct clk_gate *gate = NULL;
1181 struct clk_pll *pll = NULL;
1182 struct clk_divider *frac = NULL;
1183 struct clk_fixed_rate *fixed_rate = NULL;
1184 struct clk_fixed_factor *fixed_factor = NULL;
1185 struct clk_pd *pd = NULL;
1187 struct clk_hw *mux_hw = NULL;
1188 const struct clk_ops *mux_ops = NULL;
1189 struct clk_hw *rate_hw = NULL;
1190 const struct clk_ops *rate_ops = NULL;
1191 struct clk_hw *gate_hw = NULL;
1192 const struct clk_ops *gate_ops = NULL;
1195 const char **parent_names = NULL;
1196 u8 rate_type_count = 0;
1199 if (rkclk && rkclk->clk_name) {
1200 clk_debug("%s: clk_name=%s, clk_type=0x%x, flags=0x%x\n",
1201 __func__, rkclk->clk_name, rkclk->clk_type,
1204 clk_err("%s: rkclk or clk_name is NULL!\n", __func__);
1208 if (rkclk->mux_info && rkclk->mux_info->mux)
1209 mux = rkclk->mux_info->mux;
1210 if (rkclk->div_info && rkclk->div_info->div)
1211 div = rkclk->div_info->div;
1212 if (rkclk->gate_info && rkclk->gate_info->gate)
1213 gate = rkclk->gate_info->gate;
1214 if (rkclk->pll_info && rkclk->pll_info->pll)
1215 pll = rkclk->pll_info->pll;
1216 if (rkclk->frac_info && rkclk->frac_info->frac)
1217 frac = rkclk->frac_info->frac;
1218 if (rkclk->fixed_rate_info && rkclk->fixed_rate_info->fixed_rate)
1219 fixed_rate = rkclk->fixed_rate_info->fixed_rate;
1220 if (rkclk->fixed_factor_info && rkclk->fixed_factor_info->fixed_factor)
1221 fixed_factor = rkclk->fixed_factor_info->fixed_factor;
1222 if (rkclk->pd_info && rkclk->pd_info->pd)
1223 pd = rkclk->pd_info->pd;
1226 switch (rkclk->clk_type) {
1227 case RKCLK_MUX_TYPE:
1228 /* only mux without specified ops will be registered here */
1229 if (rkclk->mux_info->clkops_idx == CLKOPS_TABLE_END) {
1230 clk_debug("use clk_register_mux\n");
1231 clk = clk_register_mux_table(NULL, rkclk->clk_name,
1232 rkclk->mux_info->parent_names,
1233 rkclk->mux_info->parent_num,
1234 rkclk->flags, mux->reg, mux->shift,
1235 mux->mask, mux->flags, NULL, &clk_lock);
1239 case RKCLK_PLL_TYPE:
1240 clk_debug("use rk_clk_register_pll\n");
1241 clk = rk_clk_register_pll(NULL, rkclk->clk_name,
1242 rkclk->pll_info->parent_name,
1243 rkclk->flags, pll->reg, pll->width,
1244 pll->mode_offset, pll->mode_shift,
1245 pll->status_offset, pll->status_shift,
1246 pll->flags, &clk_lock);
1249 case RKCLK_DIV_TYPE:
1250 /* only div without specified ops will be registered here */
1251 if (rkclk->div_info->clkops_idx == CLKOPS_TABLE_END) {
1252 clk_debug("use clk_register_divider\n");
1253 clk = clk_register_divider(NULL, rkclk->clk_name,
1254 rkclk->div_info->parent_name,
1255 rkclk->flags, div->reg, div->shift,
1256 div->width, div->flags, &clk_lock);
1260 case RKCLK_FRAC_TYPE:
1261 if (rkclk->frac_info->clkops_idx == CLKOPS_TABLE_END) {
1262 clk_err("frac node without specified ops!\n");
1266 case RKCLK_GATE_TYPE:
1267 clk_debug("use clk_register_gate\n");
1268 clk = clk_register_gate(NULL, rkclk->clk_name,
1269 rkclk->gate_info->parent_name, rkclk->flags,
1270 gate->reg, gate->bit_idx, gate->flags,
1273 case RKCLK_FIXED_RATE_TYPE:
1274 clk_debug("use clk_register_fixed_rate\n");
1275 clk = clk_register_fixed_rate(NULL, rkclk->clk_name,
1276 rkclk->fixed_rate_info->parent_name,
1277 rkclk->flags, fixed_rate->fixed_rate);
1279 case RKCLK_FIXED_FACTOR_TYPE:
1280 clk_debug("use clk_register_fixed_factor\n");
1281 clk = clk_register_fixed_factor(NULL, rkclk->clk_name,
1282 rkclk->fixed_factor_info->parent_name,
1283 rkclk->flags, fixed_factor->mult,
1287 clk_debug("use rk_clk_register_pd\n");
1288 clk = rk_clk_register_pd(NULL, rkclk->clk_name,
1289 rkclk->pd_info->parent_name, rkclk->flags,
1298 if (rkclk->clk_type & RKCLK_DIV_TYPE)
1300 if (rkclk->clk_type & RKCLK_PLL_TYPE)
1302 if (rkclk->clk_type & RKCLK_FRAC_TYPE)
1304 if (rkclk->clk_type & RKCLK_FIXED_RATE_TYPE)
1306 if (rkclk->clk_type & RKCLK_FIXED_FACTOR_TYPE)
1309 if (rate_type_count > 1) {
1310 clk_err("Invalid rkclk type!\n");
1314 clk_debug("use clk_register_composite\n");
1316 /* prepare args for clk_register_composite */
1318 /* prepare parent_num && parent_names
1319 * priority: MUX > DIV=PLL=FRAC=FIXED_FACTOR > GATE
1321 if (rkclk->clk_type & RKCLK_MUX_TYPE) {
1322 parent_num = rkclk->mux_info->parent_num;
1323 parent_names = rkclk->mux_info->parent_names;
1324 } else if (rkclk->clk_type & RKCLK_DIV_TYPE ) {
1326 parent_names = &(rkclk->div_info->parent_name);
1327 } else if (rkclk->clk_type & RKCLK_PLL_TYPE) {
1329 parent_names = &(rkclk->pll_info->parent_name);
1330 } else if (rkclk->clk_type & RKCLK_FRAC_TYPE) {
1332 parent_names = &(rkclk->frac_info->parent_name);
1333 } else if (rkclk->clk_type & RKCLK_FIXED_FACTOR_TYPE) {
1335 parent_names = &(rkclk->fixed_factor_info->parent_name);
1336 } else if (rkclk->clk_type & RKCLK_GATE_TYPE) {
1338 parent_names = &(rkclk->gate_info->parent_name);
1341 /* prepare mux_hw && mux_ops */
1342 if (rkclk->clk_type & RKCLK_MUX_TYPE) {
1344 mux_ops = &clk_mux_ops;
1347 /* prepare rate_hw && rate_ops
1348 * priority: DIV=PLL=FRAC=FIXED_FACTOR > MUX
1350 if (rkclk->clk_type & RKCLK_DIV_TYPE) {
1352 if (rkclk->div_info->clkops_idx != CLKOPS_TABLE_END)
1353 rate_ops = rk_get_clkops(rkclk->div_info->clkops_idx);
1355 rate_ops = &clk_divider_ops;
1356 } else if (rkclk->clk_type & RKCLK_PLL_TYPE) {
1358 rate_ops = rk_get_pll_ops(pll->flags);
1359 } else if (rkclk->clk_type & RKCLK_FRAC_TYPE) {
1360 rate_hw = &frac->hw;
1361 rate_ops = rk_get_clkops(rkclk->frac_info->clkops_idx);
1362 } else if (rkclk->clk_type & RKCLK_FIXED_FACTOR_TYPE) {
1363 rate_hw = &fixed_factor->hw;
1364 rate_ops = &clk_fixed_factor_ops;
1365 } else if ((rkclk->clk_type & RKCLK_MUX_TYPE) &&
1366 (rkclk->mux_info->clkops_idx != CLKOPS_TABLE_END)) {
1367 /* when a mux node has specified clkops_idx, prepare rate_hw &&
1368 * rate_ops and use clk_register_composite to register it later.
1371 rate_hw = kzalloc(sizeof(struct clk_hw), GFP_KERNEL);
1373 clk_err("%s: fail to alloc rate_hw!\n", __func__);
1376 rate_ops = rk_get_clkops(rkclk->mux_info->clkops_idx);
1379 if (rkclk->clk_type & RKCLK_GATE_TYPE) {
1380 gate_hw = &gate->hw;
1381 gate_ops = &clk_gate_ops;
1384 clk_debug("parent_num=%d, mux_hw=%d mux_ops=%d, rate_hw=%d rate_ops=%d,"
1385 " gate_hw=%d gate_ops=%d\n",
1386 parent_num, mux_hw?1:0, mux_ops?1:0, rate_hw?1:0,
1387 rate_ops?1:0, gate_hw?1:0, gate_ops?1:0);
1389 clk = clk_register_composite(NULL, rkclk->clk_name, parent_names,
1390 parent_num, mux_hw, mux_ops, rate_hw, rate_ops,
1391 gate_hw, gate_ops, rkclk->flags);
1395 clk_debug("clk name=%s, flags=0x%lx\n", clk->name, clk->flags);
1396 clk_register_clkdev(clk, rkclk->clk_name, NULL);
1398 clk_err("%s: clk(\"%s\") register clk error\n", __func__,
1405 static int _rkclk_add_provider(struct device_node *np)
1407 int i, cnt, ret = 0;
1408 const char *name = NULL;
1409 struct clk *clk = NULL;
1410 struct clk_onecell_data *clk_data = NULL;
1415 cnt = of_property_count_strings(np, "clock-output-names");
1417 clk_err("%s: error in clock-output-names, cnt=%d\n", __func__,
1422 clk_debug("%s: cnt = %d\n", __func__, cnt);
1425 clk_debug("%s: nothing to do\n", __func__);
1430 of_property_read_string(np, "clock-output-names", &name);
1431 clk_debug("clock-output-names = %s\n", name);
1433 clk = clk_get_sys(NULL, name);
1435 clk_err("%s: fail to get %s\n", __func__, name);
1439 ret = of_clk_add_provider(np, of_clk_src_simple_get, clk);
1440 clk_debug("use of_clk_src_simple_get, ret=%d\n", ret);
1442 clk_data = kzalloc(sizeof(struct clk_onecell_data), GFP_KERNEL);
1446 clk_data->clks = kzalloc(cnt * sizeof(struct clk *), GFP_KERNEL);
1447 if (!clk_data->clks) {
1452 clk_data->clk_num = cnt;
1454 for (i=0; i<cnt; i++) {
1455 of_property_read_string_index(np, "clock-output-names",
1457 clk_debug("clock-output-names[%d]=%s\n", i, name);
1459 /* ignore empty slots */
1460 if (!strcmp("reserved", name))
1463 clk = clk_get_sys(NULL, name);
1465 clk_err("%s: fail to get %s\n", __func__, name);
1469 clk_data->clks[i] = clk;
1472 ret = of_clk_add_provider(np, of_clk_src_onecell_get, clk_data);
1473 clk_debug("use of_clk_src_onecell_get, ret=%d\n", ret);
1479 static void rkclk_add_provider(struct device_node *np)
1481 struct device_node *node, *node_reg, *node_tmp, *node_prd;
1482 const char *compatible;
1485 for_each_available_child_of_node(np, node) {
1486 of_property_read_string(node, "compatible", &compatible);
1488 if (strcmp(compatible, "rockchip,rk-fixed-rate-cons") == 0) {
1489 for_each_available_child_of_node(node, node_prd) {
1490 _rkclk_add_provider(node_prd);
1492 } else if (strcmp(compatible, "rockchip,rk-fixed-factor-cons") == 0) {
1493 for_each_available_child_of_node(node, node_prd) {
1494 _rkclk_add_provider(node_prd);
1496 } else if (strcmp(compatible, "rockchip,rk-clock-regs") == 0) {
1497 for_each_available_child_of_node(node, node_reg) {
1498 of_property_read_string(node_reg, "compatible", &compatible);
1500 if (strcmp(compatible, "rockchip,rk-pll-cons") == 0) {
1501 for_each_available_child_of_node(node_reg, node_prd) {
1502 _rkclk_add_provider(node_prd);
1504 } else if (strcmp(compatible, "rockchip,rk-sel-cons") == 0) {
1505 for_each_available_child_of_node(node_reg, node_tmp) {
1506 for_each_available_child_of_node(node_tmp,
1508 _rkclk_add_provider(node_prd);
1511 } else if (strcmp(compatible, "rockchip,rk-gate-cons") == 0) {
1512 for_each_available_child_of_node(node_reg, node_prd) {
1513 _rkclk_add_provider(node_prd);
1516 clk_err("%s: unknown\n", __func__);
1519 } else if (strcmp(compatible, "rockchip,rk-pd-cons") == 0) {
1520 for_each_available_child_of_node(node, node_prd) {
1521 _rkclk_add_provider(node_prd);
1523 } else if (strcmp(compatible, "rockchip,rk-clock-special-regs") == 0) {
1524 for_each_available_child_of_node(node, node_prd) {
1525 _rkclk_add_provider(node_prd);
1528 clk_err("%s: unknown\n", __func__);
1534 static void rkclk_cache_parents(struct rkclk *rkclk)
1536 struct clk *clk, *parent;
1541 clk = clk_get(NULL, rkclk->clk_name);
1543 clk_err("%s: %s clk_get error\n",
1544 __func__, rkclk->clk_name);
1547 clk_debug("%s: %s clk_get success\n",
1548 __func__, __clk_get_name(clk));
1551 num_parents = __clk_get_num_parents(clk);
1552 clk_debug("\t\tnum_parents=%d, parent=%s\n", num_parents,
1553 __clk_get_name(__clk_get_parent(clk)));
1555 for (i=0; i<num_parents; i++) {
1556 /* parent will be cached after this func is called */
1557 parent = clk_get_parent_by_index(clk, i);
1558 if (IS_ERR(parent)) {
1559 clk_err("fail to get parents[%d]=%s\n", i,
1560 clk->parent_names[i]);
1563 clk_debug("\t\tparents[%d]: %s\n", i,
1564 __clk_get_name(parent));
1569 void rk_dump_cru(void)
1571 printk(KERN_WARNING "CRU:\n");
1572 print_hex_dump(KERN_WARNING, "", DUMP_PREFIX_OFFSET, 32, 4, rk_cru_base,
1575 EXPORT_SYMBOL_GPL(rk_dump_cru);
1579 void rkclk_dump_info(struct rkclk *rkclk)
1581 struct clk_mux *mux = NULL;
1582 struct clk_divider *div = NULL;
1583 struct clk_gate *gate = NULL;
1584 struct clk_pll *pll = NULL;
1585 struct clk_divider *frac = NULL;
1586 struct clk_fixed_rate *fixed_rate = NULL;
1587 struct clk_fixed_factor *fixed_factor = NULL;
1588 struct clk_pd *pd = NULL;
1592 clk_debug("%s: clkname=%s, type=0x%x, flags=0x%x\n",
1593 __func__, (rkclk->clk_name)?(rkclk->clk_name):NULL,
1594 rkclk->clk_type, rkclk->flags);
1596 if (rkclk->mux_info && rkclk->mux_info->mux)
1597 mux = rkclk->mux_info->mux;
1598 if (rkclk->div_info && rkclk->div_info->div)
1599 div = rkclk->div_info->div;
1600 if (rkclk->pll_info && rkclk->pll_info->pll)
1601 pll = rkclk->pll_info->pll;
1602 if (rkclk->frac_info && rkclk->frac_info->frac)
1603 frac = rkclk->frac_info->frac;
1604 if (rkclk->gate_info && rkclk->gate_info->gate)
1605 gate = rkclk->gate_info->gate;
1606 if (rkclk->fixed_rate_info && rkclk->fixed_rate_info->fixed_rate)
1607 fixed_rate = rkclk->fixed_rate_info->fixed_rate;
1608 if (rkclk->fixed_factor_info && rkclk->fixed_factor_info->fixed_factor)
1609 fixed_factor = rkclk->fixed_factor_info->fixed_factor;
1610 if (rkclk->pd_info && rkclk->pd_info->pd)
1611 pd = rkclk->pd_info->pd;
1614 if (rkclk->mux_info) {
1615 clk_debug("\t\tmux_info: name=%s, clkops_idx=%u\n",
1616 rkclk->mux_info->clk_name,
1617 rkclk->mux_info->clkops_idx);
1618 for (i = 0; i < rkclk->mux_info->parent_num; i++)
1619 clk_debug("\t\t\tparent[%d]: %s\n", i,
1620 rkclk->mux_info->parent_names[i]);
1622 clk_debug("\t\tmux: reg=0x%x, mask=0x%x, shift=0x%x, "
1623 "mux_flags=0x%x\n", (u32)mux->reg,
1624 mux->mask, mux->shift, mux->flags);
1628 if (rkclk->pll_info) {
1629 clk_debug("\t\tpll_info: name=%s, parent=%s, clkops_idx=0x%x\n",
1630 rkclk->pll_info->clk_name,
1631 rkclk->pll_info->parent_name,
1632 rkclk->pll_info->clkops_idx);
1634 clk_debug("\t\tpll: reg=0x%x, width=0x%x, "
1635 "mode_offset=0x%x, mode_shift=%u, "
1636 "status_offset=0x%x, status_shift=%u, "
1638 (u32)pll->reg, pll->width,
1639 pll->mode_offset, pll->mode_shift,
1640 pll->status_offset, pll->status_shift,
1645 if (rkclk->div_info) {
1646 clk_debug("\t\tdiv_info: name=%s, div_type=0x%x, parent=%s, "
1648 rkclk->div_info->clk_name,
1649 rkclk->div_info->div_type,
1650 rkclk->div_info->parent_name,
1651 rkclk->div_info->clkops_idx);
1653 clk_debug("\t\tdiv: reg=0x%x, shift=0x%x, width=0x%x, "
1654 "div_flags=0x%x\n", (u32)div->reg,
1655 div->shift, div->width, div->flags);
1659 if (rkclk->frac_info) {
1660 clk_debug("\t\tfrac_info: name=%s, parent=%s, clkops_idx=%d\n",
1661 rkclk->frac_info->clk_name,
1662 rkclk->frac_info->parent_name,
1663 rkclk->frac_info->clkops_idx);
1665 clk_debug("\t\tfrac: reg=0x%x, shift=0x%x, width=0x%x, "
1666 "div_flags=0x%x\n", (u32)frac->reg,
1667 frac->shift, frac->width, frac->flags);
1671 if (rkclk->gate_info) {
1672 clk_debug("\t\tgate_info: name=%s, parent=%s\n",
1673 rkclk->gate_info->clk_name,
1674 rkclk->gate_info->parent_name);
1676 clk_debug("\t\tgate: reg=0x%x, bit_idx=%d, "
1677 "gate_flags=0x%x\n", (u32)gate->reg,
1678 gate->bit_idx, gate->flags);
1682 if (rkclk->fixed_rate_info) {
1683 clk_debug("\t\tfixed_rate_info: name=%s\n",
1684 rkclk->fixed_rate_info->clk_name);
1686 clk_debug("\t\tfixed_rate=%lu, fixed_rate_flags=0x%x\n",
1687 fixed_rate->fixed_rate, fixed_rate->flags);
1691 if (rkclk->fixed_factor_info) {
1692 clk_debug("\t\tfixed_factor_info: name=%s, parent=%s\n",
1693 rkclk->fixed_factor_info->clk_name,
1694 rkclk->fixed_factor_info->parent_name);
1696 clk_debug("\t\tfixed_factor: mult=%u, div=%u\n",
1697 fixed_factor->mult, fixed_factor->div);
1701 if (rkclk->pd_info) {
1702 clk_debug("\t\tpd_info: name=%s, parent=%s\n",
1703 rkclk->pd_info->clk_name,
1704 rkclk->pd_info->parent_name);
1706 clk_debug("\t\tpd: id=%u\n", pd->id);
1711 void rkclk_dump_info(struct rkclk *rkclk) {}
1716 char* pd_table[] = {
1723 void rk_clk_pd_test(void)
1730 for (j = 0; j < ARRAY_SIZE(pd_table); j++) {
1732 clk = clk_get(NULL, pd_table[j]);
1734 ret = clk_prepare_enable(clk);
1735 printk("%s: clk_prepare_enable %s, ret=%d\n", __func__,
1736 __clk_get_name(clk), ret);
1738 state = __clk_is_enabled(clk);
1739 printk("%s: clk_pd %s is %s\n", __func__, __clk_get_name(clk),
1740 state ? "enable" : "disable");
1742 clk_disable_unprepare(clk);
1743 printk("%s: clk_disable_unprepare %s\n", __func__,
1744 __clk_get_name(clk));
1746 state = __clk_is_enabled(clk);
1747 printk("%s: clk_pd %s is %s\n", __func__, __clk_get_name(clk),
1748 state ? "enable" : "disable");
1759 struct test_table t_table[] = {
1760 {.name = "clk_gpu", .rate = 297000000},
1761 {.name = "dclk_lcdc0", .rate = 100000000},
1762 {.name = "aclk_lcdc0", .rate = 297000000},
1764 {.name = "clk_sdmmc", .rate = 50000000},
1765 {.name = "clk_emmc", .rate = 50000000},
1766 {.name = "clk_sdio", .rate = 50000000},
1768 {.name = "clk_i2s_div", .rate = 300000000},
1769 {.name = "clk_i2s_frac",.rate = 22579200},
1770 {.name = "clk_i2s", .rate = 11289600},
1771 {.name = "clk_spdif", .rate = 11289600},
1773 {.name = "cif_out_pll", .rate = 48000000},
1774 {.name = "clk_cif0", .rate = 12000000},
1776 {.name = "clk_uart0", .rate = 12288000},
1777 {.name = "clk_uart1", .rate = 48000000},
1778 {.name = "clk_hsadc", .rate = 12288000},
1779 {.name = "clk_mac", .rate = 50000000},
1781 // {.name = "clk_apll", .rate = 500000000},
1782 // {.name = "clk_dpll", .rate = 400000000},
1783 {.name = "clk_cpll", .rate = 600000000},
1784 {.name = "clk_gpll", .rate = 800000000},
1786 {.name = "clk_core", .rate = 100000000},
1787 {.name = "clk_core", .rate = 24000000},
1788 {.name = "clk_core", .rate = 500000000},
1792 void rk_clk_test(void)
1794 const char *clk_name;
1796 unsigned long rate=0, recalc_rate=0, round_rate=0, get_rate=0;
1800 for (j = 0; j < ARRAY_SIZE(t_table); j++) {
1801 clk_debug(">>>>>>test %u\n", j);
1803 clk_name = t_table[j].name;
1804 rate = t_table[j].rate;
1806 clk = clk_get(NULL, clk_name);
1808 clk_err("%s: clk(\"%s\") \tclk_get error\n",
1809 __func__, clk_name);
1811 clk_debug("%s: clk(\"%s\") \tclk_get success\n",
1812 __func__, clk_name);
1814 /* TEST: clk_round_rate */
1815 round_rate = clk_round_rate(clk, rate);
1816 clk_debug("%s: clk(\"%s\") \tclk_round_rate from %lu to %lu\n",
1817 __func__, clk_name, rate, round_rate);
1819 /* TEST: clk_set_rate */
1820 ret = clk_set_rate(clk, rate);
1822 clk_err("%s: clk(\"%s\") \tclk_set_rate error, ret=%d\n",
1823 __func__, clk_name, ret);
1825 clk_debug("%s: clk(\"%s\") \tclk_set_rate success\n",
1826 __func__, clk_name);
1829 /* TEST: recalc_rate\clk_get_rate */
1830 if (clk->ops->recalc_rate) {
1831 recalc_rate = clk->ops->recalc_rate(clk->hw,
1833 clk_debug("%s: clk(\"%s\") \tclk_recalc_rate %lu\n",
1834 __func__, clk_name, recalc_rate);
1836 clk_debug("%s: clk(\"%s\") have no recalc ops\n",
1837 __func__, clk_name);
1838 get_rate = clk_get_rate(clk);
1839 clk_debug("%s: clk(\"%s\") \tclk_get_rate %lu\n",
1840 __func__, clk_name, get_rate);
1849 void rk_clk_test(void) {}
1851 EXPORT_SYMBOL_GPL(rk_clk_test);
1853 static int rkclk_panic(struct notifier_block *this, unsigned long ev, void *ptr)
1859 static struct notifier_block rkclk_panic_block = {
1860 .notifier_call = rkclk_panic,
1863 void __init rkclk_init_clks(struct device_node *node);
1865 static struct device_node * clk_root_node=NULL;
1866 static void __init rk_clk_tree_init(struct device_node *np)
1868 struct device_node *node, *node_init;
1869 struct rkclk *rkclk;
1870 const char *compatible;
1872 printk("%s start!\n", __func__);
1874 node_init = of_find_node_by_name(NULL, "clocks-init");
1876 clk_err("%s: can not get clocks-init node\n", __func__);
1880 clk_root_node = of_find_node_by_name(NULL, "clock_regs");
1881 rk_cru_base = of_iomap(clk_root_node, 0);
1883 clk_err("%s: could not map cru region\n", __func__);
1887 node = of_parse_phandle(np, "rockchip,grf", 0);
1889 rk_grf_base = of_iomap(node, 0);
1892 rk_grf_base = RK_GRF_VIRT;
1895 for_each_available_child_of_node(np, node) {
1897 of_property_read_string(node, "compatible",
1900 if (strcmp(compatible, "rockchip,rk-fixed-rate-cons") == 0) {
1901 if (rkclk_init_fixed_rate(node) != 0) {
1902 clk_err("%s: init fixed_rate err\n", __func__);
1905 } else if (strcmp(compatible, "rockchip,rk-fixed-factor-cons") == 0) {
1906 if (rkclk_init_fixed_factor(node) != 0) {
1907 clk_err("%s: init fixed_factor err\n", __func__);
1910 } else if (strcmp(compatible, "rockchip,rk-clock-regs") == 0) {
1911 if (rkclk_init_regcon(node) != 0) {
1912 clk_err("%s: init reg cons err\n", __func__);
1915 } else if (strcmp(compatible, "rockchip,rk-pd-cons") == 0) {
1916 if (rkclk_init_pd(node) != 0) {
1917 clk_err("%s: init pd err\n", __func__);
1920 } else if (strcmp(compatible, "rockchip,rk-clock-special-regs") == 0) {
1921 if (rkclk_init_special_regs(node) != 0) {
1922 clk_err("%s: init special reg err\n", __func__);
1926 clk_err("%s: unknown\n", __func__);
1930 list_for_each_entry(rkclk, &rk_clks, node) {
1932 rkclk_dump_info(rkclk);
1934 rkclk_register(rkclk);
1937 rkclk_add_provider(np);
1939 /* fill clock parents cache after all clocks have been registered */
1940 list_for_each_entry(rkclk, &rk_clks, node) {
1942 rkclk_cache_parents(rkclk);
1945 rkclk_init_clks(node_init);
1949 atomic_notifier_chain_register(&panic_notifier_list, &rkclk_panic_block);
1951 CLK_OF_DECLARE(rk_clocks, "rockchip,rk-clocks", rk_clk_tree_init);
1954 /***************************** rockchip clks init******************************/
1955 const char *of_clk_init_rate_get_info(struct device_node *np,
1956 int index,u32 *rate)
1958 struct of_phandle_args clkspec;
1959 const char *clk_name;
1965 rc = of_parse_phandle_with_args(np, "rockchip,clocks-init-rate",
1966 "#clock-init-cells", index, &clkspec);
1970 if (of_property_read_string_index(clkspec.np, "clock-output-names", 0,
1974 *rate= clkspec.args[0];
1976 of_node_put(clkspec.np);
1980 const char *of_clk_init_parent_get_info(struct device_node *np, int index,
1981 const char **clk_child_name)
1983 struct of_phandle_args clkspec;
1984 const char *clk_name;
1987 struct device_node *node = NULL;
1992 rc = of_parse_phandle_with_args(np, "rockchip,clocks-init-parent",
1993 "#clock-init-cells", index, &clkspec);
1997 if (of_property_read_string_index(clkspec.np, "clock-output-names", 0,
2002 phandle = clkspec.args[0];
2004 of_node_put(clkspec.np);
2008 node = of_find_node_by_phandle(phandle);
2013 if (of_property_read_string_index(node, "clock-output-names", 0,
2014 clk_child_name) < 0)
2017 of_node_put(node);//???
2026 static int __init rkclk_init_enable(void)
2028 struct device_node *node;
2029 int cnt, i, ret = 0;
2030 const char *clk_name;
2034 node = of_find_node_by_name(NULL, "clocks-enable");
2036 clk_err("%s: can not get clocks-enable node\n", __func__);
2040 cnt = of_count_phandle_with_args(node, "clocks", "#clock-cells");
2044 clk_debug("%s: cnt = %d\n", __func__, cnt);
2047 for (i = 0; i < cnt ; i++) {
2048 clk_name = of_clk_get_parent_name(node, i);
2049 clk = clk_get(NULL, clk_name);
2050 if (IS_ERR_OR_NULL(clk)) {
2051 clk_err("%s: fail to get %s\n", __func__, clk_name);
2055 ret = clk_prepare_enable(clk);
2057 clk_err("%s: fail to prepare_enable %s\n", __func__,
2061 clk_debug("%s: prepare_enable %s OK\n", __func__,
2069 static int uboot_logo_on = 0;
2071 static void __init rk_get_uboot_display_flag(void)
2073 struct device_node *node;
2075 node = of_find_node_by_name(NULL, "fb");
2077 of_property_read_u32(node, "rockchip,uboot-logo-on", &uboot_logo_on);
2079 printk("%s: uboot_logo_on = %d\n", __FUNCTION__, uboot_logo_on);
2082 static const char *of_clk_uboot_has_init_get_name(struct device_node *np, int index)
2084 struct of_phandle_args clkspec;
2085 const char *clk_name;
2091 rc = of_parse_phandle_with_args(np, "rockchip,clocks-uboot-has-init",
2092 "#clock-cells", index, &clkspec);
2096 if (of_property_read_string_index(clkspec.np, "clock-output-names",
2097 clkspec.args_count ? clkspec.args[0] : 0,
2101 of_node_put(clkspec.np);
2105 /* If clk has been inited, return 1; else return 0. */
2106 static int rkclk_uboot_has_init(struct device_node *np, const char *clk_name)
2112 if ((!np) || (!clk_name))
2115 cnt = of_count_phandle_with_args(np, "rockchip,clocks-uboot-has-init",
2120 for (i = 0; i < cnt ; i++) {
2121 name = of_clk_uboot_has_init_get_name(np, i);
2122 if (name && (!strcmp(clk_name, name)))
2129 void __init rkclk_init_clks(struct device_node *np)
2131 //struct device_node *np;
2132 int i,cnt_parent,cnt_rate;
2135 struct clk *clk_p, *clk_c;
2136 const char *clk_name, *clk_parent_name;
2139 rk_get_uboot_display_flag();
2141 cnt_parent = of_count_phandle_with_args(np,
2142 "rockchip,clocks-init-parent", "#clock-init-cells");
2144 printk("%s: cnt_parent = %d\n",__FUNCTION__,cnt_parent);
2146 for (i = 0; i < cnt_parent; i++) {
2147 clk_parent_name=NULL;
2148 clk_name=of_clk_init_parent_get_info(np, i,&clk_parent_name);
2150 if(clk_name==NULL||clk_parent_name==NULL)
2153 clk_c=clk_get(NULL,clk_name);
2154 clk_p=clk_get(NULL,clk_parent_name);
2156 if(IS_ERR(clk_c)||IS_ERR(clk_p))
2159 clk_set_parent(clk_c, clk_p);
2161 clk_debug("%s: set %s parent = %s\n", __FUNCTION__, clk_name,
2165 cnt_rate = of_count_phandle_with_args(np, "rockchip,clocks-init-rate",
2166 "#clock-init-cells");
2168 printk("%s: cnt_rate = %d\n",__FUNCTION__,cnt_rate);
2170 for (i = 0; i < cnt_rate; i++) {
2171 clk_name=of_clk_init_rate_get_info(np, i, &clk_rate);
2176 if (uboot_logo_on && rkclk_uboot_has_init(np, clk_name)) {
2177 printk("%s: %s has been inited in uboot, ingored\n",
2178 __FUNCTION__, clk_name);
2182 clk_c = clk_get(NULL, clk_name);
2187 if((clk_rate<1*MHZ)||(clk_rate>2000*MHZ))
2188 clk_err("warning: clk_rate < 1*MHZ or > 2000*MHZ\n");
2190 clk_set_rate(clk_c, clk_rate);
2192 clk_debug("%s: set %s rate = %u\n", __FUNCTION__, clk_name,
2196 rkclk_init_enable();
2200 u32 clk_suspend_clkgt_info_get(u32 *clk_ungt_msk,u32 *clk_ungt_msk_last,u32 buf_cnt)
2203 struct device_node *node,*node_gt;
2207 void __iomem *cru_base,*gt_base, *reg_n, *reg_p;
2210 cru_base= of_iomap(clk_root_node, 0);
2212 for_each_available_child_of_node(clk_root_node, node) {
2214 if (of_device_is_compatible(node,"rockchip,rk-gate-cons"))
2217 for_each_available_child_of_node(node, node_gt) {
2221 clk_err("%s:save buf is overflow\n",__FUNCTION__);
2225 ret = of_property_read_u32_array(node_gt,"rockchip,suspend-clkgating-setting",temp_val,2);
2228 clk_ungt_msk[gt_cnt]=temp_val[0];
2229 clk_ungt_msk_last[gt_cnt]=temp_val[1];
2233 clk_ungt_msk[gt_cnt]=0xffff;
2234 clk_ungt_msk_last[gt_cnt]=0xffff;
2239 gt_base=of_iomap(node_gt, 0);
2245 reg_n=of_iomap(node_gt, 0);
2247 if(((long)reg_n-(long)reg_p)!=4)
2249 printk("%s: gt reg is not continue\n",__FUNCTION__);
2255 clk_debug("%s:gt%d,reg=%p,val=(%x,%x)\n",__FUNCTION__,gt_cnt, reg_n,
2256 clk_ungt_msk[gt_cnt], clk_ungt_msk_last[gt_cnt]);
2268 clk_err("%s:save buf is not Enough\n",__FUNCTION__);
2271 clk_debug("%s:crubase=%x,gtbase=%x\n",__FUNCTION__,cru_base,gt_base);
2273 return (u32)(gt_base-cru_base);