2 * Copyright 2014 Google, Inc
3 * Author: Alexandru M Stan <amstan@chromium.org>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
16 #include <linux/slab.h>
17 #include <linux/clk.h>
18 #include <linux/clk-provider.h>
20 #include <linux/kernel.h>
23 struct rockchip_mmc_clock {
30 #define to_mmc_clock(_hw) container_of(_hw, struct rockchip_mmc_clock, hw)
32 #define RK3288_MMC_CLKGEN_DIV 2
34 static unsigned long rockchip_mmc_recalc(struct clk_hw *hw,
35 unsigned long parent_rate)
37 return parent_rate / RK3288_MMC_CLKGEN_DIV;
40 #define ROCKCHIP_MMC_DELAY_SEL BIT(10)
41 #define ROCKCHIP_MMC_DEGREE_MASK 0x3
42 #define ROCKCHIP_MMC_DELAYNUM_OFFSET 2
43 #define ROCKCHIP_MMC_DELAYNUM_MASK (0xff << ROCKCHIP_MMC_DELAYNUM_OFFSET)
45 #define PSECS_PER_SEC 1000000000000LL
48 * Each fine delay is between 40ps-80ps. Assume each fine delay is 60ps to
49 * simplify calculations. So 45degs could be anywhere between 33deg and 66deg.
51 #define ROCKCHIP_MMC_DELAY_ELEMENT_PSEC 60
53 static int rockchip_mmc_get_phase(struct clk_hw *hw)
55 struct rockchip_mmc_clock *mmc_clock = to_mmc_clock(hw);
56 unsigned long rate = clk_get_rate(hw->clk);
61 raw_value = readl(mmc_clock->reg) >> (mmc_clock->shift);
63 degrees = (raw_value & ROCKCHIP_MMC_DEGREE_MASK) * 90;
65 if (raw_value & ROCKCHIP_MMC_DELAY_SEL) {
66 /* degrees/delaynum * 10000 */
67 unsigned long factor = (ROCKCHIP_MMC_DELAY_ELEMENT_PSEC / 10) *
68 36 * (rate / 1000000);
70 delay_num = (raw_value & ROCKCHIP_MMC_DELAYNUM_MASK);
71 delay_num >>= ROCKCHIP_MMC_DELAYNUM_OFFSET;
72 degrees += delay_num * factor / 10000;
78 static int rockchip_mmc_set_phase(struct clk_hw *hw, int degrees)
80 struct rockchip_mmc_clock *mmc_clock = to_mmc_clock(hw);
81 unsigned long rate = clk_get_rate(hw->clk);
82 u8 nineties, remainder;
87 /* allow 22 to be 22.5 */
89 /* floor to 22.5 increment */
90 degrees -= ((degrees) * 10 % 225) / 10;
92 nineties = degrees / 90;
94 remainder = (degrees % 90) / 22;
96 delay = PSECS_PER_SEC;
100 do_div(delay, ROCKCHIP_MMC_DELAY_ELEMENT_PSEC);
103 delay_num = (u8) min(delay, 255ULL);
105 raw_value = delay_num ? ROCKCHIP_MMC_DELAY_SEL : 0;
106 raw_value |= delay_num << ROCKCHIP_MMC_DELAYNUM_OFFSET;
107 raw_value |= nineties;
108 writel(HIWORD_UPDATE(raw_value, 0x07ff, mmc_clock->shift), mmc_clock->reg);
110 pr_debug("%s->set_phase(%d) delay_nums=%u reg[0x%p]=0x%03x actual_degrees=%d\n",
111 clk_hw_get_name(hw), degrees, delay_num,
112 mmc_clock->reg, raw_value>>(mmc_clock->shift),
113 rockchip_mmc_get_phase(hw)
119 static const struct clk_ops rockchip_mmc_clk_ops = {
120 .recalc_rate = rockchip_mmc_recalc,
121 .get_phase = rockchip_mmc_get_phase,
122 .set_phase = rockchip_mmc_set_phase,
125 struct clk *rockchip_clk_register_mmc(const char *name,
126 const char *const *parent_names, u8 num_parents,
127 void __iomem *reg, int shift)
129 struct clk_init_data init;
130 struct rockchip_mmc_clock *mmc_clock;
133 mmc_clock = kmalloc(sizeof(*mmc_clock), GFP_KERNEL);
138 init.num_parents = num_parents;
139 init.parent_names = parent_names;
140 init.ops = &rockchip_mmc_clk_ops;
142 mmc_clock->hw.init = &init;
143 mmc_clock->reg = reg;
144 mmc_clock->shift = shift;
146 clk = clk_register(NULL, &mmc_clock->hw);