drivers/clk/rockchip/clk-pll.c

   1 /*
   2  * Copyright (c) 2014 MundoReader S.L.
   3  * Author: Heiko Stuebner <heiko@sntech.de>
   4  *
   5  * Copyright (c) 2015 Rockchip Electronics Co. Ltd.
   6  * Author: Xing Zheng <zhengxing@rock-chips.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  */
  18
  19 #include <asm/div64.h>
  20 #include <linux/slab.h>
  21 #include <linux/io.h>
  22 #include <linux/delay.h>
  23 #include <linux/clk-provider.h>
  24 #include <linux/regmap.h>
  25 #include <linux/clk.h>
  26 #include <linux/gcd.h>
  27 #include "clk.h"
  28
  29 #define PLL_MODE_MASK           0x3
  30 #define PLL_MODE_SLOW           0x0
  31 #define PLL_MODE_NORM           0x1
  32 #define PLL_MODE_DEEP           0x2
  33 #define PLL_RK3328_MODE_MASK    0x1
  34
  35 struct rockchip_clk_pll {
  36         struct clk_hw           hw;
  37
  38         struct clk_mux          pll_mux;
  39         const struct clk_ops    *pll_mux_ops;
  40
  41         struct notifier_block   clk_nb;
  42
  43         void __iomem            *reg_base;
  44         int                     lock_offset;
  45         unsigned int            lock_shift;
  46         enum rockchip_pll_type  type;
  47         u8                      flags;
  48         const struct rockchip_pll_rate_table *rate_table;
  49         unsigned int            rate_count;
  50         spinlock_t              *lock;
  51
  52         struct rockchip_clk_provider *ctx;
  53 };
  54
  55 #define to_rockchip_clk_pll(_hw) container_of(_hw, struct rockchip_clk_pll, hw)
  56 #define to_rockchip_clk_pll_nb(nb) \
  57                         container_of(nb, struct rockchip_clk_pll, clk_nb)
  58
  59 static void rockchip_rk3366_pll_get_params(struct rockchip_clk_pll *pll,
  60                                         struct rockchip_pll_rate_table *rate);
  61 static int rockchip_rk3366_pll_set_params(struct rockchip_clk_pll *pll,
  62                                 const struct rockchip_pll_rate_table *rate);
  63
  64 #define MHZ                     (1000UL * 1000UL)
  65 #define KHZ                     (1000UL)
  66
  67 /* CLK_PLL_TYPE_RK3066_AUTO type ops */
  68 #define PLL_FREF_MIN            (269 * KHZ)
  69 #define PLL_FREF_MAX            (2200 * MHZ)
  70
  71 #define PLL_FVCO_MIN            (440 * MHZ)
  72 #define PLL_FVCO_MAX            (2200 * MHZ)
  73
  74 #define PLL_FOUT_MIN            (27500 * KHZ)
  75 #define PLL_FOUT_MAX            (2200 * MHZ)
  76
  77 #define PLL_NF_MAX              (4096)
  78 #define PLL_NR_MAX              (64)
  79 #define PLL_NO_MAX              (16)
  80
  81 /* CLK_PLL_TYPE_RK3036/3366/3399_AUTO type ops */
  82 #define MIN_FOUTVCO_FREQ        (800 * MHZ)
  83 #define MAX_FOUTVCO_FREQ        (2000 * MHZ)
  84
  85 static struct rockchip_pll_rate_table auto_table;
  86
  87 static struct rockchip_pll_rate_table *rk_pll_rate_table_get(void)
  88 {
  89         return &auto_table;
  90 }
  91
  92 static int rockchip_pll_clk_set_postdiv(unsigned long fout_hz,
  93                                         u32 *postdiv1,
  94                                         u32 *postdiv2,
  95                                         u32 *foutvco)
  96 {
  97         unsigned long freq;
  98
  99         if (fout_hz < MIN_FOUTVCO_FREQ) {
 100                 for (*postdiv1 = 1; *postdiv1 <= 7; (*postdiv1)++) {
 101                         for (*postdiv2 = 1; *postdiv2 <= 7; (*postdiv2)++) {
 102                                 freq = fout_hz * (*postdiv1) * (*postdiv2);
 103                                 if (freq >= MIN_FOUTVCO_FREQ &&
 104                                     freq <= MAX_FOUTVCO_FREQ) {
 105                                         *foutvco = freq;
 106                                         return 0;
 107                                 }
 108                         }
 109                         pr_err("CANNOT FIND postdiv1/2 to make fout in range from 800M to 2000M,fout = %lu\n",
 110                                fout_hz);
 111                 }
 112         } else {
 113                 *postdiv1 = 1;
 114                 *postdiv2 = 1;
 115         }
 116         return 0;
 117 }
 118
 119 static struct rockchip_pll_rate_table *
 120 rockchip_pll_clk_set_by_auto(struct rockchip_clk_pll *pll,
 121                              unsigned long fin_hz,
 122                              unsigned long fout_hz)
 123 {
 124         struct rockchip_pll_rate_table *rate_table = rk_pll_rate_table_get();
 125         /* FIXME set postdiv1/2 always 1*/
 126         u32 foutvco = fout_hz;
 127         u64 fin_64, frac_64;
 128         u32 f_frac, postdiv1, postdiv2;
 129         unsigned long clk_gcd = 0;
 130
 131         if (fin_hz == 0 || fout_hz == 0 || fout_hz == fin_hz)
 132                 return NULL;
 133
 134         rockchip_pll_clk_set_postdiv(fout_hz, &postdiv1, &postdiv2, &foutvco);
 135         rate_table->postdiv1 = postdiv1;
 136         rate_table->postdiv2 = postdiv2;
 137         rate_table->dsmpd = 1;
 138
 139         if (fin_hz / MHZ * MHZ == fin_hz && fout_hz / MHZ * MHZ == fout_hz) {
 140                 fin_hz /= MHZ;
 141                 foutvco /= MHZ;
 142                 clk_gcd = gcd(fin_hz, foutvco);
 143                 rate_table->refdiv = fin_hz / clk_gcd;
 144                 rate_table->fbdiv = foutvco / clk_gcd;
 145
 146                 rate_table->frac = 0;
 147
 148                 pr_debug("fin = %lu, fout = %lu, clk_gcd = %lu, refdiv = %u, fbdiv = %u, postdiv1 = %u, postdiv2 = %u, frac = %u\n",
 149                          fin_hz, fout_hz, clk_gcd, rate_table->refdiv,
 150                          rate_table->fbdiv, rate_table->postdiv1,
 151                          rate_table->postdiv2, rate_table->frac);
 152         } else {
 153                 pr_debug("frac div running, fin_hz = %lu, fout_hz = %lu, fin_INT_mhz = %lu, fout_INT_mhz = %lu\n",
 154                          fin_hz, fout_hz,
 155                          fin_hz / MHZ * MHZ,
 156                          fout_hz / MHZ * MHZ);
 157                 pr_debug("frac get postdiv1 = %u,  postdiv2 = %u, foutvco = %u\n",
 158                          rate_table->postdiv1, rate_table->postdiv2, foutvco);
 159                 clk_gcd = gcd(fin_hz / MHZ, foutvco / MHZ);
 160                 rate_table->refdiv = fin_hz / MHZ / clk_gcd;
 161                 rate_table->fbdiv = foutvco / MHZ / clk_gcd;
 162                 pr_debug("frac get refdiv = %u,  fbdiv = %u\n",
 163                          rate_table->refdiv, rate_table->fbdiv);
 164
 165                 rate_table->frac = 0;
 166
 167                 f_frac = (foutvco % MHZ);
 168                 fin_64 = fin_hz;
 169                 do_div(fin_64, (u64)rate_table->refdiv);
 170                 frac_64 = (u64)f_frac << 24;
 171                 do_div(frac_64, fin_64);
 172                 rate_table->frac = (u32)frac_64;
 173                 if (rate_table->frac > 0)
 174                         rate_table->dsmpd = 0;
 175                 pr_debug("frac = %x\n", rate_table->frac);
 176         }
 177         return rate_table;
 178 }
 179
 180 static struct rockchip_pll_rate_table *
 181 rockchip_rk3066_pll_clk_set_by_auto(struct rockchip_clk_pll *pll,
 182                                     unsigned long fin_hz,
 183                                     unsigned long fout_hz)
 184 {
 185         struct rockchip_pll_rate_table *rate_table = rk_pll_rate_table_get();
 186         u32 nr, nf, no, nonr;
 187         u32 nr_out, nf_out, no_out;
 188         u32 n;
 189         u32 numerator, denominator;
 190         u64 fref, fvco, fout;
 191         unsigned long clk_gcd = 0;
 192
 193         nr_out = PLL_NR_MAX + 1;
 194         no_out = 0;
 195         nf_out = 0;
 196
 197         if (fin_hz == 0 || fout_hz == 0 || fout_hz == fin_hz)
 198                 return NULL;
 199
 200         clk_gcd = gcd(fin_hz, fout_hz);
 201
 202         numerator = fout_hz / clk_gcd;
 203         denominator = fin_hz / clk_gcd;
 204
 205         for (n = 1;; n++) {
 206                 nf = numerator * n;
 207                 nonr = denominator * n;
 208                 if (nf > PLL_NF_MAX || nonr > (PLL_NO_MAX * PLL_NR_MAX))
 209                         break;
 210
 211                 for (no = 1; no <= PLL_NO_MAX; no++) {
 212                         if (!(no == 1 || !(no % 2)))
 213                                 continue;
 214
 215                         if (nonr % no)
 216                                 continue;
 217                         nr = nonr / no;
 218
 219                         if (nr > PLL_NR_MAX)
 220                                 continue;
 221
 222                         fref = fin_hz / nr;
 223                         if (fref < PLL_FREF_MIN || fref > PLL_FREF_MAX)
 224                                 continue;
 225
 226                         fvco = fref * nf;
 227                         if (fvco < PLL_FVCO_MIN || fvco > PLL_FVCO_MAX)
 228                                 continue;
 229
 230                         fout = fvco / no;
 231                         if (fout < PLL_FOUT_MIN || fout > PLL_FOUT_MAX)
 232                                 continue;
 233
 234                         /* select the best from all available PLL settings */
 235                         if ((no > no_out) ||
 236                             ((no == no_out) && (nr < nr_out))) {
 237                                 nr_out = nr;
 238                                 nf_out = nf;
 239                                 no_out = no;
 240                         }
 241                 }
 242         }
 243
 244         /* output the best PLL setting */
 245         if ((nr_out <= PLL_NR_MAX) && (no_out > 0)) {
 246                 if (rate_table->nr && rate_table->nf && rate_table->no) {
 247                         rate_table->nr = nr_out;
 248                         rate_table->nf = nf_out;
 249                         rate_table->no = no_out;
 250                 }
 251         } else {
 252                 return NULL;
 253         }
 254
 255         return rate_table;
 256 }
 257
 258 static const struct rockchip_pll_rate_table *rockchip_get_pll_settings(
 259                             struct rockchip_clk_pll *pll, unsigned long rate)
 260 {
 261         const struct rockchip_pll_rate_table  *rate_table = pll->rate_table;
 262         int i;
 263
 264         for (i = 0; i < pll->rate_count; i++) {
 265                 if (rate == rate_table[i].rate)
 266                         return &rate_table[i];
 267         }
 268
 269         if (pll->type == pll_rk3066 || pll->type == pll_rk3328)
 270                 return rockchip_rk3066_pll_clk_set_by_auto(pll, 24 * MHZ, rate);
 271         else
 272                 return rockchip_pll_clk_set_by_auto(pll, 24 * MHZ, rate);
 273 }
 274
 275 static long rockchip_pll_round_rate(struct clk_hw *hw,
 276                             unsigned long drate, unsigned long *prate)
 277 {
 278         return drate;
 279 }
 280
 281 /*
 282  * Wait for the pll to reach the locked state.
 283  * The calling set_rate function is responsible for making sure the
 284  * grf regmap is available.
 285  */
 286 static int rockchip_pll_wait_lock(struct rockchip_clk_pll *pll)
 287 {
 288         struct regmap *grf = rockchip_clk_get_grf(pll->ctx);
 289         unsigned int val;
 290         int delay = 24000000, ret;
 291
 292         while (delay > 0) {
 293                 ret = regmap_read(grf, pll->lock_offset, &val);
 294                 if (ret) {
 295                         pr_err("%s: failed to read pll lock status: %d\n",
 296                                __func__, ret);
 297                         return ret;
 298                 }
 299
 300                 if (val & BIT(pll->lock_shift))
 301                         return 0;
 302                 delay--;
 303         }
 304
 305         pr_err("%s: timeout waiting for pll to lock\n", __func__);
 306         return -ETIMEDOUT;
 307 }
 308
 309 /**
 310  * PLL used in RK3036
 311  */
 312
 313 #define RK3036_PLLCON(i)                        (i * 0x4)
 314 #define RK3036_PLLCON0_FBDIV_MASK               0xfff
 315 #define RK3036_PLLCON0_FBDIV_SHIFT              0
 316 #define RK3036_PLLCON0_POSTDIV1_MASK            0x7
 317 #define RK3036_PLLCON0_POSTDIV1_SHIFT           12
 318 #define RK3036_PLLCON1_REFDIV_MASK              0x3f
 319 #define RK3036_PLLCON1_REFDIV_SHIFT             0
 320 #define RK3036_PLLCON1_POSTDIV2_MASK            0x7
 321 #define RK3036_PLLCON1_POSTDIV2_SHIFT           6
 322 #define RK3036_PLLCON1_DSMPD_MASK               0x1
 323 #define RK3036_PLLCON1_DSMPD_SHIFT              12
 324 #define RK3036_PLLCON2_FRAC_MASK                0xffffff
 325 #define RK3036_PLLCON2_FRAC_SHIFT               0
 326
 327 #define RK3036_PLLCON1_PWRDOWN                  (1 << 13)
 328
 329 static void rockchip_rk3036_pll_get_params(struct rockchip_clk_pll *pll,
 330                                         struct rockchip_pll_rate_table *rate)
 331 {
 332         u32 pllcon;
 333
 334         pllcon = readl_relaxed(pll->reg_base + RK3036_PLLCON(0));
 335         rate->fbdiv = ((pllcon >> RK3036_PLLCON0_FBDIV_SHIFT)
 336                                 & RK3036_PLLCON0_FBDIV_MASK);
 337         rate->postdiv1 = ((pllcon >> RK3036_PLLCON0_POSTDIV1_SHIFT)
 338                                 & RK3036_PLLCON0_POSTDIV1_MASK);
 339
 340         pllcon = readl_relaxed(pll->reg_base + RK3036_PLLCON(1));
 341         rate->refdiv = ((pllcon >> RK3036_PLLCON1_REFDIV_SHIFT)
 342                                 & RK3036_PLLCON1_REFDIV_MASK);
 343         rate->postdiv2 = ((pllcon >> RK3036_PLLCON1_POSTDIV2_SHIFT)
 344                                 & RK3036_PLLCON1_POSTDIV2_MASK);
 345         rate->dsmpd = ((pllcon >> RK3036_PLLCON1_DSMPD_SHIFT)
 346                                 & RK3036_PLLCON1_DSMPD_MASK);
 347
 348         pllcon = readl_relaxed(pll->reg_base + RK3036_PLLCON(2));
 349         rate->frac = ((pllcon >> RK3036_PLLCON2_FRAC_SHIFT)
 350                                 & RK3036_PLLCON2_FRAC_MASK);
 351 }
 352
 353 static unsigned long rockchip_rk3036_pll_recalc_rate(struct clk_hw *hw,
 354                                                      unsigned long prate)
 355 {
 356         struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
 357         struct rockchip_pll_rate_table cur;
 358         u64 rate64 = prate;
 359
 360         if (pll->type == pll_rk3366)
 361                 rockchip_rk3366_pll_get_params(pll, &cur);
 362         else
 363                 rockchip_rk3036_pll_get_params(pll, &cur);
 364
 365         rate64 *= cur.fbdiv;
 366         do_div(rate64, cur.refdiv);
 367
 368         if (cur.dsmpd == 0) {
 369                 /* fractional mode */
 370                 u64 frac_rate64 = prate * cur.frac;
 371
 372                 do_div(frac_rate64, cur.refdiv);
 373                 rate64 += frac_rate64 >> 24;
 374         }
 375
 376         do_div(rate64, cur.postdiv1);
 377         do_div(rate64, cur.postdiv2);
 378
 379         return (unsigned long)rate64;
 380 }
 381
 382 static int rockchip_rk3036_pll_set_params(struct rockchip_clk_pll *pll,
 383                                 const struct rockchip_pll_rate_table *rate)
 384 {
 385         const struct clk_ops *pll_mux_ops = pll->pll_mux_ops;
 386         struct clk_mux *pll_mux = &pll->pll_mux;
 387         struct rockchip_pll_rate_table cur;
 388         u32 pllcon;
 389         int rate_change_remuxed = 0;
 390         int cur_parent;
 391         int ret;
 392
 393         pr_debug("%s: rate settings for %lu fbdiv: %d, postdiv1: %d, refdiv: %d, postdiv2: %d, dsmpd: %d, frac: %d\n",
 394                 __func__, rate->rate, rate->fbdiv, rate->postdiv1, rate->refdiv,
 395                 rate->postdiv2, rate->dsmpd, rate->frac);
 396
 397         rockchip_rk3036_pll_get_params(pll, &cur);
 398         cur.rate = 0;
 399
 400         cur_parent = pll_mux_ops->get_parent(&pll_mux->hw);
 401         if (cur_parent == PLL_MODE_NORM) {
 402                 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW);
 403                 rate_change_remuxed = 1;
 404         }
 405
 406         /* update pll values */
 407         writel_relaxed(HIWORD_UPDATE(rate->fbdiv, RK3036_PLLCON0_FBDIV_MASK,
 408                                           RK3036_PLLCON0_FBDIV_SHIFT) |
 409                        HIWORD_UPDATE(rate->postdiv1, RK3036_PLLCON0_POSTDIV1_MASK,
 410                                              RK3036_PLLCON0_POSTDIV1_SHIFT),
 411                        pll->reg_base + RK3036_PLLCON(0));
 412
 413         writel_relaxed(HIWORD_UPDATE(rate->refdiv, RK3036_PLLCON1_REFDIV_MASK,
 414                                                    RK3036_PLLCON1_REFDIV_SHIFT) |
 415                        HIWORD_UPDATE(rate->postdiv2, RK3036_PLLCON1_POSTDIV2_MASK,
 416                                                      RK3036_PLLCON1_POSTDIV2_SHIFT) |
 417                        HIWORD_UPDATE(rate->dsmpd, RK3036_PLLCON1_DSMPD_MASK,
 418                                                   RK3036_PLLCON1_DSMPD_SHIFT),
 419                        pll->reg_base + RK3036_PLLCON(1));
 420
 421         /* GPLL CON2 is not HIWORD_MASK */
 422         pllcon = readl_relaxed(pll->reg_base + RK3036_PLLCON(2));
 423         pllcon &= ~(RK3036_PLLCON2_FRAC_MASK << RK3036_PLLCON2_FRAC_SHIFT);
 424         pllcon |= rate->frac << RK3036_PLLCON2_FRAC_SHIFT;
 425         writel_relaxed(pllcon, pll->reg_base + RK3036_PLLCON(2));
 426
 427         /* wait for the pll to lock */
 428         ret = rockchip_pll_wait_lock(pll);
 429         if (ret) {
 430                 pr_warn("%s: pll update unsucessful, trying to restore old params\n",
 431                         __func__);
 432                 rockchip_rk3036_pll_set_params(pll, &cur);
 433         }
 434
 435         if (rate_change_remuxed)
 436                 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_NORM);
 437
 438         return ret;
 439 }
 440
 441 static int rockchip_rk3036_pll_set_rate(struct clk_hw *hw, unsigned long drate,
 442                                         unsigned long prate)
 443 {
 444         struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
 445         const struct rockchip_pll_rate_table *rate;
 446         unsigned long old_rate = rockchip_rk3036_pll_recalc_rate(hw, prate);
 447         struct regmap *grf = rockchip_clk_get_grf(pll->ctx);
 448
 449         if (IS_ERR(grf)) {
 450                 pr_debug("%s: grf regmap not available, aborting rate change\n",
 451                          __func__);
 452                 return PTR_ERR(grf);
 453         }
 454
 455         pr_debug("%s: changing %s from %lu to %lu with a parent rate of %lu\n",
 456                  __func__, __clk_get_name(hw->clk), old_rate, drate, prate);
 457
 458         /* Get required rate settings from table */
 459         rate = rockchip_get_pll_settings(pll, drate);
 460         if (!rate) {
 461                 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
 462                         drate, __clk_get_name(hw->clk));
 463                 return -EINVAL;
 464         }
 465
 466         if (pll->type == pll_rk3366)
 467                 return rockchip_rk3366_pll_set_params(pll, rate);
 468
 469         return rockchip_rk3036_pll_set_params(pll, rate);
 470 }
 471
 472 static int rockchip_rk3036_pll_enable(struct clk_hw *hw)
 473 {
 474         struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
 475
 476         writel(HIWORD_UPDATE(0, RK3036_PLLCON1_PWRDOWN, 0),
 477                pll->reg_base + RK3036_PLLCON(1));
 478
 479         return 0;
 480 }
 481
 482 static void rockchip_rk3036_pll_disable(struct clk_hw *hw)
 483 {
 484         struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
 485
 486         writel(HIWORD_UPDATE(RK3036_PLLCON1_PWRDOWN,
 487                              RK3036_PLLCON1_PWRDOWN, 0),
 488                pll->reg_base + RK3036_PLLCON(1));
 489 }
 490
 491 static int rockchip_rk3036_pll_is_enabled(struct clk_hw *hw)
 492 {
 493         struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
 494         u32 pllcon = readl(pll->reg_base + RK3036_PLLCON(1));
 495
 496         return !(pllcon & RK3036_PLLCON1_PWRDOWN);
 497 }
 498
 499 static void rockchip_rk3036_pll_init(struct clk_hw *hw)
 500 {
 501         struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
 502         const struct rockchip_pll_rate_table *rate;
 503         struct rockchip_pll_rate_table cur;
 504         unsigned long drate;
 505
 506         if (!(pll->flags & ROCKCHIP_PLL_SYNC_RATE))
 507                 return;
 508
 509         drate = clk_hw_get_rate(hw);
 510         rate = rockchip_get_pll_settings(pll, drate);
 511
 512         /* when no rate setting for the current rate, rely on clk_set_rate */
 513         if (!rate)
 514                 return;
 515
 516         if (pll->type == pll_rk3366)
 517                 rockchip_rk3366_pll_get_params(pll, &cur);
 518         else
 519                 rockchip_rk3036_pll_get_params(pll, &cur);
 520
 521         pr_debug("%s: pll %s@%lu: Hz\n", __func__, __clk_get_name(hw->clk),
 522                  drate);
 523         pr_debug("old - fbdiv: %d, postdiv1: %d, refdiv: %d, postdiv2: %d, dsmpd: %d, frac: %d\n",
 524                  cur.fbdiv, cur.postdiv1, cur.refdiv, cur.postdiv2,
 525                  cur.dsmpd, cur.frac);
 526         pr_debug("new - fbdiv: %d, postdiv1: %d, refdiv: %d, postdiv2: %d, dsmpd: %d, frac: %d\n",
 527                  rate->fbdiv, rate->postdiv1, rate->refdiv, rate->postdiv2,
 528                  rate->dsmpd, rate->frac);
 529
 530         if (rate->fbdiv != cur.fbdiv || rate->postdiv1 != cur.postdiv1 ||
 531                 rate->refdiv != cur.refdiv || rate->postdiv2 != cur.postdiv2 ||
 532                 rate->dsmpd != cur.dsmpd || rate->frac != cur.frac) {
 533                 struct clk *parent = clk_get_parent(hw->clk);
 534
 535                 if (!parent) {
 536                         pr_warn("%s: parent of %s not available\n",
 537                                 __func__, __clk_get_name(hw->clk));
 538                         return;
 539                 }
 540
 541                 pr_debug("%s: pll %s: rate params do not match rate table, adjusting\n",
 542                          __func__, __clk_get_name(hw->clk));
 543                 if (pll->type == pll_rk3366)
 544                         rockchip_rk3366_pll_set_params(pll, rate);
 545                 else
 546                         rockchip_rk3036_pll_set_params(pll, rate);
 547         }
 548 }
 549
 550 static const struct clk_ops rockchip_rk3036_pll_clk_norate_ops = {
 551         .recalc_rate = rockchip_rk3036_pll_recalc_rate,
 552         .enable = rockchip_rk3036_pll_enable,
 553         .disable = rockchip_rk3036_pll_disable,
 554         .is_enabled = rockchip_rk3036_pll_is_enabled,
 555 };
 556
 557 static const struct clk_ops rockchip_rk3036_pll_clk_ops = {
 558         .recalc_rate = rockchip_rk3036_pll_recalc_rate,
 559         .round_rate = rockchip_pll_round_rate,
 560         .set_rate = rockchip_rk3036_pll_set_rate,
 561         .enable = rockchip_rk3036_pll_enable,
 562         .disable = rockchip_rk3036_pll_disable,
 563         .is_enabled = rockchip_rk3036_pll_is_enabled,
 564         .init = rockchip_rk3036_pll_init,
 565 };
 566
 567 /**
 568  * PLL used in RK3066, RK3188 and RK3288
 569  */
 570
 571 #define RK3066_PLL_RESET_DELAY(nr)      ((nr * 500) / 24 + 1)
 572
 573 #define RK3066_PLLCON(i)                (i * 0x4)
 574 #define RK3066_PLLCON0_OD_MASK          0xf
 575 #define RK3066_PLLCON0_OD_SHIFT         0
 576 #define RK3066_PLLCON0_NR_MASK          0x3f
 577 #define RK3066_PLLCON0_NR_SHIFT         8
 578 #define RK3066_PLLCON1_NF_MASK          0x1fff
 579 #define RK3066_PLLCON1_NF_SHIFT         0
 580 #define RK3066_PLLCON2_NB_MASK          0xfff
 581 #define RK3066_PLLCON2_NB_SHIFT         0
 582 #define RK3066_PLLCON3_RESET            (1 << 5)
 583 #define RK3066_PLLCON3_PWRDOWN          (1 << 1)
 584 #define RK3066_PLLCON3_BYPASS           (1 << 0)
 585
 586 static void rockchip_rk3066_pll_get_params(struct rockchip_clk_pll *pll,
 587                                         struct rockchip_pll_rate_table *rate)
 588 {
 589         u32 pllcon;
 590
 591         pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(0));
 592         rate->nr = ((pllcon >> RK3066_PLLCON0_NR_SHIFT)
 593                                 & RK3066_PLLCON0_NR_MASK) + 1;
 594         rate->no = ((pllcon >> RK3066_PLLCON0_OD_SHIFT)
 595                                 & RK3066_PLLCON0_OD_MASK) + 1;
 596
 597         pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(1));
 598         rate->nf = ((pllcon >> RK3066_PLLCON1_NF_SHIFT)
 599                                 & RK3066_PLLCON1_NF_MASK) + 1;
 600
 601         pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(2));
 602         rate->nb = ((pllcon >> RK3066_PLLCON2_NB_SHIFT)
 603                                 & RK3066_PLLCON2_NB_MASK) + 1;
 604 }
 605
 606 static unsigned long rockchip_rk3066_pll_recalc_rate(struct clk_hw *hw,
 607                                                      unsigned long prate)
 608 {
 609         struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
 610         struct rockchip_pll_rate_table cur;
 611         u64 rate64 = prate;
 612         u32 pllcon;
 613
 614         pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(3));
 615         if (pllcon & RK3066_PLLCON3_BYPASS) {
 616                 pr_debug("%s: pll %s is bypassed\n", __func__,
 617                         clk_hw_get_name(hw));
 618                 return prate;
 619         }
 620
 621         rockchip_rk3066_pll_get_params(pll, &cur);
 622
 623         rate64 *= cur.nf;
 624         do_div(rate64, cur.nr);
 625         do_div(rate64, cur.no);
 626
 627         return (unsigned long)rate64;
 628 }
 629
 630 static int rockchip_rk3066_pll_set_params(struct rockchip_clk_pll *pll,
 631                                 const struct rockchip_pll_rate_table *rate)
 632 {
 633         const struct clk_ops *pll_mux_ops = pll->pll_mux_ops;
 634         struct clk_mux *pll_mux = &pll->pll_mux;
 635         struct rockchip_pll_rate_table cur;
 636         int rate_change_remuxed = 0;
 637         int cur_parent;
 638         int ret;
 639
 640         pr_debug("%s: rate settings for %lu (nr, no, nf): (%d, %d, %d)\n",
 641                  __func__, rate->rate, rate->nr, rate->no, rate->nf);
 642
 643         rockchip_rk3066_pll_get_params(pll, &cur);
 644         cur.rate = 0;
 645
 646         cur_parent = pll_mux_ops->get_parent(&pll_mux->hw);
 647         if (cur_parent == PLL_MODE_NORM) {
 648                 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW);
 649                 rate_change_remuxed = 1;
 650         }
 651
 652         /* enter reset mode */
 653         writel(HIWORD_UPDATE(RK3066_PLLCON3_RESET, RK3066_PLLCON3_RESET, 0),
 654                pll->reg_base + RK3066_PLLCON(3));
 655
 656         /* update pll values */
 657         writel(HIWORD_UPDATE(rate->nr - 1, RK3066_PLLCON0_NR_MASK,
 658                                            RK3066_PLLCON0_NR_SHIFT) |
 659                HIWORD_UPDATE(rate->no - 1, RK3066_PLLCON0_OD_MASK,
 660                                            RK3066_PLLCON0_OD_SHIFT),
 661                pll->reg_base + RK3066_PLLCON(0));
 662
 663         writel_relaxed(HIWORD_UPDATE(rate->nf - 1, RK3066_PLLCON1_NF_MASK,
 664                                                    RK3066_PLLCON1_NF_SHIFT),
 665                        pll->reg_base + RK3066_PLLCON(1));
 666         writel_relaxed(HIWORD_UPDATE(rate->nb - 1, RK3066_PLLCON2_NB_MASK,
 667                                                    RK3066_PLLCON2_NB_SHIFT),
 668                        pll->reg_base + RK3066_PLLCON(2));
 669
 670         /* leave reset and wait the reset_delay */
 671         writel(HIWORD_UPDATE(0, RK3066_PLLCON3_RESET, 0),
 672                pll->reg_base + RK3066_PLLCON(3));
 673         udelay(RK3066_PLL_RESET_DELAY(rate->nr));
 674
 675         /* wait for the pll to lock */
 676         ret = rockchip_pll_wait_lock(pll);
 677         if (ret) {
 678                 pr_warn("%s: pll update unsucessful, trying to restore old params\n",
 679                         __func__);
 680                 rockchip_rk3066_pll_set_params(pll, &cur);
 681         }
 682
 683         if (rate_change_remuxed)
 684                 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_NORM);
 685
 686         return ret;
 687 }
 688
 689 static int rockchip_rk3066_pll_set_rate(struct clk_hw *hw, unsigned long drate,
 690                                         unsigned long prate)
 691 {
 692         struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
 693         const struct rockchip_pll_rate_table *rate;
 694         unsigned long old_rate = rockchip_rk3066_pll_recalc_rate(hw, prate);
 695         struct regmap *grf = rockchip_clk_get_grf(pll->ctx);
 696
 697         if (IS_ERR(grf)) {
 698                 pr_debug("%s: grf regmap not available, aborting rate change\n",
 699                          __func__);
 700                 return PTR_ERR(grf);
 701         }
 702
 703         pr_debug("%s: changing %s from %lu to %lu with a parent rate of %lu\n",
 704                  __func__, clk_hw_get_name(hw), old_rate, drate, prate);
 705
 706         /* Get required rate settings from table */
 707         rate = rockchip_get_pll_settings(pll, drate);
 708         if (!rate) {
 709                 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
 710                         drate, clk_hw_get_name(hw));
 711                 return -EINVAL;
 712         }
 713
 714         return rockchip_rk3066_pll_set_params(pll, rate);
 715 }
 716
 717 static int rockchip_rk3066_pll_enable(struct clk_hw *hw)
 718 {
 719         struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
 720
 721         writel(HIWORD_UPDATE(0, RK3066_PLLCON3_PWRDOWN, 0),
 722                pll->reg_base + RK3066_PLLCON(3));
 723
 724         return 0;
 725 }
 726
 727 static void rockchip_rk3066_pll_disable(struct clk_hw *hw)
 728 {
 729         struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
 730
 731         writel(HIWORD_UPDATE(RK3066_PLLCON3_PWRDOWN,
 732                              RK3066_PLLCON3_PWRDOWN, 0),
 733                pll->reg_base + RK3066_PLLCON(3));
 734 }
 735
 736 static int rockchip_rk3066_pll_is_enabled(struct clk_hw *hw)
 737 {
 738         struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
 739         u32 pllcon = readl(pll->reg_base + RK3066_PLLCON(3));
 740
 741         return !(pllcon & RK3066_PLLCON3_PWRDOWN);
 742 }
 743
 744 static void rockchip_rk3066_pll_init(struct clk_hw *hw)
 745 {
 746         struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
 747         const struct rockchip_pll_rate_table *rate;
 748         struct rockchip_pll_rate_table cur;
 749         unsigned long drate;
 750
 751         if (!(pll->flags & ROCKCHIP_PLL_SYNC_RATE))
 752                 return;
 753
 754         drate = clk_hw_get_rate(hw);
 755         rate = rockchip_get_pll_settings(pll, drate);
 756
 757         /* when no rate setting for the current rate, rely on clk_set_rate */
 758         if (!rate)
 759                 return;
 760
 761         rockchip_rk3066_pll_get_params(pll, &cur);
 762
 763         pr_debug("%s: pll %s@%lu: nr (%d:%d); no (%d:%d); nf(%d:%d), nb(%d:%d)\n",
 764                  __func__, clk_hw_get_name(hw), drate, rate->nr, cur.nr,
 765                  rate->no, cur.no, rate->nf, cur.nf, rate->nb, cur.nb);
 766         if (rate->nr != cur.nr || rate->no != cur.no || rate->nf != cur.nf
 767                                                      || rate->nb != cur.nb) {
 768                 struct regmap *grf = rockchip_clk_get_grf(pll->ctx);
 769
 770                 if (IS_ERR(grf))
 771                         return;
 772
 773                 pr_debug("%s: pll %s: rate params do not match rate table, adjusting\n",
 774                          __func__, clk_hw_get_name(hw));
 775                 rockchip_rk3066_pll_set_params(pll, rate);
 776         }
 777 }
 778
 779 static const struct clk_ops rockchip_rk3066_pll_clk_norate_ops = {
 780         .recalc_rate = rockchip_rk3066_pll_recalc_rate,
 781         .enable = rockchip_rk3066_pll_enable,
 782         .disable = rockchip_rk3066_pll_disable,
 783         .is_enabled = rockchip_rk3066_pll_is_enabled,
 784 };
 785
 786 static const struct clk_ops rockchip_rk3066_pll_clk_ops = {
 787         .recalc_rate = rockchip_rk3066_pll_recalc_rate,
 788         .round_rate = rockchip_pll_round_rate,
 789         .set_rate = rockchip_rk3066_pll_set_rate,
 790         .enable = rockchip_rk3066_pll_enable,
 791         .disable = rockchip_rk3066_pll_disable,
 792         .is_enabled = rockchip_rk3066_pll_is_enabled,
 793         .init = rockchip_rk3066_pll_init,
 794 };
 795
 796 /**
 797  * PLL used in RK3366
 798  */
 799
 800 #define RK3366_PLLCON(i)                        (i * 0x4)
 801 #define RK3366_PLLCON0_FBDIV_MASK               0xfff
 802 #define RK3366_PLLCON0_FBDIV_SHIFT              0
 803 #define RK3366_PLLCON0_POSTDIV1_MASK            0x7
 804 #define RK3366_PLLCON0_POSTDIV1_SHIFT           12
 805 #define RK3366_PLLCON1_REFDIV_MASK              0x3f
 806 #define RK3366_PLLCON1_REFDIV_SHIFT             0
 807 #define RK3366_PLLCON1_POSTDIV2_MASK            0x7
 808 #define RK3366_PLLCON1_POSTDIV2_SHIFT           6
 809 #define RK3366_PLLCON2_FRAC_MASK                0xffffff
 810 #define RK3366_PLLCON2_FRAC_SHIFT               0
 811 #define RK3366_PLLCON3_DSMPD_MASK               0x1
 812 #define RK3366_PLLCON3_DSMPD_SHIFT              2
 813
 814 #define RK3366_PLLCON3_PWRDOWN                  (1 << 0)
 815
 816 static void rockchip_rk3366_pll_get_params(struct rockchip_clk_pll *pll,
 817                                         struct rockchip_pll_rate_table *rate)
 818 {
 819         u32 pllcon;
 820
 821         pllcon = readl_relaxed(pll->reg_base + RK3366_PLLCON(0));
 822         rate->fbdiv = ((pllcon >> RK3366_PLLCON0_FBDIV_SHIFT)
 823                                 & RK3366_PLLCON0_FBDIV_MASK);
 824         rate->postdiv1 = ((pllcon >> RK3366_PLLCON0_POSTDIV1_SHIFT)
 825                                 & RK3366_PLLCON0_POSTDIV1_MASK);
 826
 827         pllcon = readl_relaxed(pll->reg_base + RK3366_PLLCON(1));
 828         rate->refdiv = ((pllcon >> RK3366_PLLCON1_REFDIV_SHIFT)
 829                                 & RK3366_PLLCON1_REFDIV_MASK);
 830         rate->postdiv2 = ((pllcon >> RK3366_PLLCON1_POSTDIV2_SHIFT)
 831                                 & RK3366_PLLCON1_POSTDIV2_MASK);
 832
 833         pllcon = readl_relaxed(pll->reg_base + RK3366_PLLCON(2));
 834         rate->frac = ((pllcon >> RK3366_PLLCON2_FRAC_SHIFT)
 835                                 & RK3366_PLLCON2_FRAC_MASK);
 836
 837         pllcon = readl_relaxed(pll->reg_base + RK3366_PLLCON(3));
 838         rate->dsmpd = ((pllcon >> RK3366_PLLCON3_DSMPD_SHIFT)
 839                                 & RK3366_PLLCON3_DSMPD_MASK);
 840 }
 841
 842 static int rockchip_rk3366_pll_set_params(struct rockchip_clk_pll *pll,
 843                                 const struct rockchip_pll_rate_table *rate)
 844 {
 845         const struct clk_ops *pll_mux_ops = pll->pll_mux_ops;
 846         struct clk_mux *pll_mux = &pll->pll_mux;
 847         struct rockchip_pll_rate_table cur;
 848         u32 pllcon;
 849         int rate_change_remuxed = 0;
 850         int cur_parent;
 851         int ret;
 852
 853         pr_debug("%s: rate settings for %lu fbdiv: %d, postdiv1: %d, refdiv: %d, postdiv2: %d, dsmpd: %d, frac: %d\n",
 854                 __func__, rate->rate, rate->fbdiv, rate->postdiv1, rate->refdiv,
 855                 rate->postdiv2, rate->dsmpd, rate->frac);
 856
 857         rockchip_rk3366_pll_get_params(pll, &cur);
 858         cur.rate = 0;
 859
 860         cur_parent = pll_mux_ops->get_parent(&pll_mux->hw);
 861         if (cur_parent == PLL_MODE_NORM) {
 862                 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW);
 863                 rate_change_remuxed = 1;
 864         }
 865
 866         /* update pll values */
 867         writel_relaxed(HIWORD_UPDATE(rate->fbdiv, RK3366_PLLCON0_FBDIV_MASK,
 868                                           RK3366_PLLCON0_FBDIV_SHIFT) |
 869                        HIWORD_UPDATE(rate->postdiv1, RK3366_PLLCON0_POSTDIV1_MASK,
 870                                              RK3366_PLLCON0_POSTDIV1_SHIFT),
 871                        pll->reg_base + RK3366_PLLCON(0));
 872
 873         writel_relaxed(HIWORD_UPDATE(rate->refdiv, RK3366_PLLCON1_REFDIV_MASK,
 874                                                    RK3366_PLLCON1_REFDIV_SHIFT) |
 875                        HIWORD_UPDATE(rate->postdiv2, RK3366_PLLCON1_POSTDIV2_MASK,
 876                                                      RK3366_PLLCON1_POSTDIV2_SHIFT),
 877                        pll->reg_base + RK3366_PLLCON(1));
 878
 879         /* GPLL CON2 is not HIWORD_MASK */
 880         pllcon = readl_relaxed(pll->reg_base + RK3366_PLLCON(2));
 881         pllcon &= ~(RK3366_PLLCON2_FRAC_MASK << RK3366_PLLCON2_FRAC_SHIFT);
 882         pllcon |= rate->frac << RK3366_PLLCON2_FRAC_SHIFT;
 883         writel_relaxed(pllcon, pll->reg_base + RK3366_PLLCON(2));
 884
 885         writel_relaxed(HIWORD_UPDATE(rate->dsmpd, RK3366_PLLCON3_DSMPD_MASK,
 886                                                   RK3366_PLLCON3_DSMPD_SHIFT),
 887                        pll->reg_base + RK3366_PLLCON(3));
 888
 889         /* wait for the pll to lock */
 890         ret = rockchip_pll_wait_lock(pll);
 891         if (ret) {
 892                 pr_warn("%s: pll update unsucessful, trying to restore old params\n",
 893                         __func__);
 894                 rockchip_rk3366_pll_set_params(pll, &cur);
 895         }
 896
 897         if (rate_change_remuxed)
 898                 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_NORM);
 899
 900         return ret;
 901 }
 902
 903 static int rockchip_rk3366_pll_enable(struct clk_hw *hw)
 904 {
 905         struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
 906
 907         writel(HIWORD_UPDATE(0, RK3366_PLLCON3_PWRDOWN, 0),
 908                pll->reg_base + RK3366_PLLCON(3));
 909
 910         return 0;
 911 }
 912
 913 static void rockchip_rk3366_pll_disable(struct clk_hw *hw)
 914 {
 915         struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
 916
 917         writel(HIWORD_UPDATE(RK3366_PLLCON3_PWRDOWN,
 918                              RK3366_PLLCON3_PWRDOWN, 0),
 919                pll->reg_base + RK3366_PLLCON(3));
 920 }
 921
 922 static int rockchip_rk3366_pll_is_enabled(struct clk_hw *hw)
 923 {
 924         struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
 925         u32 pllcon = readl(pll->reg_base + RK3366_PLLCON(3));
 926
 927         return !(pllcon & RK3366_PLLCON3_PWRDOWN);
 928 }
 929
 930 static const struct clk_ops rockchip_rk3366_pll_clk_norate_ops = {
 931         .recalc_rate = rockchip_rk3036_pll_recalc_rate,
 932         .enable = rockchip_rk3366_pll_enable,
 933         .disable = rockchip_rk3366_pll_disable,
 934         .is_enabled = rockchip_rk3366_pll_is_enabled,
 935 };
 936
 937 static const struct clk_ops rockchip_rk3366_pll_clk_ops = {
 938         .recalc_rate = rockchip_rk3036_pll_recalc_rate,
 939         .round_rate = rockchip_pll_round_rate,
 940         .set_rate = rockchip_rk3036_pll_set_rate,
 941         .enable = rockchip_rk3366_pll_enable,
 942         .disable = rockchip_rk3366_pll_disable,
 943         .is_enabled = rockchip_rk3366_pll_is_enabled,
 944         .init = rockchip_rk3036_pll_init,
 945 };
 946
 947 /**
 948  * PLL used in RK3399
 949  */
 950
 951 #define RK3399_PLLCON(i)                        (i * 0x4)
 952 #define RK3399_PLLCON0_FBDIV_MASK               0xfff
 953 #define RK3399_PLLCON0_FBDIV_SHIFT              0
 954 #define RK3399_PLLCON1_REFDIV_MASK              0x3f
 955 #define RK3399_PLLCON1_REFDIV_SHIFT             0
 956 #define RK3399_PLLCON1_POSTDIV1_MASK            0x7
 957 #define RK3399_PLLCON1_POSTDIV1_SHIFT           8
 958 #define RK3399_PLLCON1_POSTDIV2_MASK            0x7
 959 #define RK3399_PLLCON1_POSTDIV2_SHIFT           12
 960 #define RK3399_PLLCON2_FRAC_MASK                0xffffff
 961 #define RK3399_PLLCON2_FRAC_SHIFT               0
 962 #define RK3399_PLLCON2_LOCK_STATUS              BIT(31)
 963 #define RK3399_PLLCON3_PWRDOWN                  BIT(0)
 964 #define RK3399_PLLCON3_DSMPD_MASK               0x1
 965 #define RK3399_PLLCON3_DSMPD_SHIFT              3
 966
 967 static int rockchip_rk3399_pll_wait_lock(struct rockchip_clk_pll *pll)
 968 {
 969         u32 pllcon;
 970         int delay = 24000000;
 971
 972         /* poll check the lock status in rk3399 xPLLCON2 */
 973         while (delay > 0) {
 974                 pllcon = readl_relaxed(pll->reg_base + RK3399_PLLCON(2));
 975                 if (pllcon & RK3399_PLLCON2_LOCK_STATUS)
 976                         return 0;
 977
 978                 delay--;
 979         }
 980
 981         pr_err("%s: timeout waiting for pll to lock\n", __func__);
 982         return -ETIMEDOUT;
 983 }
 984
 985 static void rockchip_rk3399_pll_get_params(struct rockchip_clk_pll *pll,
 986                                         struct rockchip_pll_rate_table *rate)
 987 {
 988         u32 pllcon;
 989
 990         pllcon = readl_relaxed(pll->reg_base + RK3399_PLLCON(0));
 991         rate->fbdiv = ((pllcon >> RK3399_PLLCON0_FBDIV_SHIFT)
 992                                 & RK3399_PLLCON0_FBDIV_MASK);
 993
 994         pllcon = readl_relaxed(pll->reg_base + RK3399_PLLCON(1));
 995         rate->refdiv = ((pllcon >> RK3399_PLLCON1_REFDIV_SHIFT)
 996                                 & RK3399_PLLCON1_REFDIV_MASK);
 997         rate->postdiv1 = ((pllcon >> RK3399_PLLCON1_POSTDIV1_SHIFT)
 998                                 & RK3399_PLLCON1_POSTDIV1_MASK);
 999         rate->postdiv2 = ((pllcon >> RK3399_PLLCON1_POSTDIV2_SHIFT)
1000                                 & RK3399_PLLCON1_POSTDIV2_MASK);
1001
1002         pllcon = readl_relaxed(pll->reg_base + RK3399_PLLCON(2));
1003         rate->frac = ((pllcon >> RK3399_PLLCON2_FRAC_SHIFT)
1004                                 & RK3399_PLLCON2_FRAC_MASK);
1005
1006         pllcon = readl_relaxed(pll->reg_base + RK3399_PLLCON(3));
1007         rate->dsmpd = ((pllcon >> RK3399_PLLCON3_DSMPD_SHIFT)
1008                                 & RK3399_PLLCON3_DSMPD_MASK);
1009 }
1010
1011 static unsigned long rockchip_rk3399_pll_recalc_rate(struct clk_hw *hw,
1012                                                      unsigned long prate)
1013 {
1014         struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
1015         struct rockchip_pll_rate_table cur;
1016         u64 rate64 = prate;
1017
1018         rockchip_rk3399_pll_get_params(pll, &cur);
1019
1020         rate64 *= cur.fbdiv;
1021         do_div(rate64, cur.refdiv);
1022
1023         if (cur.dsmpd == 0) {
1024                 /* fractional mode */
1025                 u64 frac_rate64 = prate * cur.frac;
1026
1027                 do_div(frac_rate64, cur.refdiv);
1028                 rate64 += frac_rate64 >> 24;
1029         }
1030
1031         do_div(rate64, cur.postdiv1);
1032         do_div(rate64, cur.postdiv2);
1033
1034         return (unsigned long)rate64;
1035 }
1036
1037 static int rockchip_rk3399_pll_set_params(struct rockchip_clk_pll *pll,
1038                                 const struct rockchip_pll_rate_table *rate)
1039 {
1040         const struct clk_ops *pll_mux_ops = pll->pll_mux_ops;
1041         struct clk_mux *pll_mux = &pll->pll_mux;
1042         struct rockchip_pll_rate_table cur;
1043         u32 pllcon;
1044         int rate_change_remuxed = 0;
1045         int cur_parent;
1046         int ret;
1047
1048         pr_debug("%s: rate settings for %lu fbdiv: %d, postdiv1: %d, refdiv: %d, postdiv2: %d, dsmpd: %d, frac: %d\n",
1049                 __func__, rate->rate, rate->fbdiv, rate->postdiv1, rate->refdiv,
1050                 rate->postdiv2, rate->dsmpd, rate->frac);
1051
1052         rockchip_rk3399_pll_get_params(pll, &cur);
1053         cur.rate = 0;
1054
1055         cur_parent = pll_mux_ops->get_parent(&pll_mux->hw);
1056         if (cur_parent == PLL_MODE_NORM) {
1057                 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW);
1058                 rate_change_remuxed = 1;
1059         }
1060
1061         /* set pll power down */
1062         writel(HIWORD_UPDATE(RK3399_PLLCON3_PWRDOWN,
1063                              RK3399_PLLCON3_PWRDOWN, 0),
1064                pll->reg_base + RK3399_PLLCON(3));
1065
1066         /* update pll values */
1067         writel_relaxed(HIWORD_UPDATE(rate->fbdiv, RK3399_PLLCON0_FBDIV_MASK,
1068                                                   RK3399_PLLCON0_FBDIV_SHIFT),
1069                        pll->reg_base + RK3399_PLLCON(0));
1070
1071         writel_relaxed(HIWORD_UPDATE(rate->refdiv, RK3399_PLLCON1_REFDIV_MASK,
1072                                                    RK3399_PLLCON1_REFDIV_SHIFT) |
1073                        HIWORD_UPDATE(rate->postdiv1, RK3399_PLLCON1_POSTDIV1_MASK,
1074                                                      RK3399_PLLCON1_POSTDIV1_SHIFT) |
1075                        HIWORD_UPDATE(rate->postdiv2, RK3399_PLLCON1_POSTDIV2_MASK,
1076                                                      RK3399_PLLCON1_POSTDIV2_SHIFT),
1077                        pll->reg_base + RK3399_PLLCON(1));
1078
1079         /* xPLL CON2 is not HIWORD_MASK */
1080         pllcon = readl_relaxed(pll->reg_base + RK3399_PLLCON(2));
1081         pllcon &= ~(RK3399_PLLCON2_FRAC_MASK << RK3399_PLLCON2_FRAC_SHIFT);
1082         pllcon |= rate->frac << RK3399_PLLCON2_FRAC_SHIFT;
1083         writel_relaxed(pllcon, pll->reg_base + RK3399_PLLCON(2));
1084
1085         writel_relaxed(HIWORD_UPDATE(rate->dsmpd, RK3399_PLLCON3_DSMPD_MASK,
1086                                             RK3399_PLLCON3_DSMPD_SHIFT),
1087                        pll->reg_base + RK3399_PLLCON(3));
1088
1089         /* set pll power up */
1090         writel(HIWORD_UPDATE(0,
1091                              RK3399_PLLCON3_PWRDOWN, 0),
1092                pll->reg_base + RK3399_PLLCON(3));
1093
1094         /* wait for the pll to lock */
1095         ret = rockchip_rk3399_pll_wait_lock(pll);
1096         if (ret) {
1097                 pr_warn("%s: pll update unsucessful, trying to restore old params\n",
1098                         __func__);
1099                 rockchip_rk3399_pll_set_params(pll, &cur);
1100         }
1101
1102         if (rate_change_remuxed)
1103                 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_NORM);
1104
1105         return ret;
1106 }
1107
1108 static int rockchip_rk3399_pll_set_rate(struct clk_hw *hw, unsigned long drate,
1109                                         unsigned long prate)
1110 {
1111         struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
1112         const struct rockchip_pll_rate_table *rate;
1113         unsigned long old_rate = rockchip_rk3399_pll_recalc_rate(hw, prate);
1114
1115         pr_debug("%s: changing %s from %lu to %lu with a parent rate of %lu\n",
1116                  __func__, __clk_get_name(hw->clk), old_rate, drate, prate);
1117
1118         /* Get required rate settings from table */
1119         rate = rockchip_get_pll_settings(pll, drate);
1120         if (!rate) {
1121                 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
1122                         drate, __clk_get_name(hw->clk));
1123                 return -EINVAL;
1124         }
1125
1126         return rockchip_rk3399_pll_set_params(pll, rate);
1127 }
1128
1129 static int rockchip_rk3399_pll_enable(struct clk_hw *hw)
1130 {
1131         struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
1132
1133         writel(HIWORD_UPDATE(0, RK3399_PLLCON3_PWRDOWN, 0),
1134                pll->reg_base + RK3399_PLLCON(3));
1135
1136         return 0;
1137 }
1138
1139 static void rockchip_rk3399_pll_disable(struct clk_hw *hw)
1140 {
1141         struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
1142
1143         writel(HIWORD_UPDATE(RK3399_PLLCON3_PWRDOWN,
1144                              RK3399_PLLCON3_PWRDOWN, 0),
1145                pll->reg_base + RK3399_PLLCON(3));
1146 }
1147
1148 static int rockchip_rk3399_pll_is_enabled(struct clk_hw *hw)
1149 {
1150         struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
1151         u32 pllcon = readl(pll->reg_base + RK3399_PLLCON(3));
1152
1153         return !(pllcon & RK3399_PLLCON3_PWRDOWN);
1154 }
1155
1156 static void rockchip_rk3399_pll_init(struct clk_hw *hw)
1157 {
1158         struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
1159         const struct rockchip_pll_rate_table *rate;
1160         struct rockchip_pll_rate_table cur;
1161         unsigned long drate;
1162
1163         if (!(pll->flags & ROCKCHIP_PLL_SYNC_RATE))
1164                 return;
1165
1166         drate = clk_hw_get_rate(hw);
1167         rate = rockchip_get_pll_settings(pll, drate);
1168
1169         /* when no rate setting for the current rate, rely on clk_set_rate */
1170         if (!rate)
1171                 return;
1172
1173         rockchip_rk3399_pll_get_params(pll, &cur);
1174
1175         pr_debug("%s: pll %s@%lu: Hz\n", __func__, __clk_get_name(hw->clk),
1176                  drate);
1177         pr_debug("old - fbdiv: %d, postdiv1: %d, refdiv: %d, postdiv2: %d, dsmpd: %d, frac: %d\n",
1178                  cur.fbdiv, cur.postdiv1, cur.refdiv, cur.postdiv2,
1179                  cur.dsmpd, cur.frac);
1180         pr_debug("new - fbdiv: %d, postdiv1: %d, refdiv: %d, postdiv2: %d, dsmpd: %d, frac: %d\n",
1181                  rate->fbdiv, rate->postdiv1, rate->refdiv, rate->postdiv2,
1182                  rate->dsmpd, rate->frac);
1183
1184         if (rate->fbdiv != cur.fbdiv || rate->postdiv1 != cur.postdiv1 ||
1185                 rate->refdiv != cur.refdiv || rate->postdiv2 != cur.postdiv2 ||
1186                 rate->dsmpd != cur.dsmpd || rate->frac != cur.frac) {
1187                 struct clk *parent = clk_get_parent(hw->clk);
1188
1189                 if (!parent) {
1190                         pr_warn("%s: parent of %s not available\n",
1191                                 __func__, __clk_get_name(hw->clk));
1192                         return;
1193                 }
1194
1195                 pr_debug("%s: pll %s: rate params do not match rate table, adjusting\n",
1196                          __func__, __clk_get_name(hw->clk));
1197                 rockchip_rk3399_pll_set_params(pll, rate);
1198         }
1199 }
1200
1201 static const struct clk_ops rockchip_rk3399_pll_clk_norate_ops = {
1202         .recalc_rate = rockchip_rk3399_pll_recalc_rate,
1203         .enable = rockchip_rk3399_pll_enable,
1204         .disable = rockchip_rk3399_pll_disable,
1205         .is_enabled = rockchip_rk3399_pll_is_enabled,
1206 };
1207
1208 static const struct clk_ops rockchip_rk3399_pll_clk_ops = {
1209         .recalc_rate = rockchip_rk3399_pll_recalc_rate,
1210         .round_rate = rockchip_pll_round_rate,
1211         .set_rate = rockchip_rk3399_pll_set_rate,
1212         .enable = rockchip_rk3399_pll_enable,
1213         .disable = rockchip_rk3399_pll_disable,
1214         .is_enabled = rockchip_rk3399_pll_is_enabled,
1215         .init = rockchip_rk3399_pll_init,
1216 };
1217
1218 /*
1219  * Common registering of pll clocks
1220  */
1221
1222 struct clk *rockchip_clk_register_pll(struct rockchip_clk_provider *ctx,
1223                 enum rockchip_pll_type pll_type,
1224                 const char *name, const char *const *parent_names,
1225                 u8 num_parents, int con_offset, int grf_lock_offset,
1226                 int lock_shift, int mode_offset, int mode_shift,
1227                 struct rockchip_pll_rate_table *rate_table,
1228                 unsigned long flags, u8 clk_pll_flags)
1229 {
1230         const char *pll_parents[3];
1231         struct clk_init_data init;
1232         struct rockchip_clk_pll *pll;
1233         struct clk_mux *pll_mux;
1234         struct clk *pll_clk, *mux_clk;
1235         char pll_name[20];
1236
1237         if (num_parents != 2) {
1238                 pr_err("%s: needs two parent clocks\n", __func__);
1239                 return ERR_PTR(-EINVAL);
1240         }
1241
1242         /* name the actual pll */
1243         snprintf(pll_name, sizeof(pll_name), "pll_%s", name);
1244
1245         pll = kzalloc(sizeof(*pll), GFP_KERNEL);
1246         if (!pll)
1247                 return ERR_PTR(-ENOMEM);
1248
1249         /* create the mux on top of the real pll */
1250         pll->pll_mux_ops = &clk_mux_ops;
1251         pll_mux = &pll->pll_mux;
1252         pll_mux->reg = ctx->reg_base + mode_offset;
1253         pll_mux->shift = mode_shift;
1254         if (pll_type == pll_rk3328)
1255                 pll_mux->mask = PLL_RK3328_MODE_MASK;
1256         else
1257                 pll_mux->mask = PLL_MODE_MASK;
1258         pll_mux->flags = 0;
1259         pll_mux->lock = &ctx->lock;
1260         pll_mux->hw.init = &init;
1261
1262         if (pll_type == pll_rk3036 ||
1263             pll_type == pll_rk3066 ||
1264             pll_type == pll_rk3328 ||
1265             pll_type == pll_rk3366 ||
1266             pll_type == pll_rk3399)
1267                 pll_mux->flags |= CLK_MUX_HIWORD_MASK;
1268
1269         /* the actual muxing is xin24m, pll-output, xin32k */
1270         pll_parents[0] = parent_names[0];
1271         pll_parents[1] = pll_name;
1272         pll_parents[2] = parent_names[1];
1273
1274         init.name = name;
1275         init.flags = CLK_SET_RATE_PARENT;
1276         init.ops = pll->pll_mux_ops;
1277         init.parent_names = pll_parents;
1278         init.num_parents = ARRAY_SIZE(pll_parents);
1279
1280         mux_clk = clk_register(NULL, &pll_mux->hw);
1281         if (IS_ERR(mux_clk))
1282                 goto err_mux;
1283
1284         /* now create the actual pll */
1285         init.name = pll_name;
1286
1287         /* keep all plls untouched for now */
1288         init.flags = flags | CLK_IGNORE_UNUSED;
1289
1290         init.parent_names = &parent_names[0];
1291         init.num_parents = 1;
1292
1293         if (rate_table) {
1294                 int len;
1295
1296                 /* find count of rates in rate_table */
1297                 for (len = 0; rate_table[len].rate != 0; )
1298                         len++;
1299
1300                 pll->rate_count = len;
1301                 pll->rate_table = kmemdup(rate_table,
1302                                         pll->rate_count *
1303                                         sizeof(struct rockchip_pll_rate_table),
1304                                         GFP_KERNEL);
1305                 WARN(!pll->rate_table,
1306                         "%s: could not allocate rate table for %s\n",
1307                         __func__, name);
1308         }
1309
1310         switch (pll_type) {
1311         case pll_rk3036:
1312                 if (!pll->rate_table)
1313                         init.ops = &rockchip_rk3036_pll_clk_norate_ops;
1314                 else
1315                         init.ops = &rockchip_rk3036_pll_clk_ops;
1316                 break;
1317         case pll_rk3066:
1318                 if (!pll->rate_table)
1319                         init.ops = &rockchip_rk3066_pll_clk_norate_ops;
1320                 else
1321                         init.ops = &rockchip_rk3066_pll_clk_ops;
1322                 break;
1323         case pll_rk3328:
1324                 if (!pll->rate_table)
1325                         init.ops = &rockchip_rk3036_pll_clk_norate_ops;
1326                 else
1327                         init.ops = &rockchip_rk3036_pll_clk_ops;
1328                 break;
1329         case pll_rk3366:
1330                 if (!pll->rate_table)
1331                         init.ops = &rockchip_rk3366_pll_clk_norate_ops;
1332                 else
1333                         init.ops = &rockchip_rk3366_pll_clk_ops;
1334                 break;
1335         case pll_rk3399:
1336                 if (!pll->rate_table)
1337                         init.ops = &rockchip_rk3399_pll_clk_norate_ops;
1338                 else
1339                         init.ops = &rockchip_rk3399_pll_clk_ops;
1340                 break;
1341         default:
1342                 pr_warn("%s: Unknown pll type for pll clk %s\n",
1343                         __func__, name);
1344         }
1345
1346         pll->hw.init = &init;
1347         pll->type = pll_type;
1348         pll->reg_base = ctx->reg_base + con_offset;
1349         pll->lock_offset = grf_lock_offset;
1350         pll->lock_shift = lock_shift;
1351         pll->flags = clk_pll_flags;
1352         pll->lock = &ctx->lock;
1353         pll->ctx = ctx;
1354
1355         pll_clk = clk_register(NULL, &pll->hw);
1356         if (IS_ERR(pll_clk)) {
1357                 pr_err("%s: failed to register pll clock %s : %ld\n",
1358                         __func__, name, PTR_ERR(pll_clk));
1359                 goto err_pll;
1360         }
1361
1362         return mux_clk;
1363
1364 err_pll:
1365         clk_unregister(mux_clk);
1366         mux_clk = pll_clk;
1367 err_mux:
1368         kfree(pll);
1369         return mux_clk;
1370 }