1 #include <linux/slab.h>
9 //static unsigned long lpj_gpll;
11 #define PLLS_IN_NORM(pll_id) (((cru_readl(RK3188_CRU_MODE_CON)&RK3188_PLL_MODE_MSK(pll_id))\
12 ==(RK3188_PLL_MODE_NORM(pll_id)&RK3188_PLL_MODE_MSK(pll_id)))\
13 &&!(cru_readl(RK3188_PLL_CONS(pll_id,3))&RK3188_PLL_BYPASS))
16 static const struct apll_clk_set apll_table[] = {
17 // (_mhz, nr, nf, no, _periph_div, _aclk_div)
18 _RK3188_APLL_SET_CLKS(2208, 1, 92, 1, 8, 81),
19 _RK3188_APLL_SET_CLKS(2184, 1, 91, 1, 8, 81),
20 _RK3188_APLL_SET_CLKS(2160, 1, 90, 1, 8, 81),
21 _RK3188_APLL_SET_CLKS(2136, 1, 89, 1, 8, 81),
22 _RK3188_APLL_SET_CLKS(2112, 1, 88, 1, 8, 81),
23 _RK3188_APLL_SET_CLKS(2088, 1, 87, 1, 8, 81),
24 _RK3188_APLL_SET_CLKS(2064, 1, 86, 1, 8, 81),
25 _RK3188_APLL_SET_CLKS(2040, 1, 85, 1, 8, 81),
26 _RK3188_APLL_SET_CLKS(2016, 1, 84, 1, 8, 81),
27 _RK3188_APLL_SET_CLKS(1992, 1, 83, 1, 8, 81),
28 _RK3188_APLL_SET_CLKS(1968, 1, 82, 1, 8, 81),
29 _RK3188_APLL_SET_CLKS(1944, 1, 81, 1, 8, 81),
30 _RK3188_APLL_SET_CLKS(1920, 1, 80, 1, 8, 81),
31 _RK3188_APLL_SET_CLKS(1896, 1, 79, 1, 8, 81),
32 _RK3188_APLL_SET_CLKS(1872, 1, 78, 1, 8, 81),
33 _RK3188_APLL_SET_CLKS(1848, 1, 77, 1, 8, 81),
34 _RK3188_APLL_SET_CLKS(1824, 1, 76, 1, 8, 81),
35 _RK3188_APLL_SET_CLKS(1800, 1, 75, 1, 8, 81),
36 _RK3188_APLL_SET_CLKS(1776, 1, 74, 1, 8, 81),
37 _RK3188_APLL_SET_CLKS(1752, 1, 73, 1, 8, 81),
38 _RK3188_APLL_SET_CLKS(1728, 1, 72, 1, 8, 81),
39 _RK3188_APLL_SET_CLKS(1704, 1, 71, 1, 8, 81),
40 _RK3188_APLL_SET_CLKS(1680, 1, 70, 1, 8, 41),
41 _RK3188_APLL_SET_CLKS(1656, 1, 69, 1, 8, 41),
42 _RK3188_APLL_SET_CLKS(1632, 1, 68, 1, 8, 41),
43 _RK3188_APLL_SET_CLKS(1608, 1, 67, 1, 8, 41),
44 _RK3188_APLL_SET_CLKS(1560, 1, 65, 1, 8, 41),
45 _RK3188_APLL_SET_CLKS(1512, 1, 63, 1, 8, 41),
46 _RK3188_APLL_SET_CLKS(1488, 1, 62, 1, 8, 41),
47 _RK3188_APLL_SET_CLKS(1464, 1, 61, 1, 8, 41),
48 _RK3188_APLL_SET_CLKS(1440, 1, 60, 1, 8, 41),
49 _RK3188_APLL_SET_CLKS(1416, 1, 59, 1, 8, 41),
50 _RK3188_APLL_SET_CLKS(1392, 1, 58, 1, 8, 41),
51 _RK3188_APLL_SET_CLKS(1368, 1, 57, 1, 8, 41),
52 _RK3188_APLL_SET_CLKS(1344, 1, 56, 1, 8, 41),
53 _RK3188_APLL_SET_CLKS(1320, 1, 55, 1, 8, 41),
54 _RK3188_APLL_SET_CLKS(1296, 1, 54, 1, 8, 41),
55 _RK3188_APLL_SET_CLKS(1272, 1, 53, 1, 8, 41),
56 _RK3188_APLL_SET_CLKS(1248, 1, 52, 1, 8, 41),
57 _RK3188_APLL_SET_CLKS(1224, 1, 51, 1, 8, 41),
58 _RK3188_APLL_SET_CLKS(1200, 1, 50, 1, 8, 41),
59 _RK3188_APLL_SET_CLKS(1176, 1, 49, 1, 8, 41),
60 _RK3188_APLL_SET_CLKS(1128, 1, 47, 1, 8, 41),
61 _RK3188_APLL_SET_CLKS(1104, 1, 46, 1, 8, 41),
62 _RK3188_APLL_SET_CLKS(1008, 1, 84, 2, 8, 41),
63 _RK3188_APLL_SET_CLKS(912, 1, 76, 2, 8, 41),
64 _RK3188_APLL_SET_CLKS(888, 1, 74, 2, 8, 41),
65 _RK3188_APLL_SET_CLKS(816, 1, 68, 2, 8, 41),
66 _RK3188_APLL_SET_CLKS(792, 1, 66, 2, 8, 41),
67 _RK3188_APLL_SET_CLKS(696, 1, 58, 2, 8, 41),
68 _RK3188_APLL_SET_CLKS(600, 1, 50, 2, 4, 41),
69 _RK3188_APLL_SET_CLKS(552, 1, 92, 4, 4, 41),
70 _RK3188_APLL_SET_CLKS(504, 1, 84, 4, 4, 41),
71 _RK3188_APLL_SET_CLKS(408, 1, 68, 4, 4, 21),
72 _RK3188_APLL_SET_CLKS(312, 1, 52, 4, 2, 21),
73 _RK3188_APLL_SET_CLKS(252, 1, 84, 8, 2, 21),
74 _RK3188_APLL_SET_CLKS(216, 1, 72, 8, 2, 21),
75 _RK3188_APLL_SET_CLKS(126, 1, 84, 16, 2, 11),
76 _RK3188_APLL_SET_CLKS(48, 1, 32, 16, 2, 11),
77 _RK3188_APLL_SET_CLKS(0, 1, 32, 16, 2, 11),
80 static const struct pll_clk_set pll_com_table[] = {
81 _RK3188_PLL_SET_CLKS(1200000, 1, 50, 1),
82 _RK3188_PLL_SET_CLKS(1188000, 2, 99, 1),
83 _RK3188_PLL_SET_CLKS(891000, 8, 594, 2),
84 _RK3188_PLL_SET_CLKS(768000, 1, 64, 2),
85 _RK3188_PLL_SET_CLKS(594000, 2, 198, 4),
86 _RK3188_PLL_SET_CLKS(408000, 1, 68, 4),
87 _RK3188_PLL_SET_CLKS(384000, 2, 128, 4),
88 _RK3188_PLL_SET_CLKS(360000, 1, 60, 4),
89 _RK3188_PLL_SET_CLKS(300000, 1, 50, 4),
90 _RK3188_PLL_SET_CLKS(297000, 2, 198, 8),
91 _RK3188_PLL_SET_CLKS(148500, 2, 99, 8),
92 _RK3188_PLL_SET_CLKS(0, 0, 0, 0),
95 static void pll_wait_lock(int pll_idx)
97 u32 pll_state[4] = {1, 0, 2, 3};
98 u32 bit = 0x20u << pll_state[pll_idx];
101 if (grf_readl(RK3188_GRF_SOC_STATUS0) & bit)
107 clk_err("PLL_ID=%d\npll_con0=%08x\npll_con1=%08x\n"
108 "pll_con2=%08x\npll_con3=%08x\n",
110 cru_readl(RK3188_PLL_CONS(pll_idx, 0)),
111 cru_readl(RK3188_PLL_CONS(pll_idx, 1)),
112 cru_readl(RK3188_PLL_CONS(pll_idx, 2)),
113 cru_readl(RK3188_PLL_CONS(pll_idx, 3)));
115 clk_err("wait pll bit 0x%x time out!\n", bit);
122 static unsigned long clk_pll_recalc_rate(struct clk_hw *hw,
123 unsigned long parent_rate)
125 struct clk_pll *pll = to_clk_pll(hw);
129 if (PLLS_IN_NORM(pll_id)) {
130 u32 pll_con0 = cru_readl(RK3188_PLL_CONS(pll_id, 0));
131 u32 pll_con1 = cru_readl(RK3188_PLL_CONS(pll_id, 1));
133 u64 rate64 = (u64)parent_rate * RK3188_PLL_NF(pll_con1);
135 do_div(rate64, RK3188_PLL_NR(pll_con0));
136 do_div(rate64, RK3188_PLL_NO(pll_con0));
141 clk_debug("pll id=%d slow mode\n", pll_id);
144 clk_debug("pll id=%d, recalc rate =%lu\n", pll->id, rate);
150 /* get rate that is most close to target */
151 static const struct apll_clk_set *apll_get_best_set(unsigned long rate,
152 const struct apll_clk_set *table)
154 const struct apll_clk_set *ps, *pt;
158 if (pt->rate == rate) {
163 if ((pt->rate > rate || (rate - pt->rate < ps->rate - rate)))
173 /* get rate that is most close to target */
174 static const struct pll_clk_set *pll_com_get_best_set(unsigned long rate,
175 const struct pll_clk_set *table)
177 const struct pll_clk_set *ps, *pt;
181 if (pt->rate == rate) {
186 if ((pt->rate > rate || (rate - pt->rate < ps->rate - rate)))
196 static long clk_apll_round_rate(struct clk_hw *hw, unsigned long rate,
197 unsigned long *prate)
199 return (apll_get_best_set(rate, apll_table)->rate);
202 static long clk_pll_com_round_rate(struct clk_hw *hw, unsigned long rate,
203 unsigned long *prate)
205 return (pll_com_get_best_set(rate, pll_com_table)->rate);
208 static long clk_pll_round_rate(struct clk_hw *hw, unsigned long rate,
209 unsigned long *prate)
211 struct clk_pll *pll = to_clk_pll(hw);
212 struct clk *parent = __clk_get_parent(hw->clk);
215 if (parent && (rate==__clk_get_rate(parent))) {
216 clk_debug("pll id=%d round rate=%lu equal to parent rate\n",
222 case RK3188_APLL_ID: {
223 rate_out = clk_apll_round_rate(hw, rate, prate);
227 rate_out = clk_pll_com_round_rate(hw, rate, prate);
236 static int _pll_clk_set_rate(struct pll_clk_set *clk_set, u8 pll_id,
239 unsigned long flags = 0;
242 clk_debug("_pll_clk_set_rate start!\n");
245 spin_lock_irqsave(lock, flags);
248 cru_writel(RK3188_PLL_MODE_SLOW(pll_id), RK3188_CRU_MODE_CON);
249 cru_writel((0x1<<(16+1))|(0x1<<1), RK3188_PLL_CONS(pll_id, 3));
256 cru_writel(clk_set->pllcon0, RK3188_PLL_CONS(pll_id, 0));
257 cru_writel(clk_set->pllcon1, RK3188_PLL_CONS(pll_id, 1));
261 cru_writel((0x1<<(16+1)), RK3188_PLL_CONS(pll_id, 3));
263 pll_wait_lock(pll_id);
266 cru_writel(RK3188_PLL_MODE_NORM(pll_id), RK3188_CRU_MODE_CON);
269 spin_unlock_irqrestore(lock, flags);
271 clk_debug("pll id=%d, dump reg: con0=0x%08x, con1=0x%08x, mode=0x%08x\n",
273 cru_readl(RK3188_PLL_CONS(pll_id,0)),
274 cru_readl(RK3188_PLL_CONS(pll_id,1)),
275 cru_readl(RK3188_CRU_MODE_CON));
277 clk_debug("_pll_clk_set_rate end!\n");
282 static int clk_pll_com_set_rate(struct clk_hw *hw, unsigned long rate,
283 unsigned long parent_rate)
285 struct clk_pll *pll = to_clk_pll(hw);
286 struct pll_clk_set *clk_set = (struct pll_clk_set *)(pll_com_table);
290 if (rate == parent_rate) {
291 clk_debug("pll id=%d set rate=%lu equal to parent rate\n",
293 cru_writel(RK3188_PLL_MODE_SLOW(pll->id), RK3188_CRU_MODE_CON);
294 cru_writel((0x1 << (16+1)) | (0x1<<1), RK3188_PLL_CONS(pll->id, 3));
295 clk_debug("pll id=%d enter slow mode, set rate OK!\n", pll->id);
299 while(clk_set->rate) {
300 if (clk_set->rate == rate) {
306 if (clk_set->rate == rate) {
307 ret = _pll_clk_set_rate(clk_set, pll->id, pll->lock);
308 clk_debug("pll id=%d set rate=%lu OK!\n", pll->id, rate);
310 clk_err("pll id=%d is no corresponding rate=%lu\n",
321 #define USE_ARM_GPLL 1
323 static int clk_apll_set_rate(struct clk_hw *hw, unsigned long rate,
324 unsigned long parent_rate)
326 struct clk_pll *pll = to_clk_pll(hw);
327 struct clk *clk = hw->clk;
328 struct clk *arm_gpll = __clk_lookup("clk_arm_gpll");
329 unsigned long arm_gpll_rate;
330 const struct apll_clk_set *ps;
331 u32 old_aclk_div = 0, new_aclk_div = 0;
337 if (rate == parent_rate) {
338 clk_debug("pll id=%d set rate=%lu equal to parent rate\n",
340 cru_writel(RK3188_PLL_MODE_SLOW(pll->id), RK3188_CRU_MODE_CON);
341 cru_writel((0x1 << (16+1)) | (0x1<<1), RK3188_PLL_CONS(pll->id, 3));
342 clk_debug("pll id=%d enter slow mode, set rate OK!\n", pll->id);
350 /* prepare arm_gpll before reparent clk_core to it */
352 clk_err("clk arm_gpll is NULL!\n");
356 /* In rk3188, arm_gpll and cpu_gpll share a same gate,
357 * and aclk_cpu selects cpu_gpll as parent, thus this
358 * gate must keep enabled.
361 if (clk_prepare(arm_gpll)) {
362 clk_err("fail to prepare arm_gpll path\n");
363 clk_unprepare(arm_gpll);
367 if (clk_enable(arm_gpll)) {
368 clk_err("fail to enable arm_gpll path\n");
369 clk_disable(arm_gpll);
370 clk_unprepare(arm_gpll);
375 arm_gpll_rate = __clk_get_rate(arm_gpll);
376 temp_div = DIV_ROUND_UP(arm_gpll_rate, __clk_get_rate(clk));
377 temp_div = (temp_div == 0) ? 1 : temp_div;
378 if (temp_div > RK3188_CORE_CLK_MAX_DIV) {
379 clk_debug("temp_div %d > max_div %d\n", temp_div,
380 RK3188_CORE_CLK_MAX_DIV);
381 clk_debug("can't get rate %lu from arm_gpll rate %lu\n",
382 __clk_get_rate(clk), arm_gpll_rate);
383 //clk_disable(arm_gpll);
384 //clk_unprepare(arm_gpll);
388 local_irq_save(flags);
390 /* firstly set div, then select arm_gpll path */
391 cru_writel(RK3188_CORE_CLK_DIV_W_MSK|RK3188_CORE_CLK_DIV(temp_div), RK3188_CRU_CLKSELS_CON(0));
392 cru_writel(RK3188_CORE_SEL_PLL_W_MSK|RK3188_CORE_SEL_GPLL, RK3188_CRU_CLKSELS_CON(0));
395 //loops_per_jiffy = lpj_gpll / temp_div;
398 local_irq_restore(flags);
400 clk_debug("temp select arm_gpll path, get rate %lu\n",
401 arm_gpll_rate/temp_div);
402 clk_debug("from arm_gpll rate %lu, temp_div %d\n", arm_gpll_rate,
406 ps = apll_get_best_set(rate, apll_table);
407 clk_debug("apll will set rate %lu\n", ps->rate);
408 clk_debug("table con:%08x,%08x,%08x, sel:%08x,%08x\n",
409 ps->pllcon0, ps->pllcon1, ps->pllcon2,
410 ps->clksel0, ps->clksel1);
412 local_irq_save(flags);
414 /* If core src don't select gpll, apll need to enter slow mode
419 cru_writel(RK3188_PLL_MODE_SLOW(pll->id), RK3188_CRU_MODE_CON);
422 cru_writel((0x1<<(16+1))|(0x1<<1), RK3188_PLL_CONS(pll->id, 3));
429 cru_writel(ps->pllcon0, RK3188_PLL_CONS(pll->id, 0));
430 cru_writel(ps->pllcon1, RK3188_PLL_CONS(pll->id, 1));
434 /* PLL power up and wait for locked */
435 cru_writel((0x1<<(16+1)), RK3188_PLL_CONS(pll->id, 3));
436 pll_wait_lock(pll->id);
438 old_aclk_div = RK3188_GET_CORE_ACLK_VAL(cru_readl(RK3188_CRU_CLKSELS_CON(1)) &
439 RK3188_CORE_ACLK_MSK);
440 new_aclk_div = RK3188_GET_CORE_ACLK_VAL(ps->clksel1 & RK3188_CORE_ACLK_MSK);
442 if (new_aclk_div >= old_aclk_div) {
443 cru_writel(ps->clksel0, RK3188_CRU_CLKSELS_CON(0));
444 cru_writel(ps->clksel1, RK3188_CRU_CLKSELS_CON(1));
447 /* PLL return from slow mode */
450 cru_writel(RK3188_PLL_MODE_NORM(pll->id), RK3188_CRU_MODE_CON);
452 /* reparent to apll, and set div to 1 */
454 cru_writel(RK3188_CORE_SEL_PLL_W_MSK|RK3188_CORE_SEL_APLL, RK3188_CRU_CLKSELS_CON(0));
455 cru_writel(RK3188_CORE_CLK_DIV_W_MSK|RK3188_CORE_CLK_DIV(1), RK3188_CRU_CLKSELS_CON(0));
458 if (old_aclk_div > new_aclk_div) {
459 cru_writel(ps->clksel0, RK3188_CRU_CLKSELS_CON(0));
460 cru_writel(ps->clksel1, RK3188_CRU_CLKSELS_CON(1));
463 //loops_per_jiffy = ps->lpj;
466 local_irq_restore(flags);
470 //clk_disable(arm_gpll);
471 //clk_unprepare(arm_gpll);
474 //clk_debug("apll set loops_per_jiffy =%lu\n", loops_per_jiffy);
476 clk_debug("apll set rate %lu, con(%x,%x,%x,%x), sel(%x,%x)\n",
478 cru_readl(RK3188_PLL_CONS(pll->id, 0)),cru_readl(RK3188_PLL_CONS(pll->id, 1)),
479 cru_readl(RK3188_PLL_CONS(pll->id, 2)),cru_readl(RK3188_PLL_CONS(pll->id, 3)),
480 cru_readl(RK3188_CRU_CLKSELS_CON(0)),cru_readl(RK3188_CRU_CLKSELS_CON(1)));
485 static int clk_dpll_set_rate(struct clk_hw *hw, unsigned long rate,
486 unsigned long parent_rate)
491 static int clk_gpll_set_rate(struct clk_hw *hw, unsigned long rate,
492 unsigned long parent_rate)
494 int ret = clk_pll_com_set_rate(hw, rate, parent_rate);
497 // lpj_gpll = CLK_LOOPS_RECALC(clk_pll_recalc_rate(hw, parent_rate));
502 static int clk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
503 unsigned long parent_rate)
505 struct clk_pll *pll = to_clk_pll(hw);
509 case RK3188_APLL_ID: {
510 ret = clk_apll_set_rate(hw, rate, parent_rate);
513 case RK3188_DPLL_ID: {
514 ret = clk_dpll_set_rate(hw, rate, parent_rate);
517 case RK3188_GPLL_ID: {
518 ret = clk_gpll_set_rate(hw, rate, parent_rate);
522 ret = clk_pll_com_set_rate(hw, rate, parent_rate);
530 const struct clk_ops clk_pll_ops = {
531 .recalc_rate = clk_pll_recalc_rate,
532 .round_rate = clk_pll_round_rate,
533 .set_rate = clk_pll_set_rate,
536 EXPORT_SYMBOL_GPL(clk_pll_ops);
539 struct clk *rk_clk_register_pll(struct device *dev, const char *name,
540 const char *parent_name, unsigned long flags, void __iomem *reg,
541 u32 width, u8 id, spinlock_t *lock)
545 struct clk_init_data init;
548 clk_debug("%s: pll name = %s, id = %d, register start!\n",__func__,name,id);
551 if(id >= END_PLL_ID){
552 clk_err("%s: PLL id = %d >= END_PLL_ID = %d\n", __func__,
554 return ERR_PTR(-EINVAL);
558 /* allocate the pll */
559 pll = kzalloc(sizeof(struct clk_pll), GFP_KERNEL);
561 clk_err("%s: could not allocate pll clk\n", __func__);
562 return ERR_PTR(-ENOMEM);
567 init.parent_names = (parent_name ? &parent_name: NULL);
568 init.num_parents = (parent_name ? 1 : 0);
569 init.ops = &clk_pll_ops;
571 /* struct clk_pll assignments */
576 pll->hw.init = &init;
578 /* register the clock */
579 clk = clk_register(dev, &pll->hw);
584 clk_debug("%s: pll name = %s, id = %d, register finish!\n",__func__,name,id);