1 #include <linux/slab.h>
3 #include <linux/rockchip/cpu.h>
9 static const struct pll_clk_set rk3188_pll_com_table[] = {
10 _RK3188_PLL_SET_CLKS(1250000, 12, 625, 1),
11 _RK3188_PLL_SET_CLKS(1200000, 1, 50, 1),
12 _RK3188_PLL_SET_CLKS(1188000, 2, 99, 1),
13 _RK3188_PLL_SET_CLKS(891000, 8, 594, 2),
14 _RK3188_PLL_SET_CLKS(768000, 1, 64, 2),
15 _RK3188_PLL_SET_CLKS(594000, 2, 198, 4),
16 _RK3188_PLL_SET_CLKS(500000, 3, 250, 4),
17 _RK3188_PLL_SET_CLKS(408000, 1, 68, 4),
18 _RK3188_PLL_SET_CLKS(396000, 1, 66, 4),
19 _RK3188_PLL_SET_CLKS(384000, 2, 128, 4),
20 _RK3188_PLL_SET_CLKS(360000, 1, 60, 4),
21 _RK3188_PLL_SET_CLKS(300000, 1, 50, 4),
22 _RK3188_PLL_SET_CLKS(297000, 2, 198, 8),
23 _RK3188_PLL_SET_CLKS(148500, 2, 99, 8),
24 _RK3188_PLL_SET_CLKS(0, 0, 0, 0),
27 static const struct pll_clk_set rk3188plus_pll_com_table[] = {
28 _RK3188PLUS_PLL_SET_CLKS(1250000, 12, 625, 1),
29 _RK3188PLUS_PLL_SET_CLKS(1200000, 1, 50, 1),
30 _RK3188PLUS_PLL_SET_CLKS(1188000, 2, 99, 1),
31 _RK3188PLUS_PLL_SET_CLKS(891000, 8, 594, 2),
32 _RK3188PLUS_PLL_SET_CLKS(768000, 1, 64, 2),
33 _RK3188PLUS_PLL_SET_CLKS(594000, 2, 198, 4),
34 _RK3188PLUS_PLL_SET_CLKS(576000, 1, 48, 2),
35 _RK3188PLUS_PLL_SET_CLKS(500000, 3, 250, 4),
36 _RK3188PLUS_PLL_SET_CLKS(408000, 1, 68, 4),
37 _RK3188PLUS_PLL_SET_CLKS(400000, 3, 200, 4),
38 _RK3188PLUS_PLL_SET_CLKS(396000, 1, 66, 4),
39 _RK3188PLUS_PLL_SET_CLKS(384000, 2, 128, 4),
40 _RK3188PLUS_PLL_SET_CLKS(360000, 1, 60, 4),
41 _RK3188PLUS_PLL_SET_CLKS(300000, 1, 50, 4),
42 _RK3188PLUS_PLL_SET_CLKS(297000, 2, 198, 8),
43 _RK3188PLUS_PLL_SET_CLKS(148500, 2, 99, 8),
44 _RK3188PLUS_PLL_SET_CLKS(0, 0, 0, 0),
47 static const struct apll_clk_set rk3188_apll_table[] = {
48 // (_mhz, nr, nf, no, _periph_div, _aclk_div)
49 _RK3188_APLL_SET_CLKS(2208, 1, 92, 1, 8, 81),
50 _RK3188_APLL_SET_CLKS(2184, 1, 91, 1, 8, 81),
51 _RK3188_APLL_SET_CLKS(2160, 1, 90, 1, 8, 81),
52 _RK3188_APLL_SET_CLKS(2136, 1, 89, 1, 8, 81),
53 _RK3188_APLL_SET_CLKS(2112, 1, 88, 1, 8, 81),
54 _RK3188_APLL_SET_CLKS(2088, 1, 87, 1, 8, 81),
55 _RK3188_APLL_SET_CLKS(2064, 1, 86, 1, 8, 81),
56 _RK3188_APLL_SET_CLKS(2040, 1, 85, 1, 8, 81),
57 _RK3188_APLL_SET_CLKS(2016, 1, 84, 1, 8, 81),
58 _RK3188_APLL_SET_CLKS(1992, 1, 83, 1, 8, 81),
59 _RK3188_APLL_SET_CLKS(1968, 1, 82, 1, 8, 81),
60 _RK3188_APLL_SET_CLKS(1944, 1, 81, 1, 8, 81),
61 _RK3188_APLL_SET_CLKS(1920, 1, 80, 1, 8, 81),
62 _RK3188_APLL_SET_CLKS(1896, 1, 79, 1, 8, 81),
63 _RK3188_APLL_SET_CLKS(1872, 1, 78, 1, 8, 81),
64 _RK3188_APLL_SET_CLKS(1848, 1, 77, 1, 8, 81),
65 _RK3188_APLL_SET_CLKS(1824, 1, 76, 1, 8, 81),
66 _RK3188_APLL_SET_CLKS(1800, 1, 75, 1, 8, 81),
67 _RK3188_APLL_SET_CLKS(1776, 1, 74, 1, 8, 81),
68 _RK3188_APLL_SET_CLKS(1752, 1, 73, 1, 8, 81),
69 _RK3188_APLL_SET_CLKS(1728, 1, 72, 1, 8, 81),
70 _RK3188_APLL_SET_CLKS(1704, 1, 71, 1, 8, 81),
71 _RK3188_APLL_SET_CLKS(1680, 1, 70, 1, 8, 41),
72 _RK3188_APLL_SET_CLKS(1656, 1, 69, 1, 8, 41),
73 _RK3188_APLL_SET_CLKS(1632, 1, 68, 1, 8, 41),
74 _RK3188_APLL_SET_CLKS(1608, 1, 67, 1, 8, 41),
75 _RK3188_APLL_SET_CLKS(1560, 1, 65, 1, 8, 41),
76 _RK3188_APLL_SET_CLKS(1512, 1, 63, 1, 8, 41),
77 _RK3188_APLL_SET_CLKS(1488, 1, 62, 1, 8, 41),
78 _RK3188_APLL_SET_CLKS(1464, 1, 61, 1, 8, 41),
79 _RK3188_APLL_SET_CLKS(1440, 1, 60, 1, 8, 41),
80 _RK3188_APLL_SET_CLKS(1416, 1, 59, 1, 8, 41),
81 _RK3188_APLL_SET_CLKS(1392, 1, 58, 1, 8, 41),
82 _RK3188_APLL_SET_CLKS(1368, 1, 57, 1, 8, 41),
83 _RK3188_APLL_SET_CLKS(1344, 1, 56, 1, 8, 41),
84 _RK3188_APLL_SET_CLKS(1320, 1, 55, 1, 8, 41),
85 _RK3188_APLL_SET_CLKS(1296, 1, 54, 1, 8, 41),
86 _RK3188_APLL_SET_CLKS(1272, 1, 53, 1, 8, 41),
87 _RK3188_APLL_SET_CLKS(1248, 1, 52, 1, 8, 41),
88 _RK3188_APLL_SET_CLKS(1224, 1, 51, 1, 8, 41),
89 _RK3188_APLL_SET_CLKS(1200, 1, 50, 1, 8, 41),
90 _RK3188_APLL_SET_CLKS(1176, 1, 49, 1, 8, 41),
91 _RK3188_APLL_SET_CLKS(1128, 1, 47, 1, 8, 41),
92 _RK3188_APLL_SET_CLKS(1104, 1, 46, 1, 8, 41),
93 _RK3188_APLL_SET_CLKS(1008, 1, 84, 2, 8, 41),
94 _RK3188_APLL_SET_CLKS(912, 1, 76, 2, 8, 41),
95 _RK3188_APLL_SET_CLKS(888, 1, 74, 2, 8, 41),
96 _RK3188_APLL_SET_CLKS(816, 1, 68, 2, 8, 41),
97 _RK3188_APLL_SET_CLKS(792, 1, 66, 2, 8, 41),
98 _RK3188_APLL_SET_CLKS(696, 1, 58, 2, 8, 41),
99 _RK3188_APLL_SET_CLKS(600, 1, 50, 2, 4, 41),
100 _RK3188_APLL_SET_CLKS(552, 1, 92, 4, 4, 41),
101 _RK3188_APLL_SET_CLKS(504, 1, 84, 4, 4, 41),
102 _RK3188_APLL_SET_CLKS(408, 1, 68, 4, 4, 21),
103 _RK3188_APLL_SET_CLKS(312, 1, 52, 4, 2, 21),
104 _RK3188_APLL_SET_CLKS(252, 1, 84, 8, 2, 21),
105 _RK3188_APLL_SET_CLKS(216, 1, 72, 8, 2, 21),
106 _RK3188_APLL_SET_CLKS(126, 1, 84, 16, 2, 11),
107 _RK3188_APLL_SET_CLKS(48, 1, 32, 16, 2, 11),
108 _RK3188_APLL_SET_CLKS(0, 1, 32, 16, 2, 11),
111 static const struct apll_clk_set rk3288_apll_table[] = {
112 // (_mhz, nr, nf, no, l2ram, m0, mp, atclk, pclk_dbg)
113 _RK3288_APLL_SET_CLKS(2208, 1, 92, 1, 2, 2, 4, 4, 4),
114 _RK3288_APLL_SET_CLKS(2184, 1, 91, 1, 2, 2, 4, 4, 4),
115 _RK3288_APLL_SET_CLKS(2160, 1, 90, 1, 2, 2, 4, 4, 4),
116 _RK3288_APLL_SET_CLKS(2136, 1, 89, 1, 2, 2, 4, 4, 4),
117 _RK3288_APLL_SET_CLKS(2112, 1, 88, 1, 2, 2, 4, 4, 4),
118 _RK3288_APLL_SET_CLKS(2088, 1, 87, 1, 2, 2, 4, 4, 4),
119 _RK3288_APLL_SET_CLKS(2064, 1, 86, 1, 2, 2, 4, 4, 4),
120 _RK3288_APLL_SET_CLKS(2040, 1, 85, 1, 2, 2, 4, 4, 4),
121 _RK3288_APLL_SET_CLKS(2016, 1, 84, 1, 2, 2, 4, 4, 4),
122 _RK3288_APLL_SET_CLKS(1992, 1, 83, 1, 2, 2, 4, 4, 4),
123 _RK3288_APLL_SET_CLKS(1968, 1, 82, 1, 2, 2, 4, 4, 4),
124 _RK3288_APLL_SET_CLKS(1944, 1, 81, 1, 2, 2, 4, 4, 4),
125 _RK3288_APLL_SET_CLKS(1920, 1, 80, 1, 2, 2, 4, 4, 4),
126 _RK3288_APLL_SET_CLKS(1896, 1, 79, 1, 2, 2, 4, 4, 4),
127 _RK3288_APLL_SET_CLKS(1872, 1, 78, 1, 2, 2, 4, 4, 4),
128 _RK3288_APLL_SET_CLKS(1848, 1, 77, 1, 2, 2, 4, 4, 4),
129 _RK3288_APLL_SET_CLKS(1824, 1, 76, 1, 2, 2, 4, 4, 4),
130 _RK3288_APLL_SET_CLKS(1800, 1, 75, 1, 2, 2, 4, 4, 4),
131 _RK3288_APLL_SET_CLKS(1776, 1, 74, 1, 2, 2, 4, 4, 4),
132 _RK3288_APLL_SET_CLKS(1752, 1, 73, 1, 2, 2, 4, 4, 4),
133 _RK3288_APLL_SET_CLKS(1728, 1, 72, 1, 2, 2, 4, 4, 4),
134 _RK3288_APLL_SET_CLKS(1704, 1, 71, 1, 2, 2, 4, 4, 4),
135 _RK3288_APLL_SET_CLKS(1680, 1, 70, 1, 2, 2, 4, 4, 4),
136 _RK3288_APLL_SET_CLKS(1656, 1, 69, 1, 2, 2, 4, 4, 4),
137 _RK3288_APLL_SET_CLKS(1632, 1, 68, 1, 2, 2, 4, 4, 4),
138 _RK3288_APLL_SET_CLKS(1608, 1, 67, 1, 2, 2, 4, 4, 4),
139 _RK3288_APLL_SET_CLKS(1560, 1, 65, 1, 2, 2, 4, 4, 4),
140 _RK3288_APLL_SET_CLKS(1512, 1, 63, 1, 2, 2, 4, 4, 4),
141 _RK3288_APLL_SET_CLKS(1488, 1, 62, 1, 2, 2, 4, 4, 4),
142 _RK3288_APLL_SET_CLKS(1464, 1, 61, 1, 2, 2, 4, 4, 4),
143 _RK3288_APLL_SET_CLKS(1440, 1, 60, 1, 2, 2, 4, 4, 4),
144 _RK3288_APLL_SET_CLKS(1416, 1, 59, 1, 2, 2, 4, 4, 4),
145 _RK3288_APLL_SET_CLKS(1392, 1, 58, 1, 2, 2, 4, 4, 4),
146 _RK3288_APLL_SET_CLKS(1368, 1, 57, 1, 2, 2, 4, 4, 4),
147 _RK3288_APLL_SET_CLKS(1344, 1, 56, 1, 2, 2, 4, 4, 4),
148 _RK3288_APLL_SET_CLKS(1320, 1, 55, 1, 2, 2, 4, 4, 4),
149 _RK3288_APLL_SET_CLKS(1296, 1, 54, 1, 2, 2, 4, 4, 4),
150 _RK3288_APLL_SET_CLKS(1272, 1, 53, 1, 2, 2, 4, 4, 4),
151 _RK3288_APLL_SET_CLKS(1248, 1, 52, 1, 2, 2, 4, 4, 4),
152 _RK3288_APLL_SET_CLKS(1224, 1, 51, 1, 2, 2, 4, 4, 4),
153 _RK3288_APLL_SET_CLKS(1200, 1, 50, 1, 2, 2, 4, 4, 4),
154 _RK3288_APLL_SET_CLKS(1176, 1, 49, 1, 2, 2, 4, 4, 4),
155 _RK3288_APLL_SET_CLKS(1128, 1, 47, 1, 2, 2, 4, 4, 4),
156 _RK3288_APLL_SET_CLKS(1104, 1, 46, 1, 2, 2, 4, 4, 4),
157 _RK3288_APLL_SET_CLKS(1008, 1, 84, 2, 2, 2, 4, 4, 4),
158 _RK3288_APLL_SET_CLKS(912, 1, 76, 2, 2, 2, 4, 4, 4),
159 _RK3288_APLL_SET_CLKS(888, 1, 74, 2, 2, 2, 4, 4, 4),
160 _RK3288_APLL_SET_CLKS(816, 1, 68, 2, 2, 2, 4, 4, 4),
161 _RK3288_APLL_SET_CLKS(792, 1, 66, 2, 2, 2, 4, 4, 4),
162 _RK3288_APLL_SET_CLKS(696, 1, 58, 2, 2, 2, 4, 4, 4),
163 _RK3288_APLL_SET_CLKS(672, 1, 56, 2, 2, 2, 4, 4, 4),
164 _RK3288_APLL_SET_CLKS(648, 1, 54, 2, 2, 2, 4, 4, 4),
165 _RK3288_APLL_SET_CLKS(624, 1, 52, 2, 2, 2, 4, 4, 4),
166 _RK3288_APLL_SET_CLKS(600, 1, 50, 2, 2, 2, 4, 4, 4),
167 _RK3288_APLL_SET_CLKS(576, 1, 48, 2, 2, 2, 4, 4, 4),
168 _RK3288_APLL_SET_CLKS(552, 1, 92, 4, 2, 2, 4, 4, 4),
169 _RK3288_APLL_SET_CLKS(528, 1, 88, 4, 2, 2, 4, 4, 4),
170 _RK3288_APLL_SET_CLKS(504, 1, 84, 4, 2, 2, 4, 4, 4),
171 _RK3288_APLL_SET_CLKS(480, 1, 80, 4, 2, 2, 4, 4, 4),
172 _RK3288_APLL_SET_CLKS(456, 1, 76, 4, 2, 2, 4, 4, 4),
173 _RK3288_APLL_SET_CLKS(408, 1, 68, 4, 2, 2, 4, 4, 4),
174 _RK3288_APLL_SET_CLKS(312, 1, 52, 4, 2, 2, 4, 4, 4),
175 _RK3288_APLL_SET_CLKS(252, 1, 84, 8, 2, 2, 4, 4, 4),
176 _RK3288_APLL_SET_CLKS(216, 1, 72, 8, 2, 2, 4, 4, 4),
177 _RK3288_APLL_SET_CLKS(126, 2, 84, 8, 2, 2, 4, 4, 4),
178 _RK3288_APLL_SET_CLKS(48, 2, 32, 8, 2, 2, 4, 4, 4),
179 _RK3288_APLL_SET_CLKS(0, 1, 32, 16, 2, 2, 4, 4, 4),
182 static const struct apll_clk_set rk3036_apll_table[] = {
183 _RK3036_APLL_SET_CLKS(1608, 1, 67, 1, 1, 1, 0, 81),
184 _RK3036_APLL_SET_CLKS(1584, 1, 66, 1, 1, 1, 0, 81),
185 _RK3036_APLL_SET_CLKS(1560, 1, 65, 1, 1, 1, 0, 81),
186 _RK3036_APLL_SET_CLKS(1536, 1, 64, 1, 1, 1, 0, 81),
187 _RK3036_APLL_SET_CLKS(1512, 1, 63, 1, 1, 1, 0, 81),
188 _RK3036_APLL_SET_CLKS(1488, 1, 62, 1, 1, 1, 0, 81),
189 _RK3036_APLL_SET_CLKS(1464, 1, 61, 1, 1, 1, 0, 81),
190 _RK3036_APLL_SET_CLKS(1440, 1, 60, 1, 1, 1, 0, 81),
191 _RK3036_APLL_SET_CLKS(1416, 1, 59, 1, 1, 1, 0, 81),
192 _RK3036_APLL_SET_CLKS(1392, 1, 58, 1, 1, 1, 0, 81),
193 _RK3036_APLL_SET_CLKS(1368, 1, 57, 1, 1, 1, 0, 81),
194 _RK3036_APLL_SET_CLKS(1344, 1, 56, 1, 1, 1, 0, 81),
195 _RK3036_APLL_SET_CLKS(1320, 1, 55, 1, 1, 1, 0, 81),
196 _RK3036_APLL_SET_CLKS(1296, 1, 54, 1, 1, 1, 0, 81),
197 _RK3036_APLL_SET_CLKS(1272, 1, 53, 1, 1, 1, 0, 81),
198 _RK3036_APLL_SET_CLKS(1248, 1, 52, 1, 1, 1, 0, 81),
199 _RK3036_APLL_SET_CLKS(1200, 1, 50, 1, 1, 1, 0, 81),
200 _RK3036_APLL_SET_CLKS(1104, 1, 46, 1, 1, 1, 0, 81),
201 _RK3036_APLL_SET_CLKS(1100, 12, 550, 1, 1, 1, 0, 81),
202 _RK3036_APLL_SET_CLKS(1008, 1, 84, 2, 1, 1, 0, 81),
203 _RK3036_APLL_SET_CLKS(1000, 6, 500, 2, 1, 1, 0, 81),
204 _RK3036_APLL_SET_CLKS(984, 1, 82, 2, 1, 1, 0, 81),
205 _RK3036_APLL_SET_CLKS(960, 1, 80, 2, 1, 1, 0, 81),
206 _RK3036_APLL_SET_CLKS(936, 1, 78, 2, 1, 1, 0, 81),
207 _RK3036_APLL_SET_CLKS(912, 1, 76, 2, 1, 1, 0, 41),
208 _RK3036_APLL_SET_CLKS(900, 4, 300, 2, 1, 1, 0, 41),
209 _RK3036_APLL_SET_CLKS(888, 1, 74, 2, 1, 1, 0, 41),
210 _RK3036_APLL_SET_CLKS(864, 1, 72, 2, 1, 1, 0, 41),
211 _RK3036_APLL_SET_CLKS(840, 1, 70, 2, 1, 1, 0, 41),
212 _RK3036_APLL_SET_CLKS(816, 1, 68, 2, 1, 1, 0, 41),
213 _RK3036_APLL_SET_CLKS(800, 6, 400, 2, 1, 1, 0, 41),
214 _RK3036_APLL_SET_CLKS(700, 6, 350, 2, 1, 1, 0, 41),
215 _RK3036_APLL_SET_CLKS(696, 1, 58, 2, 1, 1, 0, 41),
216 _RK3036_APLL_SET_CLKS(600, 1, 75, 3, 1, 1, 0, 41),
217 _RK3036_APLL_SET_CLKS(504, 1, 63, 3, 1, 1, 0, 41),
218 _RK3036_APLL_SET_CLKS(500, 6, 250, 2, 1, 1, 0, 41),
219 _RK3036_APLL_SET_CLKS(408, 1, 68, 2, 2, 1, 0, 41),
220 _RK3036_APLL_SET_CLKS(312, 1, 52, 2, 2, 1, 0, 41),
221 _RK3036_APLL_SET_CLKS(216, 1, 72, 4, 2, 1, 0, 41),
222 _RK3036_APLL_SET_CLKS(96, 1, 64, 4, 4, 1, 0, 21),
223 _RK3036_APLL_SET_CLKS(0, 1, 0, 1, 1, 1, 0, 21),
226 static const struct pll_clk_set rk3036plus_pll_com_table[] = {
227 _RK3036_PLL_SET_CLKS(1188000, 2, 99, 1, 1, 1, 0),
228 _RK3036_PLL_SET_CLKS(594000, 2, 99, 2, 1, 1, 0),
229 /*_RK3036_PLL_SET_CLKS(297000, 2, 99, 4, 1, 1, 0),*/
232 static const struct pll_clk_set rk312xplus_pll_com_table[] = {
233 /*_RK3036_PLL_SET_CLKS(1064000, 3, 133, 1, 1, 1, 0),*/
234 /*_RK3036_PLL_SET_CLKS(798000, 2, 133, 2, 1, 1, 0),*/
235 _RK3036_PLL_SET_CLKS(594000, 2, 99, 2, 1, 1, 0),
236 _RK3036_PLL_SET_CLKS(500000, 6, 250, 2, 1, 1, 0),
237 _RK3036_PLL_SET_CLKS(400000, 6, 400, 2, 2, 1, 0),
240 static const struct apll_clk_set rk3368_apllb_table[] = {
241 /*(_mhz, nr, nf, no, aclkm, atclk, pclk_dbg)*/
242 _RK3368_APLL_SET_CLKS(1608, 1, 67, 1, 2, 6, 6),
243 _RK3368_APLL_SET_CLKS(1560, 1, 65, 1, 2, 6, 6),
244 _RK3368_APLL_SET_CLKS(1512, 1, 63, 1, 2, 6, 6),
245 _RK3368_APLL_SET_CLKS(1488, 1, 62, 1, 2, 5, 5),
246 _RK3368_APLL_SET_CLKS(1464, 1, 61, 1, 2, 5, 5),
247 _RK3368_APLL_SET_CLKS(1440, 1, 60, 1, 2, 5, 5),
248 _RK3368_APLL_SET_CLKS(1416, 1, 59, 1, 2, 5, 5),
249 _RK3368_APLL_SET_CLKS(1392, 1, 58, 1, 2, 5, 5),
250 _RK3368_APLL_SET_CLKS(1368, 1, 57, 1, 2, 5, 5),
251 _RK3368_APLL_SET_CLKS(1344, 1, 56, 1, 2, 5, 5),
252 _RK3368_APLL_SET_CLKS(1320, 1, 55, 1, 2, 5, 5),
253 _RK3368_APLL_SET_CLKS(1296, 1, 54, 1, 2, 5, 5),
254 _RK3368_APLL_SET_CLKS(1272, 1, 53, 1, 2, 5, 5),
255 _RK3368_APLL_SET_CLKS(1248, 1, 52, 1, 2, 5, 5),
256 _RK3368_APLL_SET_CLKS(1224, 1, 51, 1, 2, 5, 5),
257 _RK3368_APLL_SET_CLKS(1200, 1, 50, 1, 2, 4, 4),
258 _RK3368_APLL_SET_CLKS(1176, 1, 49, 1, 2, 4, 4),
259 _RK3368_APLL_SET_CLKS(1128, 1, 47, 1, 2, 4, 4),
260 _RK3368_APLL_SET_CLKS(1104, 1, 46, 1, 2, 4, 4),
261 _RK3368_APLL_SET_CLKS(1008, 1, 84, 2, 2, 4, 4),
262 _RK3368_APLL_SET_CLKS(912, 1, 76, 2, 2, 4, 4),
263 _RK3368_APLL_SET_CLKS(888, 1, 74, 2, 2, 3, 3),
264 _RK3368_APLL_SET_CLKS(816, 1, 68, 2, 2, 3, 3),
265 _RK3368_APLL_SET_CLKS(792, 1, 66, 2, 2, 3, 3),
266 _RK3368_APLL_SET_CLKS(696, 1, 58, 2, 2, 3, 3),
267 _RK3368_APLL_SET_CLKS(672, 1, 56, 2, 2, 3, 3),
268 _RK3368_APLL_SET_CLKS(648, 1, 54, 2, 2, 3, 3),
269 _RK3368_APLL_SET_CLKS(624, 1, 52, 2, 2, 3, 3),
270 _RK3368_APLL_SET_CLKS(600, 1, 50, 2, 2, 2, 2),
271 _RK3368_APLL_SET_CLKS(576, 1, 48, 2, 2, 2, 2),
272 _RK3368_APLL_SET_CLKS(552, 1, 92, 4, 2, 2, 2),
273 _RK3368_APLL_SET_CLKS(528, 1, 88, 4, 2, 2, 2),
274 _RK3368_APLL_SET_CLKS(504, 1, 84, 4, 2, 2, 2),
275 _RK3368_APLL_SET_CLKS(480, 1, 80, 4, 2, 2, 2),
276 _RK3368_APLL_SET_CLKS(456, 1, 76, 4, 2, 2, 2),
277 _RK3368_APLL_SET_CLKS(408, 1, 68, 4, 2, 2, 2),
278 _RK3368_APLL_SET_CLKS(312, 1, 52, 4, 2, 2, 2),
279 _RK3368_APLL_SET_CLKS(252, 1, 84, 8, 2, 1, 1),
280 _RK3368_APLL_SET_CLKS(216, 1, 72, 8, 2, 1, 1),
281 _RK3368_APLL_SET_CLKS(126, 2, 84, 8, 2, 1, 1),
282 _RK3368_APLL_SET_CLKS(48, 2, 32, 8, 2, 1, 1),
283 _RK3368_APLL_SET_CLKS(0, 1, 32, 16, 2, 1, 1),
286 static const struct apll_clk_set rk3368_aplll_table[] = {
287 /*(_mhz, nr, nf, no, aclkm, atclk, pclk_dbg)*/
288 _RK3368_APLL_SET_CLKS(1608, 1, 67, 1, 2, 7, 7),
289 _RK3368_APLL_SET_CLKS(1560, 1, 65, 1, 2, 7, 7),
290 _RK3368_APLL_SET_CLKS(1512, 1, 63, 1, 2, 7, 7),
291 _RK3368_APLL_SET_CLKS(1488, 1, 62, 1, 2, 6, 6),
292 _RK3368_APLL_SET_CLKS(1464, 1, 61, 1, 2, 6, 6),
293 _RK3368_APLL_SET_CLKS(1440, 1, 60, 1, 2, 6, 6),
294 _RK3368_APLL_SET_CLKS(1416, 1, 59, 1, 2, 6, 6),
295 _RK3368_APLL_SET_CLKS(1392, 1, 58, 1, 2, 6, 6),
296 _RK3368_APLL_SET_CLKS(1368, 1, 57, 1, 2, 6, 6),
297 _RK3368_APLL_SET_CLKS(1344, 1, 56, 1, 2, 6, 6),
298 _RK3368_APLL_SET_CLKS(1320, 1, 55, 1, 2, 6, 6),
299 _RK3368_APLL_SET_CLKS(1296, 1, 54, 1, 2, 6, 6),
300 _RK3368_APLL_SET_CLKS(1272, 1, 53, 1, 2, 6, 6),
301 _RK3368_APLL_SET_CLKS(1248, 1, 52, 1, 2, 5, 5),
302 _RK3368_APLL_SET_CLKS(1224, 1, 51, 1, 2, 5, 5),
303 _RK3368_APLL_SET_CLKS(1200, 1, 50, 1, 2, 5, 5),
304 _RK3368_APLL_SET_CLKS(1176, 1, 49, 1, 2, 5, 5),
305 _RK3368_APLL_SET_CLKS(1128, 1, 47, 1, 2, 5, 5),
306 _RK3368_APLL_SET_CLKS(1104, 1, 46, 1, 2, 5, 5),
307 _RK3368_APLL_SET_CLKS(1008, 1, 84, 2, 2, 5, 5),
308 _RK3368_APLL_SET_CLKS(912, 1, 76, 2, 2, 4, 4),
309 _RK3368_APLL_SET_CLKS(888, 1, 74, 2, 2, 4, 4),
310 _RK3368_APLL_SET_CLKS(816, 1, 68, 2, 2, 4, 4),
311 _RK3368_APLL_SET_CLKS(792, 1, 66, 2, 2, 4, 4),
312 _RK3368_APLL_SET_CLKS(696, 1, 58, 2, 2, 3, 3),
313 _RK3368_APLL_SET_CLKS(672, 1, 56, 2, 2, 3, 3),
314 _RK3368_APLL_SET_CLKS(648, 1, 54, 2, 2, 3, 3),
315 _RK3368_APLL_SET_CLKS(624, 1, 52, 2, 2, 3, 3),
316 _RK3368_APLL_SET_CLKS(600, 1, 50, 2, 2, 3, 3),
317 _RK3368_APLL_SET_CLKS(576, 1, 48, 2, 2, 3, 3),
318 _RK3368_APLL_SET_CLKS(552, 1, 92, 4, 2, 3, 3),
319 _RK3368_APLL_SET_CLKS(528, 1, 88, 4, 2, 3, 3),
320 _RK3368_APLL_SET_CLKS(504, 1, 84, 4, 2, 3, 3),
321 _RK3368_APLL_SET_CLKS(480, 1, 80, 4, 2, 2, 2),
322 _RK3368_APLL_SET_CLKS(456, 1, 76, 4, 2, 2, 2),
323 _RK3368_APLL_SET_CLKS(408, 1, 68, 4, 2, 2, 2),
324 _RK3368_APLL_SET_CLKS(312, 1, 52, 4, 2, 2, 2),
325 _RK3368_APLL_SET_CLKS(252, 1, 84, 8, 2, 2, 2),
326 _RK3368_APLL_SET_CLKS(216, 1, 72, 8, 2, 1, 1),
327 _RK3368_APLL_SET_CLKS(126, 2, 84, 8, 2, 1, 1),
328 _RK3368_APLL_SET_CLKS(48, 2, 32, 8, 2, 1, 1),
329 _RK3368_APLL_SET_CLKS(0, 1, 32, 16, 2, 1, 1),
332 static const struct pll_clk_set rk3368_pll_table_low_jitter[] = {
333 /* _khz, nr, nf, no, nb */
334 _RK3188PLUS_PLL_SET_CLKS_NB(1188000, 1, 99, 2, 1),
335 _RK3188PLUS_PLL_SET_CLKS( 0, 0, 0, 0),
338 static void pll_wait_lock(struct clk_hw *hw)
340 struct clk_pll *pll = to_clk_pll(hw);
341 int delay = 24000000;
344 if (grf_readl(pll->status_offset) & (1 << pll->status_shift))
350 clk_err("pll %s: can't lock! status_shift=%u\n"
351 "pll_con0=%08x\npll_con1=%08x\n"
352 "pll_con2=%08x\npll_con3=%08x\n",
353 __clk_get_name(hw->clk),
355 cru_readl(pll->reg + RK3188_PLL_CON(0)),
356 cru_readl(pll->reg + RK3188_PLL_CON(1)),
357 cru_readl(pll->reg + RK3188_PLL_CON(2)),
358 cru_readl(pll->reg + RK3188_PLL_CON(3)));
364 static void rk3036_pll_wait_lock(struct clk_hw *hw)
366 struct clk_pll *pll = to_clk_pll(hw);
367 int delay = 24000000;
371 if (cru_readl(pll->status_offset) & (1 << pll->status_shift))
377 clk_err("pll %s: can't lock! status_shift=%u\n"
378 "pll_con0=%08x\npll_con1=%08x\n"
380 __clk_get_name(hw->clk),
382 cru_readl(pll->reg + RK3188_PLL_CON(0)),
383 cru_readl(pll->reg + RK3188_PLL_CON(1)),
384 cru_readl(pll->reg + RK3188_PLL_CON(2)));
391 /* get rate that is most close to target */
392 static const struct apll_clk_set *apll_get_best_set(unsigned long rate,
393 const struct apll_clk_set *table)
395 const struct apll_clk_set *ps, *pt;
399 if (pt->rate == rate) {
404 if ((pt->rate > rate || (rate - pt->rate < ps->rate - rate)))
414 /* get rate that is most close to target */
415 static const struct pll_clk_set *pll_com_get_best_set(unsigned long rate,
416 const struct pll_clk_set *table)
418 const struct pll_clk_set *ps, *pt;
422 if (pt->rate == rate) {
427 if ((pt->rate > rate || (rate - pt->rate < ps->rate - rate)))
437 /* CLK_PLL_3188 type ops */
438 static unsigned long clk_pll_recalc_rate_3188(struct clk_hw *hw,
439 unsigned long parent_rate)
441 struct clk_pll *pll = to_clk_pll(hw);
445 if (_RK3188_PLL_MODE_IS_NORM(pll->mode_offset, pll->mode_shift)) {
446 u32 pll_con0 = cru_readl(pll->reg + RK3188_PLL_CON(0));
447 u32 pll_con1 = cru_readl(pll->reg + RK3188_PLL_CON(1));
449 u64 rate64 = (u64)parent_rate * RK3188_PLL_NF(pll_con1);
451 do_div(rate64, RK3188_PLL_NR(pll_con0));
452 do_div(rate64, RK3188_PLL_NO(pll_con0));
458 clk_debug("pll %s is in slow mode\n", __clk_get_name(hw->clk));
461 clk_debug("pll %s recalc rate =%lu\n", __clk_get_name(hw->clk), rate);
466 static long clk_pll_round_rate_3188(struct clk_hw *hw, unsigned long rate,
467 unsigned long *prate)
469 struct clk *parent = __clk_get_parent(hw->clk);
471 if (parent && (rate==__clk_get_rate(parent))) {
472 clk_debug("pll %s round rate=%lu equal to parent rate\n",
473 __clk_get_name(hw->clk), rate);
477 return (pll_com_get_best_set(rate, rk3188_pll_com_table)->rate);
480 static int _pll_clk_set_rate_3188(struct pll_clk_set *clk_set,
483 struct clk_pll *pll = to_clk_pll(hw);
484 unsigned long flags = 0;
487 clk_debug("%s start!\n", __func__);
490 spin_lock_irqsave(pll->lock, flags);
493 cru_writel(_RK3188_PLL_MODE_SLOW_SET(pll->mode_shift), pll->mode_offset);
495 cru_writel((0x1 << (16+1)) | (0x1<<1), pll->reg + RK3188_PLL_CON(3));
502 cru_writel(clk_set->pllcon0, pll->reg + RK3188_PLL_CON(0));
503 cru_writel(clk_set->pllcon1, pll->reg + RK3188_PLL_CON(1));
508 cru_writel((0x1<<(16+1)), pll->reg + RK3188_PLL_CON(3));
513 cru_writel(_RK3188_PLL_MODE_NORM_SET(pll->mode_shift), pll->mode_offset);
516 spin_unlock_irqrestore(pll->lock, flags);
518 clk_debug("pll %s dump reg: con0=0x%08x, con1=0x%08x, mode=0x%08x\n",
519 __clk_get_name(hw->clk),
520 cru_readl(pll->reg + RK3188_PLL_CON(0)),
521 cru_readl(pll->reg + RK3188_PLL_CON(1)),
522 cru_readl(pll->mode_offset));
524 clk_debug("%s end!\n", __func__);
529 static int clk_pll_set_rate_3188(struct clk_hw *hw, unsigned long rate,
530 unsigned long parent_rate)
532 struct clk_pll *pll = to_clk_pll(hw);
533 struct pll_clk_set *clk_set = (struct pll_clk_set *)(rk3188_pll_com_table);
537 if (rate == parent_rate) {
538 clk_debug("pll %s set rate=%lu equal to parent rate\n",
539 __clk_get_name(hw->clk), rate);
540 cru_writel(_RK3188_PLL_MODE_SLOW_SET(pll->mode_shift),
543 cru_writel((0x1 << (16+1)) | (0x1<<1), pll->reg + RK3188_PLL_CON(3));
544 clk_debug("pll %s enter slow mode, set rate OK!\n",
545 __clk_get_name(hw->clk));
549 while(clk_set->rate) {
550 if (clk_set->rate == rate) {
556 if (clk_set->rate == rate) {
557 ret = _pll_clk_set_rate_3188(clk_set, hw);
558 clk_debug("pll %s set rate=%lu OK!\n", __clk_get_name(hw->clk),
561 clk_err("pll %s is no corresponding rate=%lu\n",
562 __clk_get_name(hw->clk), rate);
569 static const struct clk_ops clk_pll_ops_3188 = {
570 .recalc_rate = clk_pll_recalc_rate_3188,
571 .round_rate = clk_pll_round_rate_3188,
572 .set_rate = clk_pll_set_rate_3188,
576 /* CLK_PLL_3188_APLL type ops */
577 static unsigned long clk_pll_recalc_rate_3188_apll(struct clk_hw *hw,
578 unsigned long parent_rate)
580 return clk_pll_recalc_rate_3188(hw, parent_rate);
583 static long clk_pll_round_rate_3188_apll(struct clk_hw *hw, unsigned long rate,
584 unsigned long *prate)
586 struct clk *parent = __clk_get_parent(hw->clk);
588 if (parent && (rate==__clk_get_rate(parent))) {
589 clk_debug("pll %s round rate=%lu equal to parent rate\n",
590 __clk_get_name(hw->clk), rate);
594 return (apll_get_best_set(rate, rk3188_apll_table)->rate);
597 /* 1: use, 0: no use */
598 #define RK3188_USE_ARM_GPLL 1
600 static int clk_pll_set_rate_3188_apll(struct clk_hw *hw, unsigned long rate,
601 unsigned long parent_rate)
603 struct clk_pll *pll = to_clk_pll(hw);
604 struct clk *clk = hw->clk;
605 struct clk *arm_gpll = __clk_lookup("clk_arm_gpll");
606 unsigned long arm_gpll_rate;
607 const struct apll_clk_set *ps;
608 u32 old_aclk_div = 0, new_aclk_div = 0;
614 if (rate == parent_rate) {
615 clk_debug("pll %s set rate=%lu equal to parent rate\n",
616 __clk_get_name(hw->clk), rate);
617 cru_writel(_RK3188_PLL_MODE_SLOW_SET(pll->mode_shift),
620 cru_writel((0x1 << (16+1)) | (0x1<<1), pll->reg + RK3188_PLL_CON(3));
621 clk_debug("pll %s enter slow mode, set rate OK!\n",
622 __clk_get_name(hw->clk));
627 #if !RK3188_USE_ARM_GPLL
631 /* prepare arm_gpll before reparent clk_core to it */
633 clk_err("clk arm_gpll is NULL!\n");
637 /* In rk3188, arm_gpll and cpu_gpll share a same gate,
638 * and aclk_cpu selects cpu_gpll as parent, thus this
639 * gate must keep enabled.
642 if (clk_prepare(arm_gpll)) {
643 clk_err("fail to prepare arm_gpll path\n");
644 clk_unprepare(arm_gpll);
648 if (clk_enable(arm_gpll)) {
649 clk_err("fail to enable arm_gpll path\n");
650 clk_disable(arm_gpll);
651 clk_unprepare(arm_gpll);
656 arm_gpll_rate = __clk_get_rate(arm_gpll);
657 temp_div = DIV_ROUND_UP(arm_gpll_rate, __clk_get_rate(clk));
658 temp_div = (temp_div == 0) ? 1 : temp_div;
659 if (temp_div > RK3188_CORE_CLK_MAX_DIV) {
660 clk_debug("temp_div %d > max_div %d\n", temp_div,
661 RK3188_CORE_CLK_MAX_DIV);
662 clk_debug("can't get rate %lu from arm_gpll rate %lu\n",
663 __clk_get_rate(clk), arm_gpll_rate);
664 //clk_disable(arm_gpll);
665 //clk_unprepare(arm_gpll);
669 local_irq_save(flags);
671 /* firstly set div, then select arm_gpll path */
672 cru_writel(RK3188_CORE_CLK_DIV_W_MSK|RK3188_CORE_CLK_DIV(temp_div),
673 RK3188_CRU_CLKSELS_CON(0));
674 cru_writel(RK3188_CORE_SEL_PLL_W_MSK|RK3188_CORE_SEL_GPLL,
675 RK3188_CRU_CLKSELS_CON(0));
678 //loops_per_jiffy = CLK_LOOPS_RECALC(arm_gpll_rate) / temp_div;
681 local_irq_restore(flags);
683 clk_debug("temp select arm_gpll path, get rate %lu\n",
684 arm_gpll_rate/temp_div);
685 clk_debug("from arm_gpll rate %lu, temp_div %d\n", arm_gpll_rate,
689 ps = apll_get_best_set(rate, rk3188_apll_table);
690 clk_debug("apll will set rate %lu\n", ps->rate);
691 clk_debug("table con:%08x,%08x,%08x, sel:%08x,%08x\n",
692 ps->pllcon0, ps->pllcon1, ps->pllcon2,
693 ps->clksel0, ps->clksel1);
695 local_irq_save(flags);
697 /* If core src don't select gpll, apll need to enter slow mode
702 cru_writel(_RK3188_PLL_MODE_SLOW_SET(pll->mode_shift), pll->mode_offset);
705 cru_writel((0x1 << (16+1)) | (0x1<<1), pll->reg + RK3188_PLL_CON(3));
712 cru_writel(ps->pllcon0, pll->reg + RK3188_PLL_CON(0));
713 cru_writel(ps->pllcon1, pll->reg + RK3188_PLL_CON(1));
717 /* PLL power up and wait for locked */
718 cru_writel((0x1<<(16+1)), pll->reg + RK3188_PLL_CON(3));
721 old_aclk_div = RK3188_GET_CORE_ACLK_VAL(cru_readl(RK3188_CRU_CLKSELS_CON(1)) &
722 RK3188_CORE_ACLK_MSK);
723 new_aclk_div = RK3188_GET_CORE_ACLK_VAL(ps->clksel1 & RK3188_CORE_ACLK_MSK);
725 if (new_aclk_div >= old_aclk_div) {
726 cru_writel(ps->clksel0, RK3188_CRU_CLKSELS_CON(0));
727 cru_writel(ps->clksel1, RK3188_CRU_CLKSELS_CON(1));
730 /* PLL return from slow mode */
733 cru_writel(_RK3188_PLL_MODE_NORM_SET(pll->mode_shift), pll->mode_offset);
735 /* reparent to apll, and set div to 1 */
737 cru_writel(RK3188_CORE_SEL_PLL_W_MSK|RK3188_CORE_SEL_APLL,
738 RK3188_CRU_CLKSELS_CON(0));
739 cru_writel(RK3188_CORE_CLK_DIV_W_MSK|RK3188_CORE_CLK_DIV(1),
740 RK3188_CRU_CLKSELS_CON(0));
743 if (old_aclk_div > new_aclk_div) {
744 cru_writel(ps->clksel0, RK3188_CRU_CLKSELS_CON(0));
745 cru_writel(ps->clksel1, RK3188_CRU_CLKSELS_CON(1));
748 //loops_per_jiffy = ps->lpj;
751 local_irq_restore(flags);
755 //clk_disable(arm_gpll);
756 //clk_unprepare(arm_gpll);
759 //clk_debug("apll set loops_per_jiffy =%lu\n", loops_per_jiffy);
761 clk_debug("apll set rate %lu, con(%x,%x,%x,%x), sel(%x,%x)\n",
763 cru_readl(pll->reg + RK3188_PLL_CON(0)),
764 cru_readl(pll->reg + RK3188_PLL_CON(1)),
765 cru_readl(pll->reg + RK3188_PLL_CON(2)),
766 cru_readl(pll->reg + RK3188_PLL_CON(3)),
767 cru_readl(RK3188_CRU_CLKSELS_CON(0)),
768 cru_readl(RK3188_CRU_CLKSELS_CON(1)));
773 static const struct clk_ops clk_pll_ops_3188_apll = {
774 .recalc_rate = clk_pll_recalc_rate_3188_apll,
775 .round_rate = clk_pll_round_rate_3188_apll,
776 .set_rate = clk_pll_set_rate_3188_apll,
780 /* CLK_PLL_3188PLUS type ops */
781 static unsigned long clk_pll_recalc_rate_3188plus(struct clk_hw *hw,
782 unsigned long parent_rate)
784 struct clk_pll *pll = to_clk_pll(hw);
788 if (_RK3188_PLL_MODE_IS_NORM(pll->mode_offset, pll->mode_shift)) {
789 u32 pll_con0 = cru_readl(pll->reg + RK3188_PLL_CON(0));
790 u32 pll_con1 = cru_readl(pll->reg + RK3188_PLL_CON(1));
792 u64 rate64 = (u64)parent_rate * RK3188PLUS_PLL_NF(pll_con1);
794 do_div(rate64, RK3188PLUS_PLL_NR(pll_con0));
795 do_div(rate64, RK3188PLUS_PLL_NO(pll_con0));
801 clk_debug("pll %s is in slow mode\n", __clk_get_name(hw->clk));
804 clk_debug("pll %s recalc rate =%lu\n", __clk_get_name(hw->clk), rate);
809 static long clk_pll_round_rate_3188plus(struct clk_hw *hw, unsigned long rate,
810 unsigned long *prate)
812 struct clk *parent = __clk_get_parent(hw->clk);
814 if (parent && (rate==__clk_get_rate(parent))) {
815 clk_debug("pll %s round rate=%lu equal to parent rate\n",
816 __clk_get_name(hw->clk), rate);
820 return (pll_com_get_best_set(rate, rk3188plus_pll_com_table)->rate);
823 static int _pll_clk_set_rate_3188plus(struct pll_clk_set *clk_set,
826 struct clk_pll *pll = to_clk_pll(hw);
827 unsigned long flags = 0;
830 clk_debug("%s start!\n", __func__);
833 spin_lock_irqsave(pll->lock, flags);
836 cru_writel(_RK3188_PLL_MODE_SLOW_SET(pll->mode_shift), pll->mode_offset);
839 cru_writel(_RK3188PLUS_PLL_RESET_SET(1), pll->reg + RK3188_PLL_CON(3));
841 cru_writel(clk_set->pllcon0, pll->reg + RK3188_PLL_CON(0));
842 cru_writel(clk_set->pllcon1, pll->reg + RK3188_PLL_CON(1));
843 cru_writel(clk_set->pllcon2, pll->reg + RK3188_PLL_CON(2));
848 cru_writel(_RK3188PLUS_PLL_RESET_SET(0), pll->reg + RK3188_PLL_CON(3));
851 udelay(clk_set->rst_dly);
856 cru_writel(_RK3188_PLL_MODE_NORM_SET(pll->mode_shift), pll->mode_offset);
859 spin_unlock_irqrestore(pll->lock, flags);
861 clk_debug("pll %s dump reg: con0=0x%08x, con1=0x%08x, mode=0x%08x\n",
862 __clk_get_name(hw->clk),
863 cru_readl(pll->reg + RK3188_PLL_CON(0)),
864 cru_readl(pll->reg + RK3188_PLL_CON(1)),
865 cru_readl(pll->mode_offset));
867 clk_debug("%s end!\n", __func__);
872 static int clk_pll_set_rate_3188plus(struct clk_hw *hw, unsigned long rate,
873 unsigned long parent_rate)
875 //struct clk_pll *pll = to_clk_pll(hw);
876 struct pll_clk_set *clk_set = (struct pll_clk_set *)(rk3188plus_pll_com_table);
880 if (rate == parent_rate) {
881 clk_debug("pll %s set rate=%lu equal to parent rate\n",
882 __clk_get_name(hw->clk), rate);
883 cru_writel(_RK3188_PLL_MODE_SLOW_SET(pll->mode_shift),
886 cru_writel((0x1 << (16+1)) | (0x1<<1), pll->reg + RK3188_PLL_CON(3));
887 clk_debug("pll %s enter slow mode, set rate OK!\n",
888 __clk_get_name(hw->clk));
893 while(clk_set->rate) {
894 if (clk_set->rate == rate) {
900 if (cpu_is_rk3288() && (rate == 297*MHZ)) {
901 if((strncmp(__clk_get_name(hw->clk), "clk_gpll",
902 strlen("clk_gpll")) == 0)) {
904 printk("rk3288 set GPLL BW 20 for HDMI!\n");
905 clk_set->pllcon2 = RK3188_PLL_CLK_BWADJ_SET(20);
909 if (clk_set->rate == rate) {
910 ret = _pll_clk_set_rate_3188plus(clk_set, hw);
911 clk_debug("pll %s set rate=%lu OK!\n", __clk_get_name(hw->clk),
914 clk_err("pll %s is no corresponding rate=%lu\n",
915 __clk_get_name(hw->clk), rate);
922 static int clk_pll_is_enabled_3188plus(struct clk_hw *hw)
925 struct clk_pll *pll = to_clk_pll(hw);
929 spin_lock_irqsave(pll->lock, flags);
931 if (_RK3188_PLL_MODE_IS_NORM(pll->mode_offset, pll->mode_shift))
937 spin_unlock_irqrestore(pll->lock, flags);
942 static int clk_pll_enable_3188plus(struct clk_hw *hw)
944 struct clk_pll *pll = to_clk_pll(hw);
946 unsigned long rst_dly;
949 clk_debug("%s enter\n", __func__);
951 if (clk_pll_is_enabled_3188plus(hw)) {
952 clk_debug("pll has been enabled\n");
957 spin_lock_irqsave(pll->lock, flags);
960 cru_writel(_RK3188_PLL_MODE_SLOW_SET(pll->mode_shift), pll->mode_offset);
963 cru_writel(_RK3188PLUS_PLL_POWERDOWN_SET(0), pll->reg + RK3188_PLL_CON(3));
966 cru_writel(_RK3188PLUS_PLL_RESET_SET(1), pll->reg + RK3188_PLL_CON(3));
968 //cru_writel(clk_set->pllcon0, pll->reg + RK3188_PLL_CON(0));
969 //cru_writel(clk_set->pllcon1, pll->reg + RK3188_PLL_CON(1));
970 //cru_writel(clk_set->pllcon2, pll->reg + RK3188_PLL_CON(2));
975 cru_writel(_RK3188PLUS_PLL_RESET_SET(0), pll->reg + RK3188_PLL_CON(3));
978 nr = RK3188PLUS_PLL_NR(cru_readl(pll->reg + RK3188_PLL_CON(0)));
979 rst_dly = ((nr*500)/24+1);
985 cru_writel(_RK3188_PLL_MODE_NORM_SET(pll->mode_shift), pll->mode_offset);
988 spin_unlock_irqrestore(pll->lock, flags);
990 clk_debug("pll %s dump reg:\n con0=0x%08x,\n con1=0x%08x,\n con2=0x%08x,\n"
991 "con3=0x%08x,\n mode=0x%08x\n",
992 __clk_get_name(hw->clk),
993 cru_readl(pll->reg + RK3188_PLL_CON(0)),
994 cru_readl(pll->reg + RK3188_PLL_CON(1)),
995 cru_readl(pll->reg + RK3188_PLL_CON(2)),
996 cru_readl(pll->reg + RK3188_PLL_CON(3)),
997 cru_readl(pll->mode_offset));
1002 static void clk_pll_disable_3188plus(struct clk_hw *hw)
1004 struct clk_pll *pll = to_clk_pll(hw);
1005 unsigned long flags;
1007 clk_debug("%s enter\n", __func__);
1010 spin_lock_irqsave(pll->lock, flags);
1013 cru_writel(_RK3188_PLL_MODE_SLOW_SET(pll->mode_shift), pll->mode_offset);
1016 cru_writel(_RK3188PLUS_PLL_POWERDOWN_SET(1), pll->reg + RK3188_PLL_CON(3));
1019 spin_unlock_irqrestore(pll->lock, flags);
1022 static const struct clk_ops clk_pll_ops_3188plus = {
1023 .recalc_rate = clk_pll_recalc_rate_3188plus,
1024 .round_rate = clk_pll_round_rate_3188plus,
1025 .set_rate = clk_pll_set_rate_3188plus,
1026 .enable = clk_pll_enable_3188plus,
1027 .disable = clk_pll_disable_3188plus,
1028 .is_enabled = clk_pll_is_enabled_3188plus,
1031 /* CLK_PLL_3188PLUS_AUTO type ops */
1032 #define PLL_FREF_MIN (269*KHZ)
1033 #define PLL_FREF_MAX (2200*MHZ)
1035 #define PLL_FVCO_MIN (440*MHZ)
1036 #define PLL_FVCO_MAX (2200*MHZ)
1038 #define PLL_FOUT_MIN (27500*KHZ)
1039 #define PLL_FOUT_MAX (2200*MHZ)
1041 #define PLL_NF_MAX (4096)
1042 #define PLL_NR_MAX (64)
1043 #define PLL_NO_MAX (16)
1045 static u32 clk_gcd(u32 numerator, u32 denominator)
1049 if (!numerator || !denominator)
1051 if (numerator > denominator) {
1068 static int pll_clk_get_best_set(unsigned long fin_hz, unsigned long fout_hz,
1069 u32 *best_nr, u32 *best_nf, u32 *best_no)
1071 u32 nr, nf, no, nonr;
1072 u32 nr_out, nf_out, no_out;
1076 u64 fref, fvco, fout;
1079 nr_out = PLL_NR_MAX + 1;
1082 if (!fin_hz || !fout_hz || fout_hz == fin_hz)
1084 gcd_val = clk_gcd(fin_hz, fout_hz);
1086 YFfenzi = fout_hz / gcd_val;
1087 YFfenmu = fin_hz / gcd_val;
1092 if (nf > PLL_NF_MAX || nonr > (PLL_NO_MAX * PLL_NR_MAX))
1095 for (no = 1; no <= PLL_NO_MAX; no++) {
1096 if (!(no == 1 || !(no % 2)))
1103 if (nr > PLL_NR_MAX)
1107 if (fref < PLL_FREF_MIN || fref > PLL_FREF_MAX)
1111 if (fvco < PLL_FVCO_MIN || fvco > PLL_FVCO_MAX)
1115 if (fout < PLL_FOUT_MIN || fout > PLL_FOUT_MAX)
1118 /* select the best from all available PLL settings */
1119 if ((no > no_out) || ((no == no_out) && (nr < nr_out))) {
1127 /* output the best PLL setting */
1128 if ((nr_out <= PLL_NR_MAX) && (no_out > 0)) {
1129 if (best_nr && best_nf && best_no) {
1140 static unsigned long clk_pll_recalc_rate_3188plus_auto(struct clk_hw *hw,
1141 unsigned long parent_rate)
1143 return clk_pll_recalc_rate_3188plus(hw, parent_rate);
1146 static long clk_pll_round_rate_3188plus_auto(struct clk_hw *hw, unsigned long rate,
1147 unsigned long *prate)
1151 for(best=rate; best>0; best--){
1152 if(!pll_clk_get_best_set(*prate, best, NULL, NULL, NULL))
1159 static int clk_pll_set_rate_3188plus_auto(struct clk_hw *hw, unsigned long rate,
1160 unsigned long parent_rate)
1164 struct pll_clk_set clk_set;
1168 best = clk_pll_round_rate_3188plus_auto(hw, rate, &parent_rate);
1173 pll_clk_get_best_set(parent_rate, best, &nr, &nf, &no);
1175 /* prepare clk_set */
1176 clk_set.rate = best;
1177 clk_set.pllcon0 = RK3188PLUS_PLL_CLKR_SET(nr)|RK3188PLUS_PLL_CLKOD_SET(no);
1178 clk_set.pllcon1 = RK3188PLUS_PLL_CLKF_SET(nf);
1179 clk_set.pllcon2 = RK3188PLUS_PLL_CLK_BWADJ_SET(nf >> 1);
1180 clk_set.rst_dly = ((nr*500)/24+1);
1182 ret = _pll_clk_set_rate_3188plus(&clk_set, hw);
1183 clk_debug("pll %s set rate=%lu OK!\n", __clk_get_name(hw->clk), best);
1189 static const struct clk_ops clk_pll_ops_3188plus_auto = {
1190 .recalc_rate = clk_pll_recalc_rate_3188plus_auto,
1191 .round_rate = clk_pll_round_rate_3188plus_auto,
1192 .set_rate = clk_pll_set_rate_3188plus_auto,
1193 .enable = clk_pll_enable_3188plus,
1194 .disable = clk_pll_disable_3188plus,
1195 .is_enabled = clk_pll_is_enabled_3188plus,
1198 static long clk_pll_round_rate_3368_low_jitter(struct clk_hw *hw,
1200 unsigned long *prate)
1203 struct pll_clk_set *p_clk_set;
1205 p_clk_set = (struct pll_clk_set *)(rk3368_pll_table_low_jitter);
1207 while (p_clk_set->rate) {
1208 if (p_clk_set->rate == rate)
1213 if (p_clk_set->rate == rate) {
1214 clk_debug("get rate from table\n");
1218 for (best = rate; best > 0; best--) {
1219 if (!pll_clk_get_best_set(*prate, best, NULL, NULL, NULL))
1223 clk_err("%s: can't round rate %lu\n", __func__, rate);
1228 static int clk_pll_set_rate_3368_low_jitter(struct clk_hw *hw,
1230 unsigned long parent_rate)
1234 struct pll_clk_set clk_set, *p_clk_set;
1237 p_clk_set = (struct pll_clk_set *)(rk3368_pll_table_low_jitter);
1239 while (p_clk_set->rate) {
1240 if (p_clk_set->rate == rate)
1245 if (p_clk_set->rate == rate) {
1246 clk_debug("get rate from table\n");
1250 best = clk_pll_round_rate_3188plus_auto(hw, rate, &parent_rate);
1255 pll_clk_get_best_set(parent_rate, best, &nr, &nf, &no);
1257 /* prepare clk_set */
1258 clk_set.rate = best;
1259 clk_set.pllcon0 = RK3188PLUS_PLL_CLKR_SET(nr)|RK3188PLUS_PLL_CLKOD_SET(no);
1260 clk_set.pllcon1 = RK3188PLUS_PLL_CLKF_SET(nf);
1261 clk_set.pllcon2 = RK3188PLUS_PLL_CLK_BWADJ_SET(nf >> 1);
1262 clk_set.rst_dly = ((nr*500)/24+1);
1264 p_clk_set = &clk_set;
1267 ret = _pll_clk_set_rate_3188plus(p_clk_set, hw);
1268 clk_debug("pll %s set rate=%lu OK!\n", __clk_get_name(hw->clk),
1274 static const struct clk_ops clk_pll_ops_3368_low_jitter = {
1275 .recalc_rate = clk_pll_recalc_rate_3188plus_auto,
1276 .round_rate = clk_pll_round_rate_3368_low_jitter,
1277 .set_rate = clk_pll_set_rate_3368_low_jitter,
1278 .enable = clk_pll_enable_3188plus,
1279 .disable = clk_pll_disable_3188plus,
1280 .is_enabled = clk_pll_is_enabled_3188plus,
1283 /* CLK_PLL_3188PLUS_APLL type ops */
1284 static unsigned long clk_pll_recalc_rate_3188plus_apll(struct clk_hw *hw,
1285 unsigned long parent_rate)
1287 return clk_pll_recalc_rate_3188plus(hw, parent_rate);
1290 static long clk_pll_round_rate_3188plus_apll(struct clk_hw *hw, unsigned long rate,
1291 unsigned long *prate)
1293 return clk_pll_round_rate_3188_apll(hw, rate, prate);
1296 /* 1: use, 0: no use */
1297 #define RK3188PLUS_USE_ARM_GPLL 1
1299 static int clk_pll_set_rate_3188plus_apll(struct clk_hw *hw, unsigned long rate,
1300 unsigned long parent_rate)
1302 struct clk_pll *pll = to_clk_pll(hw);
1303 struct clk *clk = hw->clk;
1304 struct clk *arm_gpll = __clk_lookup("clk_arm_gpll");
1305 unsigned long arm_gpll_rate;
1306 const struct apll_clk_set *ps;
1307 u32 old_aclk_div = 0, new_aclk_div = 0;
1309 unsigned long flags;
1313 if (rate == parent_rate) {
1314 clk_debug("pll %s set rate=%lu equal to parent rate\n",
1315 __clk_get_name(hw->clk), rate);
1316 cru_writel(_RK3188_PLL_MODE_SLOW_SET(pll->mode_shift),
1318 /* pll power down */
1319 cru_writel((0x1 << (16+1)) | (0x1<<1), pll->reg + RK3188_PLL_CON(3));
1320 clk_debug("pll %s enter slow mode, set rate OK!\n",
1321 __clk_get_name(hw->clk));
1327 #if !RK3188PLUS_USE_ARM_GPLL
1331 /* prepare arm_gpll before reparent clk_core to it */
1333 clk_err("clk arm_gpll is NULL!\n");
1337 /* In rk3188plus, arm_gpll and cpu_gpll share a same gate,
1338 * and aclk_cpu selects cpu_gpll as parent, thus this
1339 * gate must keep enabled.
1342 if (clk_prepare(arm_gpll)) {
1343 clk_err("fail to prepare arm_gpll path\n");
1344 clk_unprepare(arm_gpll);
1348 if (clk_enable(arm_gpll)) {
1349 clk_err("fail to enable arm_gpll path\n");
1350 clk_disable(arm_gpll);
1351 clk_unprepare(arm_gpll);
1356 arm_gpll_rate = __clk_get_rate(arm_gpll);
1357 temp_div = DIV_ROUND_UP(arm_gpll_rate, __clk_get_rate(clk));
1358 temp_div = (temp_div == 0) ? 1 : temp_div;
1359 if (temp_div > RK3188_CORE_CLK_MAX_DIV) {
1360 clk_debug("temp_div %d > max_div %d\n", temp_div,
1361 RK3188_CORE_CLK_MAX_DIV);
1362 clk_debug("can't get rate %lu from arm_gpll rate %lu\n",
1363 __clk_get_rate(clk), arm_gpll_rate);
1364 //clk_disable(arm_gpll);
1365 //clk_unprepare(arm_gpll);
1369 local_irq_save(flags);
1371 /* firstly set div, then select arm_gpll path */
1372 cru_writel(RK3188_CORE_CLK_DIV_W_MSK|RK3188_CORE_CLK_DIV(temp_div),
1373 RK3188_CRU_CLKSELS_CON(0));
1374 cru_writel(RK3188_CORE_SEL_PLL_W_MSK|RK3188_CORE_SEL_GPLL,
1375 RK3188_CRU_CLKSELS_CON(0));
1378 //loops_per_jiffy = CLK_LOOPS_RECALC(arm_gpll_rate) / temp_div;
1381 local_irq_restore(flags);
1383 clk_debug("temp select arm_gpll path, get rate %lu\n",
1384 arm_gpll_rate/temp_div);
1385 clk_debug("from arm_gpll rate %lu, temp_div %d\n", arm_gpll_rate,
1389 ps = apll_get_best_set(rate, rk3188_apll_table);
1390 clk_debug("apll will set rate %lu\n", ps->rate);
1391 clk_debug("table con:%08x,%08x,%08x, sel:%08x,%08x\n",
1392 ps->pllcon0, ps->pllcon1, ps->pllcon2,
1393 ps->clksel0, ps->clksel1);
1395 local_irq_save(flags);
1397 /* If core src don't select gpll, apll need to enter slow mode
1402 cru_writel(_RK3188_PLL_MODE_SLOW_SET(pll->mode_shift), pll->mode_offset);
1404 /* PLL enter rest */
1405 cru_writel(_RK3188PLUS_PLL_RESET_SET(1), pll->reg + RK3188_PLL_CON(3));
1407 cru_writel(ps->pllcon0, pll->reg + RK3188_PLL_CON(0));
1408 cru_writel(ps->pllcon1, pll->reg + RK3188_PLL_CON(1));
1409 cru_writel(ps->pllcon2, pll->reg + RK3188_PLL_CON(2));
1413 /* return from rest */
1414 cru_writel(_RK3188PLUS_PLL_RESET_SET(0), pll->reg + RK3188_PLL_CON(3));
1417 udelay(ps->rst_dly);
1420 old_aclk_div = RK3188_GET_CORE_ACLK_VAL(cru_readl(RK3188_CRU_CLKSELS_CON(1)) &
1421 RK3188_CORE_ACLK_MSK);
1422 new_aclk_div = RK3188_GET_CORE_ACLK_VAL(ps->clksel1 & RK3188_CORE_ACLK_MSK);
1424 if (new_aclk_div >= old_aclk_div) {
1425 cru_writel(ps->clksel0, RK3188_CRU_CLKSELS_CON(0));
1426 cru_writel(ps->clksel1, RK3188_CRU_CLKSELS_CON(1));
1429 /* PLL return from slow mode */
1432 cru_writel(_RK3188_PLL_MODE_NORM_SET(pll->mode_shift), pll->mode_offset);
1434 /* reparent to apll, and set div to 1 */
1436 cru_writel(RK3188_CORE_SEL_PLL_W_MSK|RK3188_CORE_SEL_APLL,
1437 RK3188_CRU_CLKSELS_CON(0));
1438 cru_writel(RK3188_CORE_CLK_DIV_W_MSK|RK3188_CORE_CLK_DIV(1),
1439 RK3188_CRU_CLKSELS_CON(0));
1442 if (old_aclk_div > new_aclk_div) {
1443 cru_writel(ps->clksel0, RK3188_CRU_CLKSELS_CON(0));
1444 cru_writel(ps->clksel1, RK3188_CRU_CLKSELS_CON(1));
1447 //loops_per_jiffy = ps->lpj;
1450 local_irq_restore(flags);
1454 //clk_disable(arm_gpll);
1455 //clk_unprepare(arm_gpll);
1458 //clk_debug("apll set loops_per_jiffy =%lu\n", loops_per_jiffy);
1460 clk_debug("apll set rate %lu, con(%x,%x,%x,%x), sel(%x,%x)\n",
1462 cru_readl(pll->reg + RK3188_PLL_CON(0)),
1463 cru_readl(pll->reg + RK3188_PLL_CON(1)),
1464 cru_readl(pll->reg + RK3188_PLL_CON(2)),
1465 cru_readl(pll->reg + RK3188_PLL_CON(3)),
1466 cru_readl(RK3188_CRU_CLKSELS_CON(0)),
1467 cru_readl(RK3188_CRU_CLKSELS_CON(1)));
1472 static const struct clk_ops clk_pll_ops_3188plus_apll = {
1473 .recalc_rate = clk_pll_recalc_rate_3188plus_apll,
1474 .round_rate = clk_pll_round_rate_3188plus_apll,
1475 .set_rate = clk_pll_set_rate_3188plus_apll,
1478 /* CLK_PLL_3288_APLL type ops */
1479 static unsigned long clk_pll_recalc_rate_3288_apll(struct clk_hw *hw,
1480 unsigned long parent_rate)
1482 return clk_pll_recalc_rate_3188plus(hw, parent_rate);
1485 static long clk_pll_round_rate_3288_apll(struct clk_hw *hw, unsigned long rate,
1486 unsigned long *prate)
1488 struct clk *parent = __clk_get_parent(hw->clk);
1490 if (parent && (rate==__clk_get_rate(parent))) {
1491 clk_debug("pll %s round rate=%lu equal to parent rate\n",
1492 __clk_get_name(hw->clk), rate);
1496 return (apll_get_best_set(rate, rk3288_apll_table)->rate);
1499 /* 1: use, 0: no use */
1500 #define RK3288_USE_ARM_GPLL 1
1502 static int clk_pll_set_rate_3288_apll(struct clk_hw *hw, unsigned long rate,
1503 unsigned long parent_rate)
1505 struct clk_pll *pll = to_clk_pll(hw);
1506 struct clk *clk = hw->clk;
1507 struct clk *arm_gpll = __clk_lookup("clk_arm_gpll");
1508 unsigned long arm_gpll_rate, temp_rate, old_rate;
1509 const struct apll_clk_set *ps;
1510 // u32 old_aclk_div = 0, new_aclk_div = 0;
1512 unsigned long flags;
1517 if (rate == parent_rate) {
1518 clk_debug("pll %s set rate=%lu equal to parent rate\n",
1519 __clk_get_name(hw->clk), rate);
1520 cru_writel(_RK3188_PLL_MODE_SLOW_SET(pll->mode_shift),
1522 /* pll power down */
1523 cru_writel((0x1 << (16+1)) | (0x1<<1), pll->reg + RK3188_PLL_CON(3));
1524 clk_debug("pll %s enter slow mode, set rate OK!\n",
1525 __clk_get_name(hw->clk));
1530 #if !RK3288_USE_ARM_GPLL
1534 /* prepare arm_gpll before reparent clk_core to it */
1536 clk_err("clk arm_gpll is NULL!\n");
1540 arm_gpll_rate = __clk_get_rate(arm_gpll);
1541 old_rate = __clk_get_rate(clk);
1543 temp_rate = (old_rate > rate) ? old_rate : rate;
1544 temp_div = DIV_ROUND_UP(arm_gpll_rate, temp_rate);
1546 if (temp_div > RK3288_CORE_CLK_MAX_DIV) {
1547 clk_debug("temp_div %d > max_div %d\n", temp_div,
1548 RK3288_CORE_CLK_MAX_DIV);
1549 clk_debug("can't get rate %lu from arm_gpll rate %lu\n",
1550 __clk_get_rate(clk), arm_gpll_rate);
1555 if (clk_prepare(arm_gpll)) {
1556 clk_err("fail to prepare arm_gpll path\n");
1557 clk_unprepare(arm_gpll);
1561 if (clk_enable(arm_gpll)) {
1562 clk_err("fail to enable arm_gpll path\n");
1563 clk_disable(arm_gpll);
1564 clk_unprepare(arm_gpll);
1569 local_irq_save(flags);
1572 if (temp_div == 1) {
1573 /* when old_rate/2 < (old_rate-arm_gpll_rate),
1574 we can set div to make rate change more gently */
1575 if (old_rate > (2*arm_gpll_rate)) {
1576 cru_writel(RK3288_CORE_CLK_DIV(2), RK3288_CRU_CLKSELS_CON(0));
1578 cru_writel(RK3288_CORE_CLK_DIV(3), RK3288_CRU_CLKSELS_CON(0));
1580 cru_writel(RK3288_CORE_SEL_PLL_W_MSK|RK3288_CORE_SEL_GPLL,
1581 RK3288_CRU_CLKSELS_CON(0));
1583 cru_writel(RK3288_CORE_CLK_DIV(2), RK3288_CRU_CLKSELS_CON(0));
1585 cru_writel(RK3288_CORE_CLK_DIV(1), RK3288_CRU_CLKSELS_CON(0));
1587 cru_writel(RK3288_CORE_SEL_PLL_W_MSK|RK3288_CORE_SEL_GPLL,
1588 RK3288_CRU_CLKSELS_CON(0));
1591 cru_writel(RK3288_CORE_CLK_DIV(temp_div), RK3288_CRU_CLKSELS_CON(0));
1592 cru_writel(RK3288_CORE_SEL_PLL_W_MSK|RK3288_CORE_SEL_GPLL,
1593 RK3288_CRU_CLKSELS_CON(0));
1597 //loops_per_jiffy = CLK_LOOPS_RECALC(arm_gpll_rate) / temp_div;
1600 local_irq_restore(flags);
1602 clk_debug("temp select arm_gpll path, get rate %lu\n",
1603 arm_gpll_rate/temp_div);
1604 clk_debug("from arm_gpll rate %lu, temp_div %d\n", arm_gpll_rate,
1608 ps = apll_get_best_set(rate, rk3288_apll_table);
1609 clk_debug("apll will set rate %lu\n", ps->rate);
1610 clk_debug("table con:%08x,%08x,%08x, sel:%08x,%08x\n",
1611 ps->pllcon0, ps->pllcon1, ps->pllcon2,
1612 ps->clksel0, ps->clksel1);
1614 local_irq_save(flags);
1616 /* If core src don't select gpll, apll need to enter slow mode
1621 cru_writel(_RK3188_PLL_MODE_SLOW_SET(pll->mode_shift), pll->mode_offset);
1623 /* PLL enter rest */
1624 cru_writel(_RK3188PLUS_PLL_RESET_SET(1), pll->reg + RK3188_PLL_CON(3));
1626 cru_writel(ps->pllcon0, pll->reg + RK3188_PLL_CON(0));
1627 cru_writel(ps->pllcon1, pll->reg + RK3188_PLL_CON(1));
1628 cru_writel(ps->pllcon2, pll->reg + RK3188_PLL_CON(2));
1632 /* return from rest */
1633 cru_writel(_RK3188PLUS_PLL_RESET_SET(0), pll->reg + RK3188_PLL_CON(3));
1636 udelay(ps->rst_dly);
1639 if (rate >= __clk_get_rate(hw->clk)) {
1640 cru_writel(ps->clksel0, RK3288_CRU_CLKSELS_CON(0));
1641 cru_writel(ps->clksel1, RK3288_CRU_CLKSELS_CON(37));
1644 /* PLL return from slow mode */
1647 cru_writel(_RK3188_PLL_MODE_NORM_SET(pll->mode_shift), pll->mode_offset);
1649 /* reparent to apll, and set div to 1 */
1651 if (temp_div == 1) {
1652 /* when rate/2 < (rate-arm_gpll_rate),
1653 we can set div to make rate change more gently */
1654 if (rate > (2*arm_gpll_rate)) {
1655 cru_writel(RK3288_CORE_CLK_DIV(2), RK3288_CRU_CLKSELS_CON(0));
1657 cru_writel(RK3288_CORE_CLK_DIV(3), RK3288_CRU_CLKSELS_CON(0));
1659 cru_writel(RK3288_CORE_SEL_PLL_W_MSK|RK3288_CORE_SEL_APLL,
1660 RK3288_CRU_CLKSELS_CON(0));
1662 cru_writel(RK3288_CORE_CLK_DIV(2), RK3288_CRU_CLKSELS_CON(0));
1664 cru_writel(RK3288_CORE_CLK_DIV(1), RK3288_CRU_CLKSELS_CON(0));
1666 cru_writel(RK3288_CORE_SEL_PLL_W_MSK|RK3288_CORE_SEL_APLL,
1667 RK3288_CRU_CLKSELS_CON(0));
1670 cru_writel(RK3288_CORE_SEL_PLL_W_MSK|RK3288_CORE_SEL_APLL,
1671 RK3288_CRU_CLKSELS_CON(0));
1672 cru_writel(RK3288_CORE_CLK_DIV(1), RK3288_CRU_CLKSELS_CON(0));
1676 if (rate < __clk_get_rate(hw->clk)) {
1677 cru_writel(ps->clksel0, RK3288_CRU_CLKSELS_CON(0));
1678 cru_writel(ps->clksel1, RK3288_CRU_CLKSELS_CON(37));
1681 //loops_per_jiffy = ps->lpj;
1684 local_irq_restore(flags);
1688 //clk_disable(arm_gpll);
1689 //clk_unprepare(arm_gpll);
1692 //clk_debug("apll set loops_per_jiffy =%lu\n", loops_per_jiffy);
1694 clk_debug("apll set rate %lu, con(%x,%x,%x,%x), sel(%x,%x)\n",
1696 cru_readl(pll->reg + RK3188_PLL_CON(0)),
1697 cru_readl(pll->reg + RK3188_PLL_CON(1)),
1698 cru_readl(pll->reg + RK3188_PLL_CON(2)),
1699 cru_readl(pll->reg + RK3188_PLL_CON(3)),
1700 cru_readl(RK3288_CRU_CLKSELS_CON(0)),
1701 cru_readl(RK3288_CRU_CLKSELS_CON(1)));
1707 static const struct clk_ops clk_pll_ops_3288_apll = {
1708 .recalc_rate = clk_pll_recalc_rate_3288_apll,
1709 .round_rate = clk_pll_round_rate_3288_apll,
1710 .set_rate = clk_pll_set_rate_3288_apll,
1713 /* CLK_PLL_3036_APLL type ops */
1715 static unsigned long rk3036_pll_clk_recalc(struct clk_hw *hw,
1716 unsigned long parent_rate)
1718 struct clk_pll *pll = to_clk_pll(hw);
1720 unsigned int dsmp = 0;
1721 u64 rate64 = 0, frac_rate64 = 0;
1723 dsmp = RK3036_PLL_GET_DSMPD(cru_readl(pll->reg + RK3188_PLL_CON(1)));
1725 if (_RK3188_PLL_MODE_IS_NORM(pll->mode_offset, pll->mode_shift)) {
1726 u32 pll_con0 = cru_readl(pll->reg + RK3188_PLL_CON(0));
1727 u32 pll_con1 = cru_readl(pll->reg + RK3188_PLL_CON(1));
1728 u32 pll_con2 = cru_readl(pll->reg + RK3188_PLL_CON(2));
1730 rate64 = (u64)parent_rate * RK3036_PLL_GET_FBDIV(pll_con0);
1731 do_div(rate64, RK3036_PLL_GET_REFDIV(pll_con1));
1733 if (FRAC_MODE == dsmp) {
1735 frac_rate64 = (u64)parent_rate
1736 * RK3036_PLL_GET_FRAC(pll_con2);
1737 do_div(frac_rate64, RK3036_PLL_GET_REFDIV(pll_con1));
1738 rate64 += frac_rate64 >> 24;
1739 clk_debug("%s frac_rate=%llu(%08x/2^24) by pass mode\n",
1740 __func__, frac_rate64 >> 24,
1741 RK3036_PLL_GET_FRAC(pll_con2));
1743 do_div(rate64, RK3036_PLL_GET_POSTDIV1(pll_con0));
1744 do_div(rate64, RK3036_PLL_GET_POSTDIV2(pll_con1));
1749 clk_debug("pll_clk_recalc rate=%lu by pass mode\n", rate);
1754 static unsigned long clk_pll_recalc_rate_3036_apll(struct clk_hw *hw,
1755 unsigned long parent_rate)
1757 return rk3036_pll_clk_recalc(hw, parent_rate);
1760 static long clk_pll_round_rate_3036_apll(struct clk_hw *hw, unsigned long rate,
1761 unsigned long *prate)
1763 struct clk *parent = __clk_get_parent(hw->clk);
1765 if (parent && (rate == __clk_get_rate(parent))) {
1766 clk_debug("pll %s round rate=%lu equal to parent rate\n",
1767 __clk_get_name(hw->clk), rate);
1771 return (apll_get_best_set(rate, rk3036_apll_table)->rate);
1774 static int rk3036_pll_clk_set_rate(struct pll_clk_set *clk_set,
1777 struct clk_pll *pll = to_clk_pll(hw);
1780 cru_writel(_RK3188_PLL_MODE_SLOW_SET(pll->mode_shift),
1783 cru_writel(clk_set->pllcon0, pll->reg + RK3188_PLL_CON(0));
1784 cru_writel(clk_set->pllcon1, pll->reg + RK3188_PLL_CON(1));
1785 cru_writel(clk_set->pllcon2, pll->reg + RK3188_PLL_CON(2));
1787 clk_debug("pllcon0%08x\n", cru_readl(pll->reg + RK3188_PLL_CON(0)));
1788 clk_debug("pllcon1%08x\n", cru_readl(pll->reg + RK3188_PLL_CON(1)));
1789 clk_debug("pllcon2%08x\n", cru_readl(pll->reg + RK3188_PLL_CON(2)));
1790 /*wating lock state*/
1791 udelay(clk_set->rst_dly);
1792 rk3036_pll_wait_lock(hw);
1794 /*return form slow*/
1795 cru_writel(_RK3188_PLL_MODE_NORM_SET(pll->mode_shift),
1801 #define MIN_FOUTVCO_FREQ (400 * 1000 * 1000)
1802 #define MAX_FOUTVCO_FREQ (1600 * 1000 * 1000)
1803 static int rk3036_pll_clk_set_postdiv(unsigned long fout_hz,
1804 u32 *postdiv1, u32 *postdiv2, u32 *foutvco)
1806 if (fout_hz < MIN_FOUTVCO_FREQ) {
1807 for (*postdiv1 = 1; *postdiv1 <= 7; (*postdiv1)++)
1808 for (*postdiv2 = 1; *postdiv2 <= 7; (*postdiv2)++) {
1809 if (fout_hz * (*postdiv1) * (*postdiv2)
1810 >= MIN_FOUTVCO_FREQ && fout_hz
1811 * (*postdiv1) * (*postdiv2)
1812 <= MAX_FOUTVCO_FREQ) {
1813 *foutvco = fout_hz * (*postdiv1)
1818 clk_debug("CANNOT FINE postdiv1/2 to make fout in range from 400M to 1600M, fout = %lu\n",
1827 static int rk3036_pll_clk_get_set(unsigned long fin_hz, unsigned long fout_hz,
1828 u32 *refdiv, u32 *fbdiv, u32 *postdiv1,
1829 u32 *postdiv2, u32 *frac)
1831 /* FIXME set postdiv1/2 always 1*/
1832 u32 gcd, foutvco = fout_hz;
1833 u64 fin_64, frac_64;
1836 if (!fin_hz || !fout_hz || fout_hz == fin_hz)
1839 rk3036_pll_clk_set_postdiv(fout_hz, postdiv1, postdiv2, &foutvco);
1840 if (fin_hz / MHZ * MHZ == fin_hz && fout_hz / MHZ * MHZ == fout_hz) {
1843 gcd = clk_gcd(fin_hz, foutvco);
1844 *refdiv = fin_hz / gcd;
1845 *fbdiv = foutvco / gcd;
1849 clk_debug("fin=%lu,fout=%lu,gcd=%u,refdiv=%u,fbdiv=%u,postdiv1=%u,postdiv2=%u,frac=%u\n",
1850 fin_hz, fout_hz, gcd, *refdiv, *fbdiv, *postdiv1, *postdiv2, *frac);
1852 clk_debug("******frac div running, fin_hz=%lu, fout_hz=%lu,fin_INT_mhz=%lu, fout_INT_mhz=%lu\n",
1853 fin_hz, fout_hz, fin_hz / MHZ * MHZ, fout_hz / MHZ * MHZ);
1854 clk_debug("******frac get postdiv1=%u, postdiv2=%u,foutvco=%u\n",
1855 *postdiv1, *postdiv2, foutvco);
1856 gcd = clk_gcd(fin_hz / MHZ, foutvco / MHZ);
1857 *refdiv = fin_hz / MHZ / gcd;
1858 *fbdiv = foutvco / MHZ / gcd;
1859 clk_debug("******frac get refdiv=%u, fbdiv=%u\n", *refdiv, *fbdiv);
1863 f_frac = (foutvco % MHZ);
1865 do_div(fin_64, (u64)*refdiv);
1866 frac_64 = (u64)f_frac << 24;
1867 do_div(frac_64, fin_64);
1868 *frac = (u32) frac_64;
1869 clk_debug("frac=%x\n", *frac);
1873 static int rk3036_pll_set_con(struct clk_hw *hw, u32 refdiv, u32 fbdiv, u32 postdiv1, u32 postdiv2, u32 frac)
1875 struct pll_clk_set temp_clk_set;
1876 temp_clk_set.pllcon0 = RK3036_PLL_SET_FBDIV(fbdiv) | RK3036_PLL_SET_POSTDIV1(postdiv1);
1877 temp_clk_set.pllcon1 = RK3036_PLL_SET_REFDIV(refdiv) | RK3036_PLL_SET_POSTDIV2(postdiv2);
1879 temp_clk_set.pllcon1 |= RK3036_PLL_SET_DSMPD(0);
1881 temp_clk_set.pllcon1 |= RK3036_PLL_SET_DSMPD(1);
1883 temp_clk_set.pllcon2 = RK3036_PLL_SET_FRAC(frac);
1884 temp_clk_set.rst_dly = 0;
1885 clk_debug("setting....\n");
1886 return rk3036_pll_clk_set_rate(&temp_clk_set, hw);
1889 static int clk_pll_set_rate_3036_apll(struct clk_hw *hw, unsigned long rate,
1890 unsigned long parent_rate)
1892 struct clk_pll *pll = to_clk_pll(hw);
1893 struct apll_clk_set *ps = (struct apll_clk_set *)(rk3036_apll_table);
1894 struct clk *arm_gpll = __clk_lookup("clk_gpll");
1895 struct clk *clk = hw->clk;
1896 unsigned long flags, arm_gpll_rate, old_rate, temp_rate;
1900 if (ps->rate == rate) {
1906 if (ps->rate != rate) {
1907 clk_err("%s: unsupport arm rate %lu\n", __func__, rate);
1912 clk_err("clk arm_gpll is NULL!\n");
1916 old_rate = __clk_get_rate(clk);
1917 arm_gpll_rate = __clk_get_rate(arm_gpll);
1918 if (soc_is_rk3128() || soc_is_rk3126())
1921 temp_rate = (old_rate > rate) ? old_rate : rate;
1922 temp_div = DIV_ROUND_UP(arm_gpll_rate, temp_rate);
1924 local_irq_save(flags);
1926 if (rate >= old_rate) {
1927 cru_writel(ps->clksel0, RK3036_CRU_CLKSELS_CON(0));
1928 cru_writel(ps->clksel1, RK3036_CRU_CLKSELS_CON(1));
1931 /* set div first, then select gpll */
1933 cru_writel(RK3036_CLK_CORE_DIV(temp_div), RK3036_CRU_CLKSELS_CON(0));
1934 cru_writel(RK3036_CORE_SEL_PLL(1), RK3036_CRU_CLKSELS_CON(0));
1936 clk_debug("temp select arm_gpll path, get rate %lu\n",
1937 arm_gpll_rate/temp_div);
1938 clk_debug("from arm_gpll rate %lu, temp_div %d\n", arm_gpll_rate,
1941 /**************enter slow mode 24M***********/
1942 /*cru_writel(_RK3188_PLL_MODE_SLOW_SET(pll->mode_shift), pll->mode_offset);*/
1943 loops_per_jiffy = LPJ_24M;
1945 cru_writel(ps->pllcon0, pll->reg + RK3188_PLL_CON(0));
1946 cru_writel(ps->pllcon1, pll->reg + RK3188_PLL_CON(1));
1947 cru_writel(ps->pllcon2, pll->reg + RK3188_PLL_CON(2));
1949 clk_debug("pllcon0 %08x\n", cru_readl(pll->reg + RK3188_PLL_CON(0)));
1950 clk_debug("pllcon1 %08x\n", cru_readl(pll->reg + RK3188_PLL_CON(1)));
1951 clk_debug("pllcon2 %08x\n", cru_readl(pll->reg + RK3188_PLL_CON(2)));
1952 clk_debug("clksel0 %08x\n", cru_readl(RK3036_CRU_CLKSELS_CON(0)));
1953 clk_debug("clksel1 %08x\n", cru_readl(RK3036_CRU_CLKSELS_CON(1)));
1955 /*wating lock state*/
1956 udelay(ps->rst_dly);
1957 rk3036_pll_wait_lock(hw);
1959 /************select apll******************/
1960 cru_writel(RK3036_CORE_SEL_PLL(0), RK3036_CRU_CLKSELS_CON(0));
1961 /**************return slow mode***********/
1962 /*cru_writel(_RK3188_PLL_MODE_NORM_SET(pll->mode_shift), pll->mode_offset);*/
1964 cru_writel(RK3036_CLK_CORE_DIV(1), RK3036_CRU_CLKSELS_CON(0));
1966 if (rate < old_rate) {
1967 cru_writel(ps->clksel0, RK3036_CRU_CLKSELS_CON(0));
1968 cru_writel(ps->clksel1, RK3036_CRU_CLKSELS_CON(1));
1971 loops_per_jiffy = ps->lpj;
1972 local_irq_restore(flags);
1976 static const struct clk_ops clk_pll_ops_3036_apll = {
1977 .recalc_rate = clk_pll_recalc_rate_3036_apll,
1978 .round_rate = clk_pll_round_rate_3036_apll,
1979 .set_rate = clk_pll_set_rate_3036_apll,
1983 /* CLK_PLL_3036_plus_autotype ops */
1985 static long clk_pll_round_rate_3036plus_auto(struct clk_hw *hw, unsigned long rate,
1986 unsigned long *prate)
1988 struct clk *parent = __clk_get_parent(hw->clk);
1990 if (parent && (rate == __clk_get_rate(parent))) {
1991 clk_debug("pll %s round rate=%lu equal to parent rate\n",
1992 __clk_get_name(hw->clk), rate);
1996 return (pll_com_get_best_set(rate, rk3036plus_pll_com_table)->rate);
1999 static int clk_pll_set_rate_3036plus_auto(struct clk_hw *hw, unsigned long rate,
2000 unsigned long parent_rate)
2002 struct pll_clk_set *clk_set = (struct pll_clk_set *)(rk3036plus_pll_com_table);
2004 clk_debug("******%s\n", __func__);
2005 while (clk_set->rate) {
2006 clk_debug("******%s clk_set->rate=%lu\n", __func__, clk_set->rate);
2007 if (clk_set->rate == rate) {
2012 if (clk_set->rate == rate) {
2013 rk3036_pll_clk_set_rate(clk_set, hw);
2015 clk_debug("gpll is no corresponding rate=%lu\n", rate);
2018 clk_debug("******%s end\n", __func__);
2023 static const struct clk_ops clk_pll_ops_3036plus_auto = {
2024 .recalc_rate = clk_pll_recalc_rate_3036_apll,
2025 .round_rate = clk_pll_round_rate_3036plus_auto,
2026 .set_rate = clk_pll_set_rate_3036plus_auto,
2029 static long clk_cpll_round_rate_312xplus(struct clk_hw *hw, unsigned long rate,
2030 unsigned long *prate)
2034 for (best = rate; best > 0; best--) {
2035 if (!pll_clk_get_best_set(*prate, best, NULL, NULL, NULL))
2042 static int clk_cpll_set_rate_312xplus(struct clk_hw *hw, unsigned long rate,
2043 unsigned long parent_rate)
2045 struct pll_clk_set *clk_set = (struct pll_clk_set *)(rk312xplus_pll_com_table);
2046 u32 refdiv, fbdiv, postdiv1, postdiv2, frac;
2048 while (clk_set->rate) {
2049 if (clk_set->rate == rate) {
2055 if (clk_set->rate == rate) {
2056 clk_debug("cpll get a rate\n");
2057 rk3036_pll_clk_set_rate(clk_set, hw);
2060 clk_debug("cpll get auto calc a rate\n");
2061 if (rk3036_pll_clk_get_set(parent_rate, rate, &refdiv, &fbdiv, &postdiv1, &postdiv2, &frac) != 0) {
2062 pr_err("cpll auto set rate error\n");
2065 clk_debug("%s get rate=%lu, refdiv=%u, fbdiv=%u, postdiv1=%u, postdiv2=%u",
2066 __func__, rate, refdiv, fbdiv, postdiv1, postdiv2);
2067 rk3036_pll_set_con(hw, refdiv, fbdiv, postdiv1, postdiv2, frac);
2071 clk_debug("setting OK\n");
2075 static const struct clk_ops clk_pll_ops_312xplus = {
2076 .recalc_rate = clk_pll_recalc_rate_3036_apll,
2077 .round_rate = clk_cpll_round_rate_312xplus,
2078 .set_rate = clk_cpll_set_rate_312xplus,
2081 static long clk_pll_round_rate_3368_apllb(struct clk_hw *hw, unsigned long rate,
2082 unsigned long *prate)
2084 struct clk *parent = __clk_get_parent(hw->clk);
2086 if (parent && (rate == __clk_get_rate(parent))) {
2087 clk_debug("pll %s round rate=%lu equal to parent rate\n",
2088 __clk_get_name(hw->clk), rate);
2092 return (apll_get_best_set(rate, rk3368_apllb_table)->rate);
2095 /* 1: use, 0: no use */
2096 #define RK3368_APLLB_USE_GPLL 1
2098 /* when define 1, we will set div to make rate change gently, but it will cost
2100 #define RK3368_APLLB_DIV_MORE 1
2102 static int clk_pll_set_rate_3368_apllb(struct clk_hw *hw, unsigned long rate,
2103 unsigned long parent_rate)
2105 struct clk_pll *pll = to_clk_pll(hw);
2106 struct clk *clk = hw->clk;
2107 struct clk *arm_gpll = __clk_lookup("clk_gpll");
2108 unsigned long arm_gpll_rate, temp_rate, old_rate;
2109 const struct apll_clk_set *ps;
2111 unsigned long flags;
2114 ps = apll_get_best_set(rate, rk3368_apllb_table);
2115 clk_debug("apllb will set rate %lu\n", ps->rate);
2116 clk_debug("table con:%08x,%08x,%08x, sel:%08x,%08x\n",
2117 ps->pllcon0, ps->pllcon1, ps->pllcon2,
2118 ps->clksel0, ps->clksel1);
2120 #if !RK3368_APLLB_USE_GPLL
2124 /* prepare arm_gpll before reparent clk_core to it */
2126 clk_err("clk arm_gpll is NULL!\n");
2130 arm_gpll_rate = __clk_get_rate(arm_gpll);
2131 old_rate = __clk_get_rate(clk);
2133 temp_rate = (old_rate > rate) ? old_rate : rate;
2134 temp_div = DIV_ROUND_UP(arm_gpll_rate, temp_rate);
2136 if (temp_div > RK3368_CORE_CLK_MAX_DIV) {
2137 clk_debug("temp_div %d > max_div %d\n", temp_div,
2138 RK3368_CORE_CLK_MAX_DIV);
2139 clk_debug("can't get rate %lu from arm_gpll rate %lu\n",
2140 __clk_get_rate(clk), arm_gpll_rate);
2144 local_irq_save(flags);
2146 if (rate >= old_rate) {
2147 cru_writel(ps->clksel0, RK3368_CRU_CLKSELS_CON(0));
2148 cru_writel(ps->clksel1, RK3368_CRU_CLKSELS_CON(1));
2152 #if RK3368_APLLB_DIV_MORE
2153 if (temp_div == 1) {
2154 /* when old_rate/2 < (old_rate-arm_gpll_rate),
2155 we can set div to make rate change more gently */
2156 if (old_rate > (2*arm_gpll_rate)) {
2157 cru_writel(RK3368_CORE_CLK_DIV(2), RK3368_CRU_CLKSELS_CON(0));
2159 cru_writel(RK3368_CORE_CLK_DIV(3), RK3368_CRU_CLKSELS_CON(0));
2161 cru_writel(RK3368_CORE_SEL_PLL_W_MSK|RK3368_CORE_SEL_GPLL,
2162 RK3368_CRU_CLKSELS_CON(0));
2164 cru_writel(RK3368_CORE_CLK_DIV(2), RK3368_CRU_CLKSELS_CON(0));
2166 cru_writel(RK3368_CORE_CLK_DIV(1), RK3368_CRU_CLKSELS_CON(0));
2168 cru_writel(RK3368_CORE_SEL_PLL_W_MSK|RK3368_CORE_SEL_GPLL,
2169 RK3368_CRU_CLKSELS_CON(0));
2172 cru_writel(RK3368_CORE_CLK_DIV(temp_div), RK3368_CRU_CLKSELS_CON(0));
2173 cru_writel(RK3368_CORE_SEL_PLL_W_MSK|RK3368_CORE_SEL_GPLL,
2174 RK3368_CRU_CLKSELS_CON(0));
2177 cru_writel(RK3368_CORE_CLK_DIV(temp_div), RK3368_CRU_CLKSELS_CON(0));
2178 cru_writel(RK3368_CORE_SEL_PLL_W_MSK|RK3368_CORE_SEL_GPLL,
2179 RK3368_CRU_CLKSELS_CON(0));
2186 local_irq_restore(flags);
2188 clk_debug("temp select arm_gpll path, get rate %lu\n",
2189 arm_gpll_rate/temp_div);
2190 clk_debug("from arm_gpll rate %lu, temp_div %d\n", arm_gpll_rate,
2194 local_irq_save(flags);
2196 /* apll enter slow mode */
2197 cru_writel(_RK3188_PLL_MODE_SLOW_SET(pll->mode_shift),
2200 /* PLL enter reset */
2201 cru_writel(_RK3188PLUS_PLL_RESET_SET(1), pll->reg + RK3188_PLL_CON(3));
2203 cru_writel(ps->pllcon0, pll->reg + RK3188_PLL_CON(0));
2204 cru_writel(ps->pllcon1, pll->reg + RK3188_PLL_CON(1));
2205 cru_writel(ps->pllcon2, pll->reg + RK3188_PLL_CON(2));
2209 /* return from rest */
2210 cru_writel(_RK3188PLUS_PLL_RESET_SET(0), pll->reg + RK3188_PLL_CON(3));
2212 /* wating lock state */
2213 udelay(ps->rst_dly);
2217 if (rate >= old_rate) {
2218 cru_writel(ps->clksel0, RK3368_CRU_CLKSELS_CON(0));
2219 cru_writel(ps->clksel1, RK3368_CRU_CLKSELS_CON(1));
2223 /* apll return from slow mode */
2224 cru_writel(_RK3188_PLL_MODE_NORM_SET(pll->mode_shift),
2227 /* reparent to apll, and set div to 1 */
2229 #if RK3368_APLLB_DIV_MORE
2230 /* when rate/2 < (rate-arm_gpll_rate), we can set div to make
2231 rate change more gently */
2232 if ((temp_div == 1) && (rate > (2*arm_gpll_rate))) {
2233 cru_writel(RK3368_CORE_CLK_DIV(2), RK3368_CRU_CLKSELS_CON(0));
2235 cru_writel(RK3368_CORE_CLK_DIV(3), RK3368_CRU_CLKSELS_CON(0));
2237 cru_writel(RK3368_CORE_SEL_PLL_W_MSK|RK3368_CORE_SEL_APLL,
2238 RK3368_CRU_CLKSELS_CON(0));
2240 cru_writel(RK3368_CORE_CLK_DIV(2), RK3368_CRU_CLKSELS_CON(0));
2243 cru_writel(RK3368_CORE_SEL_PLL_W_MSK|RK3368_CORE_SEL_APLL,
2244 RK3368_CRU_CLKSELS_CON(0));
2246 cru_writel(RK3368_CORE_SEL_PLL_W_MSK|RK3368_CORE_SEL_APLL,
2247 RK3368_CRU_CLKSELS_CON(0));
2251 cru_writel(RK3368_CORE_CLK_DIV(1), RK3368_CRU_CLKSELS_CON(0));
2253 if (rate < old_rate) {
2254 cru_writel(ps->clksel0, RK3368_CRU_CLKSELS_CON(0));
2255 cru_writel(ps->clksel1, RK3368_CRU_CLKSELS_CON(1));
2260 local_irq_restore(flags);
2265 clk_debug("apll set rate %lu, con(%x,%x,%x,%x), sel(%x,%x)\n",
2267 cru_readl(pll->reg + RK3188_PLL_CON(0)),
2268 cru_readl(pll->reg + RK3188_PLL_CON(1)),
2269 cru_readl(pll->reg + RK3188_PLL_CON(2)),
2270 cru_readl(pll->reg + RK3188_PLL_CON(3)),
2271 cru_readl(RK3368_CRU_CLKSELS_CON(0)),
2272 cru_readl(RK3368_CRU_CLKSELS_CON(1)));
2277 static const struct clk_ops clk_pll_ops_3368_apllb = {
2278 .recalc_rate = clk_pll_recalc_rate_3188plus,
2279 .round_rate = clk_pll_round_rate_3368_apllb,
2280 .set_rate = clk_pll_set_rate_3368_apllb,
2283 static long clk_pll_round_rate_3368_aplll(struct clk_hw *hw, unsigned long rate,
2284 unsigned long *prate)
2286 struct clk *parent = __clk_get_parent(hw->clk);
2288 if (parent && (rate == __clk_get_rate(parent))) {
2289 clk_debug("pll %s round rate=%lu equal to parent rate\n",
2290 __clk_get_name(hw->clk), rate);
2294 return (apll_get_best_set(rate, rk3368_aplll_table)->rate);
2297 /* 1: use, 0: no use */
2298 #define RK3368_APLLL_USE_GPLL 1
2300 /* when define 1, we will set div to make rate change gently, but it will cost
2302 #define RK3368_APLLL_DIV_MORE 1
2304 static int clk_pll_set_rate_3368_aplll(struct clk_hw *hw, unsigned long rate,
2305 unsigned long parent_rate)
2307 struct clk_pll *pll = to_clk_pll(hw);
2308 struct clk *clk = hw->clk;
2309 struct clk *arm_gpll = __clk_lookup("clk_gpll");
2310 unsigned long arm_gpll_rate, temp_rate, old_rate;
2311 const struct apll_clk_set *ps;
2313 unsigned long flags;
2316 ps = apll_get_best_set(rate, rk3368_aplll_table);
2317 clk_debug("aplll will set rate %lu\n", ps->rate);
2318 clk_debug("table con:%08x,%08x,%08x, sel:%08x,%08x\n",
2319 ps->pllcon0, ps->pllcon1, ps->pllcon2,
2320 ps->clksel0, ps->clksel1);
2322 #if !RK3368_APLLL_USE_GPLL
2326 /* prepare arm_gpll before reparent clk_core to it */
2328 clk_err("clk arm_gpll is NULL!\n");
2332 arm_gpll_rate = __clk_get_rate(arm_gpll);
2333 old_rate = __clk_get_rate(clk);
2335 temp_rate = (old_rate > rate) ? old_rate : rate;
2336 temp_div = DIV_ROUND_UP(arm_gpll_rate, temp_rate);
2338 if (temp_div > RK3368_CORE_CLK_MAX_DIV) {
2339 clk_debug("temp_div %d > max_div %d\n", temp_div,
2340 RK3368_CORE_CLK_MAX_DIV);
2341 clk_debug("can't get rate %lu from arm_gpll rate %lu\n",
2342 __clk_get_rate(clk), arm_gpll_rate);
2346 local_irq_save(flags);
2348 if (rate >= old_rate) {
2349 cru_writel(ps->clksel0, RK3368_CRU_CLKSELS_CON(2));
2350 cru_writel(ps->clksel1, RK3368_CRU_CLKSELS_CON(3));
2354 #if RK3368_APLLL_DIV_MORE
2355 if (temp_div == 1) {
2356 /* when old_rate/2 < (old_rate-arm_gpll_rate),
2357 we can set div to make rate change more gently */
2358 if (old_rate > (2*arm_gpll_rate)) {
2359 cru_writel(RK3368_CORE_CLK_DIV(2), RK3368_CRU_CLKSELS_CON(2));
2361 cru_writel(RK3368_CORE_CLK_DIV(3), RK3368_CRU_CLKSELS_CON(2));
2363 cru_writel(RK3368_CORE_SEL_PLL_W_MSK|RK3368_CORE_SEL_GPLL,
2364 RK3368_CRU_CLKSELS_CON(2));
2366 cru_writel(RK3368_CORE_CLK_DIV(2), RK3368_CRU_CLKSELS_CON(2));
2368 cru_writel(RK3368_CORE_CLK_DIV(1), RK3368_CRU_CLKSELS_CON(2));
2370 cru_writel(RK3368_CORE_SEL_PLL_W_MSK|RK3368_CORE_SEL_GPLL,
2371 RK3368_CRU_CLKSELS_CON(2));
2374 cru_writel(RK3368_CORE_CLK_DIV(temp_div), RK3368_CRU_CLKSELS_CON(2));
2375 cru_writel(RK3368_CORE_SEL_PLL_W_MSK|RK3368_CORE_SEL_GPLL,
2376 RK3368_CRU_CLKSELS_CON(2));
2379 cru_writel(RK3368_CORE_CLK_DIV(temp_div), RK3368_CRU_CLKSELS_CON(2));
2380 cru_writel(RK3368_CORE_SEL_PLL_W_MSK|RK3368_CORE_SEL_GPLL,
2381 RK3368_CRU_CLKSELS_CON(2));
2388 local_irq_restore(flags);
2390 clk_debug("temp select arm_gpll path, get rate %lu\n",
2391 arm_gpll_rate/temp_div);
2392 clk_debug("from arm_gpll rate %lu, temp_div %d\n", arm_gpll_rate,
2396 local_irq_save(flags);
2398 /* apll enter slow mode */
2399 cru_writel(_RK3188_PLL_MODE_SLOW_SET(pll->mode_shift),
2402 /* PLL enter reset */
2403 cru_writel(_RK3188PLUS_PLL_RESET_SET(1), pll->reg + RK3188_PLL_CON(3));
2405 cru_writel(ps->pllcon0, pll->reg + RK3188_PLL_CON(0));
2406 cru_writel(ps->pllcon1, pll->reg + RK3188_PLL_CON(1));
2407 cru_writel(ps->pllcon2, pll->reg + RK3188_PLL_CON(2));
2411 /* return from rest */
2412 cru_writel(_RK3188PLUS_PLL_RESET_SET(0), pll->reg + RK3188_PLL_CON(3));
2414 /* wating lock state */
2415 udelay(ps->rst_dly);
2419 if (rate >= old_rate) {
2420 cru_writel(ps->clksel0, RK3368_CRU_CLKSELS_CON(2));
2421 cru_writel(ps->clksel1, RK3368_CRU_CLKSELS_CON(3));
2425 /* apll return from slow mode */
2426 cru_writel(_RK3188_PLL_MODE_NORM_SET(pll->mode_shift),
2429 /* reparent to apll, and set div to 1 */
2431 #if RK3368_APLLL_DIV_MORE
2432 /* when rate/2 < (rate-arm_gpll_rate), we can set div to make
2433 rate change more gently */
2434 if ((temp_div == 1) && (rate > (2*arm_gpll_rate))) {
2435 cru_writel(RK3368_CORE_CLK_DIV(2), RK3368_CRU_CLKSELS_CON(2));
2437 cru_writel(RK3368_CORE_CLK_DIV(3), RK3368_CRU_CLKSELS_CON(2));
2439 cru_writel(RK3368_CORE_SEL_PLL_W_MSK|RK3368_CORE_SEL_APLL,
2440 RK3368_CRU_CLKSELS_CON(2));
2442 cru_writel(RK3368_CORE_CLK_DIV(2), RK3368_CRU_CLKSELS_CON(2));
2445 cru_writel(RK3368_CORE_SEL_PLL_W_MSK|RK3368_CORE_SEL_APLL,
2446 RK3368_CRU_CLKSELS_CON(2));
2448 cru_writel(RK3368_CORE_SEL_PLL_W_MSK|RK3368_CORE_SEL_APLL,
2449 RK3368_CRU_CLKSELS_CON(2));
2453 cru_writel(RK3368_CORE_CLK_DIV(1), RK3368_CRU_CLKSELS_CON(2));
2455 if (rate < old_rate) {
2456 cru_writel(ps->clksel0, RK3368_CRU_CLKSELS_CON(2));
2457 cru_writel(ps->clksel1, RK3368_CRU_CLKSELS_CON(3));
2462 local_irq_restore(flags);
2467 clk_debug("apll set rate %lu, con(%x,%x,%x,%x), sel(%x,%x)\n",
2469 cru_readl(pll->reg + RK3188_PLL_CON(0)),
2470 cru_readl(pll->reg + RK3188_PLL_CON(1)),
2471 cru_readl(pll->reg + RK3188_PLL_CON(2)),
2472 cru_readl(pll->reg + RK3188_PLL_CON(3)),
2473 cru_readl(RK3368_CRU_CLKSELS_CON(2)),
2474 cru_readl(RK3368_CRU_CLKSELS_CON(3)));
2479 static const struct clk_ops clk_pll_ops_3368_aplll = {
2480 .recalc_rate = clk_pll_recalc_rate_3188plus,
2481 .round_rate = clk_pll_round_rate_3368_aplll,
2482 .set_rate = clk_pll_set_rate_3368_aplll,
2485 const struct clk_ops *rk_get_pll_ops(u32 pll_flags)
2487 switch (pll_flags) {
2489 return &clk_pll_ops_3188;
2491 case CLK_PLL_3188_APLL:
2492 return &clk_pll_ops_3188_apll;
2494 case CLK_PLL_3188PLUS:
2495 return &clk_pll_ops_3188plus;
2497 case CLK_PLL_3188PLUS_APLL:
2498 return &clk_pll_ops_3188plus_apll;
2500 case CLK_PLL_3288_APLL:
2501 return &clk_pll_ops_3288_apll;
2503 case CLK_PLL_3188PLUS_AUTO:
2504 return &clk_pll_ops_3188plus_auto;
2506 case CLK_PLL_3036_APLL:
2507 return &clk_pll_ops_3036_apll;
2509 case CLK_PLL_3036PLUS_AUTO:
2510 return &clk_pll_ops_3036plus_auto;
2512 case CLK_PLL_312XPLUS:
2513 return &clk_pll_ops_312xplus;
2515 case CLK_PLL_3368_APLLB:
2516 return &clk_pll_ops_3368_apllb;
2518 case CLK_PLL_3368_APLLL:
2519 return &clk_pll_ops_3368_aplll;
2521 case CLK_PLL_3368_LOW_JITTER:
2522 return &clk_pll_ops_3368_low_jitter;
2525 clk_err("%s: unknown pll_flags!\n", __func__);
2530 struct clk *rk_clk_register_pll(struct device *dev, const char *name,
2531 const char *parent_name, unsigned long flags, u32 reg,
2532 u32 width, u32 mode_offset, u8 mode_shift,
2533 u32 status_offset, u8 status_shift, u32 pll_flags,
2536 struct clk_pll *pll;
2538 struct clk_init_data init;
2541 clk_debug("%s: pll name = %s, pll_flags = 0x%x, register start!\n",
2542 __func__, name, pll_flags);
2544 /* allocate the pll */
2545 pll = kzalloc(sizeof(struct clk_pll), GFP_KERNEL);
2547 clk_err("%s: could not allocate pll clk\n", __func__);
2548 return ERR_PTR(-ENOMEM);
2553 init.parent_names = (parent_name ? &parent_name: NULL);
2554 init.num_parents = (parent_name ? 1 : 0);
2555 init.ops = rk_get_pll_ops(pll_flags);
2557 /* struct clk_pll assignments */
2560 pll->mode_offset = mode_offset;
2561 pll->mode_shift = mode_shift;
2562 pll->status_offset = status_offset;
2563 pll->status_shift = status_shift;
2564 pll->flags = pll_flags;
2566 pll->hw.init = &init;
2568 /* register the clock */
2569 clk = clk_register(dev, &pll->hw);
2574 clk_debug("%s: pll name = %s, pll_flags = 0x%x, register finish!\n",
2575 __func__, name, pll_flags);