1 #include <linux/slab.h>
3 #include <linux/rockchip/cpu.h>
9 static const struct pll_clk_set rk3188_pll_com_table[] = {
10 _RK3188_PLL_SET_CLKS(1250000, 12, 625, 1),
11 _RK3188_PLL_SET_CLKS(1200000, 1, 50, 1),
12 _RK3188_PLL_SET_CLKS(1188000, 2, 99, 1),
13 _RK3188_PLL_SET_CLKS(891000, 8, 594, 2),
14 _RK3188_PLL_SET_CLKS(768000, 1, 64, 2),
15 _RK3188_PLL_SET_CLKS(594000, 2, 198, 4),
16 _RK3188_PLL_SET_CLKS(500000, 3, 250, 4),
17 _RK3188_PLL_SET_CLKS(408000, 1, 68, 4),
18 _RK3188_PLL_SET_CLKS(396000, 1, 66, 4),
19 _RK3188_PLL_SET_CLKS(384000, 2, 128, 4),
20 _RK3188_PLL_SET_CLKS(360000, 1, 60, 4),
21 _RK3188_PLL_SET_CLKS(300000, 1, 50, 4),
22 _RK3188_PLL_SET_CLKS(297000, 2, 198, 8),
23 _RK3188_PLL_SET_CLKS(148500, 2, 99, 8),
24 _RK3188_PLL_SET_CLKS(0, 0, 0, 0),
27 static const struct pll_clk_set rk3188plus_pll_com_table[] = {
28 _RK3188PLUS_PLL_SET_CLKS(1250000, 12, 625, 1),
29 _RK3188PLUS_PLL_SET_CLKS(1200000, 1, 50, 1),
30 _RK3188PLUS_PLL_SET_CLKS(1188000, 2, 99, 1),
31 _RK3188PLUS_PLL_SET_CLKS(891000, 8, 594, 2),
32 _RK3188PLUS_PLL_SET_CLKS(768000, 1, 64, 2),
33 _RK3188PLUS_PLL_SET_CLKS(594000, 2, 198, 4),
34 _RK3188PLUS_PLL_SET_CLKS(576000, 1, 48, 2),
35 _RK3188PLUS_PLL_SET_CLKS(500000, 3, 250, 4),
36 _RK3188PLUS_PLL_SET_CLKS(408000, 1, 68, 4),
37 _RK3188PLUS_PLL_SET_CLKS(400000, 3, 200, 4),
38 _RK3188PLUS_PLL_SET_CLKS(396000, 1, 66, 4),
39 _RK3188PLUS_PLL_SET_CLKS(384000, 2, 128, 4),
40 _RK3188PLUS_PLL_SET_CLKS(360000, 1, 60, 4),
41 _RK3188PLUS_PLL_SET_CLKS(300000, 1, 50, 4),
42 _RK3188PLUS_PLL_SET_CLKS(297000, 2, 198, 8),
43 _RK3188PLUS_PLL_SET_CLKS(148500, 2, 99, 8),
44 _RK3188PLUS_PLL_SET_CLKS(0, 0, 0, 0),
47 static const struct apll_clk_set rk3188_apll_table[] = {
48 // (_mhz, nr, nf, no, _periph_div, _aclk_div)
49 _RK3188_APLL_SET_CLKS(2208, 1, 92, 1, 8, 81),
50 _RK3188_APLL_SET_CLKS(2184, 1, 91, 1, 8, 81),
51 _RK3188_APLL_SET_CLKS(2160, 1, 90, 1, 8, 81),
52 _RK3188_APLL_SET_CLKS(2136, 1, 89, 1, 8, 81),
53 _RK3188_APLL_SET_CLKS(2112, 1, 88, 1, 8, 81),
54 _RK3188_APLL_SET_CLKS(2088, 1, 87, 1, 8, 81),
55 _RK3188_APLL_SET_CLKS(2064, 1, 86, 1, 8, 81),
56 _RK3188_APLL_SET_CLKS(2040, 1, 85, 1, 8, 81),
57 _RK3188_APLL_SET_CLKS(2016, 1, 84, 1, 8, 81),
58 _RK3188_APLL_SET_CLKS(1992, 1, 83, 1, 8, 81),
59 _RK3188_APLL_SET_CLKS(1968, 1, 82, 1, 8, 81),
60 _RK3188_APLL_SET_CLKS(1944, 1, 81, 1, 8, 81),
61 _RK3188_APLL_SET_CLKS(1920, 1, 80, 1, 8, 81),
62 _RK3188_APLL_SET_CLKS(1896, 1, 79, 1, 8, 81),
63 _RK3188_APLL_SET_CLKS(1872, 1, 78, 1, 8, 81),
64 _RK3188_APLL_SET_CLKS(1848, 1, 77, 1, 8, 81),
65 _RK3188_APLL_SET_CLKS(1824, 1, 76, 1, 8, 81),
66 _RK3188_APLL_SET_CLKS(1800, 1, 75, 1, 8, 81),
67 _RK3188_APLL_SET_CLKS(1776, 1, 74, 1, 8, 81),
68 _RK3188_APLL_SET_CLKS(1752, 1, 73, 1, 8, 81),
69 _RK3188_APLL_SET_CLKS(1728, 1, 72, 1, 8, 81),
70 _RK3188_APLL_SET_CLKS(1704, 1, 71, 1, 8, 81),
71 _RK3188_APLL_SET_CLKS(1680, 1, 70, 1, 8, 41),
72 _RK3188_APLL_SET_CLKS(1656, 1, 69, 1, 8, 41),
73 _RK3188_APLL_SET_CLKS(1632, 1, 68, 1, 8, 41),
74 _RK3188_APLL_SET_CLKS(1608, 1, 67, 1, 8, 41),
75 _RK3188_APLL_SET_CLKS(1560, 1, 65, 1, 8, 41),
76 _RK3188_APLL_SET_CLKS(1512, 1, 63, 1, 8, 41),
77 _RK3188_APLL_SET_CLKS(1488, 1, 62, 1, 8, 41),
78 _RK3188_APLL_SET_CLKS(1464, 1, 61, 1, 8, 41),
79 _RK3188_APLL_SET_CLKS(1440, 1, 60, 1, 8, 41),
80 _RK3188_APLL_SET_CLKS(1416, 1, 59, 1, 8, 41),
81 _RK3188_APLL_SET_CLKS(1392, 1, 58, 1, 8, 41),
82 _RK3188_APLL_SET_CLKS(1368, 1, 57, 1, 8, 41),
83 _RK3188_APLL_SET_CLKS(1344, 1, 56, 1, 8, 41),
84 _RK3188_APLL_SET_CLKS(1320, 1, 55, 1, 8, 41),
85 _RK3188_APLL_SET_CLKS(1296, 1, 54, 1, 8, 41),
86 _RK3188_APLL_SET_CLKS(1272, 1, 53, 1, 8, 41),
87 _RK3188_APLL_SET_CLKS(1248, 1, 52, 1, 8, 41),
88 _RK3188_APLL_SET_CLKS(1224, 1, 51, 1, 8, 41),
89 _RK3188_APLL_SET_CLKS(1200, 1, 50, 1, 8, 41),
90 _RK3188_APLL_SET_CLKS(1176, 1, 49, 1, 8, 41),
91 _RK3188_APLL_SET_CLKS(1128, 1, 47, 1, 8, 41),
92 _RK3188_APLL_SET_CLKS(1104, 1, 46, 1, 8, 41),
93 _RK3188_APLL_SET_CLKS(1008, 1, 84, 2, 8, 41),
94 _RK3188_APLL_SET_CLKS(912, 1, 76, 2, 8, 41),
95 _RK3188_APLL_SET_CLKS(888, 1, 74, 2, 8, 41),
96 _RK3188_APLL_SET_CLKS(816, 1, 68, 2, 8, 41),
97 _RK3188_APLL_SET_CLKS(792, 1, 66, 2, 8, 41),
98 _RK3188_APLL_SET_CLKS(696, 1, 58, 2, 8, 41),
99 _RK3188_APLL_SET_CLKS(600, 1, 50, 2, 4, 41),
100 _RK3188_APLL_SET_CLKS(552, 1, 92, 4, 4, 41),
101 _RK3188_APLL_SET_CLKS(504, 1, 84, 4, 4, 41),
102 _RK3188_APLL_SET_CLKS(408, 1, 68, 4, 4, 21),
103 _RK3188_APLL_SET_CLKS(312, 1, 52, 4, 2, 21),
104 _RK3188_APLL_SET_CLKS(252, 1, 84, 8, 2, 21),
105 _RK3188_APLL_SET_CLKS(216, 1, 72, 8, 2, 21),
106 _RK3188_APLL_SET_CLKS(126, 1, 84, 16, 2, 11),
107 _RK3188_APLL_SET_CLKS(48, 1, 32, 16, 2, 11),
108 _RK3188_APLL_SET_CLKS(0, 1, 32, 16, 2, 11),
111 static const struct apll_clk_set rk3288_apll_table[] = {
112 // (_mhz, nr, nf, no, l2ram, m0, mp, atclk, pclk_dbg)
113 _RK3288_APLL_SET_CLKS(2208, 1, 92, 1, 2, 2, 4, 4, 4),
114 _RK3288_APLL_SET_CLKS(2184, 1, 91, 1, 2, 2, 4, 4, 4),
115 _RK3288_APLL_SET_CLKS(2160, 1, 90, 1, 2, 2, 4, 4, 4),
116 _RK3288_APLL_SET_CLKS(2136, 1, 89, 1, 2, 2, 4, 4, 4),
117 _RK3288_APLL_SET_CLKS(2112, 1, 88, 1, 2, 2, 4, 4, 4),
118 _RK3288_APLL_SET_CLKS(2088, 1, 87, 1, 2, 2, 4, 4, 4),
119 _RK3288_APLL_SET_CLKS(2064, 1, 86, 1, 2, 2, 4, 4, 4),
120 _RK3288_APLL_SET_CLKS(2040, 1, 85, 1, 2, 2, 4, 4, 4),
121 _RK3288_APLL_SET_CLKS(2016, 1, 84, 1, 2, 2, 4, 4, 4),
122 _RK3288_APLL_SET_CLKS(1992, 1, 83, 1, 2, 2, 4, 4, 4),
123 _RK3288_APLL_SET_CLKS(1968, 1, 82, 1, 2, 2, 4, 4, 4),
124 _RK3288_APLL_SET_CLKS(1944, 1, 81, 1, 2, 2, 4, 4, 4),
125 _RK3288_APLL_SET_CLKS(1920, 1, 80, 1, 2, 2, 4, 4, 4),
126 _RK3288_APLL_SET_CLKS(1896, 1, 79, 1, 2, 2, 4, 4, 4),
127 _RK3288_APLL_SET_CLKS(1872, 1, 78, 1, 2, 2, 4, 4, 4),
128 _RK3288_APLL_SET_CLKS(1848, 1, 77, 1, 2, 2, 4, 4, 4),
129 _RK3288_APLL_SET_CLKS(1824, 1, 76, 1, 2, 2, 4, 4, 4),
130 _RK3288_APLL_SET_CLKS(1800, 1, 75, 1, 2, 2, 4, 4, 4),
131 _RK3288_APLL_SET_CLKS(1776, 1, 74, 1, 2, 2, 4, 4, 4),
132 _RK3288_APLL_SET_CLKS(1752, 1, 73, 1, 2, 2, 4, 4, 4),
133 _RK3288_APLL_SET_CLKS(1728, 1, 72, 1, 2, 2, 4, 4, 4),
134 _RK3288_APLL_SET_CLKS(1704, 1, 71, 1, 2, 2, 4, 4, 4),
135 _RK3288_APLL_SET_CLKS(1680, 1, 70, 1, 2, 2, 4, 4, 4),
136 _RK3288_APLL_SET_CLKS(1656, 1, 69, 1, 2, 2, 4, 4, 4),
137 _RK3288_APLL_SET_CLKS(1632, 1, 68, 1, 2, 2, 4, 4, 4),
138 _RK3288_APLL_SET_CLKS(1608, 1, 67, 1, 2, 2, 4, 4, 4),
139 _RK3288_APLL_SET_CLKS(1560, 1, 65, 1, 2, 2, 4, 4, 4),
140 _RK3288_APLL_SET_CLKS(1512, 1, 63, 1, 2, 2, 4, 4, 4),
141 _RK3288_APLL_SET_CLKS(1488, 1, 62, 1, 2, 2, 4, 4, 4),
142 _RK3288_APLL_SET_CLKS(1464, 1, 61, 1, 2, 2, 4, 4, 4),
143 _RK3288_APLL_SET_CLKS(1440, 1, 60, 1, 2, 2, 4, 4, 4),
144 _RK3288_APLL_SET_CLKS(1416, 1, 59, 1, 2, 2, 4, 4, 4),
145 _RK3288_APLL_SET_CLKS(1392, 1, 58, 1, 2, 2, 4, 4, 4),
146 _RK3288_APLL_SET_CLKS(1368, 1, 57, 1, 2, 2, 4, 4, 4),
147 _RK3288_APLL_SET_CLKS(1344, 1, 56, 1, 2, 2, 4, 4, 4),
148 _RK3288_APLL_SET_CLKS(1320, 1, 55, 1, 2, 2, 4, 4, 4),
149 _RK3288_APLL_SET_CLKS(1296, 1, 54, 1, 2, 2, 4, 4, 4),
150 _RK3288_APLL_SET_CLKS(1272, 1, 53, 1, 2, 2, 4, 4, 4),
151 _RK3288_APLL_SET_CLKS(1248, 1, 52, 1, 2, 2, 4, 4, 4),
152 _RK3288_APLL_SET_CLKS(1224, 1, 51, 1, 2, 2, 4, 4, 4),
153 _RK3288_APLL_SET_CLKS(1200, 1, 50, 1, 2, 2, 4, 4, 4),
154 _RK3288_APLL_SET_CLKS(1176, 1, 49, 1, 2, 2, 4, 4, 4),
155 _RK3288_APLL_SET_CLKS(1128, 1, 47, 1, 2, 2, 4, 4, 4),
156 _RK3288_APLL_SET_CLKS(1104, 1, 46, 1, 2, 2, 4, 4, 4),
157 _RK3288_APLL_SET_CLKS(1008, 1, 84, 2, 2, 2, 4, 4, 4),
158 _RK3288_APLL_SET_CLKS(912, 1, 76, 2, 2, 2, 4, 4, 4),
159 _RK3288_APLL_SET_CLKS(888, 1, 74, 2, 2, 2, 4, 4, 4),
160 _RK3288_APLL_SET_CLKS(816, 1, 68, 2, 2, 2, 4, 4, 4),
161 _RK3288_APLL_SET_CLKS(792, 1, 66, 2, 2, 2, 4, 4, 4),
162 _RK3288_APLL_SET_CLKS(696, 1, 58, 2, 2, 2, 4, 4, 4),
163 _RK3288_APLL_SET_CLKS(672, 1, 56, 2, 2, 2, 4, 4, 4),
164 _RK3288_APLL_SET_CLKS(648, 1, 54, 2, 2, 2, 4, 4, 4),
165 _RK3288_APLL_SET_CLKS(624, 1, 52, 2, 2, 2, 4, 4, 4),
166 _RK3288_APLL_SET_CLKS(600, 1, 50, 2, 2, 2, 4, 4, 4),
167 _RK3288_APLL_SET_CLKS(576, 1, 48, 2, 2, 2, 4, 4, 4),
168 _RK3288_APLL_SET_CLKS(552, 1, 92, 4, 2, 2, 4, 4, 4),
169 _RK3288_APLL_SET_CLKS(528, 1, 88, 4, 2, 2, 4, 4, 4),
170 _RK3288_APLL_SET_CLKS(504, 1, 84, 4, 2, 2, 4, 4, 4),
171 _RK3288_APLL_SET_CLKS(480, 1, 80, 4, 2, 2, 4, 4, 4),
172 _RK3288_APLL_SET_CLKS(456, 1, 76, 4, 2, 2, 4, 4, 4),
173 _RK3288_APLL_SET_CLKS(408, 1, 68, 4, 2, 2, 4, 4, 4),
174 _RK3288_APLL_SET_CLKS(312, 1, 52, 4, 2, 2, 4, 4, 4),
175 _RK3288_APLL_SET_CLKS(252, 1, 84, 8, 2, 2, 4, 4, 4),
176 _RK3288_APLL_SET_CLKS(216, 1, 72, 8, 2, 2, 4, 4, 4),
177 _RK3288_APLL_SET_CLKS(126, 2, 84, 8, 2, 2, 4, 4, 4),
178 _RK3288_APLL_SET_CLKS(48, 2, 32, 8, 2, 2, 4, 4, 4),
179 _RK3288_APLL_SET_CLKS(0, 1, 32, 16, 2, 2, 4, 4, 4),
182 static const struct apll_clk_set rk3036_apll_table[] = {
183 _RK3036_APLL_SET_CLKS(1608, 1, 67, 1, 1, 1, 0, 81),
184 _RK3036_APLL_SET_CLKS(1584, 1, 66, 1, 1, 1, 0, 81),
185 _RK3036_APLL_SET_CLKS(1560, 1, 65, 1, 1, 1, 0, 81),
186 _RK3036_APLL_SET_CLKS(1536, 1, 64, 1, 1, 1, 0, 81),
187 _RK3036_APLL_SET_CLKS(1512, 1, 63, 1, 1, 1, 0, 81),
188 _RK3036_APLL_SET_CLKS(1488, 1, 62, 1, 1, 1, 0, 81),
189 _RK3036_APLL_SET_CLKS(1464, 1, 61, 1, 1, 1, 0, 81),
190 _RK3036_APLL_SET_CLKS(1440, 1, 60, 1, 1, 1, 0, 81),
191 _RK3036_APLL_SET_CLKS(1416, 1, 59, 1, 1, 1, 0, 81),
192 _RK3036_APLL_SET_CLKS(1392, 1, 58, 1, 1, 1, 0, 81),
193 _RK3036_APLL_SET_CLKS(1368, 1, 57, 1, 1, 1, 0, 81),
194 _RK3036_APLL_SET_CLKS(1344, 1, 56, 1, 1, 1, 0, 81),
195 _RK3036_APLL_SET_CLKS(1320, 1, 55, 1, 1, 1, 0, 81),
196 _RK3036_APLL_SET_CLKS(1296, 1, 54, 1, 1, 1, 0, 81),
197 _RK3036_APLL_SET_CLKS(1272, 1, 53, 1, 1, 1, 0, 81),
198 _RK3036_APLL_SET_CLKS(1248, 1, 52, 1, 1, 1, 0, 81),
199 _RK3036_APLL_SET_CLKS(1200, 1, 50, 1, 1, 1, 0, 81),
200 _RK3036_APLL_SET_CLKS(1104, 1, 46, 1, 1, 1, 0, 81),
201 _RK3036_APLL_SET_CLKS(1100, 12, 550, 1, 1, 1, 0, 81),
202 _RK3036_APLL_SET_CLKS(1008, 1, 84, 2, 1, 1, 0, 81),
203 _RK3036_APLL_SET_CLKS(1000, 6, 500, 2, 1, 1, 0, 81),
204 _RK3036_APLL_SET_CLKS(984, 1, 82, 2, 1, 1, 0, 81),
205 _RK3036_APLL_SET_CLKS(960, 1, 80, 2, 1, 1, 0, 81),
206 _RK3036_APLL_SET_CLKS(936, 1, 78, 2, 1, 1, 0, 81),
207 _RK3036_APLL_SET_CLKS(912, 1, 76, 2, 1, 1, 0, 41),
208 _RK3036_APLL_SET_CLKS(900, 4, 300, 2, 1, 1, 0, 41),
209 _RK3036_APLL_SET_CLKS(888, 1, 74, 2, 1, 1, 0, 41),
210 _RK3036_APLL_SET_CLKS(864, 1, 72, 2, 1, 1, 0, 41),
211 _RK3036_APLL_SET_CLKS(840, 1, 70, 2, 1, 1, 0, 41),
212 _RK3036_APLL_SET_CLKS(816, 1, 68, 2, 1, 1, 0, 41),
213 _RK3036_APLL_SET_CLKS(800, 6, 400, 2, 1, 1, 0, 41),
214 _RK3036_APLL_SET_CLKS(700, 6, 350, 2, 1, 1, 0, 41),
215 _RK3036_APLL_SET_CLKS(696, 1, 58, 2, 1, 1, 0, 41),
216 _RK3036_APLL_SET_CLKS(600, 1, 75, 3, 1, 1, 0, 41),
217 _RK3036_APLL_SET_CLKS(504, 1, 63, 3, 1, 1, 0, 41),
218 _RK3036_APLL_SET_CLKS(500, 6, 250, 2, 1, 1, 0, 41),
219 _RK3036_APLL_SET_CLKS(408, 1, 68, 2, 2, 1, 0, 41),
220 _RK3036_APLL_SET_CLKS(312, 1, 52, 2, 2, 1, 0, 41),
221 _RK3036_APLL_SET_CLKS(216, 1, 72, 4, 2, 1, 0, 41),
222 _RK3036_APLL_SET_CLKS(96, 1, 64, 4, 4, 1, 0, 21),
223 _RK3036_APLL_SET_CLKS(0, 1, 0, 1, 1, 1, 0, 21),
226 static const struct pll_clk_set rk3036plus_pll_com_table[] = {
227 _RK3036_PLL_SET_CLKS(1188000, 2, 99, 1, 1, 1, 0),
228 _RK3036_PLL_SET_CLKS(594000, 2, 99, 2, 1, 1, 0),
229 /*_RK3036_PLL_SET_CLKS(297000, 2, 99, 4, 1, 1, 0),*/
232 static const struct pll_clk_set rk312xplus_pll_com_table[] = {
233 /*_RK3036_PLL_SET_CLKS(1064000, 3, 133, 1, 1, 1, 0),*/
234 /*_RK3036_PLL_SET_CLKS(798000, 2, 133, 2, 1, 1, 0),*/
235 _RK3036_PLL_SET_CLKS(1000000, 3, 125, 1, 1, 1, 0),
236 _RK3036_PLL_SET_CLKS(594000, 2, 99, 2, 1, 1, 0),
237 _RK3036_PLL_SET_CLKS(500000, 3, 125, 2, 1, 1, 0),
238 _RK3036_PLL_SET_CLKS(400000, 3, 200, 2, 2, 1, 0),
241 static const struct apll_clk_set rk3368_apllb_table[] = {
242 /*(_mhz, nr, nf, no, aclkm, atclk, pclk_dbg)*/
243 _RK3368_APLL_SET_CLKS(1608, 1, 67, 1, 2, 6, 6),
244 _RK3368_APLL_SET_CLKS(1560, 1, 65, 1, 2, 6, 6),
245 _RK3368_APLL_SET_CLKS(1512, 1, 63, 1, 2, 6, 6),
246 _RK3368_APLL_SET_CLKS(1488, 1, 62, 1, 2, 5, 5),
247 _RK3368_APLL_SET_CLKS(1464, 1, 61, 1, 2, 5, 5),
248 _RK3368_APLL_SET_CLKS(1440, 1, 60, 1, 2, 5, 5),
249 _RK3368_APLL_SET_CLKS(1416, 1, 59, 1, 2, 5, 5),
250 _RK3368_APLL_SET_CLKS(1392, 1, 58, 1, 2, 5, 5),
251 _RK3368_APLL_SET_CLKS(1368, 1, 57, 1, 2, 5, 5),
252 _RK3368_APLL_SET_CLKS(1344, 1, 56, 1, 2, 5, 5),
253 _RK3368_APLL_SET_CLKS(1320, 1, 55, 1, 2, 5, 5),
254 _RK3368_APLL_SET_CLKS(1296, 1, 54, 1, 2, 5, 5),
255 _RK3368_APLL_SET_CLKS(1272, 1, 53, 1, 2, 5, 5),
256 _RK3368_APLL_SET_CLKS(1248, 1, 52, 1, 2, 5, 5),
257 _RK3368_APLL_SET_CLKS(1224, 1, 51, 1, 2, 5, 5),
258 _RK3368_APLL_SET_CLKS(1200, 1, 50, 1, 2, 4, 4),
259 _RK3368_APLL_SET_CLKS(1176, 1, 49, 1, 2, 4, 4),
260 _RK3368_APLL_SET_CLKS(1128, 1, 47, 1, 2, 4, 4),
261 _RK3368_APLL_SET_CLKS(1104, 1, 46, 1, 2, 4, 4),
262 _RK3368_APLL_SET_CLKS(1008, 1, 84, 2, 2, 4, 4),
263 _RK3368_APLL_SET_CLKS(912, 1, 76, 2, 2, 4, 4),
264 _RK3368_APLL_SET_CLKS(888, 1, 74, 2, 2, 3, 3),
265 _RK3368_APLL_SET_CLKS(816, 1, 68, 2, 2, 3, 3),
266 _RK3368_APLL_SET_CLKS(792, 1, 66, 2, 2, 3, 3),
267 _RK3368_APLL_SET_CLKS(696, 1, 58, 2, 2, 3, 3),
268 _RK3368_APLL_SET_CLKS(672, 1, 56, 2, 2, 3, 3),
269 _RK3368_APLL_SET_CLKS(648, 1, 54, 2, 2, 3, 3),
270 _RK3368_APLL_SET_CLKS(624, 1, 52, 2, 2, 3, 3),
271 _RK3368_APLL_SET_CLKS(600, 1, 50, 2, 2, 2, 2),
272 _RK3368_APLL_SET_CLKS(576, 1, 48, 2, 2, 2, 2),
273 _RK3368_APLL_SET_CLKS(552, 1, 92, 4, 2, 2, 2),
274 _RK3368_APLL_SET_CLKS(528, 1, 88, 4, 2, 2, 2),
275 _RK3368_APLL_SET_CLKS(504, 1, 84, 4, 2, 2, 2),
276 _RK3368_APLL_SET_CLKS(480, 1, 80, 4, 2, 2, 2),
277 _RK3368_APLL_SET_CLKS(456, 1, 76, 4, 2, 2, 2),
278 _RK3368_APLL_SET_CLKS(408, 1, 68, 4, 2, 2, 2),
279 _RK3368_APLL_SET_CLKS(312, 1, 52, 4, 2, 2, 2),
280 _RK3368_APLL_SET_CLKS(252, 1, 84, 8, 2, 1, 1),
281 _RK3368_APLL_SET_CLKS(216, 1, 72, 8, 2, 1, 1),
282 _RK3368_APLL_SET_CLKS(126, 2, 84, 8, 2, 1, 1),
283 _RK3368_APLL_SET_CLKS(48, 2, 32, 8, 2, 1, 1),
284 _RK3368_APLL_SET_CLKS(0, 1, 32, 16, 2, 1, 1),
287 static const struct apll_clk_set rk3368_aplll_table[] = {
288 /*(_mhz, nr, nf, no, aclkm, atclk, pclk_dbg)*/
289 _RK3368_APLL_SET_CLKS(1608, 1, 67, 1, 2, 7, 7),
290 _RK3368_APLL_SET_CLKS(1560, 1, 65, 1, 2, 7, 7),
291 _RK3368_APLL_SET_CLKS(1512, 1, 63, 1, 2, 7, 7),
292 _RK3368_APLL_SET_CLKS(1488, 1, 62, 1, 2, 6, 6),
293 _RK3368_APLL_SET_CLKS(1464, 1, 61, 1, 2, 6, 6),
294 _RK3368_APLL_SET_CLKS(1440, 1, 60, 1, 2, 6, 6),
295 _RK3368_APLL_SET_CLKS(1416, 1, 59, 1, 2, 6, 6),
296 _RK3368_APLL_SET_CLKS(1392, 1, 58, 1, 2, 6, 6),
297 _RK3368_APLL_SET_CLKS(1368, 1, 57, 1, 2, 6, 6),
298 _RK3368_APLL_SET_CLKS(1344, 1, 56, 1, 2, 6, 6),
299 _RK3368_APLL_SET_CLKS(1320, 1, 55, 1, 2, 6, 6),
300 _RK3368_APLL_SET_CLKS(1296, 1, 54, 1, 2, 6, 6),
301 _RK3368_APLL_SET_CLKS(1272, 1, 53, 1, 2, 6, 6),
302 _RK3368_APLL_SET_CLKS(1248, 1, 52, 1, 2, 5, 5),
303 _RK3368_APLL_SET_CLKS(1224, 1, 51, 1, 2, 5, 5),
304 _RK3368_APLL_SET_CLKS(1200, 1, 50, 1, 2, 5, 5),
305 _RK3368_APLL_SET_CLKS(1176, 1, 49, 1, 2, 5, 5),
306 _RK3368_APLL_SET_CLKS(1128, 1, 47, 1, 2, 5, 5),
307 _RK3368_APLL_SET_CLKS(1104, 1, 46, 1, 2, 5, 5),
308 _RK3368_APLL_SET_CLKS(1008, 1, 84, 2, 2, 5, 5),
309 _RK3368_APLL_SET_CLKS(912, 1, 76, 2, 2, 4, 4),
310 _RK3368_APLL_SET_CLKS(888, 1, 74, 2, 2, 4, 4),
311 _RK3368_APLL_SET_CLKS(816, 1, 68, 2, 2, 4, 4),
312 _RK3368_APLL_SET_CLKS(792, 1, 66, 2, 2, 4, 4),
313 _RK3368_APLL_SET_CLKS(696, 1, 58, 2, 2, 3, 3),
314 _RK3368_APLL_SET_CLKS(672, 1, 56, 2, 2, 3, 3),
315 _RK3368_APLL_SET_CLKS(648, 1, 54, 2, 2, 3, 3),
316 _RK3368_APLL_SET_CLKS(624, 1, 52, 2, 2, 3, 3),
317 _RK3368_APLL_SET_CLKS(600, 1, 50, 2, 2, 3, 3),
318 _RK3368_APLL_SET_CLKS(576, 1, 48, 2, 2, 3, 3),
319 _RK3368_APLL_SET_CLKS(552, 1, 92, 4, 2, 3, 3),
320 _RK3368_APLL_SET_CLKS(528, 1, 88, 4, 2, 3, 3),
321 _RK3368_APLL_SET_CLKS(504, 1, 84, 4, 2, 3, 3),
322 _RK3368_APLL_SET_CLKS(480, 1, 80, 4, 2, 2, 2),
323 _RK3368_APLL_SET_CLKS(456, 1, 76, 4, 2, 2, 2),
324 _RK3368_APLL_SET_CLKS(408, 1, 68, 4, 2, 2, 2),
325 _RK3368_APLL_SET_CLKS(312, 1, 52, 4, 2, 2, 2),
326 _RK3368_APLL_SET_CLKS(252, 1, 84, 8, 2, 2, 2),
327 _RK3368_APLL_SET_CLKS(216, 1, 72, 8, 2, 1, 1),
328 _RK3368_APLL_SET_CLKS(126, 2, 84, 8, 2, 1, 1),
329 _RK3368_APLL_SET_CLKS(48, 2, 32, 8, 2, 1, 1),
330 _RK3368_APLL_SET_CLKS(0, 1, 32, 16, 2, 1, 1),
333 static const struct pll_clk_set rk3368_pll_table_low_jitter[] = {
334 /* _khz, nr, nf, no, nb */
335 _RK3188PLUS_PLL_SET_CLKS_NB(1188000, 1, 99, 2, 1),
336 _RK3188PLUS_PLL_SET_CLKS_NB(400000, 1, 100, 6, 1),
337 _RK3188PLUS_PLL_SET_CLKS( 0, 0, 0, 0),
340 static void pll_wait_lock(struct clk_hw *hw)
342 struct clk_pll *pll = to_clk_pll(hw);
343 int delay = 24000000;
346 if (grf_readl(pll->status_offset) & (1 << pll->status_shift))
352 clk_err("pll %s: can't lock! status_shift=%u\n"
353 "pll_con0=%08x\npll_con1=%08x\n"
354 "pll_con2=%08x\npll_con3=%08x\n",
355 __clk_get_name(hw->clk),
357 cru_readl(pll->reg + RK3188_PLL_CON(0)),
358 cru_readl(pll->reg + RK3188_PLL_CON(1)),
359 cru_readl(pll->reg + RK3188_PLL_CON(2)),
360 cru_readl(pll->reg + RK3188_PLL_CON(3)));
366 static void rk3036_pll_wait_lock(struct clk_hw *hw)
368 struct clk_pll *pll = to_clk_pll(hw);
369 int delay = 24000000;
373 if (cru_readl(pll->status_offset) & (1 << pll->status_shift))
379 clk_err("pll %s: can't lock! status_shift=%u\n"
380 "pll_con0=%08x\npll_con1=%08x\n"
382 __clk_get_name(hw->clk),
384 cru_readl(pll->reg + RK3188_PLL_CON(0)),
385 cru_readl(pll->reg + RK3188_PLL_CON(1)),
386 cru_readl(pll->reg + RK3188_PLL_CON(2)));
393 /* get rate that is most close to target */
394 static const struct apll_clk_set *apll_get_best_set(unsigned long rate,
395 const struct apll_clk_set *table)
397 const struct apll_clk_set *ps, *pt;
401 if (pt->rate == rate) {
406 if ((pt->rate > rate || (rate - pt->rate < ps->rate - rate)))
416 /* get rate that is most close to target */
417 static const struct pll_clk_set *pll_com_get_best_set(unsigned long rate,
418 const struct pll_clk_set *table)
420 const struct pll_clk_set *ps, *pt;
424 if (pt->rate == rate) {
429 if ((pt->rate > rate || (rate - pt->rate < ps->rate - rate)))
439 /* CLK_PLL_3188 type ops */
440 static unsigned long clk_pll_recalc_rate_3188(struct clk_hw *hw,
441 unsigned long parent_rate)
443 struct clk_pll *pll = to_clk_pll(hw);
447 if (_RK3188_PLL_MODE_IS_NORM(pll->mode_offset, pll->mode_shift)) {
448 u32 pll_con0 = cru_readl(pll->reg + RK3188_PLL_CON(0));
449 u32 pll_con1 = cru_readl(pll->reg + RK3188_PLL_CON(1));
451 u64 rate64 = (u64)parent_rate * RK3188_PLL_NF(pll_con1);
453 do_div(rate64, RK3188_PLL_NR(pll_con0));
454 do_div(rate64, RK3188_PLL_NO(pll_con0));
460 clk_debug("pll %s is in slow mode\n", __clk_get_name(hw->clk));
463 clk_debug("pll %s recalc rate =%lu\n", __clk_get_name(hw->clk), rate);
468 static long clk_pll_round_rate_3188(struct clk_hw *hw, unsigned long rate,
469 unsigned long *prate)
471 struct clk *parent = __clk_get_parent(hw->clk);
473 if (parent && (rate==__clk_get_rate(parent))) {
474 clk_debug("pll %s round rate=%lu equal to parent rate\n",
475 __clk_get_name(hw->clk), rate);
479 return (pll_com_get_best_set(rate, rk3188_pll_com_table)->rate);
482 static int _pll_clk_set_rate_3188(struct pll_clk_set *clk_set,
485 struct clk_pll *pll = to_clk_pll(hw);
486 unsigned long flags = 0;
489 clk_debug("%s start!\n", __func__);
492 spin_lock_irqsave(pll->lock, flags);
495 cru_writel(_RK3188_PLL_MODE_SLOW_SET(pll->mode_shift), pll->mode_offset);
497 cru_writel((0x1 << (16+1)) | (0x1<<1), pll->reg + RK3188_PLL_CON(3));
504 cru_writel(clk_set->pllcon0, pll->reg + RK3188_PLL_CON(0));
505 cru_writel(clk_set->pllcon1, pll->reg + RK3188_PLL_CON(1));
510 cru_writel((0x1<<(16+1)), pll->reg + RK3188_PLL_CON(3));
515 cru_writel(_RK3188_PLL_MODE_NORM_SET(pll->mode_shift), pll->mode_offset);
518 spin_unlock_irqrestore(pll->lock, flags);
520 clk_debug("pll %s dump reg: con0=0x%08x, con1=0x%08x, mode=0x%08x\n",
521 __clk_get_name(hw->clk),
522 cru_readl(pll->reg + RK3188_PLL_CON(0)),
523 cru_readl(pll->reg + RK3188_PLL_CON(1)),
524 cru_readl(pll->mode_offset));
526 clk_debug("%s end!\n", __func__);
531 static int clk_pll_set_rate_3188(struct clk_hw *hw, unsigned long rate,
532 unsigned long parent_rate)
534 struct clk_pll *pll = to_clk_pll(hw);
535 struct pll_clk_set *clk_set = (struct pll_clk_set *)(rk3188_pll_com_table);
539 if (rate == parent_rate) {
540 clk_debug("pll %s set rate=%lu equal to parent rate\n",
541 __clk_get_name(hw->clk), rate);
542 cru_writel(_RK3188_PLL_MODE_SLOW_SET(pll->mode_shift),
545 cru_writel((0x1 << (16+1)) | (0x1<<1), pll->reg + RK3188_PLL_CON(3));
546 clk_debug("pll %s enter slow mode, set rate OK!\n",
547 __clk_get_name(hw->clk));
551 while(clk_set->rate) {
552 if (clk_set->rate == rate) {
558 if (clk_set->rate == rate) {
559 ret = _pll_clk_set_rate_3188(clk_set, hw);
560 clk_debug("pll %s set rate=%lu OK!\n", __clk_get_name(hw->clk),
563 clk_err("pll %s is no corresponding rate=%lu\n",
564 __clk_get_name(hw->clk), rate);
571 static const struct clk_ops clk_pll_ops_3188 = {
572 .recalc_rate = clk_pll_recalc_rate_3188,
573 .round_rate = clk_pll_round_rate_3188,
574 .set_rate = clk_pll_set_rate_3188,
578 /* CLK_PLL_3188_APLL type ops */
579 static unsigned long clk_pll_recalc_rate_3188_apll(struct clk_hw *hw,
580 unsigned long parent_rate)
582 return clk_pll_recalc_rate_3188(hw, parent_rate);
585 static long clk_pll_round_rate_3188_apll(struct clk_hw *hw, unsigned long rate,
586 unsigned long *prate)
588 struct clk *parent = __clk_get_parent(hw->clk);
590 if (parent && (rate==__clk_get_rate(parent))) {
591 clk_debug("pll %s round rate=%lu equal to parent rate\n",
592 __clk_get_name(hw->clk), rate);
596 return (apll_get_best_set(rate, rk3188_apll_table)->rate);
599 /* 1: use, 0: no use */
600 #define RK3188_USE_ARM_GPLL 1
602 static int clk_pll_set_rate_3188_apll(struct clk_hw *hw, unsigned long rate,
603 unsigned long parent_rate)
605 struct clk_pll *pll = to_clk_pll(hw);
606 struct clk *clk = hw->clk;
607 struct clk *arm_gpll = __clk_lookup("clk_arm_gpll");
608 unsigned long arm_gpll_rate;
609 const struct apll_clk_set *ps;
610 u32 old_aclk_div = 0, new_aclk_div = 0;
616 if (rate == parent_rate) {
617 clk_debug("pll %s set rate=%lu equal to parent rate\n",
618 __clk_get_name(hw->clk), rate);
619 cru_writel(_RK3188_PLL_MODE_SLOW_SET(pll->mode_shift),
622 cru_writel((0x1 << (16+1)) | (0x1<<1), pll->reg + RK3188_PLL_CON(3));
623 clk_debug("pll %s enter slow mode, set rate OK!\n",
624 __clk_get_name(hw->clk));
629 #if !RK3188_USE_ARM_GPLL
633 /* prepare arm_gpll before reparent clk_core to it */
635 clk_err("clk arm_gpll is NULL!\n");
639 /* In rk3188, arm_gpll and cpu_gpll share a same gate,
640 * and aclk_cpu selects cpu_gpll as parent, thus this
641 * gate must keep enabled.
644 if (clk_prepare(arm_gpll)) {
645 clk_err("fail to prepare arm_gpll path\n");
646 clk_unprepare(arm_gpll);
650 if (clk_enable(arm_gpll)) {
651 clk_err("fail to enable arm_gpll path\n");
652 clk_disable(arm_gpll);
653 clk_unprepare(arm_gpll);
658 arm_gpll_rate = __clk_get_rate(arm_gpll);
659 temp_div = DIV_ROUND_UP(arm_gpll_rate, __clk_get_rate(clk));
660 temp_div = (temp_div == 0) ? 1 : temp_div;
661 if (temp_div > RK3188_CORE_CLK_MAX_DIV) {
662 clk_debug("temp_div %d > max_div %d\n", temp_div,
663 RK3188_CORE_CLK_MAX_DIV);
664 clk_debug("can't get rate %lu from arm_gpll rate %lu\n",
665 __clk_get_rate(clk), arm_gpll_rate);
666 //clk_disable(arm_gpll);
667 //clk_unprepare(arm_gpll);
671 local_irq_save(flags);
673 /* firstly set div, then select arm_gpll path */
674 cru_writel(RK3188_CORE_CLK_DIV_W_MSK|RK3188_CORE_CLK_DIV(temp_div),
675 RK3188_CRU_CLKSELS_CON(0));
676 cru_writel(RK3188_CORE_SEL_PLL_W_MSK|RK3188_CORE_SEL_GPLL,
677 RK3188_CRU_CLKSELS_CON(0));
680 //loops_per_jiffy = CLK_LOOPS_RECALC(arm_gpll_rate) / temp_div;
683 local_irq_restore(flags);
685 clk_debug("temp select arm_gpll path, get rate %lu\n",
686 arm_gpll_rate/temp_div);
687 clk_debug("from arm_gpll rate %lu, temp_div %d\n", arm_gpll_rate,
691 ps = apll_get_best_set(rate, rk3188_apll_table);
692 clk_debug("apll will set rate %lu\n", ps->rate);
693 clk_debug("table con:%08x,%08x,%08x, sel:%08x,%08x\n",
694 ps->pllcon0, ps->pllcon1, ps->pllcon2,
695 ps->clksel0, ps->clksel1);
697 local_irq_save(flags);
699 /* If core src don't select gpll, apll need to enter slow mode
704 cru_writel(_RK3188_PLL_MODE_SLOW_SET(pll->mode_shift), pll->mode_offset);
707 cru_writel((0x1 << (16+1)) | (0x1<<1), pll->reg + RK3188_PLL_CON(3));
714 cru_writel(ps->pllcon0, pll->reg + RK3188_PLL_CON(0));
715 cru_writel(ps->pllcon1, pll->reg + RK3188_PLL_CON(1));
719 /* PLL power up and wait for locked */
720 cru_writel((0x1<<(16+1)), pll->reg + RK3188_PLL_CON(3));
723 old_aclk_div = RK3188_GET_CORE_ACLK_VAL(cru_readl(RK3188_CRU_CLKSELS_CON(1)) &
724 RK3188_CORE_ACLK_MSK);
725 new_aclk_div = RK3188_GET_CORE_ACLK_VAL(ps->clksel1 & RK3188_CORE_ACLK_MSK);
727 if (new_aclk_div >= old_aclk_div) {
728 cru_writel(ps->clksel0, RK3188_CRU_CLKSELS_CON(0));
729 cru_writel(ps->clksel1, RK3188_CRU_CLKSELS_CON(1));
732 /* PLL return from slow mode */
735 cru_writel(_RK3188_PLL_MODE_NORM_SET(pll->mode_shift), pll->mode_offset);
737 /* reparent to apll, and set div to 1 */
739 cru_writel(RK3188_CORE_SEL_PLL_W_MSK|RK3188_CORE_SEL_APLL,
740 RK3188_CRU_CLKSELS_CON(0));
741 cru_writel(RK3188_CORE_CLK_DIV_W_MSK|RK3188_CORE_CLK_DIV(1),
742 RK3188_CRU_CLKSELS_CON(0));
745 if (old_aclk_div > new_aclk_div) {
746 cru_writel(ps->clksel0, RK3188_CRU_CLKSELS_CON(0));
747 cru_writel(ps->clksel1, RK3188_CRU_CLKSELS_CON(1));
750 //loops_per_jiffy = ps->lpj;
753 local_irq_restore(flags);
757 //clk_disable(arm_gpll);
758 //clk_unprepare(arm_gpll);
761 //clk_debug("apll set loops_per_jiffy =%lu\n", loops_per_jiffy);
763 clk_debug("apll set rate %lu, con(%x,%x,%x,%x), sel(%x,%x)\n",
765 cru_readl(pll->reg + RK3188_PLL_CON(0)),
766 cru_readl(pll->reg + RK3188_PLL_CON(1)),
767 cru_readl(pll->reg + RK3188_PLL_CON(2)),
768 cru_readl(pll->reg + RK3188_PLL_CON(3)),
769 cru_readl(RK3188_CRU_CLKSELS_CON(0)),
770 cru_readl(RK3188_CRU_CLKSELS_CON(1)));
775 static const struct clk_ops clk_pll_ops_3188_apll = {
776 .recalc_rate = clk_pll_recalc_rate_3188_apll,
777 .round_rate = clk_pll_round_rate_3188_apll,
778 .set_rate = clk_pll_set_rate_3188_apll,
782 /* CLK_PLL_3188PLUS type ops */
783 static unsigned long clk_pll_recalc_rate_3188plus(struct clk_hw *hw,
784 unsigned long parent_rate)
786 struct clk_pll *pll = to_clk_pll(hw);
790 if (_RK3188_PLL_MODE_IS_NORM(pll->mode_offset, pll->mode_shift)) {
791 u32 pll_con0 = cru_readl(pll->reg + RK3188_PLL_CON(0));
792 u32 pll_con1 = cru_readl(pll->reg + RK3188_PLL_CON(1));
794 u64 rate64 = (u64)parent_rate * RK3188PLUS_PLL_NF(pll_con1);
796 do_div(rate64, RK3188PLUS_PLL_NR(pll_con0));
797 do_div(rate64, RK3188PLUS_PLL_NO(pll_con0));
803 clk_debug("pll %s is in slow mode\n", __clk_get_name(hw->clk));
806 clk_debug("pll %s recalc rate =%lu\n", __clk_get_name(hw->clk), rate);
811 static long clk_pll_round_rate_3188plus(struct clk_hw *hw, unsigned long rate,
812 unsigned long *prate)
814 struct clk *parent = __clk_get_parent(hw->clk);
816 if (parent && (rate==__clk_get_rate(parent))) {
817 clk_debug("pll %s round rate=%lu equal to parent rate\n",
818 __clk_get_name(hw->clk), rate);
822 return (pll_com_get_best_set(rate, rk3188plus_pll_com_table)->rate);
825 static int _pll_clk_set_rate_3188plus(struct pll_clk_set *clk_set,
828 struct clk_pll *pll = to_clk_pll(hw);
829 unsigned long flags = 0;
832 clk_debug("%s start!\n", __func__);
835 spin_lock_irqsave(pll->lock, flags);
838 cru_writel(_RK3188_PLL_MODE_SLOW_SET(pll->mode_shift), pll->mode_offset);
841 cru_writel(_RK3188PLUS_PLL_RESET_SET(1), pll->reg + RK3188_PLL_CON(3));
843 cru_writel(clk_set->pllcon0, pll->reg + RK3188_PLL_CON(0));
844 cru_writel(clk_set->pllcon1, pll->reg + RK3188_PLL_CON(1));
845 cru_writel(clk_set->pllcon2, pll->reg + RK3188_PLL_CON(2));
850 cru_writel(_RK3188PLUS_PLL_RESET_SET(0), pll->reg + RK3188_PLL_CON(3));
853 udelay(clk_set->rst_dly);
858 cru_writel(_RK3188_PLL_MODE_NORM_SET(pll->mode_shift), pll->mode_offset);
861 spin_unlock_irqrestore(pll->lock, flags);
863 clk_debug("pll %s dump reg: con0=0x%08x, con1=0x%08x, mode=0x%08x\n",
864 __clk_get_name(hw->clk),
865 cru_readl(pll->reg + RK3188_PLL_CON(0)),
866 cru_readl(pll->reg + RK3188_PLL_CON(1)),
867 cru_readl(pll->mode_offset));
869 clk_debug("%s end!\n", __func__);
874 static int clk_pll_set_rate_3188plus(struct clk_hw *hw, unsigned long rate,
875 unsigned long parent_rate)
877 //struct clk_pll *pll = to_clk_pll(hw);
878 struct pll_clk_set *clk_set = (struct pll_clk_set *)(rk3188plus_pll_com_table);
882 if (rate == parent_rate) {
883 clk_debug("pll %s set rate=%lu equal to parent rate\n",
884 __clk_get_name(hw->clk), rate);
885 cru_writel(_RK3188_PLL_MODE_SLOW_SET(pll->mode_shift),
888 cru_writel((0x1 << (16+1)) | (0x1<<1), pll->reg + RK3188_PLL_CON(3));
889 clk_debug("pll %s enter slow mode, set rate OK!\n",
890 __clk_get_name(hw->clk));
895 while(clk_set->rate) {
896 if (clk_set->rate == rate) {
902 if (cpu_is_rk3288() && ((rate == 297*MHZ) || (rate == 594*MHZ))) {
903 if((strncmp(__clk_get_name(hw->clk), "clk_gpll",
904 strlen("clk_gpll")) == 0)) {
906 printk("rk3288 set GPLL BW 20 for HDMI!\n");
907 clk_set->pllcon2 = RK3188_PLL_CLK_BWADJ_SET(20);
911 if (clk_set->rate == rate) {
912 ret = _pll_clk_set_rate_3188plus(clk_set, hw);
913 clk_debug("pll %s set rate=%lu OK!\n", __clk_get_name(hw->clk),
916 clk_err("pll %s is no corresponding rate=%lu\n",
917 __clk_get_name(hw->clk), rate);
924 static int clk_pll_is_enabled_3188plus(struct clk_hw *hw)
927 struct clk_pll *pll = to_clk_pll(hw);
931 spin_lock_irqsave(pll->lock, flags);
933 if (_RK3188_PLL_MODE_IS_NORM(pll->mode_offset, pll->mode_shift))
939 spin_unlock_irqrestore(pll->lock, flags);
944 static int clk_pll_enable_3188plus(struct clk_hw *hw)
946 struct clk_pll *pll = to_clk_pll(hw);
948 unsigned long rst_dly;
951 clk_debug("%s enter\n", __func__);
953 if (clk_pll_is_enabled_3188plus(hw)) {
954 clk_debug("pll has been enabled\n");
959 spin_lock_irqsave(pll->lock, flags);
962 cru_writel(_RK3188_PLL_MODE_SLOW_SET(pll->mode_shift), pll->mode_offset);
965 cru_writel(_RK3188PLUS_PLL_POWERDOWN_SET(0), pll->reg + RK3188_PLL_CON(3));
968 cru_writel(_RK3188PLUS_PLL_RESET_SET(1), pll->reg + RK3188_PLL_CON(3));
970 //cru_writel(clk_set->pllcon0, pll->reg + RK3188_PLL_CON(0));
971 //cru_writel(clk_set->pllcon1, pll->reg + RK3188_PLL_CON(1));
972 //cru_writel(clk_set->pllcon2, pll->reg + RK3188_PLL_CON(2));
977 cru_writel(_RK3188PLUS_PLL_RESET_SET(0), pll->reg + RK3188_PLL_CON(3));
980 nr = RK3188PLUS_PLL_NR(cru_readl(pll->reg + RK3188_PLL_CON(0)));
981 rst_dly = ((nr*500)/24+1);
987 cru_writel(_RK3188_PLL_MODE_NORM_SET(pll->mode_shift), pll->mode_offset);
990 spin_unlock_irqrestore(pll->lock, flags);
992 clk_debug("pll %s dump reg:\n con0=0x%08x,\n con1=0x%08x,\n con2=0x%08x,\n"
993 "con3=0x%08x,\n mode=0x%08x\n",
994 __clk_get_name(hw->clk),
995 cru_readl(pll->reg + RK3188_PLL_CON(0)),
996 cru_readl(pll->reg + RK3188_PLL_CON(1)),
997 cru_readl(pll->reg + RK3188_PLL_CON(2)),
998 cru_readl(pll->reg + RK3188_PLL_CON(3)),
999 cru_readl(pll->mode_offset));
1004 static void clk_pll_disable_3188plus(struct clk_hw *hw)
1006 struct clk_pll *pll = to_clk_pll(hw);
1007 unsigned long flags;
1009 clk_debug("%s enter\n", __func__);
1012 spin_lock_irqsave(pll->lock, flags);
1015 cru_writel(_RK3188_PLL_MODE_SLOW_SET(pll->mode_shift), pll->mode_offset);
1018 cru_writel(_RK3188PLUS_PLL_POWERDOWN_SET(1), pll->reg + RK3188_PLL_CON(3));
1021 spin_unlock_irqrestore(pll->lock, flags);
1024 static const struct clk_ops clk_pll_ops_3188plus = {
1025 .recalc_rate = clk_pll_recalc_rate_3188plus,
1026 .round_rate = clk_pll_round_rate_3188plus,
1027 .set_rate = clk_pll_set_rate_3188plus,
1028 .enable = clk_pll_enable_3188plus,
1029 .disable = clk_pll_disable_3188plus,
1030 .is_enabled = clk_pll_is_enabled_3188plus,
1033 /* CLK_PLL_3188PLUS_AUTO type ops */
1034 #define PLL_FREF_MIN (269*KHZ)
1035 #define PLL_FREF_MAX (2200*MHZ)
1037 #define PLL_FVCO_MIN (440*MHZ)
1038 #define PLL_FVCO_MAX (2200*MHZ)
1040 #define PLL_FOUT_MIN (27500*KHZ)
1041 #define PLL_FOUT_MAX (2200*MHZ)
1043 #define PLL_NF_MAX (4096)
1044 #define PLL_NR_MAX (64)
1045 #define PLL_NO_MAX (16)
1047 static u32 clk_gcd(u32 numerator, u32 denominator)
1051 if (!numerator || !denominator)
1053 if (numerator > denominator) {
1070 static int pll_clk_get_best_set(unsigned long fin_hz, unsigned long fout_hz,
1071 u32 *best_nr, u32 *best_nf, u32 *best_no)
1073 u32 nr, nf, no, nonr;
1074 u32 nr_out, nf_out, no_out;
1078 u64 fref, fvco, fout;
1081 nr_out = PLL_NR_MAX + 1;
1084 if (!fin_hz || !fout_hz || fout_hz == fin_hz)
1086 gcd_val = clk_gcd(fin_hz, fout_hz);
1088 YFfenzi = fout_hz / gcd_val;
1089 YFfenmu = fin_hz / gcd_val;
1094 if (nf > PLL_NF_MAX || nonr > (PLL_NO_MAX * PLL_NR_MAX))
1097 for (no = 1; no <= PLL_NO_MAX; no++) {
1098 if (!(no == 1 || !(no % 2)))
1105 if (nr > PLL_NR_MAX)
1109 if (fref < PLL_FREF_MIN || fref > PLL_FREF_MAX)
1113 if (fvco < PLL_FVCO_MIN || fvco > PLL_FVCO_MAX)
1117 if (fout < PLL_FOUT_MIN || fout > PLL_FOUT_MAX)
1120 /* select the best from all available PLL settings */
1121 if ((no > no_out) || ((no == no_out) && (nr < nr_out))) {
1129 /* output the best PLL setting */
1130 if ((nr_out <= PLL_NR_MAX) && (no_out > 0)) {
1131 if (best_nr && best_nf && best_no) {
1142 static unsigned long clk_pll_recalc_rate_3188plus_auto(struct clk_hw *hw,
1143 unsigned long parent_rate)
1145 return clk_pll_recalc_rate_3188plus(hw, parent_rate);
1148 static long clk_pll_round_rate_3188plus_auto(struct clk_hw *hw, unsigned long rate,
1149 unsigned long *prate)
1153 for(best=rate; best>0; best--){
1154 if(!pll_clk_get_best_set(*prate, best, NULL, NULL, NULL))
1161 static int clk_pll_set_rate_3188plus_auto(struct clk_hw *hw, unsigned long rate,
1162 unsigned long parent_rate)
1166 struct pll_clk_set clk_set;
1170 best = clk_pll_round_rate_3188plus_auto(hw, rate, &parent_rate);
1175 pll_clk_get_best_set(parent_rate, best, &nr, &nf, &no);
1177 /* prepare clk_set */
1178 clk_set.rate = best;
1179 clk_set.pllcon0 = RK3188PLUS_PLL_CLKR_SET(nr)|RK3188PLUS_PLL_CLKOD_SET(no);
1180 clk_set.pllcon1 = RK3188PLUS_PLL_CLKF_SET(nf);
1181 clk_set.pllcon2 = RK3188PLUS_PLL_CLK_BWADJ_SET(nf >> 1);
1182 clk_set.rst_dly = ((nr*500)/24+1);
1184 ret = _pll_clk_set_rate_3188plus(&clk_set, hw);
1185 clk_debug("pll %s set rate=%lu OK!\n", __clk_get_name(hw->clk), best);
1191 static const struct clk_ops clk_pll_ops_3188plus_auto = {
1192 .recalc_rate = clk_pll_recalc_rate_3188plus_auto,
1193 .round_rate = clk_pll_round_rate_3188plus_auto,
1194 .set_rate = clk_pll_set_rate_3188plus_auto,
1195 .enable = clk_pll_enable_3188plus,
1196 .disable = clk_pll_disable_3188plus,
1197 .is_enabled = clk_pll_is_enabled_3188plus,
1200 static long clk_pll_round_rate_3368_low_jitter(struct clk_hw *hw,
1202 unsigned long *prate)
1205 struct pll_clk_set *p_clk_set;
1207 p_clk_set = (struct pll_clk_set *)(rk3368_pll_table_low_jitter);
1209 while (p_clk_set->rate) {
1210 if (p_clk_set->rate == rate)
1215 if (p_clk_set->rate == rate) {
1216 clk_debug("get rate from table\n");
1220 for (best = rate; best > 0; best--) {
1221 if (!pll_clk_get_best_set(*prate, best, NULL, NULL, NULL))
1225 clk_err("%s: can't round rate %lu\n", __func__, rate);
1230 static int clk_pll_set_rate_3368_low_jitter(struct clk_hw *hw,
1232 unsigned long parent_rate)
1236 struct pll_clk_set clk_set, *p_clk_set;
1239 p_clk_set = (struct pll_clk_set *)(rk3368_pll_table_low_jitter);
1241 while (p_clk_set->rate) {
1242 if (p_clk_set->rate == rate)
1247 if (p_clk_set->rate == rate) {
1248 clk_debug("get rate from table\n");
1252 best = clk_pll_round_rate_3188plus_auto(hw, rate, &parent_rate);
1257 pll_clk_get_best_set(parent_rate, best, &nr, &nf, &no);
1259 /* prepare clk_set */
1260 clk_set.rate = best;
1261 clk_set.pllcon0 = RK3188PLUS_PLL_CLKR_SET(nr)|RK3188PLUS_PLL_CLKOD_SET(no);
1262 clk_set.pllcon1 = RK3188PLUS_PLL_CLKF_SET(nf);
1263 clk_set.pllcon2 = RK3188PLUS_PLL_CLK_BWADJ_SET(nf >> 1);
1264 clk_set.rst_dly = ((nr*500)/24+1);
1266 p_clk_set = &clk_set;
1269 ret = _pll_clk_set_rate_3188plus(p_clk_set, hw);
1270 clk_debug("pll %s set rate=%lu OK!\n", __clk_get_name(hw->clk),
1276 static const struct clk_ops clk_pll_ops_3368_low_jitter = {
1277 .recalc_rate = clk_pll_recalc_rate_3188plus_auto,
1278 .round_rate = clk_pll_round_rate_3368_low_jitter,
1279 .set_rate = clk_pll_set_rate_3368_low_jitter,
1280 .enable = clk_pll_enable_3188plus,
1281 .disable = clk_pll_disable_3188plus,
1282 .is_enabled = clk_pll_is_enabled_3188plus,
1285 /* CLK_PLL_3188PLUS_APLL type ops */
1286 static unsigned long clk_pll_recalc_rate_3188plus_apll(struct clk_hw *hw,
1287 unsigned long parent_rate)
1289 return clk_pll_recalc_rate_3188plus(hw, parent_rate);
1292 static long clk_pll_round_rate_3188plus_apll(struct clk_hw *hw, unsigned long rate,
1293 unsigned long *prate)
1295 return clk_pll_round_rate_3188_apll(hw, rate, prate);
1298 /* 1: use, 0: no use */
1299 #define RK3188PLUS_USE_ARM_GPLL 1
1301 static int clk_pll_set_rate_3188plus_apll(struct clk_hw *hw, unsigned long rate,
1302 unsigned long parent_rate)
1304 struct clk_pll *pll = to_clk_pll(hw);
1305 struct clk *clk = hw->clk;
1306 struct clk *arm_gpll = __clk_lookup("clk_arm_gpll");
1307 unsigned long arm_gpll_rate;
1308 const struct apll_clk_set *ps;
1309 u32 old_aclk_div = 0, new_aclk_div = 0;
1311 unsigned long flags;
1315 if (rate == parent_rate) {
1316 clk_debug("pll %s set rate=%lu equal to parent rate\n",
1317 __clk_get_name(hw->clk), rate);
1318 cru_writel(_RK3188_PLL_MODE_SLOW_SET(pll->mode_shift),
1320 /* pll power down */
1321 cru_writel((0x1 << (16+1)) | (0x1<<1), pll->reg + RK3188_PLL_CON(3));
1322 clk_debug("pll %s enter slow mode, set rate OK!\n",
1323 __clk_get_name(hw->clk));
1329 #if !RK3188PLUS_USE_ARM_GPLL
1333 /* prepare arm_gpll before reparent clk_core to it */
1335 clk_err("clk arm_gpll is NULL!\n");
1339 /* In rk3188plus, arm_gpll and cpu_gpll share a same gate,
1340 * and aclk_cpu selects cpu_gpll as parent, thus this
1341 * gate must keep enabled.
1344 if (clk_prepare(arm_gpll)) {
1345 clk_err("fail to prepare arm_gpll path\n");
1346 clk_unprepare(arm_gpll);
1350 if (clk_enable(arm_gpll)) {
1351 clk_err("fail to enable arm_gpll path\n");
1352 clk_disable(arm_gpll);
1353 clk_unprepare(arm_gpll);
1358 arm_gpll_rate = __clk_get_rate(arm_gpll);
1359 temp_div = DIV_ROUND_UP(arm_gpll_rate, __clk_get_rate(clk));
1360 temp_div = (temp_div == 0) ? 1 : temp_div;
1361 if (temp_div > RK3188_CORE_CLK_MAX_DIV) {
1362 clk_debug("temp_div %d > max_div %d\n", temp_div,
1363 RK3188_CORE_CLK_MAX_DIV);
1364 clk_debug("can't get rate %lu from arm_gpll rate %lu\n",
1365 __clk_get_rate(clk), arm_gpll_rate);
1366 //clk_disable(arm_gpll);
1367 //clk_unprepare(arm_gpll);
1371 local_irq_save(flags);
1373 /* firstly set div, then select arm_gpll path */
1374 cru_writel(RK3188_CORE_CLK_DIV_W_MSK|RK3188_CORE_CLK_DIV(temp_div),
1375 RK3188_CRU_CLKSELS_CON(0));
1376 cru_writel(RK3188_CORE_SEL_PLL_W_MSK|RK3188_CORE_SEL_GPLL,
1377 RK3188_CRU_CLKSELS_CON(0));
1380 //loops_per_jiffy = CLK_LOOPS_RECALC(arm_gpll_rate) / temp_div;
1383 local_irq_restore(flags);
1385 clk_debug("temp select arm_gpll path, get rate %lu\n",
1386 arm_gpll_rate/temp_div);
1387 clk_debug("from arm_gpll rate %lu, temp_div %d\n", arm_gpll_rate,
1391 ps = apll_get_best_set(rate, rk3188_apll_table);
1392 clk_debug("apll will set rate %lu\n", ps->rate);
1393 clk_debug("table con:%08x,%08x,%08x, sel:%08x,%08x\n",
1394 ps->pllcon0, ps->pllcon1, ps->pllcon2,
1395 ps->clksel0, ps->clksel1);
1397 local_irq_save(flags);
1399 /* If core src don't select gpll, apll need to enter slow mode
1404 cru_writel(_RK3188_PLL_MODE_SLOW_SET(pll->mode_shift), pll->mode_offset);
1406 /* PLL enter rest */
1407 cru_writel(_RK3188PLUS_PLL_RESET_SET(1), pll->reg + RK3188_PLL_CON(3));
1409 cru_writel(ps->pllcon0, pll->reg + RK3188_PLL_CON(0));
1410 cru_writel(ps->pllcon1, pll->reg + RK3188_PLL_CON(1));
1411 cru_writel(ps->pllcon2, pll->reg + RK3188_PLL_CON(2));
1415 /* return from rest */
1416 cru_writel(_RK3188PLUS_PLL_RESET_SET(0), pll->reg + RK3188_PLL_CON(3));
1419 udelay(ps->rst_dly);
1422 old_aclk_div = RK3188_GET_CORE_ACLK_VAL(cru_readl(RK3188_CRU_CLKSELS_CON(1)) &
1423 RK3188_CORE_ACLK_MSK);
1424 new_aclk_div = RK3188_GET_CORE_ACLK_VAL(ps->clksel1 & RK3188_CORE_ACLK_MSK);
1426 if (new_aclk_div >= old_aclk_div) {
1427 cru_writel(ps->clksel0, RK3188_CRU_CLKSELS_CON(0));
1428 cru_writel(ps->clksel1, RK3188_CRU_CLKSELS_CON(1));
1431 /* PLL return from slow mode */
1434 cru_writel(_RK3188_PLL_MODE_NORM_SET(pll->mode_shift), pll->mode_offset);
1436 /* reparent to apll, and set div to 1 */
1438 cru_writel(RK3188_CORE_SEL_PLL_W_MSK|RK3188_CORE_SEL_APLL,
1439 RK3188_CRU_CLKSELS_CON(0));
1440 cru_writel(RK3188_CORE_CLK_DIV_W_MSK|RK3188_CORE_CLK_DIV(1),
1441 RK3188_CRU_CLKSELS_CON(0));
1444 if (old_aclk_div > new_aclk_div) {
1445 cru_writel(ps->clksel0, RK3188_CRU_CLKSELS_CON(0));
1446 cru_writel(ps->clksel1, RK3188_CRU_CLKSELS_CON(1));
1449 //loops_per_jiffy = ps->lpj;
1452 local_irq_restore(flags);
1456 //clk_disable(arm_gpll);
1457 //clk_unprepare(arm_gpll);
1460 //clk_debug("apll set loops_per_jiffy =%lu\n", loops_per_jiffy);
1462 clk_debug("apll set rate %lu, con(%x,%x,%x,%x), sel(%x,%x)\n",
1464 cru_readl(pll->reg + RK3188_PLL_CON(0)),
1465 cru_readl(pll->reg + RK3188_PLL_CON(1)),
1466 cru_readl(pll->reg + RK3188_PLL_CON(2)),
1467 cru_readl(pll->reg + RK3188_PLL_CON(3)),
1468 cru_readl(RK3188_CRU_CLKSELS_CON(0)),
1469 cru_readl(RK3188_CRU_CLKSELS_CON(1)));
1474 static const struct clk_ops clk_pll_ops_3188plus_apll = {
1475 .recalc_rate = clk_pll_recalc_rate_3188plus_apll,
1476 .round_rate = clk_pll_round_rate_3188plus_apll,
1477 .set_rate = clk_pll_set_rate_3188plus_apll,
1480 /* CLK_PLL_3288_APLL type ops */
1481 static unsigned long clk_pll_recalc_rate_3288_apll(struct clk_hw *hw,
1482 unsigned long parent_rate)
1484 return clk_pll_recalc_rate_3188plus(hw, parent_rate);
1487 static long clk_pll_round_rate_3288_apll(struct clk_hw *hw, unsigned long rate,
1488 unsigned long *prate)
1490 struct clk *parent = __clk_get_parent(hw->clk);
1492 if (parent && (rate==__clk_get_rate(parent))) {
1493 clk_debug("pll %s round rate=%lu equal to parent rate\n",
1494 __clk_get_name(hw->clk), rate);
1498 return (apll_get_best_set(rate, rk3288_apll_table)->rate);
1501 /* 1: use, 0: no use */
1502 #define RK3288_USE_ARM_GPLL 1
1504 static int clk_pll_set_rate_3288_apll(struct clk_hw *hw, unsigned long rate,
1505 unsigned long parent_rate)
1507 struct clk_pll *pll = to_clk_pll(hw);
1508 struct clk *clk = hw->clk;
1509 struct clk *arm_gpll = __clk_lookup("clk_arm_gpll");
1510 unsigned long arm_gpll_rate, temp_rate, old_rate;
1511 const struct apll_clk_set *ps;
1512 // u32 old_aclk_div = 0, new_aclk_div = 0;
1514 unsigned long flags;
1519 if (rate == parent_rate) {
1520 clk_debug("pll %s set rate=%lu equal to parent rate\n",
1521 __clk_get_name(hw->clk), rate);
1522 cru_writel(_RK3188_PLL_MODE_SLOW_SET(pll->mode_shift),
1524 /* pll power down */
1525 cru_writel((0x1 << (16+1)) | (0x1<<1), pll->reg + RK3188_PLL_CON(3));
1526 clk_debug("pll %s enter slow mode, set rate OK!\n",
1527 __clk_get_name(hw->clk));
1532 #if !RK3288_USE_ARM_GPLL
1536 /* prepare arm_gpll before reparent clk_core to it */
1538 clk_err("clk arm_gpll is NULL!\n");
1542 arm_gpll_rate = __clk_get_rate(arm_gpll);
1543 old_rate = __clk_get_rate(clk);
1545 temp_rate = (old_rate > rate) ? old_rate : rate;
1546 temp_div = DIV_ROUND_UP(arm_gpll_rate, temp_rate);
1548 if (temp_div > RK3288_CORE_CLK_MAX_DIV) {
1549 clk_debug("temp_div %d > max_div %d\n", temp_div,
1550 RK3288_CORE_CLK_MAX_DIV);
1551 clk_debug("can't get rate %lu from arm_gpll rate %lu\n",
1552 __clk_get_rate(clk), arm_gpll_rate);
1557 if (clk_prepare(arm_gpll)) {
1558 clk_err("fail to prepare arm_gpll path\n");
1559 clk_unprepare(arm_gpll);
1563 if (clk_enable(arm_gpll)) {
1564 clk_err("fail to enable arm_gpll path\n");
1565 clk_disable(arm_gpll);
1566 clk_unprepare(arm_gpll);
1571 local_irq_save(flags);
1574 if (temp_div == 1) {
1575 /* when old_rate/2 < (old_rate-arm_gpll_rate),
1576 we can set div to make rate change more gently */
1577 if (old_rate > (2*arm_gpll_rate)) {
1578 cru_writel(RK3288_CORE_CLK_DIV(2), RK3288_CRU_CLKSELS_CON(0));
1580 cru_writel(RK3288_CORE_CLK_DIV(3), RK3288_CRU_CLKSELS_CON(0));
1582 cru_writel(RK3288_CORE_SEL_PLL_W_MSK|RK3288_CORE_SEL_GPLL,
1583 RK3288_CRU_CLKSELS_CON(0));
1585 cru_writel(RK3288_CORE_CLK_DIV(2), RK3288_CRU_CLKSELS_CON(0));
1587 cru_writel(RK3288_CORE_CLK_DIV(1), RK3288_CRU_CLKSELS_CON(0));
1589 cru_writel(RK3288_CORE_SEL_PLL_W_MSK|RK3288_CORE_SEL_GPLL,
1590 RK3288_CRU_CLKSELS_CON(0));
1593 cru_writel(RK3288_CORE_CLK_DIV(temp_div), RK3288_CRU_CLKSELS_CON(0));
1594 cru_writel(RK3288_CORE_SEL_PLL_W_MSK|RK3288_CORE_SEL_GPLL,
1595 RK3288_CRU_CLKSELS_CON(0));
1599 //loops_per_jiffy = CLK_LOOPS_RECALC(arm_gpll_rate) / temp_div;
1602 local_irq_restore(flags);
1604 clk_debug("temp select arm_gpll path, get rate %lu\n",
1605 arm_gpll_rate/temp_div);
1606 clk_debug("from arm_gpll rate %lu, temp_div %d\n", arm_gpll_rate,
1610 ps = apll_get_best_set(rate, rk3288_apll_table);
1611 clk_debug("apll will set rate %lu\n", ps->rate);
1612 clk_debug("table con:%08x,%08x,%08x, sel:%08x,%08x\n",
1613 ps->pllcon0, ps->pllcon1, ps->pllcon2,
1614 ps->clksel0, ps->clksel1);
1616 local_irq_save(flags);
1618 /* If core src don't select gpll, apll need to enter slow mode
1623 cru_writel(_RK3188_PLL_MODE_SLOW_SET(pll->mode_shift), pll->mode_offset);
1625 /* PLL enter rest */
1626 cru_writel(_RK3188PLUS_PLL_RESET_SET(1), pll->reg + RK3188_PLL_CON(3));
1628 cru_writel(ps->pllcon0, pll->reg + RK3188_PLL_CON(0));
1629 cru_writel(ps->pllcon1, pll->reg + RK3188_PLL_CON(1));
1630 cru_writel(ps->pllcon2, pll->reg + RK3188_PLL_CON(2));
1634 /* return from rest */
1635 cru_writel(_RK3188PLUS_PLL_RESET_SET(0), pll->reg + RK3188_PLL_CON(3));
1638 udelay(ps->rst_dly);
1641 if (rate >= __clk_get_rate(hw->clk)) {
1642 cru_writel(ps->clksel0, RK3288_CRU_CLKSELS_CON(0));
1643 cru_writel(ps->clksel1, RK3288_CRU_CLKSELS_CON(37));
1646 /* PLL return from slow mode */
1649 cru_writel(_RK3188_PLL_MODE_NORM_SET(pll->mode_shift), pll->mode_offset);
1651 /* reparent to apll, and set div to 1 */
1653 if (temp_div == 1) {
1654 /* when rate/2 < (rate-arm_gpll_rate),
1655 we can set div to make rate change more gently */
1656 if (rate > (2*arm_gpll_rate)) {
1657 cru_writel(RK3288_CORE_CLK_DIV(2), RK3288_CRU_CLKSELS_CON(0));
1659 cru_writel(RK3288_CORE_CLK_DIV(3), RK3288_CRU_CLKSELS_CON(0));
1661 cru_writel(RK3288_CORE_SEL_PLL_W_MSK|RK3288_CORE_SEL_APLL,
1662 RK3288_CRU_CLKSELS_CON(0));
1664 cru_writel(RK3288_CORE_CLK_DIV(2), RK3288_CRU_CLKSELS_CON(0));
1666 cru_writel(RK3288_CORE_CLK_DIV(1), RK3288_CRU_CLKSELS_CON(0));
1668 cru_writel(RK3288_CORE_SEL_PLL_W_MSK|RK3288_CORE_SEL_APLL,
1669 RK3288_CRU_CLKSELS_CON(0));
1672 cru_writel(RK3288_CORE_SEL_PLL_W_MSK|RK3288_CORE_SEL_APLL,
1673 RK3288_CRU_CLKSELS_CON(0));
1674 cru_writel(RK3288_CORE_CLK_DIV(1), RK3288_CRU_CLKSELS_CON(0));
1678 if (rate < __clk_get_rate(hw->clk)) {
1679 cru_writel(ps->clksel0, RK3288_CRU_CLKSELS_CON(0));
1680 cru_writel(ps->clksel1, RK3288_CRU_CLKSELS_CON(37));
1683 //loops_per_jiffy = ps->lpj;
1686 local_irq_restore(flags);
1690 //clk_disable(arm_gpll);
1691 //clk_unprepare(arm_gpll);
1694 //clk_debug("apll set loops_per_jiffy =%lu\n", loops_per_jiffy);
1696 clk_debug("apll set rate %lu, con(%x,%x,%x,%x), sel(%x,%x)\n",
1698 cru_readl(pll->reg + RK3188_PLL_CON(0)),
1699 cru_readl(pll->reg + RK3188_PLL_CON(1)),
1700 cru_readl(pll->reg + RK3188_PLL_CON(2)),
1701 cru_readl(pll->reg + RK3188_PLL_CON(3)),
1702 cru_readl(RK3288_CRU_CLKSELS_CON(0)),
1703 cru_readl(RK3288_CRU_CLKSELS_CON(1)));
1709 static const struct clk_ops clk_pll_ops_3288_apll = {
1710 .recalc_rate = clk_pll_recalc_rate_3288_apll,
1711 .round_rate = clk_pll_round_rate_3288_apll,
1712 .set_rate = clk_pll_set_rate_3288_apll,
1715 /* CLK_PLL_3036_APLL type ops */
1717 static unsigned long rk3036_pll_clk_recalc(struct clk_hw *hw,
1718 unsigned long parent_rate)
1720 struct clk_pll *pll = to_clk_pll(hw);
1722 unsigned int dsmp = 0;
1723 u64 rate64 = 0, frac_rate64 = 0;
1725 dsmp = RK3036_PLL_GET_DSMPD(cru_readl(pll->reg + RK3188_PLL_CON(1)));
1727 if (_RK3188_PLL_MODE_IS_NORM(pll->mode_offset, pll->mode_shift)) {
1728 u32 pll_con0 = cru_readl(pll->reg + RK3188_PLL_CON(0));
1729 u32 pll_con1 = cru_readl(pll->reg + RK3188_PLL_CON(1));
1730 u32 pll_con2 = cru_readl(pll->reg + RK3188_PLL_CON(2));
1732 rate64 = (u64)parent_rate * RK3036_PLL_GET_FBDIV(pll_con0);
1733 do_div(rate64, RK3036_PLL_GET_REFDIV(pll_con1));
1735 if (FRAC_MODE == dsmp) {
1737 frac_rate64 = (u64)parent_rate
1738 * RK3036_PLL_GET_FRAC(pll_con2);
1739 do_div(frac_rate64, RK3036_PLL_GET_REFDIV(pll_con1));
1740 rate64 += frac_rate64 >> 24;
1741 clk_debug("%s frac_rate=%llu(%08x/2^24) by pass mode\n",
1742 __func__, frac_rate64 >> 24,
1743 RK3036_PLL_GET_FRAC(pll_con2));
1745 do_div(rate64, RK3036_PLL_GET_POSTDIV1(pll_con0));
1746 do_div(rate64, RK3036_PLL_GET_POSTDIV2(pll_con1));
1751 clk_debug("pll_clk_recalc rate=%lu by pass mode\n", rate);
1756 static unsigned long clk_pll_recalc_rate_3036_apll(struct clk_hw *hw,
1757 unsigned long parent_rate)
1759 return rk3036_pll_clk_recalc(hw, parent_rate);
1762 static long clk_pll_round_rate_3036_apll(struct clk_hw *hw, unsigned long rate,
1763 unsigned long *prate)
1765 struct clk *parent = __clk_get_parent(hw->clk);
1767 if (parent && (rate == __clk_get_rate(parent))) {
1768 clk_debug("pll %s round rate=%lu equal to parent rate\n",
1769 __clk_get_name(hw->clk), rate);
1773 return (apll_get_best_set(rate, rk3036_apll_table)->rate);
1776 static int rk3036_pll_clk_set_rate(struct pll_clk_set *clk_set,
1779 struct clk_pll *pll = to_clk_pll(hw);
1782 cru_writel(_RK3188_PLL_MODE_SLOW_SET(pll->mode_shift),
1785 cru_writel(clk_set->pllcon0, pll->reg + RK3188_PLL_CON(0));
1786 cru_writel(clk_set->pllcon1, pll->reg + RK3188_PLL_CON(1));
1787 cru_writel(clk_set->pllcon2, pll->reg + RK3188_PLL_CON(2));
1789 clk_debug("pllcon0%08x\n", cru_readl(pll->reg + RK3188_PLL_CON(0)));
1790 clk_debug("pllcon1%08x\n", cru_readl(pll->reg + RK3188_PLL_CON(1)));
1791 clk_debug("pllcon2%08x\n", cru_readl(pll->reg + RK3188_PLL_CON(2)));
1792 /*wating lock state*/
1793 udelay(clk_set->rst_dly);
1794 rk3036_pll_wait_lock(hw);
1796 /*return form slow*/
1797 cru_writel(_RK3188_PLL_MODE_NORM_SET(pll->mode_shift),
1803 #define MIN_FOUTVCO_FREQ (400 * 1000 * 1000)
1804 #define MAX_FOUTVCO_FREQ (1600 * 1000 * 1000)
1805 static int rk3036_pll_clk_set_postdiv(unsigned long fout_hz,
1806 u32 *postdiv1, u32 *postdiv2, u32 *foutvco)
1808 if (fout_hz < MIN_FOUTVCO_FREQ) {
1809 for (*postdiv1 = 1; *postdiv1 <= 7; (*postdiv1)++)
1810 for (*postdiv2 = 1; *postdiv2 <= 7; (*postdiv2)++) {
1811 if (fout_hz * (*postdiv1) * (*postdiv2)
1812 >= MIN_FOUTVCO_FREQ && fout_hz
1813 * (*postdiv1) * (*postdiv2)
1814 <= MAX_FOUTVCO_FREQ) {
1815 *foutvco = fout_hz * (*postdiv1)
1820 clk_debug("CANNOT FINE postdiv1/2 to make fout in range from 400M to 1600M, fout = %lu\n",
1829 static int rk3036_pll_clk_get_set(unsigned long fin_hz, unsigned long fout_hz,
1830 u32 *refdiv, u32 *fbdiv, u32 *postdiv1,
1831 u32 *postdiv2, u32 *frac)
1833 /* FIXME set postdiv1/2 always 1*/
1834 u32 gcd, foutvco = fout_hz;
1835 u64 fin_64, frac_64;
1838 if (!fin_hz || !fout_hz || fout_hz == fin_hz)
1841 rk3036_pll_clk_set_postdiv(fout_hz, postdiv1, postdiv2, &foutvco);
1842 if (fin_hz / MHZ * MHZ == fin_hz && fout_hz / MHZ * MHZ == fout_hz) {
1845 gcd = clk_gcd(fin_hz, foutvco);
1846 *refdiv = fin_hz / gcd;
1847 *fbdiv = foutvco / gcd;
1851 clk_debug("fin=%lu,fout=%lu,gcd=%u,refdiv=%u,fbdiv=%u,postdiv1=%u,postdiv2=%u,frac=%u\n",
1852 fin_hz, fout_hz, gcd, *refdiv, *fbdiv, *postdiv1, *postdiv2, *frac);
1854 clk_debug("******frac div running, fin_hz=%lu, fout_hz=%lu,fin_INT_mhz=%lu, fout_INT_mhz=%lu\n",
1855 fin_hz, fout_hz, fin_hz / MHZ * MHZ, fout_hz / MHZ * MHZ);
1856 clk_debug("******frac get postdiv1=%u, postdiv2=%u,foutvco=%u\n",
1857 *postdiv1, *postdiv2, foutvco);
1858 gcd = clk_gcd(fin_hz / MHZ, foutvco / MHZ);
1859 *refdiv = fin_hz / MHZ / gcd;
1860 *fbdiv = foutvco / MHZ / gcd;
1861 clk_debug("******frac get refdiv=%u, fbdiv=%u\n", *refdiv, *fbdiv);
1865 f_frac = (foutvco % MHZ);
1867 do_div(fin_64, (u64)*refdiv);
1868 frac_64 = (u64)f_frac << 24;
1869 do_div(frac_64, fin_64);
1870 *frac = (u32) frac_64;
1871 clk_debug("frac=%x\n", *frac);
1875 static int rk3036_pll_set_con(struct clk_hw *hw, u32 refdiv, u32 fbdiv, u32 postdiv1, u32 postdiv2, u32 frac)
1877 struct pll_clk_set temp_clk_set;
1878 temp_clk_set.pllcon0 = RK3036_PLL_SET_FBDIV(fbdiv) | RK3036_PLL_SET_POSTDIV1(postdiv1);
1879 temp_clk_set.pllcon1 = RK3036_PLL_SET_REFDIV(refdiv) | RK3036_PLL_SET_POSTDIV2(postdiv2);
1881 temp_clk_set.pllcon1 |= RK3036_PLL_SET_DSMPD(0);
1883 temp_clk_set.pllcon1 |= RK3036_PLL_SET_DSMPD(1);
1885 temp_clk_set.pllcon2 = RK3036_PLL_SET_FRAC(frac);
1886 temp_clk_set.rst_dly = 0;
1887 clk_debug("setting....\n");
1888 return rk3036_pll_clk_set_rate(&temp_clk_set, hw);
1891 static int clk_pll_set_rate_3036_apll(struct clk_hw *hw, unsigned long rate,
1892 unsigned long parent_rate)
1894 struct clk_pll *pll = to_clk_pll(hw);
1895 struct apll_clk_set *ps = (struct apll_clk_set *)(rk3036_apll_table);
1896 struct clk *arm_gpll = __clk_lookup("clk_gpll");
1897 struct clk *clk = hw->clk;
1898 unsigned long flags, arm_gpll_rate, old_rate, temp_rate;
1902 if (ps->rate == rate) {
1908 if (ps->rate != rate) {
1909 clk_err("%s: unsupport arm rate %lu\n", __func__, rate);
1914 clk_err("clk arm_gpll is NULL!\n");
1918 old_rate = __clk_get_rate(clk);
1919 arm_gpll_rate = __clk_get_rate(arm_gpll);
1920 if (soc_is_rk3128() || soc_is_rk3126())
1923 temp_rate = (old_rate > rate) ? old_rate : rate;
1924 temp_div = DIV_ROUND_UP(arm_gpll_rate, temp_rate);
1926 local_irq_save(flags);
1928 if (rate >= old_rate) {
1929 cru_writel(ps->clksel0, RK3036_CRU_CLKSELS_CON(0));
1930 cru_writel(ps->clksel1, RK3036_CRU_CLKSELS_CON(1));
1933 /* set div first, then select gpll */
1935 cru_writel(RK3036_CLK_CORE_DIV(temp_div), RK3036_CRU_CLKSELS_CON(0));
1936 cru_writel(RK3036_CORE_SEL_PLL(1), RK3036_CRU_CLKSELS_CON(0));
1938 clk_debug("temp select arm_gpll path, get rate %lu\n",
1939 arm_gpll_rate/temp_div);
1940 clk_debug("from arm_gpll rate %lu, temp_div %d\n", arm_gpll_rate,
1943 /**************enter slow mode 24M***********/
1944 /*cru_writel(_RK3188_PLL_MODE_SLOW_SET(pll->mode_shift), pll->mode_offset);*/
1945 loops_per_jiffy = LPJ_24M;
1947 cru_writel(ps->pllcon0, pll->reg + RK3188_PLL_CON(0));
1948 cru_writel(ps->pllcon1, pll->reg + RK3188_PLL_CON(1));
1949 cru_writel(ps->pllcon2, pll->reg + RK3188_PLL_CON(2));
1951 clk_debug("pllcon0 %08x\n", cru_readl(pll->reg + RK3188_PLL_CON(0)));
1952 clk_debug("pllcon1 %08x\n", cru_readl(pll->reg + RK3188_PLL_CON(1)));
1953 clk_debug("pllcon2 %08x\n", cru_readl(pll->reg + RK3188_PLL_CON(2)));
1954 clk_debug("clksel0 %08x\n", cru_readl(RK3036_CRU_CLKSELS_CON(0)));
1955 clk_debug("clksel1 %08x\n", cru_readl(RK3036_CRU_CLKSELS_CON(1)));
1957 /*wating lock state*/
1958 udelay(ps->rst_dly);
1959 rk3036_pll_wait_lock(hw);
1961 /************select apll******************/
1962 cru_writel(RK3036_CORE_SEL_PLL(0), RK3036_CRU_CLKSELS_CON(0));
1963 /**************return slow mode***********/
1964 cru_writel(_RK3188_PLL_MODE_NORM_SET(pll->mode_shift), pll->mode_offset);
1966 cru_writel(RK3036_CLK_CORE_DIV(1), RK3036_CRU_CLKSELS_CON(0));
1968 if (rate < old_rate) {
1969 cru_writel(ps->clksel0, RK3036_CRU_CLKSELS_CON(0));
1970 cru_writel(ps->clksel1, RK3036_CRU_CLKSELS_CON(1));
1973 loops_per_jiffy = ps->lpj;
1974 local_irq_restore(flags);
1978 static const struct clk_ops clk_pll_ops_3036_apll = {
1979 .recalc_rate = clk_pll_recalc_rate_3036_apll,
1980 .round_rate = clk_pll_round_rate_3036_apll,
1981 .set_rate = clk_pll_set_rate_3036_apll,
1985 /* CLK_PLL_3036_plus_autotype ops */
1987 static long clk_pll_round_rate_3036plus_auto(struct clk_hw *hw, unsigned long rate,
1988 unsigned long *prate)
1990 struct clk *parent = __clk_get_parent(hw->clk);
1992 if (parent && (rate == __clk_get_rate(parent))) {
1993 clk_debug("pll %s round rate=%lu equal to parent rate\n",
1994 __clk_get_name(hw->clk), rate);
1998 return (pll_com_get_best_set(rate, rk3036plus_pll_com_table)->rate);
2001 static int clk_pll_set_rate_3036plus_auto(struct clk_hw *hw, unsigned long rate,
2002 unsigned long parent_rate)
2004 struct pll_clk_set *clk_set = (struct pll_clk_set *)(rk3036plus_pll_com_table);
2006 clk_debug("******%s\n", __func__);
2007 while (clk_set->rate) {
2008 clk_debug("******%s clk_set->rate=%lu\n", __func__, clk_set->rate);
2009 if (clk_set->rate == rate) {
2014 if (clk_set->rate == rate) {
2015 rk3036_pll_clk_set_rate(clk_set, hw);
2017 clk_debug("gpll is no corresponding rate=%lu\n", rate);
2020 clk_debug("******%s end\n", __func__);
2025 static const struct clk_ops clk_pll_ops_3036plus_auto = {
2026 .recalc_rate = clk_pll_recalc_rate_3036_apll,
2027 .round_rate = clk_pll_round_rate_3036plus_auto,
2028 .set_rate = clk_pll_set_rate_3036plus_auto,
2031 static long clk_cpll_round_rate_312xplus(struct clk_hw *hw, unsigned long rate,
2032 unsigned long *prate)
2036 for (best = rate; best > 0; best--) {
2037 if (!pll_clk_get_best_set(*prate, best, NULL, NULL, NULL))
2044 static int clk_cpll_set_rate_312xplus(struct clk_hw *hw, unsigned long rate,
2045 unsigned long parent_rate)
2047 struct pll_clk_set *clk_set = (struct pll_clk_set *)(rk312xplus_pll_com_table);
2048 u32 refdiv, fbdiv, postdiv1, postdiv2, frac;
2050 while (clk_set->rate) {
2051 if (clk_set->rate == rate) {
2057 if (clk_set->rate == rate) {
2058 clk_debug("cpll get a rate %ld\n", rate);
2059 rk3036_pll_clk_set_rate(clk_set, hw);
2062 clk_debug("cpll get auto calc a rate\n");
2063 if (rk3036_pll_clk_get_set(parent_rate, rate, &refdiv, &fbdiv, &postdiv1, &postdiv2, &frac) != 0) {
2064 pr_err("cpll auto set rate error\n");
2067 clk_debug("%s get rate=%lu, refdiv=%u, fbdiv=%u, postdiv1=%u, postdiv2=%u",
2068 __func__, rate, refdiv, fbdiv, postdiv1, postdiv2);
2069 rk3036_pll_set_con(hw, refdiv, fbdiv, postdiv1, postdiv2, frac);
2073 clk_debug("setting OK\n");
2077 static const struct clk_ops clk_pll_ops_312xplus = {
2078 .recalc_rate = clk_pll_recalc_rate_3036_apll,
2079 .round_rate = clk_cpll_round_rate_312xplus,
2080 .set_rate = clk_cpll_set_rate_312xplus,
2083 static long clk_pll_round_rate_3368_apllb(struct clk_hw *hw, unsigned long rate,
2084 unsigned long *prate)
2086 struct clk *parent = __clk_get_parent(hw->clk);
2088 if (parent && (rate == __clk_get_rate(parent))) {
2089 clk_debug("pll %s round rate=%lu equal to parent rate\n",
2090 __clk_get_name(hw->clk), rate);
2094 return (apll_get_best_set(rate, rk3368_apllb_table)->rate);
2097 /* 1: use, 0: no use */
2098 #define RK3368_APLLB_USE_GPLL 1
2100 /* when define 1, we will set div to make rate change gently, but it will cost
2102 #define RK3368_APLLB_DIV_MORE 1
2104 static int clk_pll_set_rate_3368_apllb(struct clk_hw *hw, unsigned long rate,
2105 unsigned long parent_rate)
2107 struct clk_pll *pll = to_clk_pll(hw);
2108 struct clk *clk = hw->clk;
2109 struct clk *arm_gpll = __clk_lookup("clk_gpll");
2110 unsigned long arm_gpll_rate, temp_rate, old_rate;
2111 const struct apll_clk_set *ps;
2113 unsigned long flags;
2116 ps = apll_get_best_set(rate, rk3368_apllb_table);
2117 clk_debug("apllb will set rate %lu\n", ps->rate);
2118 clk_debug("table con:%08x,%08x,%08x, sel:%08x,%08x\n",
2119 ps->pllcon0, ps->pllcon1, ps->pllcon2,
2120 ps->clksel0, ps->clksel1);
2122 #if !RK3368_APLLB_USE_GPLL
2126 /* prepare arm_gpll before reparent clk_core to it */
2128 clk_err("clk arm_gpll is NULL!\n");
2132 arm_gpll_rate = __clk_get_rate(arm_gpll);
2133 old_rate = __clk_get_rate(clk);
2135 temp_rate = (old_rate > rate) ? old_rate : rate;
2136 temp_div = DIV_ROUND_UP(arm_gpll_rate, temp_rate);
2138 if (temp_div > RK3368_CORE_CLK_MAX_DIV) {
2139 clk_debug("temp_div %d > max_div %d\n", temp_div,
2140 RK3368_CORE_CLK_MAX_DIV);
2141 clk_debug("can't get rate %lu from arm_gpll rate %lu\n",
2142 __clk_get_rate(clk), arm_gpll_rate);
2146 local_irq_save(flags);
2148 if (rate >= old_rate) {
2149 cru_writel(ps->clksel0, RK3368_CRU_CLKSELS_CON(0));
2150 cru_writel(ps->clksel1, RK3368_CRU_CLKSELS_CON(1));
2154 #if RK3368_APLLB_DIV_MORE
2155 if (temp_div == 1) {
2156 /* when old_rate/2 < (old_rate-arm_gpll_rate),
2157 we can set div to make rate change more gently */
2158 if (old_rate > (2*arm_gpll_rate)) {
2159 cru_writel(RK3368_CORE_CLK_DIV(2), RK3368_CRU_CLKSELS_CON(0));
2161 cru_writel(RK3368_CORE_CLK_DIV(3), RK3368_CRU_CLKSELS_CON(0));
2163 cru_writel(RK3368_CORE_SEL_PLL_W_MSK|RK3368_CORE_SEL_GPLL,
2164 RK3368_CRU_CLKSELS_CON(0));
2166 cru_writel(RK3368_CORE_CLK_DIV(2), RK3368_CRU_CLKSELS_CON(0));
2168 cru_writel(RK3368_CORE_CLK_DIV(1), RK3368_CRU_CLKSELS_CON(0));
2170 cru_writel(RK3368_CORE_SEL_PLL_W_MSK|RK3368_CORE_SEL_GPLL,
2171 RK3368_CRU_CLKSELS_CON(0));
2174 cru_writel(RK3368_CORE_CLK_DIV(temp_div), RK3368_CRU_CLKSELS_CON(0));
2175 cru_writel(RK3368_CORE_SEL_PLL_W_MSK|RK3368_CORE_SEL_GPLL,
2176 RK3368_CRU_CLKSELS_CON(0));
2179 cru_writel(RK3368_CORE_CLK_DIV(temp_div), RK3368_CRU_CLKSELS_CON(0));
2180 cru_writel(RK3368_CORE_SEL_PLL_W_MSK|RK3368_CORE_SEL_GPLL,
2181 RK3368_CRU_CLKSELS_CON(0));
2188 local_irq_restore(flags);
2190 clk_debug("temp select arm_gpll path, get rate %lu\n",
2191 arm_gpll_rate/temp_div);
2192 clk_debug("from arm_gpll rate %lu, temp_div %d\n", arm_gpll_rate,
2196 local_irq_save(flags);
2198 /* apll enter slow mode */
2199 cru_writel(_RK3188_PLL_MODE_SLOW_SET(pll->mode_shift),
2202 /* PLL enter reset */
2203 cru_writel(_RK3188PLUS_PLL_RESET_SET(1), pll->reg + RK3188_PLL_CON(3));
2205 cru_writel(ps->pllcon0, pll->reg + RK3188_PLL_CON(0));
2206 cru_writel(ps->pllcon1, pll->reg + RK3188_PLL_CON(1));
2207 cru_writel(ps->pllcon2, pll->reg + RK3188_PLL_CON(2));
2211 /* return from rest */
2212 cru_writel(_RK3188PLUS_PLL_RESET_SET(0), pll->reg + RK3188_PLL_CON(3));
2214 /* wating lock state */
2215 udelay(ps->rst_dly);
2219 if (rate >= old_rate) {
2220 cru_writel(ps->clksel0, RK3368_CRU_CLKSELS_CON(0));
2221 cru_writel(ps->clksel1, RK3368_CRU_CLKSELS_CON(1));
2225 /* apll return from slow mode */
2226 cru_writel(_RK3188_PLL_MODE_NORM_SET(pll->mode_shift),
2229 /* reparent to apll, and set div to 1 */
2231 #if RK3368_APLLB_DIV_MORE
2232 /* when rate/2 < (rate-arm_gpll_rate), we can set div to make
2233 rate change more gently */
2234 if ((temp_div == 1) && (rate > (2*arm_gpll_rate))) {
2235 cru_writel(RK3368_CORE_CLK_DIV(2), RK3368_CRU_CLKSELS_CON(0));
2237 cru_writel(RK3368_CORE_CLK_DIV(3), RK3368_CRU_CLKSELS_CON(0));
2239 cru_writel(RK3368_CORE_SEL_PLL_W_MSK|RK3368_CORE_SEL_APLL,
2240 RK3368_CRU_CLKSELS_CON(0));
2242 cru_writel(RK3368_CORE_CLK_DIV(2), RK3368_CRU_CLKSELS_CON(0));
2245 cru_writel(RK3368_CORE_SEL_PLL_W_MSK|RK3368_CORE_SEL_APLL,
2246 RK3368_CRU_CLKSELS_CON(0));
2248 cru_writel(RK3368_CORE_SEL_PLL_W_MSK|RK3368_CORE_SEL_APLL,
2249 RK3368_CRU_CLKSELS_CON(0));
2253 cru_writel(RK3368_CORE_CLK_DIV(1), RK3368_CRU_CLKSELS_CON(0));
2255 if (rate < old_rate) {
2256 cru_writel(ps->clksel0, RK3368_CRU_CLKSELS_CON(0));
2257 cru_writel(ps->clksel1, RK3368_CRU_CLKSELS_CON(1));
2262 local_irq_restore(flags);
2267 clk_debug("apll set rate %lu, con(%x,%x,%x,%x), sel(%x,%x)\n",
2269 cru_readl(pll->reg + RK3188_PLL_CON(0)),
2270 cru_readl(pll->reg + RK3188_PLL_CON(1)),
2271 cru_readl(pll->reg + RK3188_PLL_CON(2)),
2272 cru_readl(pll->reg + RK3188_PLL_CON(3)),
2273 cru_readl(RK3368_CRU_CLKSELS_CON(0)),
2274 cru_readl(RK3368_CRU_CLKSELS_CON(1)));
2279 static const struct clk_ops clk_pll_ops_3368_apllb = {
2280 .recalc_rate = clk_pll_recalc_rate_3188plus,
2281 .round_rate = clk_pll_round_rate_3368_apllb,
2282 .set_rate = clk_pll_set_rate_3368_apllb,
2285 static long clk_pll_round_rate_3368_aplll(struct clk_hw *hw, unsigned long rate,
2286 unsigned long *prate)
2288 struct clk *parent = __clk_get_parent(hw->clk);
2290 if (parent && (rate == __clk_get_rate(parent))) {
2291 clk_debug("pll %s round rate=%lu equal to parent rate\n",
2292 __clk_get_name(hw->clk), rate);
2296 return (apll_get_best_set(rate, rk3368_aplll_table)->rate);
2299 /* 1: use, 0: no use */
2300 #define RK3368_APLLL_USE_GPLL 1
2302 /* when define 1, we will set div to make rate change gently, but it will cost
2304 #define RK3368_APLLL_DIV_MORE 1
2306 static int clk_pll_set_rate_3368_aplll(struct clk_hw *hw, unsigned long rate,
2307 unsigned long parent_rate)
2309 struct clk_pll *pll = to_clk_pll(hw);
2310 struct clk *clk = hw->clk;
2311 struct clk *arm_gpll = __clk_lookup("clk_gpll");
2312 unsigned long arm_gpll_rate, temp_rate, old_rate;
2313 const struct apll_clk_set *ps;
2315 unsigned long flags;
2318 ps = apll_get_best_set(rate, rk3368_aplll_table);
2319 clk_debug("aplll will set rate %lu\n", ps->rate);
2320 clk_debug("table con:%08x,%08x,%08x, sel:%08x,%08x\n",
2321 ps->pllcon0, ps->pllcon1, ps->pllcon2,
2322 ps->clksel0, ps->clksel1);
2324 #if !RK3368_APLLL_USE_GPLL
2328 /* prepare arm_gpll before reparent clk_core to it */
2330 clk_err("clk arm_gpll is NULL!\n");
2334 arm_gpll_rate = __clk_get_rate(arm_gpll);
2335 old_rate = __clk_get_rate(clk);
2337 temp_rate = (old_rate > rate) ? old_rate : rate;
2338 temp_div = DIV_ROUND_UP(arm_gpll_rate, temp_rate);
2340 if (temp_div > RK3368_CORE_CLK_MAX_DIV) {
2341 clk_debug("temp_div %d > max_div %d\n", temp_div,
2342 RK3368_CORE_CLK_MAX_DIV);
2343 clk_debug("can't get rate %lu from arm_gpll rate %lu\n",
2344 __clk_get_rate(clk), arm_gpll_rate);
2348 local_irq_save(flags);
2350 if (rate >= old_rate) {
2351 cru_writel(ps->clksel0, RK3368_CRU_CLKSELS_CON(2));
2352 cru_writel(ps->clksel1, RK3368_CRU_CLKSELS_CON(3));
2356 #if RK3368_APLLL_DIV_MORE
2357 if (temp_div == 1) {
2358 /* when old_rate/2 < (old_rate-arm_gpll_rate),
2359 we can set div to make rate change more gently */
2360 if (old_rate > (2*arm_gpll_rate)) {
2361 cru_writel(RK3368_CORE_CLK_DIV(2), RK3368_CRU_CLKSELS_CON(2));
2363 cru_writel(RK3368_CORE_CLK_DIV(3), RK3368_CRU_CLKSELS_CON(2));
2365 cru_writel(RK3368_CORE_SEL_PLL_W_MSK|RK3368_CORE_SEL_GPLL,
2366 RK3368_CRU_CLKSELS_CON(2));
2368 cru_writel(RK3368_CORE_CLK_DIV(2), RK3368_CRU_CLKSELS_CON(2));
2370 cru_writel(RK3368_CORE_CLK_DIV(1), RK3368_CRU_CLKSELS_CON(2));
2372 cru_writel(RK3368_CORE_SEL_PLL_W_MSK|RK3368_CORE_SEL_GPLL,
2373 RK3368_CRU_CLKSELS_CON(2));
2376 cru_writel(RK3368_CORE_CLK_DIV(temp_div), RK3368_CRU_CLKSELS_CON(2));
2377 cru_writel(RK3368_CORE_SEL_PLL_W_MSK|RK3368_CORE_SEL_GPLL,
2378 RK3368_CRU_CLKSELS_CON(2));
2381 cru_writel(RK3368_CORE_CLK_DIV(temp_div), RK3368_CRU_CLKSELS_CON(2));
2382 cru_writel(RK3368_CORE_SEL_PLL_W_MSK|RK3368_CORE_SEL_GPLL,
2383 RK3368_CRU_CLKSELS_CON(2));
2390 local_irq_restore(flags);
2392 clk_debug("temp select arm_gpll path, get rate %lu\n",
2393 arm_gpll_rate/temp_div);
2394 clk_debug("from arm_gpll rate %lu, temp_div %d\n", arm_gpll_rate,
2398 local_irq_save(flags);
2400 /* apll enter slow mode */
2401 cru_writel(_RK3188_PLL_MODE_SLOW_SET(pll->mode_shift),
2404 /* PLL enter reset */
2405 cru_writel(_RK3188PLUS_PLL_RESET_SET(1), pll->reg + RK3188_PLL_CON(3));
2407 cru_writel(ps->pllcon0, pll->reg + RK3188_PLL_CON(0));
2408 cru_writel(ps->pllcon1, pll->reg + RK3188_PLL_CON(1));
2409 cru_writel(ps->pllcon2, pll->reg + RK3188_PLL_CON(2));
2413 /* return from rest */
2414 cru_writel(_RK3188PLUS_PLL_RESET_SET(0), pll->reg + RK3188_PLL_CON(3));
2416 /* wating lock state */
2417 udelay(ps->rst_dly);
2421 if (rate >= old_rate) {
2422 cru_writel(ps->clksel0, RK3368_CRU_CLKSELS_CON(2));
2423 cru_writel(ps->clksel1, RK3368_CRU_CLKSELS_CON(3));
2427 /* apll return from slow mode */
2428 cru_writel(_RK3188_PLL_MODE_NORM_SET(pll->mode_shift),
2431 /* reparent to apll, and set div to 1 */
2433 #if RK3368_APLLL_DIV_MORE
2434 /* when rate/2 < (rate-arm_gpll_rate), we can set div to make
2435 rate change more gently */
2436 if ((temp_div == 1) && (rate > (2*arm_gpll_rate))) {
2437 cru_writel(RK3368_CORE_CLK_DIV(2), RK3368_CRU_CLKSELS_CON(2));
2439 cru_writel(RK3368_CORE_CLK_DIV(3), RK3368_CRU_CLKSELS_CON(2));
2441 cru_writel(RK3368_CORE_SEL_PLL_W_MSK|RK3368_CORE_SEL_APLL,
2442 RK3368_CRU_CLKSELS_CON(2));
2444 cru_writel(RK3368_CORE_CLK_DIV(2), RK3368_CRU_CLKSELS_CON(2));
2447 cru_writel(RK3368_CORE_SEL_PLL_W_MSK|RK3368_CORE_SEL_APLL,
2448 RK3368_CRU_CLKSELS_CON(2));
2450 cru_writel(RK3368_CORE_SEL_PLL_W_MSK|RK3368_CORE_SEL_APLL,
2451 RK3368_CRU_CLKSELS_CON(2));
2455 cru_writel(RK3368_CORE_CLK_DIV(1), RK3368_CRU_CLKSELS_CON(2));
2457 if (rate < old_rate) {
2458 cru_writel(ps->clksel0, RK3368_CRU_CLKSELS_CON(2));
2459 cru_writel(ps->clksel1, RK3368_CRU_CLKSELS_CON(3));
2464 local_irq_restore(flags);
2469 clk_debug("apll set rate %lu, con(%x,%x,%x,%x), sel(%x,%x)\n",
2471 cru_readl(pll->reg + RK3188_PLL_CON(0)),
2472 cru_readl(pll->reg + RK3188_PLL_CON(1)),
2473 cru_readl(pll->reg + RK3188_PLL_CON(2)),
2474 cru_readl(pll->reg + RK3188_PLL_CON(3)),
2475 cru_readl(RK3368_CRU_CLKSELS_CON(2)),
2476 cru_readl(RK3368_CRU_CLKSELS_CON(3)));
2481 static const struct clk_ops clk_pll_ops_3368_aplll = {
2482 .recalc_rate = clk_pll_recalc_rate_3188plus,
2483 .round_rate = clk_pll_round_rate_3368_aplll,
2484 .set_rate = clk_pll_set_rate_3368_aplll,
2487 const struct clk_ops *rk_get_pll_ops(u32 pll_flags)
2489 switch (pll_flags) {
2491 return &clk_pll_ops_3188;
2493 case CLK_PLL_3188_APLL:
2494 return &clk_pll_ops_3188_apll;
2496 case CLK_PLL_3188PLUS:
2497 return &clk_pll_ops_3188plus;
2499 case CLK_PLL_3188PLUS_APLL:
2500 return &clk_pll_ops_3188plus_apll;
2502 case CLK_PLL_3288_APLL:
2503 return &clk_pll_ops_3288_apll;
2505 case CLK_PLL_3188PLUS_AUTO:
2506 return &clk_pll_ops_3188plus_auto;
2508 case CLK_PLL_3036_APLL:
2509 return &clk_pll_ops_3036_apll;
2511 case CLK_PLL_3036PLUS_AUTO:
2512 return &clk_pll_ops_3036plus_auto;
2514 case CLK_PLL_312XPLUS:
2515 return &clk_pll_ops_312xplus;
2517 case CLK_PLL_3368_APLLB:
2518 return &clk_pll_ops_3368_apllb;
2520 case CLK_PLL_3368_APLLL:
2521 return &clk_pll_ops_3368_aplll;
2523 case CLK_PLL_3368_LOW_JITTER:
2524 return &clk_pll_ops_3368_low_jitter;
2527 clk_err("%s: unknown pll_flags!\n", __func__);
2532 struct clk *rk_clk_register_pll(struct device *dev, const char *name,
2533 const char *parent_name, unsigned long flags, u32 reg,
2534 u32 width, u32 mode_offset, u8 mode_shift,
2535 u32 status_offset, u8 status_shift, u32 pll_flags,
2538 struct clk_pll *pll;
2540 struct clk_init_data init;
2543 clk_debug("%s: pll name = %s, pll_flags = 0x%x, register start!\n",
2544 __func__, name, pll_flags);
2546 /* allocate the pll */
2547 pll = kzalloc(sizeof(struct clk_pll), GFP_KERNEL);
2549 clk_err("%s: could not allocate pll clk\n", __func__);
2550 return ERR_PTR(-ENOMEM);
2555 init.parent_names = (parent_name ? &parent_name: NULL);
2556 init.num_parents = (parent_name ? 1 : 0);
2557 init.ops = rk_get_pll_ops(pll_flags);
2559 /* struct clk_pll assignments */
2562 pll->mode_offset = mode_offset;
2563 pll->mode_shift = mode_shift;
2564 pll->status_offset = status_offset;
2565 pll->status_shift = status_shift;
2566 pll->flags = pll_flags;
2568 pll->hw.init = &init;
2570 /* register the clock */
2571 clk = clk_register(dev, &pll->hw);
2576 clk_debug("%s: pll name = %s, pll_flags = 0x%x, register finish!\n",
2577 __func__, name, pll_flags);