drivers/clk/rockchip/clk-pll.c

   1 #include <linux/slab.h>
   2 #include <asm/io.h>
   3
   4 #include "clk-ops.h"
   5 #include "clk-pll.h"
   6
   7
   8
   9 //static unsigned long lpj_gpll;
  10
  11
  12 static const struct apll_clk_set apll_table[] = {
  13         //            (_mhz,    nr,     nf,     no,     _periph_div,    _aclk_div)
  14         _RK3188_APLL_SET_CLKS(2208,     1,      92,     1,      8,      81),
  15         _RK3188_APLL_SET_CLKS(2184,     1,      91,     1,      8,      81),
  16         _RK3188_APLL_SET_CLKS(2160,     1,      90,     1,      8,      81),
  17         _RK3188_APLL_SET_CLKS(2136,     1,      89,     1,      8,      81),
  18         _RK3188_APLL_SET_CLKS(2112,     1,      88,     1,      8,      81),
  19         _RK3188_APLL_SET_CLKS(2088,     1,      87,     1,      8,      81),
  20         _RK3188_APLL_SET_CLKS(2064,     1,      86,     1,      8,      81),
  21         _RK3188_APLL_SET_CLKS(2040,     1,      85,     1,      8,      81),
  22         _RK3188_APLL_SET_CLKS(2016,     1,      84,     1,      8,      81),
  23         _RK3188_APLL_SET_CLKS(1992,     1,      83,     1,      8,      81),
  24         _RK3188_APLL_SET_CLKS(1968,     1,      82,     1,      8,      81),
  25         _RK3188_APLL_SET_CLKS(1944,     1,      81,     1,      8,      81),
  26         _RK3188_APLL_SET_CLKS(1920,     1,      80,     1,      8,      81),
  27         _RK3188_APLL_SET_CLKS(1896,     1,      79,     1,      8,      81),
  28         _RK3188_APLL_SET_CLKS(1872,     1,      78,     1,      8,      81),
  29         _RK3188_APLL_SET_CLKS(1848,     1,      77,     1,      8,      81),
  30         _RK3188_APLL_SET_CLKS(1824,     1,      76,     1,      8,      81),
  31         _RK3188_APLL_SET_CLKS(1800,     1,      75,     1,      8,      81),
  32         _RK3188_APLL_SET_CLKS(1776,     1,      74,     1,      8,      81),
  33         _RK3188_APLL_SET_CLKS(1752,     1,      73,     1,      8,      81),
  34         _RK3188_APLL_SET_CLKS(1728,     1,      72,     1,      8,      81),
  35         _RK3188_APLL_SET_CLKS(1704,     1,      71,     1,      8,      81),
  36         _RK3188_APLL_SET_CLKS(1680,     1,      70,     1,      8,      41),
  37         _RK3188_APLL_SET_CLKS(1656,     1,      69,     1,      8,      41),
  38         _RK3188_APLL_SET_CLKS(1632,     1,      68,     1,      8,      41),
  39         _RK3188_APLL_SET_CLKS(1608,     1,      67,     1,      8,      41),
  40         _RK3188_APLL_SET_CLKS(1560,     1,      65,     1,      8,      41),
  41         _RK3188_APLL_SET_CLKS(1512,     1,      63,     1,      8,      41),
  42         _RK3188_APLL_SET_CLKS(1488,     1,      62,     1,      8,      41),
  43         _RK3188_APLL_SET_CLKS(1464,     1,      61,     1,      8,      41),
  44         _RK3188_APLL_SET_CLKS(1440,     1,      60,     1,      8,      41),
  45         _RK3188_APLL_SET_CLKS(1416,     1,      59,     1,      8,      41),
  46         _RK3188_APLL_SET_CLKS(1392,     1,      58,     1,      8,      41),
  47         _RK3188_APLL_SET_CLKS(1368,     1,      57,     1,      8,      41),
  48         _RK3188_APLL_SET_CLKS(1344,     1,      56,     1,      8,      41),
  49         _RK3188_APLL_SET_CLKS(1320,     1,      55,     1,      8,      41),
  50         _RK3188_APLL_SET_CLKS(1296,     1,      54,     1,      8,      41),
  51         _RK3188_APLL_SET_CLKS(1272,     1,      53,     1,      8,      41),
  52         _RK3188_APLL_SET_CLKS(1248,     1,      52,     1,      8,      41),
  53         _RK3188_APLL_SET_CLKS(1224,     1,      51,     1,      8,      41),
  54         _RK3188_APLL_SET_CLKS(1200,     1,      50,     1,      8,      41),
  55         _RK3188_APLL_SET_CLKS(1176,     1,      49,     1,      8,      41),
  56         _RK3188_APLL_SET_CLKS(1128,     1,      47,     1,      8,      41),
  57         _RK3188_APLL_SET_CLKS(1104,     1,      46,     1,      8,      41),
  58         _RK3188_APLL_SET_CLKS(1008,     1,      84,     2,      8,      41),
  59         _RK3188_APLL_SET_CLKS(912,      1,      76,     2,      8,      41),
  60         _RK3188_APLL_SET_CLKS(888,      1,      74,     2,      8,      41),
  61         _RK3188_APLL_SET_CLKS(816,      1,      68,     2,      8,      41),
  62         _RK3188_APLL_SET_CLKS(792,      1,      66,     2,      8,      41),
  63         _RK3188_APLL_SET_CLKS(696,      1,      58,     2,      8,      41),
  64         _RK3188_APLL_SET_CLKS(600,      1,      50,     2,      4,      41),
  65         _RK3188_APLL_SET_CLKS(552,      1,      92,     4,      4,      41),
  66         _RK3188_APLL_SET_CLKS(504,      1,      84,     4,      4,      41),
  67         _RK3188_APLL_SET_CLKS(408,      1,      68,     4,      4,      21),
  68         _RK3188_APLL_SET_CLKS(312,      1,      52,     4,      2,      21),
  69         _RK3188_APLL_SET_CLKS(252,      1,      84,     8,      2,      21),
  70         _RK3188_APLL_SET_CLKS(216,      1,      72,     8,      2,      21),
  71         _RK3188_APLL_SET_CLKS(126,      1,      84,     16,     2,      11),
  72         _RK3188_APLL_SET_CLKS(48,       1,      32,     16,     2,      11),
  73         _RK3188_APLL_SET_CLKS(0,        1,      32,     16,     2,      11),
  74 };
  75
  76 static const struct pll_clk_set pll_com_table[] = {
  77         _RK3188_PLL_SET_CLKS(1200000,   1,      50,     1),
  78         _RK3188_PLL_SET_CLKS(1188000,   2,      99,     1),
  79         _RK3188_PLL_SET_CLKS(891000,    8,      594,    2),
  80         _RK3188_PLL_SET_CLKS(768000,    1,      64,     2),
  81         _RK3188_PLL_SET_CLKS(594000,    2,      198,    4),
  82         _RK3188_PLL_SET_CLKS(408000,    1,      68,     4),
  83         _RK3188_PLL_SET_CLKS(384000,    2,      128,    4),
  84         _RK3188_PLL_SET_CLKS(360000,    1,      60,     4),
  85         _RK3188_PLL_SET_CLKS(300000,    1,      50,     4),
  86         _RK3188_PLL_SET_CLKS(297000,    2,      198,    8),
  87         _RK3188_PLL_SET_CLKS(148500,    2,      99,     8),
  88         _RK3188_PLL_SET_CLKS(0,         0,      0,      0),
  89 };
  90
  91 static void pll_wait_lock(struct clk_hw *hw)
  92 {
  93         struct clk_pll *pll = to_clk_pll(hw);
  94         int delay = 24000000;
  95
  96
  97         while (delay > 0) {
  98                 if (grf_readl(pll->status_offset) & (1 << pll->status_shift))
  99                         break;
 100                 delay--;
 101         }
 102
 103         if (delay == 0) {
 104                 clk_err("pll %s: can't lock! status_shift=%u\n"
 105                                 "pll_con0=%08x\npll_con1=%08x\n"
 106                                 "pll_con2=%08x\npll_con3=%08x\n",
 107                                 __clk_get_name(hw->clk),
 108                                 pll->status_shift,
 109                                 readl(pll->reg + RK3188_PLL_CON(0)),
 110                                 readl(pll->reg + RK3188_PLL_CON(1)),
 111                                 readl(pll->reg + RK3188_PLL_CON(2)),
 112                                 readl(pll->reg + RK3188_PLL_CON(3)));
 113
 114                 while(1);
 115         }
 116 }
 117
 118
 119 /* recalc_rate */
 120 static unsigned long clk_pll_recalc_rate_3188(struct clk_hw *hw,
 121                 unsigned long parent_rate)
 122 {
 123         struct clk_pll *pll = to_clk_pll(hw);
 124         unsigned long rate;
 125
 126
 127         if (_RK3188_PLL_MODE_IS_NORM(pll->mode_offset, pll->mode_shift)) {
 128                 u32 pll_con0 = readl(pll->reg + RK3188_PLL_CON(0));
 129                 u32 pll_con1 = readl(pll->reg + RK3188_PLL_CON(1));
 130
 131                 u64 rate64 = (u64)parent_rate * RK3188_PLL_NF(pll_con1);
 132
 133                 do_div(rate64, RK3188_PLL_NR(pll_con0));
 134                 do_div(rate64, RK3188_PLL_NO(pll_con0));
 135
 136                 rate = rate64;
 137         } else {
 138                 /*FIXME*/
 139                 rate = parent_rate;
 140                 clk_debug("pll %s is in slow mode\n", __clk_get_name(hw->clk));
 141         }
 142
 143         clk_debug("pll %s recalc rate =%lu\n", __clk_get_name(hw->clk), rate);
 144
 145         return rate;
 146 }
 147
 148 /* round_rate */
 149 /* get rate that is most close to target */
 150 static const struct apll_clk_set *apll_get_best_set(unsigned long rate,
 151                 const struct apll_clk_set *table)
 152 {
 153         const struct apll_clk_set *ps, *pt;
 154
 155         ps = pt = table;
 156         while (pt->rate) {
 157                 if (pt->rate == rate) {
 158                         ps = pt;
 159                         break;
 160                 }
 161
 162                 if ((pt->rate > rate || (rate - pt->rate < ps->rate - rate)))
 163                         ps = pt;
 164                 if (pt->rate < rate)
 165                         break;
 166                 pt++;
 167         }
 168
 169         return ps;
 170 }
 171
 172 /* get rate that is most close to target */
 173 static const struct pll_clk_set *pll_com_get_best_set(unsigned long rate,
 174                 const struct pll_clk_set *table)
 175 {
 176         const struct pll_clk_set *ps, *pt;
 177
 178         ps = pt = table;
 179         while (pt->rate) {
 180                 if (pt->rate == rate) {
 181                         ps = pt;
 182                         break;
 183                 }
 184
 185                 if ((pt->rate > rate || (rate - pt->rate < ps->rate - rate)))
 186                         ps = pt;
 187                 if (pt->rate < rate)
 188                         break;
 189                 pt++;
 190         }
 191
 192         return ps;
 193 }
 194
 195 static long clk_pll_round_rate_3188_apll(struct clk_hw *hw, unsigned long rate,
 196                 unsigned long *prate)
 197 {
 198         struct clk *parent = __clk_get_parent(hw->clk);
 199
 200         if (parent && (rate==__clk_get_rate(parent))) {
 201                 clk_debug("pll %s round rate=%lu equal to parent rate\n",
 202                                 __clk_get_name(hw->clk), rate);
 203                 return rate;
 204         }
 205
 206         return (apll_get_best_set(rate, apll_table)->rate);
 207 }
 208
 209 static long clk_pll_round_rate_3188(struct clk_hw *hw, unsigned long rate,
 210                 unsigned long *prate)
 211 {
 212         struct clk *parent = __clk_get_parent(hw->clk);
 213
 214         if (parent && (rate==__clk_get_rate(parent))) {
 215                 clk_debug("pll %s round rate=%lu equal to parent rate\n",
 216                                 __clk_get_name(hw->clk), rate);
 217                 return rate;
 218         }
 219
 220         return (pll_com_get_best_set(rate, pll_com_table)->rate);
 221 }
 222
 223 /* set_rate */
 224 static int _pll_clk_set_rate_rk3188(struct pll_clk_set *clk_set,
 225                 struct clk_hw *hw, spinlock_t *lock)
 226 {
 227         struct clk_pll *pll = to_clk_pll(hw);
 228         unsigned long flags = 0;
 229
 230
 231         clk_debug("%s start!\n", __func__);
 232
 233         if(lock)
 234                 spin_lock_irqsave(lock, flags);
 235
 236         //enter slowmode
 237         cru_writel(_RK3188_PLL_MODE_SLOW_SET(pll->mode_shift), pll->mode_offset);
 238         //pll power down
 239         writel((0x1 << (16+1)) | (0x1<<1), pll->reg + RK3188_PLL_CON(3));
 240         dsb();
 241         dsb();
 242         dsb();
 243         dsb();
 244         dsb();
 245         dsb();
 246         writel(clk_set->pllcon0, pll->reg + RK3188_PLL_CON(0));
 247         writel(clk_set->pllcon1, pll->reg + RK3188_PLL_CON(1));
 248
 249         udelay(1);
 250
 251         //pll no power down
 252         writel((0x1<<(16+1)), pll->reg + RK3188_PLL_CON(3));
 253
 254         pll_wait_lock(hw);
 255
 256         //return from slow
 257         cru_writel(_RK3188_PLL_MODE_NORM_SET(pll->mode_shift), pll->mode_offset);
 258
 259         if (lock)
 260                 spin_unlock_irqrestore(lock, flags);
 261
 262         clk_debug("pll %s dump reg: con0=0x%08x, con1=0x%08x, mode=0x%08x\n",
 263                         __clk_get_name(hw->clk),
 264                         readl(pll->reg + RK3188_PLL_CON(0)),
 265                         readl(pll->reg + RK3188_PLL_CON(1)),
 266                         cru_readl(pll->mode_offset));
 267
 268         clk_debug("%s end!\n", __func__);
 269
 270         return 0;
 271 }
 272
 273 static int clk_pll_set_rate_3188(struct clk_hw *hw, unsigned long rate,
 274                 unsigned long parent_rate)
 275 {
 276         struct clk_pll *pll = to_clk_pll(hw);
 277         struct pll_clk_set *clk_set = (struct pll_clk_set *)(pll_com_table);
 278         int ret = 0;
 279
 280
 281         if (rate == parent_rate) {
 282                 clk_debug("pll %s set rate=%lu equal to parent rate\n",
 283                                 __clk_get_name(hw->clk), rate);
 284                 cru_writel(_RK3188_PLL_MODE_SLOW_SET(pll->mode_shift),
 285                                 pll->mode_offset);
 286                 /* pll power down */
 287                 writel((0x1 << (16+1)) | (0x1<<1), pll->reg + RK3188_PLL_CON(3));
 288                 clk_debug("pll %s enter slow mode, set rate OK!\n",
 289                                 __clk_get_name(hw->clk));
 290                 return 0;
 291         }
 292
 293         while(clk_set->rate) {
 294                 if (clk_set->rate == rate) {
 295                         break;
 296                 }
 297                 clk_set++;
 298         }
 299
 300         if (clk_set->rate == rate) {
 301                 ret = _pll_clk_set_rate_rk3188(clk_set, hw, pll->lock);
 302                 clk_debug("pll %s set rate=%lu OK!\n", __clk_get_name(hw->clk),
 303                                 rate);
 304         } else {
 305                 clk_err("pll %s is no corresponding rate=%lu\n",
 306                                 __clk_get_name(hw->clk), rate);
 307                 return -EINVAL;
 308         }
 309
 310         return ret;
 311 }
 312
 313 /* 1: use
 314  * 0: no use
 315  */
 316 #define USE_ARM_GPLL    1
 317
 318 static int clk_pll_set_rate_3188_apll(struct clk_hw *hw, unsigned long rate,
 319                 unsigned long parent_rate)
 320 {
 321         struct clk_pll *pll = to_clk_pll(hw);
 322         struct clk *clk = hw->clk;
 323         struct clk *arm_gpll = __clk_lookup("clk_arm_gpll");
 324         unsigned long arm_gpll_rate;
 325         const struct apll_clk_set *ps;
 326         u32 old_aclk_div = 0, new_aclk_div = 0;
 327         u32 temp_div;
 328         unsigned long flags;
 329         int sel_gpll = 0;
 330
 331
 332         if (rate == parent_rate) {
 333                 clk_debug("pll %s set rate=%lu equal to parent rate\n",
 334                                 __clk_get_name(hw->clk), rate);
 335                 cru_writel(_RK3188_PLL_MODE_SLOW_SET(pll->mode_shift),
 336                                 pll->mode_offset);
 337                 /* pll power down */
 338                 writel((0x1 << (16+1)) | (0x1<<1), pll->reg + RK3188_PLL_CON(3));
 339                 clk_debug("pll %s enter slow mode, set rate OK!\n",
 340                                 __clk_get_name(hw->clk));
 341                 return 0;
 342         }
 343
 344
 345 #if !USE_ARM_GPLL
 346         goto CHANGE_APLL;
 347 #endif
 348
 349         /* prepare arm_gpll before reparent clk_core to it */
 350         if (!arm_gpll) {
 351                 clk_err("clk arm_gpll is NULL!\n");
 352                 goto CHANGE_APLL;
 353         }
 354
 355         /* In rk3188, arm_gpll and cpu_gpll share a same gate,
 356          * and aclk_cpu selects cpu_gpll as parent, thus this
 357          * gate must keep enabled.
 358          */
 359 #if 0
 360         if (clk_prepare(arm_gpll)) {
 361                 clk_err("fail to prepare arm_gpll path\n");
 362                 clk_unprepare(arm_gpll);
 363                 goto CHANGE_APLL;
 364         }
 365
 366         if (clk_enable(arm_gpll)) {
 367                 clk_err("fail to enable arm_gpll path\n");
 368                 clk_disable(arm_gpll);
 369                 clk_unprepare(arm_gpll);
 370                 goto CHANGE_APLL;
 371         }
 372 #endif
 373
 374         arm_gpll_rate = __clk_get_rate(arm_gpll);
 375         temp_div = DIV_ROUND_UP(arm_gpll_rate, __clk_get_rate(clk));
 376         temp_div = (temp_div == 0) ? 1 : temp_div;
 377         if (temp_div > RK3188_CORE_CLK_MAX_DIV) {
 378                 clk_debug("temp_div %d > max_div %d\n", temp_div,
 379                                 RK3188_CORE_CLK_MAX_DIV);
 380                 clk_debug("can't get rate %lu from arm_gpll rate %lu\n",
 381                                 __clk_get_rate(clk), arm_gpll_rate);
 382                 //clk_disable(arm_gpll);
 383                 //clk_unprepare(arm_gpll);
 384                 goto CHANGE_APLL;
 385         }
 386
 387         local_irq_save(flags);
 388
 389         /* firstly set div, then select arm_gpll path */
 390         cru_writel(RK3188_CORE_CLK_DIV_W_MSK|RK3188_CORE_CLK_DIV(temp_div),
 391                         RK3188_CRU_CLKSELS_CON(0));
 392         cru_writel(RK3188_CORE_SEL_PLL_W_MSK|RK3188_CORE_SEL_GPLL,
 393                         RK3188_CRU_CLKSELS_CON(0));
 394
 395         sel_gpll = 1;
 396         //loops_per_jiffy = lpj_gpll / temp_div;
 397         smp_wmb();
 398
 399         local_irq_restore(flags);
 400
 401         clk_debug("temp select arm_gpll path, get rate %lu\n",
 402                         arm_gpll_rate/temp_div);
 403         clk_debug("from arm_gpll rate %lu, temp_div %d\n", arm_gpll_rate,
 404                         temp_div);
 405
 406 CHANGE_APLL:
 407         ps = apll_get_best_set(rate, apll_table);
 408         clk_debug("apll will set rate %lu\n", ps->rate);
 409         clk_debug("table con:%08x,%08x,%08x, sel:%08x,%08x\n",
 410                         ps->pllcon0, ps->pllcon1, ps->pllcon2,
 411                         ps->clksel0, ps->clksel1);
 412
 413         local_irq_save(flags);
 414
 415         /* If core src don't select gpll, apll need to enter slow mode
 416          * before power down
 417          */
 418         //FIXME
 419         //if (!sel_gpll)
 420         cru_writel(_RK3188_PLL_MODE_SLOW_SET(pll->mode_shift), pll->mode_offset);
 421
 422         /* PLL power down */
 423         writel((0x1 << (16+1)) | (0x1<<1), pll->reg + RK3188_PLL_CON(3));
 424         dsb();
 425         dsb();
 426         dsb();
 427         dsb();
 428         dsb();
 429         dsb();
 430         writel(ps->pllcon0, pll->reg + RK3188_PLL_CON(0));
 431         writel(ps->pllcon1, pll->reg + RK3188_PLL_CON(1));
 432
 433         udelay(1);
 434
 435         /* PLL power up and wait for locked */
 436         writel((0x1<<(16+1)), pll->reg + RK3188_PLL_CON(3));
 437         pll_wait_lock(hw);
 438
 439         old_aclk_div = RK3188_GET_CORE_ACLK_VAL(cru_readl(RK3188_CRU_CLKSELS_CON(1)) &
 440                         RK3188_CORE_ACLK_MSK);
 441         new_aclk_div = RK3188_GET_CORE_ACLK_VAL(ps->clksel1 & RK3188_CORE_ACLK_MSK);
 442
 443         if (new_aclk_div >= old_aclk_div) {
 444                 cru_writel(ps->clksel0, RK3188_CRU_CLKSELS_CON(0));
 445                 cru_writel(ps->clksel1, RK3188_CRU_CLKSELS_CON(1));
 446         }
 447
 448         /* PLL return from slow mode */
 449         //FIXME
 450         //if (!sel_gpll)
 451         cru_writel(_RK3188_PLL_MODE_NORM_SET(pll->mode_shift), pll->mode_offset);
 452
 453         /* reparent to apll, and set div to 1 */
 454         if (sel_gpll) {
 455                 cru_writel(RK3188_CORE_SEL_PLL_W_MSK|RK3188_CORE_SEL_APLL,
 456                                 RK3188_CRU_CLKSELS_CON(0));
 457                 cru_writel(RK3188_CORE_CLK_DIV_W_MSK|RK3188_CORE_CLK_DIV(1),
 458                                 RK3188_CRU_CLKSELS_CON(0));
 459         }
 460
 461         if (old_aclk_div > new_aclk_div) {
 462                 cru_writel(ps->clksel0, RK3188_CRU_CLKSELS_CON(0));
 463                 cru_writel(ps->clksel1, RK3188_CRU_CLKSELS_CON(1));
 464         }
 465
 466         //loops_per_jiffy = ps->lpj;
 467         smp_wmb();
 468
 469         local_irq_restore(flags);
 470
 471         if (sel_gpll) {
 472                 sel_gpll = 0;
 473                 //clk_disable(arm_gpll);
 474                 //clk_unprepare(arm_gpll);
 475         }
 476
 477         //clk_debug("apll set loops_per_jiffy =%lu\n", loops_per_jiffy);
 478
 479         clk_debug("apll set rate %lu, con(%x,%x,%x,%x), sel(%x,%x)\n",
 480                         ps->rate,
 481                         readl(pll->reg + RK3188_PLL_CON(0)),
 482                         readl(pll->reg + RK3188_PLL_CON(1)),
 483                         readl(pll->reg + RK3188_PLL_CON(2)),
 484                         readl(pll->reg + RK3188_PLL_CON(3)),
 485                         cru_readl(RK3188_CRU_CLKSELS_CON(0)),
 486                         cru_readl(RK3188_CRU_CLKSELS_CON(1)));
 487
 488         return 0;
 489 }
 490
 491 static const struct clk_ops clk_pll_ops_3188 = {
 492         .recalc_rate = clk_pll_recalc_rate_3188,
 493         .round_rate = clk_pll_round_rate_3188,
 494         .set_rate = clk_pll_set_rate_3188,
 495 };
 496
 497 static const struct clk_ops clk_pll_ops_3188_apll = {
 498         .recalc_rate = clk_pll_recalc_rate_3188,
 499         .round_rate = clk_pll_round_rate_3188_apll,
 500         .set_rate = clk_pll_set_rate_3188_apll,
 501 };
 502
 503 static const struct clk_ops clk_pll_ops_3188plus = {
 504 #if 0
 505         .recalc_rate = clk_pll_recalc_rate,
 506         .round_rate = clk_pll_round_rate,
 507         .set_rate = clk_pll_set_rate,
 508 #endif
 509 };
 510
 511 static const struct clk_ops clk_pll_ops_3188plus_apll = {
 512 #if 0
 513         .recalc_rate = clk_pll_recalc_rate,
 514         .round_rate = clk_pll_round_rate,
 515         .set_rate = clk_pll_set_rate,
 516 #endif
 517 };
 518
 519 const struct clk_ops *rk_get_pll_ops(u32 pll_flags)
 520 {
 521         switch (pll_flags) {
 522                 case CLK_PLL_3188:
 523                         return &clk_pll_ops_3188;
 524
 525                 case CLK_PLL_3188_APLL:
 526                         return &clk_pll_ops_3188_apll;
 527
 528                 case CLK_PLL_3188PLUS:
 529                         return &clk_pll_ops_3188plus;
 530
 531                 case CLK_PLL_3188PLUS_APLL:
 532                         return &clk_pll_ops_3188plus_apll;
 533
 534                 default:
 535                         clk_err("%s: unknown pll_flags!\n", __func__);
 536                         return NULL;
 537         }
 538 }
 539
 540
 541 struct clk *rk_clk_register_pll(struct device *dev, const char *name,
 542                 const char *parent_name, unsigned long flags, void __iomem *reg,
 543                 u32 width, u32 mode_offset, u8 mode_shift,
 544                 u32 status_offset, u8 status_shift, u32 pll_flags,
 545                 spinlock_t *lock)
 546 {
 547         struct clk_pll *pll;
 548         struct clk *clk;
 549         struct clk_init_data init;
 550
 551
 552         clk_debug("%s: pll name = %s, pll_flags = 0x%x, register start!\n",
 553                         __func__, name, pll_flags);
 554
 555         /* allocate the pll */
 556         pll = kzalloc(sizeof(struct clk_pll), GFP_KERNEL);
 557         if (!pll) {
 558                 clk_err("%s: could not allocate pll clk\n", __func__);
 559                 return ERR_PTR(-ENOMEM);
 560         }
 561
 562         init.name = name;
 563         init.flags = flags;
 564         init.parent_names = (parent_name ? &parent_name: NULL);
 565         init.num_parents = (parent_name ? 1 : 0);
 566         init.ops = rk_get_pll_ops(pll_flags);
 567
 568         /* struct clk_pll assignments */
 569         pll->reg = reg;
 570         pll->width = width;
 571         pll->mode_offset = mode_offset;
 572         pll->mode_shift = mode_shift;
 573         pll->status_offset = status_offset;
 574         pll->status_shift = status_shift;
 575         pll->flags = pll_flags;
 576         pll->lock = lock;
 577         pll->hw.init = &init;
 578
 579         /* register the clock */
 580         clk = clk_register(dev, &pll->hw);
 581
 582         if (IS_ERR(clk))
 583                 kfree(pll);
 584
 585         clk_debug("%s: pll name = %s, pll_flags = 0x%x, register finish!\n",
 586                         __func__, name, pll_flags);
 587
 588         return clk;
 589 }
 590