drivers/clk/rockchip/clk-rk3399.c

   1 /*
   2  * Copyright (c) 2016 Rockchip Electronics Co. Ltd.
   3  * Author: Xing Zheng <zhengxing@rock-chips.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; either version 2 of the License, or
   8  * (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <linux/clk-provider.h>
  17 #include <linux/of.h>
  18 #include <linux/of_address.h>
  19 #include <linux/platform_device.h>
  20 #include <linux/regmap.h>
  21 #include <dt-bindings/clock/rk3399-cru.h>
  22 #include "clk.h"
  23
  24 enum rk3399_plls {
  25         lpll, bpll, dpll, cpll, gpll, npll, vpll,
  26 };
  27
  28 enum rk3399_pmu_plls {
  29         ppll,
  30 };
  31
  32 static struct rockchip_pll_rate_table rk3399_pll_rates[] = {
  33         /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
  34         RK3036_PLL_RATE(2208000000, 1, 92, 1, 1, 1, 0),
  35         RK3036_PLL_RATE(2184000000, 1, 91, 1, 1, 1, 0),
  36         RK3036_PLL_RATE(2160000000, 1, 90, 1, 1, 1, 0),
  37         RK3036_PLL_RATE(2136000000, 1, 89, 1, 1, 1, 0),
  38         RK3036_PLL_RATE(2112000000, 1, 88, 1, 1, 1, 0),
  39         RK3036_PLL_RATE(2088000000, 1, 87, 1, 1, 1, 0),
  40         RK3036_PLL_RATE(2064000000, 1, 86, 1, 1, 1, 0),
  41         RK3036_PLL_RATE(2040000000, 1, 85, 1, 1, 1, 0),
  42         RK3036_PLL_RATE(2016000000, 1, 84, 1, 1, 1, 0),
  43         RK3036_PLL_RATE(1992000000, 1, 83, 1, 1, 1, 0),
  44         RK3036_PLL_RATE(1968000000, 1, 82, 1, 1, 1, 0),
  45         RK3036_PLL_RATE(1944000000, 1, 81, 1, 1, 1, 0),
  46         RK3036_PLL_RATE(1920000000, 1, 80, 1, 1, 1, 0),
  47         RK3036_PLL_RATE(1896000000, 1, 79, 1, 1, 1, 0),
  48         RK3036_PLL_RATE(1872000000, 1, 78, 1, 1, 1, 0),
  49         RK3036_PLL_RATE(1848000000, 1, 77, 1, 1, 1, 0),
  50         RK3036_PLL_RATE(1824000000, 1, 76, 1, 1, 1, 0),
  51         RK3036_PLL_RATE(1800000000, 1, 75, 1, 1, 1, 0),
  52         RK3036_PLL_RATE(1776000000, 1, 74, 1, 1, 1, 0),
  53         RK3036_PLL_RATE(1752000000, 1, 73, 1, 1, 1, 0),
  54         RK3036_PLL_RATE(1728000000, 1, 72, 1, 1, 1, 0),
  55         RK3036_PLL_RATE(1704000000, 1, 71, 1, 1, 1, 0),
  56         RK3036_PLL_RATE(1680000000, 1, 70, 1, 1, 1, 0),
  57         RK3036_PLL_RATE(1656000000, 1, 69, 1, 1, 1, 0),
  58         RK3036_PLL_RATE(1632000000, 1, 68, 1, 1, 1, 0),
  59         RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0),
  60         RK3036_PLL_RATE(1584000000, 1, 66, 1, 1, 1, 0),
  61         RK3036_PLL_RATE(1560000000, 1, 65, 1, 1, 1, 0),
  62         RK3036_PLL_RATE(1536000000, 1, 64, 1, 1, 1, 0),
  63         RK3036_PLL_RATE(1512000000, 1, 63, 1, 1, 1, 0),
  64         RK3036_PLL_RATE(1488000000, 1, 62, 1, 1, 1, 0),
  65         RK3036_PLL_RATE(1464000000, 1, 61, 1, 1, 1, 0),
  66         RK3036_PLL_RATE(1440000000, 1, 60, 1, 1, 1, 0),
  67         RK3036_PLL_RATE(1416000000, 1, 59, 1, 1, 1, 0),
  68         RK3036_PLL_RATE(1392000000, 1, 58, 1, 1, 1, 0),
  69         RK3036_PLL_RATE(1368000000, 1, 57, 1, 1, 1, 0),
  70         RK3036_PLL_RATE(1344000000, 1, 56, 1, 1, 1, 0),
  71         RK3036_PLL_RATE(1320000000, 1, 55, 1, 1, 1, 0),
  72         RK3036_PLL_RATE(1296000000, 1, 54, 1, 1, 1, 0),
  73         RK3036_PLL_RATE(1272000000, 1, 53, 1, 1, 1, 0),
  74         RK3036_PLL_RATE(1248000000, 1, 52, 1, 1, 1, 0),
  75         RK3036_PLL_RATE(1200000000, 1, 50, 1, 1, 1, 0),
  76         RK3036_PLL_RATE(1188000000, 2, 99, 1, 1, 1, 0),
  77         RK3036_PLL_RATE(1104000000, 1, 46, 1, 1, 1, 0),
  78         RK3036_PLL_RATE(1100000000, 12, 550, 1, 1, 1, 0),
  79         RK3036_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0),
  80         RK3036_PLL_RATE(1000000000, 6, 500, 2, 1, 1, 0),
  81         RK3036_PLL_RATE( 984000000, 1, 82, 2, 1, 1, 0),
  82         RK3036_PLL_RATE( 960000000, 1, 80, 2, 1, 1, 0),
  83         RK3036_PLL_RATE( 936000000, 1, 78, 2, 1, 1, 0),
  84         RK3036_PLL_RATE( 912000000, 1, 76, 2, 1, 1, 0),
  85         RK3036_PLL_RATE( 900000000, 4, 300, 2, 1, 1, 0),
  86         RK3036_PLL_RATE( 888000000, 1, 74, 2, 1, 1, 0),
  87         RK3036_PLL_RATE( 864000000, 1, 72, 2, 1, 1, 0),
  88         RK3036_PLL_RATE( 840000000, 1, 70, 2, 1, 1, 0),
  89         RK3036_PLL_RATE( 816000000, 1, 68, 2, 1, 1, 0),
  90         RK3036_PLL_RATE( 800000000, 6, 400, 2, 1, 1, 0),
  91         RK3036_PLL_RATE( 700000000, 6, 350, 2, 1, 1, 0),
  92         RK3036_PLL_RATE( 696000000, 1, 58, 2, 1, 1, 0),
  93         RK3036_PLL_RATE( 676000000, 3, 169, 2, 1, 1, 0),
  94         RK3036_PLL_RATE( 600000000, 1, 75, 3, 1, 1, 0),
  95         RK3036_PLL_RATE( 594000000, 1, 99, 4, 1, 1, 0),
  96         RK3036_PLL_RATE( 504000000, 1, 63, 3, 1, 1, 0),
  97         RK3036_PLL_RATE( 500000000, 6, 250, 2, 1, 1, 0),
  98         RK3036_PLL_RATE( 408000000, 1, 68, 2, 2, 1, 0),
  99         RK3036_PLL_RATE( 312000000, 1, 52, 2, 2, 1, 0),
 100         RK3036_PLL_RATE( 297000000, 1, 99, 4, 2, 1, 0),
 101         RK3036_PLL_RATE( 216000000, 1, 72, 4, 2, 1, 0),
 102         RK3036_PLL_RATE( 148500000, 1, 99, 4, 4, 1, 0),
 103         RK3036_PLL_RATE( 106500000, 1, 71, 4, 4, 1, 0),
 104         RK3036_PLL_RATE(  96000000, 1, 64, 4, 4, 1, 0),
 105         RK3036_PLL_RATE(  74250000, 2, 99, 4, 4, 1, 0),
 106         RK3036_PLL_RATE(  65000000, 1, 65, 6, 4, 1, 0),
 107         RK3036_PLL_RATE(  54000000, 1, 54, 6, 4, 1, 0),
 108         RK3036_PLL_RATE(  27000000, 1, 27, 6, 4, 1, 0),
 109         { /* sentinel */ },
 110 };
 111
 112 static struct rockchip_pll_rate_table rk3399_vpll_rates[] = {
 113         /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
 114         RK3036_PLL_RATE( 594000000, 1, 123, 5, 1, 0, 12582912),  /* vco = 2970000000 */
 115         RK3036_PLL_RATE( 593406593, 1, 123, 5, 1, 0, 10508804),  /* vco = 2967032965 */
 116         RK3036_PLL_RATE( 297000000, 1, 123, 5, 2, 0, 12582912),  /* vco = 2970000000 */
 117         RK3036_PLL_RATE( 296703297, 1, 123, 5, 2, 0, 10508807),  /* vco = 2967032970 */
 118         RK3036_PLL_RATE( 148500000, 1, 129, 7, 3, 0, 15728640),  /* vco = 3118500000 */
 119         RK3036_PLL_RATE( 148351648, 1, 123, 5, 4, 0, 10508800),  /* vco = 2967032960 */
 120         RK3036_PLL_RATE( 106500000, 1, 124, 7, 4, 0,  4194304),  /* vco = 2982000000 */
 121         RK3036_PLL_RATE(  74250000, 1, 129, 7, 6, 0, 15728640),  /* vco = 3118500000 */
 122         RK3036_PLL_RATE(  74175824, 1, 129, 7, 6, 0, 13550823),  /* vco = 3115384608 */
 123         RK3036_PLL_RATE(  65000000, 1, 113, 7, 6, 0, 12582912),  /* vco = 2730000000 */
 124         RK3036_PLL_RATE(  59340659, 1, 121, 7, 7, 0,  2581098),  /* vco = 2907692291 */
 125         RK3036_PLL_RATE(  54000000, 1, 110, 7, 7, 0,  4194304),  /* vco = 2646000000 */
 126         RK3036_PLL_RATE(  27000000, 1,  55, 7, 7, 0,  2097152),  /* vco = 1323000000 */
 127         RK3036_PLL_RATE(  26973027, 1,  55, 7, 7, 0,  1173232),  /* vco = 1321678323 */
 128         { /* sentinel */ },
 129 };
 130
 131 /* CRU parents */
 132 PNAME(mux_pll_p)                                = { "xin24m", "xin32k" };
 133
 134 PNAME(mux_armclkl_p)                            = { "clk_core_l_lpll_src",
 135                                                     "clk_core_l_bpll_src",
 136                                                     "clk_core_l_dpll_src",
 137                                                     "clk_core_l_gpll_src" };
 138 PNAME(mux_armclkb_p)                            = { "clk_core_b_lpll_src",
 139                                                     "clk_core_b_bpll_src",
 140                                                     "clk_core_b_dpll_src",
 141                                                     "clk_core_b_gpll_src" };
 142 PNAME(mux_ddrclk_p)                             = { "clk_ddrc_lpll_src",
 143                                                     "clk_ddrc_bpll_src",
 144                                                     "clk_ddrc_dpll_src",
 145                                                     "clk_ddrc_gpll_src" };
 146
 147 PNAME(mux_pll_src_vpll_cpll_gpll_p)             = { "vpll", "cpll", "gpll" };
 148 PNAME(mux_pll_src_dmyvpll_cpll_gpll_p)          = { "dummy_vpll", "cpll", "gpll" };
 149
 150 #ifdef RK3399_TWO_PLL_FOR_VOP
 151 PNAME(mux_aclk_cci_p)                           = { "dummy_cpll",
 152                                                     "gpll_aclk_cci_src",
 153                                                     "npll_aclk_cci_src",
 154                                                     "vpll_aclk_cci_src" };
 155 PNAME(mux_cci_trace_p)                          = { "dummy_cpll",
 156                                                     "gpll_cci_trace" };
 157 PNAME(mux_cs_p)                                 = { "dummy_cpll", "gpll_cs",
 158                                                     "npll_cs"};
 159 PNAME(mux_aclk_perihp_p)                        = { "dummy_cpll",
 160                                                     "gpll_aclk_perihp_src" };
 161
 162 PNAME(mux_pll_src_cpll_gpll_p)                  = { "dummy_cpll", "gpll" };
 163 PNAME(mux_pll_src_cpll_gpll_npll_p)             = { "dummy_cpll", "gpll", "npll" };
 164 PNAME(mux_pll_src_cpll_gpll_ppll_p)             = { "dummy_cpll", "gpll", "ppll" };
 165 PNAME(mux_pll_src_cpll_gpll_upll_p)             = { "dummy_cpll", "gpll", "upll" };
 166 PNAME(mux_pll_src_npll_cpll_gpll_p)             = { "npll", "dummy_cpll", "gpll" };
 167 PNAME(mux_pll_src_cpll_gpll_npll_ppll_p)        = { "dummy_cpll", "gpll", "npll",
 168                                                     "ppll" };
 169 PNAME(mux_pll_src_cpll_gpll_npll_24m_p)         = { "dummy_cpll", "gpll", "npll",
 170                                                     "xin24m" };
 171 PNAME(mux_pll_src_cpll_gpll_npll_usbphy480m_p)  = { "dummy_cpll", "gpll", "npll",
 172                                                     "clk_usbphy_480m" };
 173 PNAME(mux_pll_src_ppll_cpll_gpll_npll_p)        = { "ppll", "dummy_cpll", "gpll",
 174                                                     "npll", "upll" };
 175 PNAME(mux_pll_src_cpll_gpll_npll_upll_24m_p)    = { "dummy_cpll", "gpll", "npll",
 176                                                     "upll", "xin24m" };
 177 PNAME(mux_pll_src_cpll_gpll_npll_ppll_upll_24m_p) = { "dummy_cpll", "gpll", "npll",
 178                                                     "ppll", "upll", "xin24m" };
 179 /*
 180  * We hope to be able to HDMI/DP can obtain better signal quality,
 181  * therefore, we move VOP pwm and aclk clocks to other PLLs, let
 182  * HDMI/DP phyclock can monopolize VPLL.
 183  */
 184 PNAME(mux_pll_src_dmyvpll_cpll_gpll_npll_p)     = { "dummy_vpll", "dummy_cpll", "gpll",
 185                                                     "npll" };
 186 PNAME(mux_pll_src_dmyvpll_cpll_gpll_24m_p)      = { "dummy_vpll", "dummy_cpll", "gpll",
 187                                                     "xin24m" };
 188 PNAME(mux_pll_src_24m_32k_cpll_gpll_p)  = { "xin24m", "xin32k",
 189                                             "dummy_cpll", "gpll" };
 190
 191 PNAME(mux_aclk_emmc_p)                  = { "dummy_cpll",
 192                                             "gpll_aclk_emmc_src" };
 193
 194 PNAME(mux_aclk_perilp0_p)               = { "dummy_cpll",
 195                                             "gpll_aclk_perilp0_src" };
 196
 197 PNAME(mux_fclk_cm0s_p)                  = { "dummy_cpll",
 198                                             "gpll_fclk_cm0s_src" };
 199
 200 PNAME(mux_hclk_perilp1_p)               = { "dummy_cpll",
 201                                             "gpll_hclk_perilp1_src" };
 202 PNAME(mux_aclk_gmac_p)                  = { "dummy_cpll",
 203                                             "gpll_aclk_gmac_src" };
 204 #else
 205 PNAME(mux_aclk_cci_p)                           = { "cpll_aclk_cci_src",
 206                                                     "gpll_aclk_cci_src",
 207                                                     "npll_aclk_cci_src",
 208                                                     "vpll_aclk_cci_src" };
 209 PNAME(mux_cci_trace_p)                          = { "cpll_cci_trace",
 210                                                     "gpll_cci_trace" };
 211 PNAME(mux_cs_p)                                 = { "cpll_cs", "gpll_cs",
 212                                                     "npll_cs"};
 213 PNAME(mux_aclk_perihp_p)                        = { "cpll_aclk_perihp_src",
 214                                                     "gpll_aclk_perihp_src" };
 215
 216 PNAME(mux_pll_src_cpll_gpll_p)                  = { "cpll", "gpll" };
 217 PNAME(mux_pll_src_cpll_gpll_npll_p)             = { "cpll", "gpll", "npll" };
 218 PNAME(mux_pll_src_cpll_gpll_ppll_p)             = { "cpll", "gpll", "ppll" };
 219 PNAME(mux_pll_src_cpll_gpll_upll_p)             = { "cpll", "gpll", "upll" };
 220 PNAME(mux_pll_src_npll_cpll_gpll_p)             = { "npll", "cpll", "gpll" };
 221 PNAME(mux_pll_src_cpll_gpll_npll_ppll_p)        = { "cpll", "gpll", "npll",
 222                                                     "ppll" };
 223 PNAME(mux_pll_src_cpll_gpll_npll_24m_p)         = { "cpll", "gpll", "npll",
 224                                                     "xin24m" };
 225 PNAME(mux_pll_src_cpll_gpll_npll_usbphy480m_p)  = { "cpll", "gpll", "npll",
 226                                                     "clk_usbphy_480m" };
 227 PNAME(mux_pll_src_ppll_cpll_gpll_npll_p)        = { "ppll", "cpll", "gpll",
 228                                                     "npll", "upll" };
 229 PNAME(mux_pll_src_cpll_gpll_npll_upll_24m_p)    = { "cpll", "gpll", "npll",
 230                                                     "upll", "xin24m" };
 231 PNAME(mux_pll_src_cpll_gpll_npll_ppll_upll_24m_p) = { "cpll", "gpll", "npll",
 232                                                     "ppll", "upll", "xin24m" };
 233 /*
 234  * We hope to be able to HDMI/DP can obtain better signal quality,
 235  * therefore, we move VOP pwm and aclk clocks to other PLLs, let
 236  * HDMI/DP phyclock can monopolize VPLL.
 237  */
 238 PNAME(mux_pll_src_dmyvpll_cpll_gpll_npll_p)     = { "dummy_vpll", "cpll", "gpll",
 239                                                     "npll" };
 240 PNAME(mux_pll_src_dmyvpll_cpll_gpll_24m_p)      = { "dummy_vpll", "cpll", "gpll",
 241                                                     "xin24m" };
 242 PNAME(mux_pll_src_24m_32k_cpll_gpll_p)  = { "xin24m", "xin32k",
 243                                             "cpll", "gpll" };
 244
 245 PNAME(mux_aclk_emmc_p)                  = { "cpll_aclk_emmc_src",
 246                                             "gpll_aclk_emmc_src" };
 247
 248 PNAME(mux_aclk_perilp0_p)               = { "cpll_aclk_perilp0_src",
 249                                             "gpll_aclk_perilp0_src" };
 250
 251 PNAME(mux_fclk_cm0s_p)                  = { "cpll_fclk_cm0s_src",
 252                                             "gpll_fclk_cm0s_src" };
 253
 254 PNAME(mux_hclk_perilp1_p)               = { "cpll_hclk_perilp1_src",
 255                                             "gpll_hclk_perilp1_src" };
 256 PNAME(mux_aclk_gmac_p)                  = { "cpll_aclk_gmac_src",
 257                                             "gpll_aclk_gmac_src" };
 258 #endif
 259
 260 PNAME(mux_dclk_vop0_p)                  = { "dclk_vop0_div",
 261                                             "dummy_dclk_vop0_frac" };
 262 PNAME(mux_dclk_vop1_p)                  = { "dclk_vop1_div",
 263                                             "dummy_dclk_vop1_frac" };
 264
 265 PNAME(mux_clk_cif_p)                    = { "clk_cifout_src", "xin24m" };
 266
 267 PNAME(mux_pll_src_24m_usbphy480m_p)     = { "xin24m", "clk_usbphy_480m" };
 268 PNAME(mux_pll_src_24m_pciephy_p)        = { "xin24m", "clk_pciephy_ref100m" };
 269 PNAME(mux_pciecore_cru_phy_p)           = { "clk_pcie_core_cru",
 270                                             "clk_pcie_core_phy" };
 271 PNAME(mux_clk_testout1_p)               = { "clk_testout1_pll_src", "xin24m" };
 272 PNAME(mux_clk_testout2_p)               = { "clk_testout2_pll_src", "xin24m" };
 273
 274 PNAME(mux_usbphy_480m_p)                = { "clk_usbphy0_480m_src",
 275                                             "clk_usbphy1_480m_src" };
 276 PNAME(mux_rmii_p)                       = { "clk_gmac", "clkin_gmac" };
 277 PNAME(mux_spdif_p)                      = { "clk_spdif_div", "clk_spdif_frac",
 278                                             "clkin_i2s", "xin12m" };
 279 PNAME(mux_i2s0_p)                       = { "clk_i2s0_div", "clk_i2s0_frac",
 280                                             "clkin_i2s", "xin12m" };
 281 PNAME(mux_i2s1_p)                       = { "clk_i2s1_div", "clk_i2s1_frac",
 282                                             "clkin_i2s", "xin12m" };
 283 PNAME(mux_i2s2_p)                       = { "clk_i2s2_div", "clk_i2s2_frac",
 284                                             "clkin_i2s", "xin12m" };
 285 PNAME(mux_i2sch_p)                      = { "clk_i2s0", "clk_i2s1",
 286                                             "clk_i2s2" };
 287 PNAME(mux_i2sout_p)                     = { "clk_i2sout_src", "xin12m" };
 288
 289 PNAME(mux_uart0_p)      = { "clk_uart0_div", "clk_uart0_frac", "xin24m" };
 290 PNAME(mux_uart1_p)      = { "clk_uart1_div", "clk_uart1_frac", "xin24m" };
 291 PNAME(mux_uart2_p)      = { "clk_uart2_div", "clk_uart2_frac", "xin24m" };
 292 PNAME(mux_uart3_p)      = { "clk_uart3_div", "clk_uart3_frac", "xin24m" };
 293
 294 /* PMU CRU parents */
 295 PNAME(mux_ppll_24m_p)           = { "ppll", "xin24m" };
 296 PNAME(mux_24m_ppll_p)           = { "xin24m", "ppll" };
 297 PNAME(mux_fclk_cm0s_pmu_ppll_p) = { "fclk_cm0s_pmu_ppll_src", "xin24m" };
 298 PNAME(mux_wifi_pmu_p)           = { "clk_wifi_div", "clk_wifi_frac" };
 299 PNAME(mux_uart4_pmu_p)          = { "clk_uart4_div", "clk_uart4_frac",
 300                                     "xin24m" };
 301 PNAME(mux_clk_testout2_2io_p)   = { "clk_testout2", "clk_32k_suspend_pmu" };
 302
 303 static struct rockchip_pll_clock rk3399_pll_clks[] __initdata = {
 304         [lpll] = PLL(pll_rk3399, PLL_APLLL, "lpll", mux_pll_p, 0, RK3399_PLL_CON(0),
 305                      RK3399_PLL_CON(3), 8, 31, 0, rk3399_pll_rates),
 306         [bpll] = PLL(pll_rk3399, PLL_APLLB, "bpll", mux_pll_p, 0, RK3399_PLL_CON(8),
 307                      RK3399_PLL_CON(11), 8, 31, 0, rk3399_pll_rates),
 308         [dpll] = PLL(pll_rk3399, PLL_DPLL, "dpll", mux_pll_p, 0, RK3399_PLL_CON(16),
 309                      RK3399_PLL_CON(19), 8, 31, 0, NULL),
 310         [cpll] = PLL(pll_rk3399, PLL_CPLL, "cpll", mux_pll_p, 0, RK3399_PLL_CON(24),
 311                      RK3399_PLL_CON(27), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rk3399_pll_rates),
 312         [gpll] = PLL(pll_rk3399, PLL_GPLL, "gpll", mux_pll_p, 0, RK3399_PLL_CON(32),
 313                      RK3399_PLL_CON(35), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rk3399_pll_rates),
 314         [npll] = PLL(pll_rk3399, PLL_NPLL, "npll",  mux_pll_p, 0, RK3399_PLL_CON(40),
 315                      RK3399_PLL_CON(43), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rk3399_pll_rates),
 316         [vpll] = PLL(pll_rk3399, PLL_VPLL, "vpll",  mux_pll_p, 0, RK3399_PLL_CON(48),
 317                      RK3399_PLL_CON(51), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rk3399_vpll_rates),
 318 };
 319
 320 static struct rockchip_pll_clock rk3399_pmu_pll_clks[] __initdata = {
 321         [ppll] = PLL(pll_rk3399, PLL_PPLL, "ppll",  mux_pll_p, 0, RK3399_PMU_PLL_CON(0),
 322                      RK3399_PMU_PLL_CON(3), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rk3399_pll_rates),
 323 };
 324
 325 #define MFLAGS CLK_MUX_HIWORD_MASK
 326 #define DFLAGS CLK_DIVIDER_HIWORD_MASK
 327 #define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)
 328 #define IFLAGS ROCKCHIP_INVERTER_HIWORD_MASK
 329
 330 static struct rockchip_clk_branch rk3399_spdif_fracmux __initdata =
 331         MUX(0, "clk_spdif_mux", mux_spdif_p, CLK_SET_RATE_PARENT,
 332                         RK3399_CLKSEL_CON(32), 13, 2, MFLAGS);
 333
 334 static struct rockchip_clk_branch rk3399_i2s0_fracmux __initdata =
 335         MUX(0, "clk_i2s0_mux", mux_i2s0_p, CLK_SET_RATE_PARENT,
 336                         RK3399_CLKSEL_CON(28), 8, 2, MFLAGS);
 337
 338 static struct rockchip_clk_branch rk3399_i2s1_fracmux __initdata =
 339         MUX(0, "clk_i2s1_mux", mux_i2s1_p, CLK_SET_RATE_PARENT,
 340                         RK3399_CLKSEL_CON(29), 8, 2, MFLAGS);
 341
 342 static struct rockchip_clk_branch rk3399_i2s2_fracmux __initdata =
 343         MUX(0, "clk_i2s2_mux", mux_i2s2_p, CLK_SET_RATE_PARENT,
 344                         RK3399_CLKSEL_CON(30), 8, 2, MFLAGS);
 345
 346 static struct rockchip_clk_branch rk3399_uart0_fracmux __initdata =
 347         MUX(SCLK_UART0, "clk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT,
 348                         RK3399_CLKSEL_CON(33), 8, 2, MFLAGS);
 349
 350 static struct rockchip_clk_branch rk3399_uart1_fracmux __initdata =
 351         MUX(SCLK_UART1, "clk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT,
 352                         RK3399_CLKSEL_CON(34), 8, 2, MFLAGS);
 353
 354 static struct rockchip_clk_branch rk3399_uart2_fracmux __initdata =
 355         MUX(SCLK_UART2, "clk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT,
 356                         RK3399_CLKSEL_CON(35), 8, 2, MFLAGS);
 357
 358 static struct rockchip_clk_branch rk3399_uart3_fracmux __initdata =
 359         MUX(SCLK_UART3, "clk_uart3", mux_uart3_p, CLK_SET_RATE_PARENT,
 360                         RK3399_CLKSEL_CON(36), 8, 2, MFLAGS);
 361
 362 static struct rockchip_clk_branch rk3399_uart4_pmu_fracmux __initdata =
 363         MUX(SCLK_UART4_PMU, "clk_uart4_pmu", mux_uart4_pmu_p, CLK_SET_RATE_PARENT,
 364                         RK3399_PMU_CLKSEL_CON(5), 8, 2, MFLAGS);
 365
 366 static struct rockchip_clk_branch rk3399_dclk_vop0_fracmux __initdata =
 367         MUX(DCLK_VOP0, "dclk_vop0", mux_dclk_vop0_p, CLK_SET_RATE_PARENT | CLK_KEEP_REQ_RATE,
 368                         RK3399_CLKSEL_CON(49), 11, 1, MFLAGS);
 369
 370 static struct rockchip_clk_branch rk3399_dclk_vop1_fracmux __initdata =
 371         MUX(DCLK_VOP1, "dclk_vop1", mux_dclk_vop1_p, CLK_SET_RATE_PARENT | CLK_KEEP_REQ_RATE,
 372                         RK3399_CLKSEL_CON(50), 11, 1, MFLAGS);
 373
 374 static struct rockchip_clk_branch rk3399_pmuclk_wifi_fracmux __initdata =
 375         MUX(SCLK_WIFI_PMU, "clk_wifi_pmu", mux_wifi_pmu_p, CLK_SET_RATE_PARENT,
 376                         RK3399_PMU_CLKSEL_CON(1), 14, 1, MFLAGS);
 377
 378 static const struct rockchip_cpuclk_reg_data rk3399_cpuclkl_data = {
 379         .core_reg = RK3399_CLKSEL_CON(0),
 380         .div_core_shift = 0,
 381         .div_core_mask = 0x1f,
 382         .mux_core_alt = 3,
 383         .mux_core_main = 0,
 384         .mux_core_shift = 6,
 385         .mux_core_mask = 0x3,
 386 };
 387
 388 static const struct rockchip_cpuclk_reg_data rk3399_cpuclkb_data = {
 389         .core_reg = RK3399_CLKSEL_CON(2),
 390         .div_core_shift = 0,
 391         .div_core_mask = 0x1f,
 392         .mux_core_alt = 3,
 393         .mux_core_main = 1,
 394         .mux_core_shift = 6,
 395         .mux_core_mask = 0x3,
 396 };
 397
 398 #define RK3399_DIV_ACLKM_MASK           0x1f
 399 #define RK3399_DIV_ACLKM_SHIFT          8
 400 #define RK3399_DIV_ATCLK_MASK           0x1f
 401 #define RK3399_DIV_ATCLK_SHIFT          0
 402 #define RK3399_DIV_PCLK_DBG_MASK        0x1f
 403 #define RK3399_DIV_PCLK_DBG_SHIFT       8
 404
 405 #define RK3399_CLKSEL0(_offs, _aclkm)                                   \
 406         {                                                               \
 407                 .reg = RK3399_CLKSEL_CON(0 + _offs),                    \
 408                 .val = HIWORD_UPDATE(_aclkm, RK3399_DIV_ACLKM_MASK,     \
 409                                 RK3399_DIV_ACLKM_SHIFT),                \
 410         }
 411 #define RK3399_CLKSEL1(_offs, _atclk, _pdbg)                            \
 412         {                                                               \
 413                 .reg = RK3399_CLKSEL_CON(1 + _offs),                    \
 414                 .val = HIWORD_UPDATE(_atclk, RK3399_DIV_ATCLK_MASK,     \
 415                                 RK3399_DIV_ATCLK_SHIFT) |               \
 416                        HIWORD_UPDATE(_pdbg, RK3399_DIV_PCLK_DBG_MASK,   \
 417                                 RK3399_DIV_PCLK_DBG_SHIFT),             \
 418         }
 419
 420 /* cluster_l: aclkm in clksel0, rest in clksel1 */
 421 #define RK3399_CPUCLKL_RATE(_prate, _aclkm, _atclk, _pdbg)              \
 422         {                                                               \
 423                 .prate = _prate##U,                                     \
 424                 .divs = {                                               \
 425                         RK3399_CLKSEL0(0, _aclkm),                      \
 426                         RK3399_CLKSEL1(0, _atclk, _pdbg),               \
 427                 },                                                      \
 428         }
 429
 430 /* cluster_b: aclkm in clksel2, rest in clksel3 */
 431 #define RK3399_CPUCLKB_RATE(_prate, _aclkm, _atclk, _pdbg)              \
 432         {                                                               \
 433                 .prate = _prate##U,                                     \
 434                 .divs = {                                               \
 435                         RK3399_CLKSEL0(2, _aclkm),                      \
 436                         RK3399_CLKSEL1(2, _atclk, _pdbg),               \
 437                 },                                                      \
 438         }
 439
 440 static struct rockchip_cpuclk_rate_table rk3399_cpuclkl_rates[] __initdata = {
 441         RK3399_CPUCLKL_RATE(1800000000, 1, 8, 8),
 442         RK3399_CPUCLKL_RATE(1704000000, 1, 8, 8),
 443         RK3399_CPUCLKL_RATE(1608000000, 1, 7, 7),
 444         RK3399_CPUCLKL_RATE(1512000000, 1, 7, 7),
 445         RK3399_CPUCLKL_RATE(1488000000, 1, 6, 6),
 446         RK3399_CPUCLKL_RATE(1416000000, 1, 6, 6),
 447         RK3399_CPUCLKL_RATE(1200000000, 1, 5, 5),
 448         RK3399_CPUCLKL_RATE(1008000000, 1, 5, 5),
 449         RK3399_CPUCLKL_RATE( 816000000, 1, 4, 4),
 450         RK3399_CPUCLKL_RATE( 696000000, 1, 3, 3),
 451         RK3399_CPUCLKL_RATE( 600000000, 1, 3, 3),
 452         RK3399_CPUCLKL_RATE( 408000000, 1, 2, 2),
 453         RK3399_CPUCLKL_RATE( 312000000, 1, 1, 1),
 454         RK3399_CPUCLKL_RATE( 216000000, 1, 1, 1),
 455         RK3399_CPUCLKL_RATE(  96000000, 1, 1, 1),
 456 };
 457
 458 static struct rockchip_cpuclk_rate_table rk3399_cpuclkb_rates[] __initdata = {
 459         RK3399_CPUCLKB_RATE(2208000000, 1, 11, 11),
 460         RK3399_CPUCLKB_RATE(2184000000, 1, 11, 11),
 461         RK3399_CPUCLKB_RATE(2088000000, 1, 10, 10),
 462         RK3399_CPUCLKB_RATE(2040000000, 1, 10, 10),
 463         RK3399_CPUCLKB_RATE(2016000000, 1, 9, 9),
 464         RK3399_CPUCLKB_RATE(1992000000, 1, 9, 9),
 465         RK3399_CPUCLKB_RATE(1896000000, 1, 9, 9),
 466         RK3399_CPUCLKB_RATE(1800000000, 1, 8, 8),
 467         RK3399_CPUCLKB_RATE(1704000000, 1, 8, 8),
 468         RK3399_CPUCLKB_RATE(1608000000, 1, 7, 7),
 469         RK3399_CPUCLKB_RATE(1512000000, 1, 7, 7),
 470         RK3399_CPUCLKB_RATE(1488000000, 1, 6, 6),
 471         RK3399_CPUCLKB_RATE(1416000000, 1, 6, 6),
 472         RK3399_CPUCLKB_RATE(1200000000, 1, 5, 5),
 473         RK3399_CPUCLKB_RATE(1008000000, 1, 5, 5),
 474         RK3399_CPUCLKB_RATE( 816000000, 1, 4, 4),
 475         RK3399_CPUCLKB_RATE( 696000000, 1, 3, 3),
 476         RK3399_CPUCLKB_RATE( 600000000, 1, 3, 3),
 477         RK3399_CPUCLKB_RATE( 408000000, 1, 2, 2),
 478         RK3399_CPUCLKB_RATE( 312000000, 1, 1, 1),
 479         RK3399_CPUCLKB_RATE( 216000000, 1, 1, 1),
 480         RK3399_CPUCLKB_RATE(  96000000, 1, 1, 1),
 481 };
 482
 483 static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
 484         /*
 485          * CRU Clock-Architecture
 486          */
 487
 488         /* usbphy */
 489         GATE(SCLK_USB2PHY0_REF, "clk_usb2phy0_ref", "xin24m", CLK_IGNORE_UNUSED,
 490                         RK3399_CLKGATE_CON(6), 5, GFLAGS),
 491         GATE(SCLK_USB2PHY1_REF, "clk_usb2phy1_ref", "xin24m", CLK_IGNORE_UNUSED,
 492                         RK3399_CLKGATE_CON(6), 6, GFLAGS),
 493
 494         GATE(SCLK_USBPHY0_480M_SRC, "clk_usbphy0_480m_src", "clk_usbphy0_480m", 0,
 495                         RK3399_CLKGATE_CON(13), 12, GFLAGS),
 496         GATE(SCLK_USBPHY1_480M_SRC, "clk_usbphy1_480m_src", "clk_usbphy1_480m", 0,
 497                         RK3399_CLKGATE_CON(13), 12, GFLAGS),
 498         MUX(0, "clk_usbphy_480m", mux_usbphy_480m_p, 0,
 499                         RK3399_CLKSEL_CON(14), 6, 1, MFLAGS),
 500
 501         MUX(0, "upll", mux_pll_src_24m_usbphy480m_p, 0,
 502                         RK3399_CLKSEL_CON(14), 15, 1, MFLAGS),
 503
 504         COMPOSITE_NODIV(SCLK_HSICPHY, "clk_hsicphy", mux_pll_src_cpll_gpll_npll_usbphy480m_p, 0,
 505                         RK3399_CLKSEL_CON(19), 0, 2, MFLAGS,
 506                         RK3399_CLKGATE_CON(6), 4, GFLAGS),
 507
 508         COMPOSITE(ACLK_USB3, "aclk_usb3", mux_pll_src_cpll_gpll_npll_p, 0,
 509                         RK3399_CLKSEL_CON(39), 6, 2, MFLAGS, 0, 5, DFLAGS,
 510                         RK3399_CLKGATE_CON(12), 0, GFLAGS),
 511         GATE(ACLK_USB3_NOC, "aclk_usb3_noc", "aclk_usb3", CLK_IGNORE_UNUSED,
 512                         RK3399_CLKGATE_CON(30), 0, GFLAGS),
 513         GATE(ACLK_USB3OTG0, "aclk_usb3otg0", "aclk_usb3", 0,
 514                         RK3399_CLKGATE_CON(30), 1, GFLAGS),
 515         GATE(ACLK_USB3OTG1, "aclk_usb3otg1", "aclk_usb3", 0,
 516                         RK3399_CLKGATE_CON(30), 2, GFLAGS),
 517         GATE(ACLK_USB3_RKSOC_AXI_PERF, "aclk_usb3_rksoc_axi_perf", "aclk_usb3", 0,
 518                         RK3399_CLKGATE_CON(30), 3, GFLAGS),
 519         GATE(ACLK_USB3_GRF, "aclk_usb3_grf", "aclk_usb3", 0,
 520                         RK3399_CLKGATE_CON(30), 4, GFLAGS),
 521
 522         GATE(SCLK_USB3OTG0_REF, "clk_usb3otg0_ref", "xin24m", 0,
 523                         RK3399_CLKGATE_CON(12), 1, GFLAGS),
 524         GATE(SCLK_USB3OTG1_REF, "clk_usb3otg1_ref", "xin24m", 0,
 525                         RK3399_CLKGATE_CON(12), 2, GFLAGS),
 526
 527         COMPOSITE(SCLK_USB3OTG0_SUSPEND, "clk_usb3otg0_suspend", mux_pll_p, 0,
 528                         RK3399_CLKSEL_CON(40), 15, 1, MFLAGS, 0, 10, DFLAGS,
 529                         RK3399_CLKGATE_CON(12), 3, GFLAGS),
 530
 531         COMPOSITE(SCLK_USB3OTG1_SUSPEND, "clk_usb3otg1_suspend", mux_pll_p, 0,
 532                         RK3399_CLKSEL_CON(41), 15, 1, MFLAGS, 0, 10, DFLAGS,
 533                         RK3399_CLKGATE_CON(12), 4, GFLAGS),
 534
 535         COMPOSITE(SCLK_UPHY0_TCPDPHY_REF, "clk_uphy0_tcpdphy_ref", mux_pll_p, 0,
 536                         RK3399_CLKSEL_CON(64), 15, 1, MFLAGS, 8, 5, DFLAGS,
 537                         RK3399_CLKGATE_CON(13), 4, GFLAGS),
 538
 539         COMPOSITE(SCLK_UPHY0_TCPDCORE, "clk_uphy0_tcpdcore", mux_pll_src_24m_32k_cpll_gpll_p, 0,
 540                         RK3399_CLKSEL_CON(64), 6, 2, MFLAGS, 0, 5, DFLAGS,
 541                         RK3399_CLKGATE_CON(13), 5, GFLAGS),
 542
 543         COMPOSITE(SCLK_UPHY1_TCPDPHY_REF, "clk_uphy1_tcpdphy_ref", mux_pll_p, 0,
 544                         RK3399_CLKSEL_CON(65), 15, 1, MFLAGS, 8, 5, DFLAGS,
 545                         RK3399_CLKGATE_CON(13), 6, GFLAGS),
 546
 547         COMPOSITE(SCLK_UPHY1_TCPDCORE, "clk_uphy1_tcpdcore", mux_pll_src_24m_32k_cpll_gpll_p, 0,
 548                         RK3399_CLKSEL_CON(65), 6, 2, MFLAGS, 0, 5, DFLAGS,
 549                         RK3399_CLKGATE_CON(13), 7, GFLAGS),
 550
 551         /* little core */
 552         GATE(0, "clk_core_l_lpll_src", "lpll", CLK_IGNORE_UNUSED,
 553                         RK3399_CLKGATE_CON(0), 0, GFLAGS),
 554         GATE(0, "clk_core_l_bpll_src", "bpll", CLK_IGNORE_UNUSED,
 555                         RK3399_CLKGATE_CON(0), 1, GFLAGS),
 556         GATE(0, "clk_core_l_dpll_src", "dpll", CLK_IGNORE_UNUSED,
 557                         RK3399_CLKGATE_CON(0), 2, GFLAGS),
 558         GATE(0, "clk_core_l_gpll_src", "gpll", CLK_IGNORE_UNUSED,
 559                         RK3399_CLKGATE_CON(0), 3, GFLAGS),
 560
 561         COMPOSITE_NOMUX(0, "aclkm_core_l", "armclkl", CLK_IGNORE_UNUSED,
 562                         RK3399_CLKSEL_CON(0), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
 563                         RK3399_CLKGATE_CON(0), 4, GFLAGS),
 564         COMPOSITE_NOMUX(0, "atclk_core_l", "armclkl", CLK_IGNORE_UNUSED,
 565                         RK3399_CLKSEL_CON(1), 0, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
 566                         RK3399_CLKGATE_CON(0), 5, GFLAGS),
 567         COMPOSITE_NOMUX(0, "pclk_dbg_core_l", "armclkl", CLK_IGNORE_UNUSED,
 568                         RK3399_CLKSEL_CON(1), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
 569                         RK3399_CLKGATE_CON(0), 6, GFLAGS),
 570
 571         GATE(ACLK_CORE_ADB400_CORE_L_2_CCI500, "aclk_core_adb400_core_l_2_cci500", "aclkm_core_l", CLK_IGNORE_UNUSED,
 572                         RK3399_CLKGATE_CON(14), 12, GFLAGS),
 573         GATE(ACLK_PERF_CORE_L, "aclk_perf_core_l", "aclkm_core_l", CLK_IGNORE_UNUSED,
 574                         RK3399_CLKGATE_CON(14), 13, GFLAGS),
 575
 576         GATE(0, "clk_dbg_pd_core_l", "armclkl", CLK_IGNORE_UNUSED,
 577                         RK3399_CLKGATE_CON(14), 9, GFLAGS),
 578         GATE(ACLK_GIC_ADB400_GIC_2_CORE_L, "aclk_core_adb400_gic_2_core_l", "armclkl", CLK_IGNORE_UNUSED,
 579                         RK3399_CLKGATE_CON(14), 10, GFLAGS),
 580         GATE(ACLK_GIC_ADB400_CORE_L_2_GIC, "aclk_core_adb400_core_l_2_gic", "armclkl", CLK_IGNORE_UNUSED,
 581                         RK3399_CLKGATE_CON(14), 11, GFLAGS),
 582         GATE(SCLK_PVTM_CORE_L, "clk_pvtm_core_l", "xin24m", 0,
 583                         RK3399_CLKGATE_CON(0), 7, GFLAGS),
 584
 585         /* big core */
 586         GATE(0, "clk_core_b_lpll_src", "lpll", CLK_IGNORE_UNUSED,
 587                         RK3399_CLKGATE_CON(1), 0, GFLAGS),
 588         GATE(0, "clk_core_b_bpll_src", "bpll", CLK_IGNORE_UNUSED,
 589                         RK3399_CLKGATE_CON(1), 1, GFLAGS),
 590         GATE(0, "clk_core_b_dpll_src", "dpll", CLK_IGNORE_UNUSED,
 591                         RK3399_CLKGATE_CON(1), 2, GFLAGS),
 592         GATE(0, "clk_core_b_gpll_src", "gpll", CLK_IGNORE_UNUSED,
 593                         RK3399_CLKGATE_CON(1), 3, GFLAGS),
 594
 595         COMPOSITE_NOMUX(0, "aclkm_core_b", "armclkb", CLK_IGNORE_UNUSED,
 596                         RK3399_CLKSEL_CON(2), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
 597                         RK3399_CLKGATE_CON(1), 4, GFLAGS),
 598         COMPOSITE_NOMUX(0, "atclk_core_b", "armclkb", CLK_IGNORE_UNUSED,
 599                         RK3399_CLKSEL_CON(3), 0, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
 600                         RK3399_CLKGATE_CON(1), 5, GFLAGS),
 601         COMPOSITE_NOMUX(0, "pclk_dbg_core_b", "armclkb", CLK_IGNORE_UNUSED,
 602                         RK3399_CLKSEL_CON(3), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
 603                         RK3399_CLKGATE_CON(1), 6, GFLAGS),
 604
 605         GATE(ACLK_CORE_ADB400_CORE_B_2_CCI500, "aclk_core_adb400_core_b_2_cci500", "aclkm_core_b", CLK_IGNORE_UNUSED,
 606                         RK3399_CLKGATE_CON(14), 5, GFLAGS),
 607         GATE(ACLK_PERF_CORE_B, "aclk_perf_core_b", "aclkm_core_b", CLK_IGNORE_UNUSED,
 608                         RK3399_CLKGATE_CON(14), 6, GFLAGS),
 609
 610         GATE(0, "clk_dbg_pd_core_b", "armclkb", CLK_IGNORE_UNUSED,
 611                         RK3399_CLKGATE_CON(14), 1, GFLAGS),
 612         GATE(ACLK_GIC_ADB400_GIC_2_CORE_B, "aclk_core_adb400_gic_2_core_b", "armclkb", CLK_IGNORE_UNUSED,
 613                         RK3399_CLKGATE_CON(14), 3, GFLAGS),
 614         GATE(ACLK_GIC_ADB400_CORE_B_2_GIC, "aclk_core_adb400_core_b_2_gic", "armclkb", CLK_IGNORE_UNUSED,
 615                         RK3399_CLKGATE_CON(14), 4, GFLAGS),
 616
 617         DIV(0, "pclken_dbg_core_b", "pclk_dbg_core_b", CLK_IGNORE_UNUSED,
 618                         RK3399_CLKSEL_CON(3), 13, 2, DFLAGS | CLK_DIVIDER_READ_ONLY),
 619
 620         GATE(0, "pclk_dbg_cxcs_pd_core_b", "pclk_dbg_core_b", CLK_IGNORE_UNUSED,
 621                         RK3399_CLKGATE_CON(14), 2, GFLAGS),
 622
 623         GATE(SCLK_PVTM_CORE_B, "clk_pvtm_core_b", "xin24m", 0,
 624                         RK3399_CLKGATE_CON(1), 7, GFLAGS),
 625
 626         /* gmac */
 627         GATE(0, "cpll_aclk_gmac_src", "cpll", CLK_IGNORE_UNUSED,
 628                         RK3399_CLKGATE_CON(6), 9, GFLAGS),
 629         GATE(0, "gpll_aclk_gmac_src", "gpll", CLK_IGNORE_UNUSED,
 630                         RK3399_CLKGATE_CON(6), 8, GFLAGS),
 631         COMPOSITE(0, "aclk_gmac_pre", mux_aclk_gmac_p, 0,
 632                         RK3399_CLKSEL_CON(20), 7, 1, MFLAGS, 0, 5, DFLAGS,
 633                         RK3399_CLKGATE_CON(6), 10, GFLAGS),
 634
 635         GATE(ACLK_GMAC, "aclk_gmac", "aclk_gmac_pre", 0,
 636                         RK3399_CLKGATE_CON(32), 0, GFLAGS),
 637         GATE(ACLK_GMAC_NOC, "aclk_gmac_noc", "aclk_gmac_pre", CLK_IGNORE_UNUSED,
 638                         RK3399_CLKGATE_CON(32), 1, GFLAGS),
 639         GATE(ACLK_PERF_GMAC, "aclk_perf_gmac", "aclk_gmac_pre", 0,
 640                         RK3399_CLKGATE_CON(32), 4, GFLAGS),
 641
 642         COMPOSITE_NOMUX(0, "pclk_gmac_pre", "aclk_gmac_pre", 0,
 643                         RK3399_CLKSEL_CON(19), 8, 3, DFLAGS,
 644                         RK3399_CLKGATE_CON(6), 11, GFLAGS),
 645         GATE(PCLK_GMAC, "pclk_gmac", "pclk_gmac_pre", 0,
 646                         RK3399_CLKGATE_CON(32), 2, GFLAGS),
 647         GATE(PCLK_GMAC_NOC, "pclk_gmac_noc", "pclk_gmac_pre", CLK_IGNORE_UNUSED,
 648                         RK3399_CLKGATE_CON(32), 3, GFLAGS),
 649
 650         COMPOSITE(SCLK_MAC, "clk_gmac", mux_pll_src_cpll_gpll_npll_p, 0,
 651                         RK3399_CLKSEL_CON(20), 14, 2, MFLAGS, 8, 5, DFLAGS,
 652                         RK3399_CLKGATE_CON(5), 5, GFLAGS),
 653
 654         MUX(SCLK_RMII_SRC, "clk_rmii_src", mux_rmii_p, CLK_SET_RATE_PARENT,
 655                         RK3399_CLKSEL_CON(19), 4, 1, MFLAGS),
 656         GATE(SCLK_MACREF_OUT, "clk_mac_refout", "clk_rmii_src", 0,
 657                         RK3399_CLKGATE_CON(5), 6, GFLAGS),
 658         GATE(SCLK_MACREF, "clk_mac_ref", "clk_rmii_src", 0,
 659                         RK3399_CLKGATE_CON(5), 7, GFLAGS),
 660         GATE(SCLK_MAC_RX, "clk_rmii_rx", "clk_rmii_src", 0,
 661                         RK3399_CLKGATE_CON(5), 8, GFLAGS),
 662         GATE(SCLK_MAC_TX, "clk_rmii_tx", "clk_rmii_src", 0,
 663                         RK3399_CLKGATE_CON(5), 9, GFLAGS),
 664
 665         /* spdif */
 666         COMPOSITE(SCLK_SPDIF_DIV, "clk_spdif_div", mux_pll_src_cpll_gpll_p, 0,
 667                         RK3399_CLKSEL_CON(32), 7, 1, MFLAGS, 0, 7, DFLAGS,
 668                         RK3399_CLKGATE_CON(8), 13, GFLAGS),
 669         COMPOSITE_FRACMUX(0, "clk_spdif_frac", "clk_spdif_div", CLK_SET_RATE_PARENT,
 670                         RK3399_CLKSEL_CON(99), 0,
 671                         RK3399_CLKGATE_CON(8), 14, GFLAGS,
 672                         &rk3399_spdif_fracmux),
 673         GATE(SCLK_SPDIF_8CH, "clk_spdif", "clk_spdif_mux", CLK_SET_RATE_PARENT,
 674                         RK3399_CLKGATE_CON(8), 15, GFLAGS),
 675
 676         COMPOSITE(SCLK_SPDIF_REC_DPTX, "clk_spdif_rec_dptx", mux_pll_src_cpll_gpll_p, 0,
 677                         RK3399_CLKSEL_CON(32), 15, 1, MFLAGS, 8, 5, DFLAGS,
 678                         RK3399_CLKGATE_CON(10), 6, GFLAGS),
 679         /* i2s */
 680         COMPOSITE(SCLK_I2S0_DIV, "clk_i2s0_div", mux_pll_src_cpll_gpll_p, 0,
 681                         RK3399_CLKSEL_CON(28), 7, 1, MFLAGS, 0, 7, DFLAGS,
 682                         RK3399_CLKGATE_CON(8), 3, GFLAGS),
 683         COMPOSITE_FRACMUX(0, "clk_i2s0_frac", "clk_i2s0_div", CLK_SET_RATE_PARENT,
 684                         RK3399_CLKSEL_CON(96), 0,
 685                         RK3399_CLKGATE_CON(8), 4, GFLAGS,
 686                         &rk3399_i2s0_fracmux),
 687         GATE(SCLK_I2S0_8CH, "clk_i2s0", "clk_i2s0_mux", CLK_SET_RATE_PARENT,
 688                         RK3399_CLKGATE_CON(8), 5, GFLAGS),
 689
 690         COMPOSITE(SCLK_I2S1_DIV, "clk_i2s1_div", mux_pll_src_cpll_gpll_p, 0,
 691                         RK3399_CLKSEL_CON(29), 7, 1, MFLAGS, 0, 7, DFLAGS,
 692                         RK3399_CLKGATE_CON(8), 6, GFLAGS),
 693         COMPOSITE_FRACMUX(0, "clk_i2s1_frac", "clk_i2s1_div", CLK_SET_RATE_PARENT,
 694                         RK3399_CLKSEL_CON(97), 0,
 695                         RK3399_CLKGATE_CON(8), 7, GFLAGS,
 696                         &rk3399_i2s1_fracmux),
 697         GATE(SCLK_I2S1_8CH, "clk_i2s1", "clk_i2s1_mux", CLK_SET_RATE_PARENT,
 698                         RK3399_CLKGATE_CON(8), 8, GFLAGS),
 699
 700         COMPOSITE(SCLK_I2S2_DIV, "clk_i2s2_div", mux_pll_src_cpll_gpll_p, 0,
 701                         RK3399_CLKSEL_CON(30), 7, 1, MFLAGS, 0, 7, DFLAGS,
 702                         RK3399_CLKGATE_CON(8), 9, GFLAGS),
 703         COMPOSITE_FRACMUX(0, "clk_i2s2_frac", "clk_i2s2_div", CLK_SET_RATE_PARENT,
 704                         RK3399_CLKSEL_CON(98), 0,
 705                         RK3399_CLKGATE_CON(8), 10, GFLAGS,
 706                         &rk3399_i2s2_fracmux),
 707         GATE(SCLK_I2S2_8CH, "clk_i2s2", "clk_i2s2_mux", CLK_SET_RATE_PARENT,
 708                         RK3399_CLKGATE_CON(8), 11, GFLAGS),
 709
 710         MUX(0, "clk_i2sout_src", mux_i2sch_p, CLK_SET_RATE_PARENT,
 711                         RK3399_CLKSEL_CON(31), 0, 2, MFLAGS),
 712         COMPOSITE_NODIV(SCLK_I2S_8CH_OUT, "clk_i2sout", mux_i2sout_p, CLK_SET_RATE_PARENT,
 713                         RK3399_CLKSEL_CON(30), 8, 2, MFLAGS,
 714                         RK3399_CLKGATE_CON(8), 12, GFLAGS),
 715
 716         /* uart */
 717         MUX(SCLK_UART0_SRC, "clk_uart0_src", mux_pll_src_cpll_gpll_upll_p, 0,
 718                         RK3399_CLKSEL_CON(33), 12, 2, MFLAGS),
 719         COMPOSITE_NOMUX(0, "clk_uart0_div", "clk_uart0_src", 0,
 720                         RK3399_CLKSEL_CON(33), 0, 7, DFLAGS,
 721                         RK3399_CLKGATE_CON(9), 0, GFLAGS),
 722         COMPOSITE_FRACMUX(0, "clk_uart0_frac", "clk_uart0_div", CLK_SET_RATE_PARENT,
 723                         RK3399_CLKSEL_CON(100), 0,
 724                         RK3399_CLKGATE_CON(9), 1, GFLAGS,
 725                         &rk3399_uart0_fracmux),
 726
 727         MUX(SCLK_UART_SRC, "clk_uart_src", mux_pll_src_cpll_gpll_p, 0,
 728                         RK3399_CLKSEL_CON(33), 15, 1, MFLAGS),
 729         COMPOSITE_NOMUX(0, "clk_uart1_div", "clk_uart_src", 0,
 730                         RK3399_CLKSEL_CON(34), 0, 7, DFLAGS,
 731                         RK3399_CLKGATE_CON(9), 2, GFLAGS),
 732         COMPOSITE_FRACMUX(0, "clk_uart1_frac", "clk_uart1_div", CLK_SET_RATE_PARENT,
 733                         RK3399_CLKSEL_CON(101), 0,
 734                         RK3399_CLKGATE_CON(9), 3, GFLAGS,
 735                         &rk3399_uart1_fracmux),
 736
 737         COMPOSITE_NOMUX(0, "clk_uart2_div", "clk_uart_src", 0,
 738                         RK3399_CLKSEL_CON(35), 0, 7, DFLAGS,
 739                         RK3399_CLKGATE_CON(9), 4, GFLAGS),
 740         COMPOSITE_FRACMUX(0, "clk_uart2_frac", "clk_uart2_div", CLK_SET_RATE_PARENT,
 741                         RK3399_CLKSEL_CON(102), 0,
 742                         RK3399_CLKGATE_CON(9), 5, GFLAGS,
 743                         &rk3399_uart2_fracmux),
 744
 745         COMPOSITE_NOMUX(0, "clk_uart3_div", "clk_uart_src", 0,
 746                         RK3399_CLKSEL_CON(36), 0, 7, DFLAGS,
 747                         RK3399_CLKGATE_CON(9), 6, GFLAGS),
 748         COMPOSITE_FRACMUX(0, "clk_uart3_frac", "clk_uart3_div", CLK_SET_RATE_PARENT,
 749                         RK3399_CLKSEL_CON(103), 0,
 750                         RK3399_CLKGATE_CON(9), 7, GFLAGS,
 751                         &rk3399_uart3_fracmux),
 752
 753         COMPOSITE(PCLK_DDR, "pclk_ddr", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED,
 754                         RK3399_CLKSEL_CON(6), 15, 1, MFLAGS, 8, 5, DFLAGS,
 755                         RK3399_CLKGATE_CON(3), 4, GFLAGS),
 756
 757         GATE(PCLK_CENTER_MAIN_NOC, "pclk_center_main_noc", "pclk_ddr", CLK_IGNORE_UNUSED,
 758                         RK3399_CLKGATE_CON(18), 10, GFLAGS),
 759         GATE(PCLK_DDR_MON, "pclk_ddr_mon", "pclk_ddr", 0,
 760                         RK3399_CLKGATE_CON(18), 12, GFLAGS),
 761         GATE(PCLK_CIC, "pclk_cic", "pclk_ddr", CLK_IGNORE_UNUSED,
 762                         RK3399_CLKGATE_CON(18), 15, GFLAGS),
 763         GATE(PCLK_DDR_SGRF, "pclk_ddr_sgrf", "pclk_ddr", CLK_IGNORE_UNUSED,
 764                         RK3399_CLKGATE_CON(19), 2, GFLAGS),
 765
 766         GATE(SCLK_PVTM_DDR, "clk_pvtm_ddr", "xin24m", 0,
 767                         RK3399_CLKGATE_CON(4), 11, GFLAGS),
 768         GATE(SCLK_DFIMON0_TIMER, "clk_dfimon0_timer", "xin24m", 0,
 769                         RK3399_CLKGATE_CON(3), 5, GFLAGS),
 770         GATE(SCLK_DFIMON1_TIMER, "clk_dfimon1_timer", "xin24m", 0,
 771                         RK3399_CLKGATE_CON(3), 6, GFLAGS),
 772
 773         /* cci */
 774         GATE(0, "cpll_aclk_cci_src", "cpll", CLK_IGNORE_UNUSED,
 775                         RK3399_CLKGATE_CON(2), 0, GFLAGS),
 776         GATE(0, "gpll_aclk_cci_src", "gpll", CLK_IGNORE_UNUSED,
 777                         RK3399_CLKGATE_CON(2), 1, GFLAGS),
 778         GATE(0, "npll_aclk_cci_src", "npll", CLK_IGNORE_UNUSED,
 779                         RK3399_CLKGATE_CON(2), 2, GFLAGS),
 780         GATE(0, "vpll_aclk_cci_src", "vpll", CLK_IGNORE_UNUSED,
 781                         RK3399_CLKGATE_CON(2), 3, GFLAGS),
 782
 783         COMPOSITE(0, "aclk_cci_pre", mux_aclk_cci_p, CLK_IGNORE_UNUSED,
 784                         RK3399_CLKSEL_CON(5), 6, 2, MFLAGS, 0, 5, DFLAGS,
 785                         RK3399_CLKGATE_CON(2), 4, GFLAGS),
 786
 787         GATE(ACLK_ADB400M_PD_CORE_L, "aclk_adb400m_pd_core_l", "aclk_cci_pre", CLK_IGNORE_UNUSED,
 788                         RK3399_CLKGATE_CON(15), 0, GFLAGS),
 789         GATE(ACLK_ADB400M_PD_CORE_B, "aclk_adb400m_pd_core_b", "aclk_cci_pre", CLK_IGNORE_UNUSED,
 790                         RK3399_CLKGATE_CON(15), 1, GFLAGS),
 791         GATE(ACLK_CCI, "aclk_cci", "aclk_cci_pre", CLK_IGNORE_UNUSED,
 792                         RK3399_CLKGATE_CON(15), 2, GFLAGS),
 793         GATE(ACLK_CCI_NOC0, "aclk_cci_noc0", "aclk_cci_pre", CLK_IGNORE_UNUSED,
 794                         RK3399_CLKGATE_CON(15), 3, GFLAGS),
 795         GATE(ACLK_CCI_NOC1, "aclk_cci_noc1", "aclk_cci_pre", CLK_IGNORE_UNUSED,
 796                         RK3399_CLKGATE_CON(15), 4, GFLAGS),
 797         GATE(ACLK_CCI_GRF, "aclk_cci_grf", "aclk_cci_pre", CLK_IGNORE_UNUSED,
 798                         RK3399_CLKGATE_CON(15), 7, GFLAGS),
 799
 800         GATE(0, "cpll_cci_trace", "cpll", CLK_IGNORE_UNUSED,
 801                         RK3399_CLKGATE_CON(2), 5, GFLAGS),
 802         GATE(0, "gpll_cci_trace", "gpll", CLK_IGNORE_UNUSED,
 803                         RK3399_CLKGATE_CON(2), 6, GFLAGS),
 804         COMPOSITE(SCLK_CCI_TRACE, "clk_cci_trace", mux_cci_trace_p, CLK_IGNORE_UNUSED,
 805                         RK3399_CLKSEL_CON(5), 15, 2, MFLAGS, 8, 5, DFLAGS,
 806                         RK3399_CLKGATE_CON(2), 7, GFLAGS),
 807
 808         GATE(0, "cpll_cs", "cpll", CLK_IGNORE_UNUSED,
 809                         RK3399_CLKGATE_CON(2), 8, GFLAGS),
 810         GATE(0, "gpll_cs", "gpll", CLK_IGNORE_UNUSED,
 811                         RK3399_CLKGATE_CON(2), 9, GFLAGS),
 812         GATE(0, "npll_cs", "npll", CLK_IGNORE_UNUSED,
 813                         RK3399_CLKGATE_CON(2), 10, GFLAGS),
 814         COMPOSITE_NOGATE(SCLK_CS, "clk_cs", mux_cs_p, CLK_IGNORE_UNUSED,
 815                         RK3399_CLKSEL_CON(4), 6, 2, MFLAGS, 0, 5, DFLAGS),
 816         GATE(0, "clk_dbg_cxcs", "clk_cs", CLK_IGNORE_UNUSED,
 817                         RK3399_CLKGATE_CON(15), 5, GFLAGS),
 818         GATE(0, "clk_dbg_noc", "clk_cs", CLK_IGNORE_UNUSED,
 819                         RK3399_CLKGATE_CON(15), 6, GFLAGS),
 820
 821         /* vcodec */
 822         COMPOSITE(0, "aclk_vcodec_pre", mux_pll_src_cpll_gpll_npll_ppll_p, 0,
 823                         RK3399_CLKSEL_CON(7), 6, 2, MFLAGS, 0, 5, DFLAGS,
 824                         RK3399_CLKGATE_CON(4), 0, GFLAGS),
 825         COMPOSITE_NOMUX(0, "hclk_vcodec_pre", "aclk_vcodec_pre", 0,
 826                         RK3399_CLKSEL_CON(7), 8, 5, DFLAGS,
 827                         RK3399_CLKGATE_CON(4), 1, GFLAGS),
 828         GATE(HCLK_VCODEC, "hclk_vcodec", "hclk_vcodec_pre", 0,
 829                         RK3399_CLKGATE_CON(17), 2, GFLAGS),
 830         GATE(0, "hclk_vcodec_noc", "hclk_vcodec_pre", CLK_IGNORE_UNUSED,
 831                         RK3399_CLKGATE_CON(17), 3, GFLAGS),
 832
 833         GATE(ACLK_VCODEC, "aclk_vcodec", "aclk_vcodec_pre", 0,
 834                         RK3399_CLKGATE_CON(17), 0, GFLAGS),
 835         GATE(0, "aclk_vcodec_noc", "aclk_vcodec_pre", CLK_IGNORE_UNUSED,
 836                         RK3399_CLKGATE_CON(17), 1, GFLAGS),
 837
 838         /* vdu */
 839         COMPOSITE(SCLK_VDU_CORE, "clk_vdu_core", mux_pll_src_cpll_gpll_npll_p, 0,
 840                         RK3399_CLKSEL_CON(9), 6, 2, MFLAGS, 0, 5, DFLAGS,
 841                         RK3399_CLKGATE_CON(4), 4, GFLAGS),
 842         COMPOSITE(SCLK_VDU_CA, "clk_vdu_ca", mux_pll_src_cpll_gpll_npll_p, 0,
 843                         RK3399_CLKSEL_CON(9), 14, 2, MFLAGS, 8, 5, DFLAGS,
 844                         RK3399_CLKGATE_CON(4), 5, GFLAGS),
 845
 846         COMPOSITE(0, "aclk_vdu_pre", mux_pll_src_cpll_gpll_npll_ppll_p, 0,
 847                         RK3399_CLKSEL_CON(8), 6, 2, MFLAGS, 0, 5, DFLAGS,
 848                         RK3399_CLKGATE_CON(4), 2, GFLAGS),
 849         COMPOSITE_NOMUX(0, "hclk_vdu_pre", "aclk_vdu_pre", 0,
 850                         RK3399_CLKSEL_CON(8), 8, 5, DFLAGS,
 851                         RK3399_CLKGATE_CON(4), 3, GFLAGS),
 852         GATE(HCLK_VDU, "hclk_vdu", "hclk_vdu_pre", 0,
 853                         RK3399_CLKGATE_CON(17), 10, GFLAGS),
 854         GATE(HCLK_VDU_NOC, "hclk_vdu_noc", "hclk_vdu_pre", CLK_IGNORE_UNUSED,
 855                         RK3399_CLKGATE_CON(17), 11, GFLAGS),
 856
 857         GATE(ACLK_VDU, "aclk_vdu", "aclk_vdu_pre", 0,
 858                         RK3399_CLKGATE_CON(17), 8, GFLAGS),
 859         GATE(ACLK_VDU_NOC, "aclk_vdu_noc", "aclk_vdu_pre", CLK_IGNORE_UNUSED,
 860                         RK3399_CLKGATE_CON(17), 9, GFLAGS),
 861
 862         /* iep */
 863         COMPOSITE(0, "aclk_iep_pre", mux_pll_src_cpll_gpll_npll_ppll_p, 0,
 864                         RK3399_CLKSEL_CON(10), 6, 2, MFLAGS, 0, 5, DFLAGS,
 865                         RK3399_CLKGATE_CON(4), 6, GFLAGS),
 866         COMPOSITE_NOMUX(0, "hclk_iep_pre", "aclk_iep_pre", 0,
 867                         RK3399_CLKSEL_CON(10), 8, 5, DFLAGS,
 868                         RK3399_CLKGATE_CON(4), 7, GFLAGS),
 869         GATE(HCLK_IEP, "hclk_iep", "hclk_iep_pre", 0,
 870                         RK3399_CLKGATE_CON(16), 2, GFLAGS),
 871         GATE(HCLK_IEP_NOC, "hclk_iep_noc", "hclk_iep_pre", CLK_IGNORE_UNUSED,
 872                         RK3399_CLKGATE_CON(16), 3, GFLAGS),
 873
 874         GATE(ACLK_IEP, "aclk_iep", "aclk_iep_pre", 0,
 875                         RK3399_CLKGATE_CON(16), 0, GFLAGS),
 876         GATE(ACLK_IEP_NOC, "aclk_iep_noc", "aclk_iep_pre", CLK_IGNORE_UNUSED,
 877                         RK3399_CLKGATE_CON(16), 1, GFLAGS),
 878
 879         /* rga */
 880         COMPOSITE(SCLK_RGA_CORE, "clk_rga_core", mux_pll_src_cpll_gpll_npll_ppll_p, 0,
 881                         RK3399_CLKSEL_CON(12), 6, 2, MFLAGS, 0, 5, DFLAGS,
 882                         RK3399_CLKGATE_CON(4), 10, GFLAGS),
 883
 884         COMPOSITE(0, "aclk_rga_pre", mux_pll_src_cpll_gpll_npll_ppll_p, 0,
 885                         RK3399_CLKSEL_CON(11), 6, 2, MFLAGS, 0, 5, DFLAGS,
 886                         RK3399_CLKGATE_CON(4), 8, GFLAGS),
 887         COMPOSITE_NOMUX(0, "hclk_rga_pre", "aclk_rga_pre", 0,
 888                         RK3399_CLKSEL_CON(11), 8, 5, DFLAGS,
 889                         RK3399_CLKGATE_CON(4), 9, GFLAGS),
 890         GATE(HCLK_RGA, "hclk_rga", "hclk_rga_pre", 0,
 891                         RK3399_CLKGATE_CON(16), 10, GFLAGS),
 892         GATE(HCLK_RGA_NOC, "hclk_rga_noc", "hclk_rga_pre", CLK_IGNORE_UNUSED,
 893                         RK3399_CLKGATE_CON(16), 11, GFLAGS),
 894
 895         GATE(ACLK_RGA, "aclk_rga", "aclk_rga_pre", 0,
 896                         RK3399_CLKGATE_CON(16), 8, GFLAGS),
 897         GATE(ACLK_RGA_NOC, "aclk_rga_noc", "aclk_rga_pre", CLK_IGNORE_UNUSED,
 898                         RK3399_CLKGATE_CON(16), 9, GFLAGS),
 899
 900         /* center */
 901         COMPOSITE(ACLK_CENTER, "aclk_center", mux_pll_src_cpll_gpll_npll_p, CLK_IGNORE_UNUSED,
 902                         RK3399_CLKSEL_CON(12), 14, 2, MFLAGS, 8, 5, DFLAGS,
 903                         RK3399_CLKGATE_CON(3), 7, GFLAGS),
 904         GATE(ACLK_CENTER_MAIN_NOC, "aclk_center_main_noc", "aclk_center", CLK_IGNORE_UNUSED,
 905                         RK3399_CLKGATE_CON(19), 0, GFLAGS),
 906         GATE(ACLK_CENTER_PERI_NOC, "aclk_center_peri_noc", "aclk_center", CLK_IGNORE_UNUSED,
 907                         RK3399_CLKGATE_CON(19), 1, GFLAGS),
 908
 909         /* gpu */
 910         COMPOSITE(0, "aclk_gpu_pre", mux_pll_src_ppll_cpll_gpll_npll_p, CLK_IGNORE_UNUSED,
 911                         RK3399_CLKSEL_CON(13), 5, 3, MFLAGS, 0, 5, DFLAGS,
 912                         RK3399_CLKGATE_CON(13), 0, GFLAGS),
 913         GATE(ACLK_GPU, "aclk_gpu", "aclk_gpu_pre", 0,
 914                         RK3399_CLKGATE_CON(30), 8, GFLAGS),
 915         GATE(ACLK_PERF_GPU, "aclk_perf_gpu", "aclk_gpu_pre", 0,
 916                         RK3399_CLKGATE_CON(30), 10, GFLAGS),
 917         GATE(ACLK_GPU_GRF, "aclk_gpu_grf", "aclk_gpu_pre", 0,
 918                         RK3399_CLKGATE_CON(30), 11, GFLAGS),
 919         GATE(SCLK_PVTM_GPU, "aclk_pvtm_gpu", "xin24m", 0,
 920                         RK3399_CLKGATE_CON(13), 1, GFLAGS),
 921
 922         /* perihp */
 923         GATE(0, "cpll_aclk_perihp_src", "cpll", CLK_IGNORE_UNUSED,
 924                         RK3399_CLKGATE_CON(5), 1, GFLAGS),
 925         GATE(0, "gpll_aclk_perihp_src", "gpll", CLK_IGNORE_UNUSED,
 926                         RK3399_CLKGATE_CON(5), 0, GFLAGS),
 927         COMPOSITE(ACLK_PERIHP, "aclk_perihp", mux_aclk_perihp_p, CLK_IGNORE_UNUSED,
 928                         RK3399_CLKSEL_CON(14), 7, 1, MFLAGS, 0, 5, DFLAGS,
 929                         RK3399_CLKGATE_CON(5), 2, GFLAGS),
 930         COMPOSITE_NOMUX(HCLK_PERIHP, "hclk_perihp", "aclk_perihp", CLK_IGNORE_UNUSED,
 931                         RK3399_CLKSEL_CON(14), 8, 2, DFLAGS,
 932                         RK3399_CLKGATE_CON(5), 3, GFLAGS),
 933         COMPOSITE_NOMUX(PCLK_PERIHP, "pclk_perihp", "aclk_perihp", CLK_IGNORE_UNUSED,
 934                         RK3399_CLKSEL_CON(14), 12, 2, DFLAGS,
 935                         RK3399_CLKGATE_CON(5), 4, GFLAGS),
 936
 937         GATE(ACLK_PERF_PCIE, "aclk_perf_pcie", "aclk_perihp", 0,
 938                         RK3399_CLKGATE_CON(20), 2, GFLAGS),
 939         GATE(ACLK_PCIE, "aclk_pcie", "aclk_perihp", 0,
 940                         RK3399_CLKGATE_CON(20), 10, GFLAGS),
 941         GATE(0, "aclk_perihp_noc", "aclk_perihp", CLK_IGNORE_UNUSED,
 942                         RK3399_CLKGATE_CON(20), 12, GFLAGS),
 943
 944         GATE(HCLK_HOST0, "hclk_host0", "hclk_perihp", 0,
 945                         RK3399_CLKGATE_CON(20), 5, GFLAGS),
 946         GATE(HCLK_HOST0_ARB, "hclk_host0_arb", "hclk_perihp", 0,
 947                         RK3399_CLKGATE_CON(20), 6, GFLAGS),
 948         GATE(HCLK_HOST1, "hclk_host1", "hclk_perihp", 0,
 949                         RK3399_CLKGATE_CON(20), 7, GFLAGS),
 950         GATE(HCLK_HOST1_ARB, "hclk_host1_arb", "hclk_perihp", 0,
 951                         RK3399_CLKGATE_CON(20), 8, GFLAGS),
 952         GATE(HCLK_HSIC, "hclk_hsic", "hclk_perihp", 0,
 953                         RK3399_CLKGATE_CON(20), 9, GFLAGS),
 954         GATE(0, "hclk_perihp_noc", "hclk_perihp", CLK_IGNORE_UNUSED,
 955                         RK3399_CLKGATE_CON(20), 13, GFLAGS),
 956         GATE(0, "hclk_ahb1tom", "hclk_perihp", CLK_IGNORE_UNUSED,
 957                         RK3399_CLKGATE_CON(20), 15, GFLAGS),
 958
 959         GATE(PCLK_PERIHP_GRF, "pclk_perihp_grf", "pclk_perihp", CLK_IGNORE_UNUSED,
 960                         RK3399_CLKGATE_CON(20), 4, GFLAGS),
 961         GATE(PCLK_PCIE, "pclk_pcie", "pclk_perihp", 0,
 962                         RK3399_CLKGATE_CON(20), 11, GFLAGS),
 963         GATE(0, "pclk_perihp_noc", "pclk_perihp", CLK_IGNORE_UNUSED,
 964                         RK3399_CLKGATE_CON(20), 14, GFLAGS),
 965         GATE(PCLK_HSICPHY, "pclk_hsicphy", "pclk_perihp", 0,
 966                         RK3399_CLKGATE_CON(31), 8, GFLAGS),
 967
 968         /* sdio & sdmmc */
 969         COMPOSITE(HCLK_SD, "hclk_sd", mux_pll_src_cpll_gpll_p, 0,
 970                         RK3399_CLKSEL_CON(13), 15, 1, MFLAGS, 8, 5, DFLAGS,
 971                         RK3399_CLKGATE_CON(12), 13, GFLAGS),
 972         GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_sd", 0,
 973                         RK3399_CLKGATE_CON(33), 8, GFLAGS),
 974         GATE(0, "hclk_sdmmc_noc", "hclk_sd", CLK_IGNORE_UNUSED,
 975                         RK3399_CLKGATE_CON(33), 9, GFLAGS),
 976
 977         COMPOSITE(SCLK_SDIO, "clk_sdio", mux_pll_src_cpll_gpll_npll_ppll_upll_24m_p, 0,
 978                         RK3399_CLKSEL_CON(15), 8, 3, MFLAGS, 0, 7, DFLAGS,
 979                         RK3399_CLKGATE_CON(6), 0, GFLAGS),
 980
 981         COMPOSITE(SCLK_SDMMC, "clk_sdmmc", mux_pll_src_cpll_gpll_npll_ppll_upll_24m_p, 0,
 982                         RK3399_CLKSEL_CON(16), 8, 3, MFLAGS, 0, 7, DFLAGS,
 983                         RK3399_CLKGATE_CON(6), 1, GFLAGS),
 984
 985         MMC(SCLK_SDMMC_DRV,     "sdmmc_drv",    "clk_sdmmc", RK3399_SDMMC_CON0, 1),
 986         MMC(SCLK_SDMMC_SAMPLE,  "sdmmc_sample", "clk_sdmmc", RK3399_SDMMC_CON1, 1),
 987
 988         MMC(SCLK_SDIO_DRV,      "sdio_drv",    "clk_sdio",  RK3399_SDIO_CON0,  1),
 989         MMC(SCLK_SDIO_SAMPLE,   "sdio_sample", "clk_sdio",  RK3399_SDIO_CON1,  1),
 990
 991         /* pcie */
 992         COMPOSITE(SCLK_PCIE_PM, "clk_pcie_pm", mux_pll_src_cpll_gpll_npll_24m_p, 0,
 993                         RK3399_CLKSEL_CON(17), 8, 3, MFLAGS, 0, 7, DFLAGS,
 994                         RK3399_CLKGATE_CON(6), 2, GFLAGS),
 995
 996         COMPOSITE_NOMUX(SCLK_PCIEPHY_REF100M, "clk_pciephy_ref100m", "npll", 0,
 997                         RK3399_CLKSEL_CON(18), 11, 5, DFLAGS,
 998                         RK3399_CLKGATE_CON(12), 6, GFLAGS),
 999         MUX(SCLK_PCIEPHY_REF, "clk_pciephy_ref", mux_pll_src_24m_pciephy_p, CLK_SET_RATE_PARENT,
1000                         RK3399_CLKSEL_CON(18), 10, 1, MFLAGS),
1001
1002         COMPOSITE(0, "clk_pcie_core_cru", mux_pll_src_cpll_gpll_npll_p, 0,
1003                         RK3399_CLKSEL_CON(18), 8, 2, MFLAGS, 0, 7, DFLAGS,
1004                         RK3399_CLKGATE_CON(6), 3, GFLAGS),
1005         MUX(SCLK_PCIE_CORE, "clk_pcie_core", mux_pciecore_cru_phy_p, CLK_SET_RATE_PARENT,
1006                         RK3399_CLKSEL_CON(18), 7, 1, MFLAGS),
1007
1008         /* emmc */
1009         COMPOSITE(SCLK_EMMC, "clk_emmc", mux_pll_src_cpll_gpll_npll_upll_24m_p, 0,
1010                         RK3399_CLKSEL_CON(22), 8, 3, MFLAGS, 0, 7, DFLAGS,
1011                         RK3399_CLKGATE_CON(6), 14, GFLAGS),
1012
1013         GATE(0, "cpll_aclk_emmc_src", "cpll", CLK_IGNORE_UNUSED,
1014                         RK3399_CLKGATE_CON(6), 13, GFLAGS),
1015         GATE(0, "gpll_aclk_emmc_src", "gpll", CLK_IGNORE_UNUSED,
1016                         RK3399_CLKGATE_CON(6), 12, GFLAGS),
1017         COMPOSITE_NOGATE(ACLK_EMMC, "aclk_emmc", mux_aclk_emmc_p, CLK_IGNORE_UNUSED,
1018                         RK3399_CLKSEL_CON(21), 7, 1, MFLAGS, 0, 5, DFLAGS),
1019         GATE(ACLK_EMMC_CORE, "aclk_emmccore", "aclk_emmc", CLK_IGNORE_UNUSED,
1020                         RK3399_CLKGATE_CON(32), 8, GFLAGS),
1021         GATE(ACLK_EMMC_NOC, "aclk_emmc_noc", "aclk_emmc", CLK_IGNORE_UNUSED,
1022                         RK3399_CLKGATE_CON(32), 9, GFLAGS),
1023         GATE(ACLK_EMMC_GRF, "aclk_emmcgrf", "aclk_emmc", CLK_IGNORE_UNUSED,
1024                         RK3399_CLKGATE_CON(32), 10, GFLAGS),
1025
1026         /* perilp0 */
1027         GATE(0, "cpll_aclk_perilp0_src", "cpll", CLK_IGNORE_UNUSED,
1028                         RK3399_CLKGATE_CON(7), 1, GFLAGS),
1029         GATE(0, "gpll_aclk_perilp0_src", "gpll", CLK_IGNORE_UNUSED,
1030                         RK3399_CLKGATE_CON(7), 0, GFLAGS),
1031         COMPOSITE(ACLK_PERILP0, "aclk_perilp0", mux_aclk_perilp0_p, CLK_IGNORE_UNUSED,
1032                         RK3399_CLKSEL_CON(23), 7, 1, MFLAGS, 0, 5, DFLAGS,
1033                         RK3399_CLKGATE_CON(7), 2, GFLAGS),
1034         COMPOSITE_NOMUX(HCLK_PERILP0, "hclk_perilp0", "aclk_perilp0", CLK_IGNORE_UNUSED,
1035                         RK3399_CLKSEL_CON(23), 8, 2, DFLAGS,
1036                         RK3399_CLKGATE_CON(7), 3, GFLAGS),
1037         COMPOSITE_NOMUX(PCLK_PERILP0, "pclk_perilp0", "aclk_perilp0", 0,
1038                         RK3399_CLKSEL_CON(23), 12, 3, DFLAGS,
1039                         RK3399_CLKGATE_CON(7), 4, GFLAGS),
1040
1041         /* aclk_perilp0 gates */
1042         GATE(ACLK_INTMEM, "aclk_intmem", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 0, GFLAGS),
1043         GATE(ACLK_TZMA, "aclk_tzma", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 1, GFLAGS),
1044         GATE(SCLK_INTMEM0, "clk_intmem0", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 2, GFLAGS),
1045         GATE(SCLK_INTMEM1, "clk_intmem1", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 3, GFLAGS),
1046         GATE(SCLK_INTMEM2, "clk_intmem2", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 4, GFLAGS),
1047         GATE(SCLK_INTMEM3, "clk_intmem3", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 5, GFLAGS),
1048         GATE(SCLK_INTMEM4, "clk_intmem4", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 6, GFLAGS),
1049         GATE(SCLK_INTMEM5, "clk_intmem5", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 7, GFLAGS),
1050         GATE(ACLK_DCF, "aclk_dcf", "aclk_perilp0", 0, RK3399_CLKGATE_CON(23), 8, GFLAGS),
1051         GATE(ACLK_DMAC0_PERILP, "aclk_dmac0_perilp", "aclk_perilp0", 0, RK3399_CLKGATE_CON(25), 5, GFLAGS),
1052         GATE(ACLK_DMAC1_PERILP, "aclk_dmac1_perilp", "aclk_perilp0", 0, RK3399_CLKGATE_CON(25), 6, GFLAGS),
1053         GATE(ACLK_PERILP0_NOC, "aclk_perilp0_noc", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(25), 7, GFLAGS),
1054
1055         /* hclk_perilp0 gates */
1056         GATE(HCLK_ROM, "hclk_rom", "hclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(24), 4, GFLAGS),
1057         GATE(HCLK_M_CRYPTO0, "hclk_m_crypto0", "hclk_perilp0", 0, RK3399_CLKGATE_CON(24), 5, GFLAGS),
1058         GATE(HCLK_S_CRYPTO0, "hclk_s_crypto0", "hclk_perilp0", 0, RK3399_CLKGATE_CON(24), 6, GFLAGS),
1059         GATE(HCLK_M_CRYPTO1, "hclk_m_crypto1", "hclk_perilp0", 0, RK3399_CLKGATE_CON(24), 14, GFLAGS),
1060         GATE(HCLK_S_CRYPTO1, "hclk_s_crypto1", "hclk_perilp0", 0, RK3399_CLKGATE_CON(24), 15, GFLAGS),
1061         GATE(HCLK_PERILP0_NOC, "hclk_perilp0_noc", "hclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(25), 8, GFLAGS),
1062
1063         /* pclk_perilp0 gates */
1064         GATE(PCLK_DCF, "pclk_dcf", "pclk_perilp0", 0, RK3399_CLKGATE_CON(23), 9, GFLAGS),
1065
1066         /* crypto */
1067         COMPOSITE(SCLK_CRYPTO0, "clk_crypto0", mux_pll_src_cpll_gpll_ppll_p, 0,
1068                         RK3399_CLKSEL_CON(24), 6, 2, MFLAGS, 0, 5, DFLAGS,
1069                         RK3399_CLKGATE_CON(7), 7, GFLAGS),
1070
1071         COMPOSITE(SCLK_CRYPTO1, "clk_crypto1", mux_pll_src_cpll_gpll_ppll_p, 0,
1072                         RK3399_CLKSEL_CON(26), 6, 2, MFLAGS, 0, 5, DFLAGS,
1073                         RK3399_CLKGATE_CON(7), 8, GFLAGS),
1074
1075         /* cm0s_perilp */
1076         GATE(0, "cpll_fclk_cm0s_src", "cpll", 0,
1077                         RK3399_CLKGATE_CON(7), 6, GFLAGS),
1078         GATE(0, "gpll_fclk_cm0s_src", "gpll", 0,
1079                         RK3399_CLKGATE_CON(7), 5, GFLAGS),
1080         COMPOSITE(FCLK_CM0S, "fclk_cm0s", mux_fclk_cm0s_p, 0,
1081                         RK3399_CLKSEL_CON(24), 15, 1, MFLAGS, 8, 5, DFLAGS,
1082                         RK3399_CLKGATE_CON(7), 9, GFLAGS),
1083
1084         /* fclk_cm0s gates */
1085         GATE(SCLK_M0_PERILP, "sclk_m0_perilp", "fclk_cm0s", 0, RK3399_CLKGATE_CON(24), 8, GFLAGS),
1086         GATE(HCLK_M0_PERILP, "hclk_m0_perilp", "fclk_cm0s", 0, RK3399_CLKGATE_CON(24), 9, GFLAGS),
1087         GATE(DCLK_M0_PERILP, "dclk_m0_perilp", "fclk_cm0s", 0, RK3399_CLKGATE_CON(24), 10, GFLAGS),
1088         GATE(SCLK_M0_PERILP_DEC, "clk_m0_perilp_dec", "fclk_cm0s", 0, RK3399_CLKGATE_CON(24), 11, GFLAGS),
1089         GATE(HCLK_M0_PERILP_NOC, "hclk_m0_perilp_noc", "fclk_cm0s", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(25), 11, GFLAGS),
1090
1091         /* perilp1 */
1092         GATE(0, "cpll_hclk_perilp1_src", "cpll", CLK_IGNORE_UNUSED,
1093                         RK3399_CLKGATE_CON(8), 1, GFLAGS),
1094         GATE(0, "gpll_hclk_perilp1_src", "gpll", CLK_IGNORE_UNUSED,
1095                         RK3399_CLKGATE_CON(8), 0, GFLAGS),
1096         COMPOSITE_NOGATE(HCLK_PERILP1, "hclk_perilp1", mux_hclk_perilp1_p, CLK_IGNORE_UNUSED,
1097                         RK3399_CLKSEL_CON(25), 7, 1, MFLAGS, 0, 5, DFLAGS),
1098         COMPOSITE_NOMUX(PCLK_PERILP1, "pclk_perilp1", "hclk_perilp1", CLK_IGNORE_UNUSED,
1099                         RK3399_CLKSEL_CON(25), 8, 3, DFLAGS,
1100                         RK3399_CLKGATE_CON(8), 2, GFLAGS),
1101
1102         /* hclk_perilp1 gates */
1103         GATE(0, "hclk_perilp1_noc", "hclk_perilp1", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(25), 9, GFLAGS),
1104         GATE(0, "hclk_sdio_noc", "hclk_perilp1", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(25), 12, GFLAGS),
1105         GATE(HCLK_I2S0_8CH, "hclk_i2s0", "hclk_perilp1", 0, RK3399_CLKGATE_CON(34), 0, GFLAGS),
1106         GATE(HCLK_I2S1_8CH, "hclk_i2s1", "hclk_perilp1", 0, RK3399_CLKGATE_CON(34), 1, GFLAGS),
1107         GATE(HCLK_I2S2_8CH, "hclk_i2s2", "hclk_perilp1", 0, RK3399_CLKGATE_CON(34), 2, GFLAGS),
1108         GATE(HCLK_SPDIF, "hclk_spdif", "hclk_perilp1", 0, RK3399_CLKGATE_CON(34), 3, GFLAGS),
1109         GATE(HCLK_SDIO, "hclk_sdio", "hclk_perilp1", 0, RK3399_CLKGATE_CON(34), 4, GFLAGS),
1110         GATE(PCLK_SPI5, "pclk_spi5", "hclk_perilp1", 0, RK3399_CLKGATE_CON(34), 5, GFLAGS),
1111         GATE(0, "hclk_sdioaudio_noc", "hclk_perilp1", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(34), 6, GFLAGS),
1112
1113         /* pclk_perilp1 gates */
1114         GATE(PCLK_UART0, "pclk_uart0", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 0, GFLAGS),
1115         GATE(PCLK_UART1, "pclk_uart1", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 1, GFLAGS),
1116         GATE(PCLK_UART2, "pclk_uart2", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 2, GFLAGS),
1117         GATE(PCLK_UART3, "pclk_uart3", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 3, GFLAGS),
1118         GATE(PCLK_I2C7, "pclk_rki2c7", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 5, GFLAGS),
1119         GATE(PCLK_I2C1, "pclk_rki2c1", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 6, GFLAGS),
1120         GATE(PCLK_I2C5, "pclk_rki2c5", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 7, GFLAGS),
1121         GATE(PCLK_I2C6, "pclk_rki2c6", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 8, GFLAGS),
1122         GATE(PCLK_I2C2, "pclk_rki2c2", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 9, GFLAGS),
1123         GATE(PCLK_I2C3, "pclk_rki2c3", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 10, GFLAGS),
1124         GATE(PCLK_MAILBOX0, "pclk_mailbox0", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 11, GFLAGS),
1125         GATE(PCLK_SARADC, "pclk_saradc", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 12, GFLAGS),
1126         GATE(PCLK_TSADC, "pclk_tsadc", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 13, GFLAGS),
1127         GATE(PCLK_EFUSE1024NS, "pclk_efuse1024ns", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 14, GFLAGS),
1128         GATE(PCLK_EFUSE1024S, "pclk_efuse1024s", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 15, GFLAGS),
1129         GATE(PCLK_SPI0, "pclk_spi0", "pclk_perilp1", 0, RK3399_CLKGATE_CON(23), 10, GFLAGS),
1130         GATE(PCLK_SPI1, "pclk_spi1", "pclk_perilp1", 0, RK3399_CLKGATE_CON(23), 11, GFLAGS),
1131         GATE(PCLK_SPI2, "pclk_spi2", "pclk_perilp1", 0, RK3399_CLKGATE_CON(23), 12, GFLAGS),
1132         GATE(PCLK_SPI4, "pclk_spi4", "pclk_perilp1", 0, RK3399_CLKGATE_CON(23), 13, GFLAGS),
1133         GATE(PCLK_PERIHP_GRF, "pclk_perilp_sgrf", "pclk_perilp1", 0, RK3399_CLKGATE_CON(24), 13, GFLAGS),
1134         GATE(0, "pclk_perilp1_noc", "pclk_perilp1", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(25), 10, GFLAGS),
1135
1136         /* saradc */
1137         COMPOSITE_NOMUX(SCLK_SARADC, "clk_saradc", "xin24m", 0,
1138                         RK3399_CLKSEL_CON(26), 8, 8, DFLAGS,
1139                         RK3399_CLKGATE_CON(9), 11, GFLAGS),
1140
1141         /* tsadc */
1142         COMPOSITE(SCLK_TSADC, "clk_tsadc", mux_pll_p, 0,
1143                         RK3399_CLKSEL_CON(27), 15, 1, MFLAGS, 0, 10, DFLAGS,
1144                         RK3399_CLKGATE_CON(9), 10, GFLAGS),
1145
1146         /* cif_testout */
1147         MUX(0, "clk_testout1_pll_src", mux_pll_src_cpll_gpll_npll_p, 0,
1148                         RK3399_CLKSEL_CON(38), 6, 2, MFLAGS),
1149         COMPOSITE(0, "clk_testout1", mux_clk_testout1_p, 0,
1150                         RK3399_CLKSEL_CON(38), 5, 1, MFLAGS, 0, 5, DFLAGS,
1151                         RK3399_CLKGATE_CON(13), 14, GFLAGS),
1152
1153         MUX(0, "clk_testout2_pll_src", mux_pll_src_cpll_gpll_npll_p, 0,
1154                         RK3399_CLKSEL_CON(38), 14, 2, MFLAGS),
1155         COMPOSITE(SCLK_TESTOUT2, "clk_testout2", mux_clk_testout2_p, 0,
1156                         RK3399_CLKSEL_CON(38), 13, 1, MFLAGS, 8, 5, DFLAGS,
1157                         RK3399_CLKGATE_CON(13), 15, GFLAGS),
1158
1159         /* vio */
1160         COMPOSITE(ACLK_VIO, "aclk_vio", mux_pll_src_cpll_gpll_ppll_p, CLK_IGNORE_UNUSED,
1161                         RK3399_CLKSEL_CON(42), 6, 2, MFLAGS, 0, 5, DFLAGS,
1162                         RK3399_CLKGATE_CON(11), 10, GFLAGS),
1163         COMPOSITE_NOMUX(PCLK_VIO, "pclk_vio", "aclk_vio", CLK_IGNORE_UNUSED,
1164                         RK3399_CLKSEL_CON(43), 0, 5, DFLAGS,
1165                         RK3399_CLKGATE_CON(11), 1, GFLAGS),
1166
1167         GATE(ACLK_VIO_NOC, "aclk_vio_noc", "aclk_vio", CLK_IGNORE_UNUSED,
1168                         RK3399_CLKGATE_CON(29), 0, GFLAGS),
1169
1170         GATE(PCLK_MIPI_DSI0, "pclk_mipi_dsi0", "pclk_vio", 0,
1171                         RK3399_CLKGATE_CON(29), 1, GFLAGS),
1172         GATE(PCLK_MIPI_DSI1, "pclk_mipi_dsi1", "pclk_vio", 0,
1173                         RK3399_CLKGATE_CON(29), 2, GFLAGS),
1174         GATE(PCLK_VIO_GRF, "pclk_vio_grf", "pclk_vio", CLK_IGNORE_UNUSED,
1175                         RK3399_CLKGATE_CON(29), 12, GFLAGS),
1176
1177         /* hdcp */
1178         COMPOSITE(ACLK_HDCP, "aclk_hdcp", mux_pll_src_cpll_gpll_ppll_p, 0,
1179                         RK3399_CLKSEL_CON(42), 14, 2, MFLAGS, 8, 5, DFLAGS,
1180                         RK3399_CLKGATE_CON(11), 12, GFLAGS),
1181         COMPOSITE_NOMUX(HCLK_HDCP, "hclk_hdcp", "aclk_hdcp", 0,
1182                         RK3399_CLKSEL_CON(43), 5, 5, DFLAGS,
1183                         RK3399_CLKGATE_CON(11), 3, GFLAGS),
1184         COMPOSITE_NOMUX(PCLK_HDCP, "pclk_hdcp", "aclk_hdcp", 0,
1185                         RK3399_CLKSEL_CON(43), 10, 5, DFLAGS,
1186                         RK3399_CLKGATE_CON(11), 10, GFLAGS),
1187
1188         GATE(ACLK_HDCP_NOC, "aclk_hdcp_noc", "aclk_hdcp", CLK_IGNORE_UNUSED,
1189                         RK3399_CLKGATE_CON(29), 4, GFLAGS),
1190         GATE(ACLK_HDCP22, "aclk_hdcp22", "aclk_hdcp", 0,
1191                         RK3399_CLKGATE_CON(29), 10, GFLAGS),
1192
1193         GATE(HCLK_HDCP_NOC, "hclk_hdcp_noc", "hclk_hdcp", CLK_IGNORE_UNUSED,
1194                         RK3399_CLKGATE_CON(29), 5, GFLAGS),
1195         GATE(HCLK_HDCP22, "hclk_hdcp22", "hclk_hdcp", 0,
1196                         RK3399_CLKGATE_CON(29), 9, GFLAGS),
1197
1198         GATE(PCLK_HDCP_NOC, "pclk_hdcp_noc", "pclk_hdcp", CLK_IGNORE_UNUSED,
1199                         RK3399_CLKGATE_CON(29), 3, GFLAGS),
1200         GATE(PCLK_HDMI_CTRL, "pclk_hdmi_ctrl", "pclk_hdcp", 0,
1201                         RK3399_CLKGATE_CON(29), 6, GFLAGS),
1202         GATE(PCLK_DP_CTRL, "pclk_dp_ctrl", "pclk_hdcp", 0,
1203                         RK3399_CLKGATE_CON(29), 7, GFLAGS),
1204         GATE(PCLK_HDCP22, "pclk_hdcp22", "pclk_hdcp", 0,
1205                         RK3399_CLKGATE_CON(29), 8, GFLAGS),
1206         GATE(PCLK_GASKET, "pclk_gasket", "pclk_hdcp", 0,
1207                         RK3399_CLKGATE_CON(29), 11, GFLAGS),
1208
1209         /* edp */
1210         COMPOSITE(SCLK_DP_CORE, "clk_dp_core", mux_pll_src_npll_cpll_gpll_p, 0,
1211                         RK3399_CLKSEL_CON(46), 6, 2, MFLAGS, 0, 5, DFLAGS,
1212                         RK3399_CLKGATE_CON(11), 8, GFLAGS),
1213
1214         COMPOSITE(PCLK_EDP, "pclk_edp", mux_pll_src_cpll_gpll_p, 0,
1215                         RK3399_CLKSEL_CON(44), 15, 1, MFLAGS, 8, 5, DFLAGS,
1216                         RK3399_CLKGATE_CON(11), 11, GFLAGS),
1217         GATE(PCLK_EDP_NOC, "pclk_edp_noc", "pclk_edp", CLK_IGNORE_UNUSED,
1218                         RK3399_CLKGATE_CON(32), 12, GFLAGS),
1219         GATE(PCLK_EDP_CTRL, "pclk_edp_ctrl", "pclk_edp", 0,
1220                         RK3399_CLKGATE_CON(32), 13, GFLAGS),
1221
1222         /* hdmi */
1223         GATE(SCLK_HDMI_SFR, "clk_hdmi_sfr", "xin24m", 0,
1224                         RK3399_CLKGATE_CON(11), 6, GFLAGS),
1225
1226         COMPOSITE(SCLK_HDMI_CEC, "clk_hdmi_cec", mux_pll_p, 0,
1227                         RK3399_CLKSEL_CON(45), 15, 1, MFLAGS, 0, 10, DFLAGS,
1228                         RK3399_CLKGATE_CON(11), 7, GFLAGS),
1229
1230         /* vop0 */
1231         COMPOSITE(ACLK_VOP0_PRE, "aclk_vop0_pre", mux_pll_src_dmyvpll_cpll_gpll_npll_p, 0,
1232                         RK3399_CLKSEL_CON(47), 6, 2, MFLAGS, 0, 5, DFLAGS,
1233                         RK3399_CLKGATE_CON(10), 8, GFLAGS),
1234         COMPOSITE_NOMUX(0, "hclk_vop0_pre", "aclk_vop0_pre", 0,
1235                         RK3399_CLKSEL_CON(47), 8, 5, DFLAGS,
1236                         RK3399_CLKGATE_CON(10), 9, GFLAGS),
1237
1238         GATE(ACLK_VOP0, "aclk_vop0", "aclk_vop0_pre", 0,
1239                         RK3399_CLKGATE_CON(28), 3, GFLAGS),
1240         GATE(ACLK_VOP0_NOC, "aclk_vop0_noc", "aclk_vop0_pre", CLK_IGNORE_UNUSED,
1241                         RK3399_CLKGATE_CON(28), 1, GFLAGS),
1242
1243         GATE(HCLK_VOP0, "hclk_vop0", "hclk_vop0_pre", 0,
1244                         RK3399_CLKGATE_CON(28), 2, GFLAGS),
1245         GATE(HCLK_VOP0_NOC, "hclk_vop0_noc", "hclk_vop0_pre", CLK_IGNORE_UNUSED,
1246                         RK3399_CLKGATE_CON(28), 0, GFLAGS),
1247
1248 #ifdef RK3399_TWO_PLL_FOR_VOP
1249         COMPOSITE(DCLK_VOP0_DIV, "dclk_vop0_div", mux_pll_src_vpll_cpll_gpll_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
1250                         RK3399_CLKSEL_CON(49), 8, 2, MFLAGS, 0, 8, DFLAGS,
1251                         RK3399_CLKGATE_CON(10), 12, GFLAGS),
1252 #else
1253         COMPOSITE(DCLK_VOP0_DIV, "dclk_vop0_div", mux_pll_src_vpll_cpll_gpll_p, CLK_SET_RATE_PARENT,
1254                         RK3399_CLKSEL_CON(49), 8, 2, MFLAGS, 0, 8, DFLAGS,
1255                         RK3399_CLKGATE_CON(10), 12, GFLAGS),
1256 #endif
1257
1258         /* The VOP0 is main screen, it is able to re-set parent rate. */
1259         COMPOSITE_FRACMUX_NOGATE(0, "dclk_vop0_frac", "dclk_vop0_div", CLK_SET_RATE_PARENT,
1260                         RK3399_CLKSEL_CON(106), 0,
1261                         &rk3399_dclk_vop0_fracmux),
1262
1263         COMPOSITE(SCLK_VOP0_PWM, "clk_vop0_pwm", mux_pll_src_dmyvpll_cpll_gpll_24m_p, 0,
1264                         RK3399_CLKSEL_CON(51), 6, 2, MFLAGS, 0, 5, DFLAGS,
1265                         RK3399_CLKGATE_CON(10), 14, GFLAGS),
1266
1267         /* vop1 */
1268         COMPOSITE(ACLK_VOP1_PRE, "aclk_vop1_pre", mux_pll_src_dmyvpll_cpll_gpll_npll_p, 0,
1269                         RK3399_CLKSEL_CON(48), 6, 2, MFLAGS, 0, 5, DFLAGS,
1270                         RK3399_CLKGATE_CON(10), 10, GFLAGS),
1271         COMPOSITE_NOMUX(0, "hclk_vop1_pre", "aclk_vop1_pre", 0,
1272                         RK3399_CLKSEL_CON(48), 8, 5, DFLAGS,
1273                         RK3399_CLKGATE_CON(10), 11, GFLAGS),
1274
1275         GATE(ACLK_VOP1, "aclk_vop1", "aclk_vop1_pre", 0,
1276                         RK3399_CLKGATE_CON(28), 7, GFLAGS),
1277         GATE(ACLK_VOP1_NOC, "aclk_vop1_noc", "aclk_vop1_pre", CLK_IGNORE_UNUSED,
1278                         RK3399_CLKGATE_CON(28), 5, GFLAGS),
1279
1280         GATE(HCLK_VOP1, "hclk_vop1", "hclk_vop1_pre", 0,
1281                         RK3399_CLKGATE_CON(28), 6, GFLAGS),
1282         GATE(HCLK_VOP1_NOC, "hclk_vop1_noc", "hclk_vop1_pre", CLK_IGNORE_UNUSED,
1283                         RK3399_CLKGATE_CON(28), 4, GFLAGS),
1284
1285         /* The VOP1 is sub screen, it is note able to re-set parent rate. */
1286 #ifdef RK3399_TWO_PLL_FOR_VOP
1287         COMPOSITE(DCLK_VOP1_DIV, "dclk_vop1_div", mux_pll_src_vpll_cpll_gpll_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
1288                         RK3399_CLKSEL_CON(50), 8, 2, MFLAGS, 0, 8, DFLAGS,
1289                         RK3399_CLKGATE_CON(10), 13, GFLAGS),
1290 #else
1291         COMPOSITE(DCLK_VOP1_DIV, "dclk_vop1_div", mux_pll_src_dmyvpll_cpll_gpll_p, 0,
1292                         RK3399_CLKSEL_CON(50), 8, 2, MFLAGS, 0, 8, DFLAGS,
1293                         RK3399_CLKGATE_CON(10), 13, GFLAGS),
1294 #endif
1295
1296         COMPOSITE_FRACMUX_NOGATE(0, "dclk_vop1_frac", "dclk_vop1_div", CLK_SET_RATE_PARENT,
1297                         RK3399_CLKSEL_CON(107), 0,
1298                         &rk3399_dclk_vop1_fracmux),
1299
1300         COMPOSITE(SCLK_VOP1_PWM, "clk_vop1_pwm", mux_pll_src_dmyvpll_cpll_gpll_24m_p, 0,
1301                         RK3399_CLKSEL_CON(52), 6, 2, MFLAGS, 0, 5, DFLAGS,
1302                         RK3399_CLKGATE_CON(10), 15, GFLAGS),
1303
1304         /* isp */
1305         COMPOSITE(ACLK_ISP0, "aclk_isp0", mux_pll_src_cpll_gpll_ppll_p, 0,
1306                         RK3399_CLKSEL_CON(53), 6, 2, MFLAGS, 0, 5, DFLAGS,
1307                         RK3399_CLKGATE_CON(12), 8, GFLAGS),
1308         COMPOSITE_NOMUX(HCLK_ISP0, "hclk_isp0", "aclk_isp0", 0,
1309                         RK3399_CLKSEL_CON(53), 8, 5, DFLAGS,
1310                         RK3399_CLKGATE_CON(12), 9, GFLAGS),
1311
1312         GATE(ACLK_ISP0_NOC, "aclk_isp0_noc", "aclk_isp0", CLK_IGNORE_UNUSED,
1313                         RK3399_CLKGATE_CON(27), 1, GFLAGS),
1314         GATE(ACLK_ISP0_WRAPPER, "aclk_isp0_wrapper", "aclk_isp0", 0,
1315                         RK3399_CLKGATE_CON(27), 5, GFLAGS),
1316         GATE(HCLK_ISP1_WRAPPER, "hclk_isp1_wrapper", "aclk_isp0", 0,
1317                         RK3399_CLKGATE_CON(27), 7, GFLAGS),
1318
1319         GATE(HCLK_ISP0_NOC, "hclk_isp0_noc", "hclk_isp0", CLK_IGNORE_UNUSED,
1320                         RK3399_CLKGATE_CON(27), 0, GFLAGS),
1321         GATE(HCLK_ISP0_WRAPPER, "hclk_isp0_wrapper", "hclk_isp0", 0,
1322                         RK3399_CLKGATE_CON(27), 4, GFLAGS),
1323
1324         COMPOSITE(SCLK_ISP0, "clk_isp0", mux_pll_src_cpll_gpll_npll_p, 0,
1325                         RK3399_CLKSEL_CON(55), 6, 2, MFLAGS, 0, 5, DFLAGS,
1326                         RK3399_CLKGATE_CON(11), 4, GFLAGS),
1327
1328         COMPOSITE(ACLK_ISP1, "aclk_isp1", mux_pll_src_cpll_gpll_ppll_p, 0,
1329                         RK3399_CLKSEL_CON(54), 6, 2, MFLAGS, 0, 5, DFLAGS,
1330                         RK3399_CLKGATE_CON(12), 10, GFLAGS),
1331         COMPOSITE_NOMUX(HCLK_ISP1, "hclk_isp1", "aclk_isp1", 0,
1332                         RK3399_CLKSEL_CON(54), 8, 5, DFLAGS,
1333                         RK3399_CLKGATE_CON(12), 11, GFLAGS),
1334
1335         GATE(ACLK_ISP1_NOC, "aclk_isp1_noc", "aclk_isp1", CLK_IGNORE_UNUSED,
1336                         RK3399_CLKGATE_CON(27), 3, GFLAGS),
1337
1338         GATE(HCLK_ISP1_NOC, "hclk_isp1_noc", "hclk_isp1", CLK_IGNORE_UNUSED,
1339                         RK3399_CLKGATE_CON(27), 2, GFLAGS),
1340         GATE(ACLK_ISP1_WRAPPER, "aclk_isp1_wrapper", "hclk_isp1", 0,
1341                         RK3399_CLKGATE_CON(27), 8, GFLAGS),
1342
1343         COMPOSITE(SCLK_ISP1, "clk_isp1", mux_pll_src_cpll_gpll_npll_p, 0,
1344                         RK3399_CLKSEL_CON(55), 14, 2, MFLAGS, 8, 5, DFLAGS,
1345                         RK3399_CLKGATE_CON(11), 5, GFLAGS),
1346
1347         /*
1348          * We use pclkin_cifinv by default GRF_SOC_CON20[9] (GSC20_9) setting in system,
1349          * so we ignore the mux and make clocks nodes as following,
1350          *
1351          * pclkin_cifinv --|-------\
1352          *                 |GSC20_9|-- pclkin_cifmux -- |G27_6| -- pclkin_isp1_wrapper
1353          * pclkin_cif    --|-------/
1354          */
1355         GATE(PCLK_ISP1_WRAPPER, "pclkin_isp1_wrapper", "pclkin_cif", 0,
1356                         RK3399_CLKGATE_CON(27), 6, GFLAGS),
1357
1358         /* cif */
1359         COMPOSITE_NODIV(0, "clk_cifout_src", mux_pll_src_cpll_gpll_npll_p, 0,
1360                         RK3399_CLKSEL_CON(56), 6, 2, MFLAGS,
1361                         RK3399_CLKGATE_CON(10), 7, GFLAGS),
1362
1363         COMPOSITE_NOGATE(SCLK_CIF_OUT, "clk_cifout", mux_clk_cif_p, 0,
1364                          RK3399_CLKSEL_CON(56), 5, 1, MFLAGS, 0, 5, DFLAGS),
1365
1366         /* gic */
1367         COMPOSITE(ACLK_GIC_PRE, "aclk_gic_pre", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED,
1368                         RK3399_CLKSEL_CON(56), 15, 1, MFLAGS, 8, 5, DFLAGS,
1369                         RK3399_CLKGATE_CON(12), 12, GFLAGS),
1370
1371         GATE(ACLK_GIC, "aclk_gic", "aclk_gic_pre", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(33), 0, GFLAGS),
1372         GATE(ACLK_GIC_NOC, "aclk_gic_noc", "aclk_gic_pre", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(33), 1, GFLAGS),
1373         GATE(ACLK_GIC_ADB400_CORE_L_2_GIC, "aclk_gic_adb400_core_l_2_gic", "aclk_gic_pre", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(33), 2, GFLAGS),
1374         GATE(ACLK_GIC_ADB400_CORE_B_2_GIC, "aclk_gic_adb400_core_b_2_gic", "aclk_gic_pre", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(33), 3, GFLAGS),
1375         GATE(ACLK_GIC_ADB400_GIC_2_CORE_L, "aclk_gic_adb400_gic_2_core_l", "aclk_gic_pre", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(33), 4, GFLAGS),
1376         GATE(ACLK_GIC_ADB400_GIC_2_CORE_B, "aclk_gic_adb400_gic_2_core_b", "aclk_gic_pre", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(33), 5, GFLAGS),
1377
1378         /* alive */
1379         /* pclk_alive_gpll_src is controlled by PMUGRF_SOC_CON0[6] */
1380         DIV(PCLK_ALIVE, "pclk_alive", "gpll", 0,
1381                         RK3399_CLKSEL_CON(57), 0, 5, DFLAGS),
1382
1383         GATE(PCLK_USBPHY_MUX_G, "pclk_usbphy_mux_g", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 4, GFLAGS),
1384         GATE(PCLK_UPHY0_TCPHY_G, "pclk_uphy0_tcphy_g", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 5, GFLAGS),
1385         GATE(PCLK_UPHY0_TCPD_G, "pclk_uphy0_tcpd_g", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 6, GFLAGS),
1386         GATE(PCLK_UPHY1_TCPHY_G, "pclk_uphy1_tcphy_g", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 8, GFLAGS),
1387         GATE(PCLK_UPHY1_TCPD_G, "pclk_uphy1_tcpd_g", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 9, GFLAGS),
1388
1389         GATE(PCLK_GRF, "pclk_grf", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(31), 1, GFLAGS),
1390         GATE(PCLK_INTR_ARB, "pclk_intr_arb", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(31), 2, GFLAGS),
1391         GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_alive", 0, RK3399_CLKGATE_CON(31), 3, GFLAGS),
1392         GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_alive", 0, RK3399_CLKGATE_CON(31), 4, GFLAGS),
1393         GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_alive", 0, RK3399_CLKGATE_CON(31), 5, GFLAGS),
1394         GATE(PCLK_TIMER0, "pclk_timer0", "pclk_alive", 0, RK3399_CLKGATE_CON(31), 6, GFLAGS),
1395         GATE(PCLK_TIMER1, "pclk_timer1", "pclk_alive", 0, RK3399_CLKGATE_CON(31), 7, GFLAGS),
1396         GATE(PCLK_PMU_INTR_ARB, "pclk_pmu_intr_arb", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(31), 9, GFLAGS),
1397         GATE(PCLK_SGRF, "pclk_sgrf", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(31), 10, GFLAGS),
1398
1399         GATE(SCLK_MIPIDPHY_REF, "clk_mipidphy_ref", "xin24m", 0, RK3399_CLKGATE_CON(11), 14, GFLAGS),
1400         GATE(SCLK_DPHY_PLL, "clk_dphy_pll", "clk_mipidphy_ref", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 0, GFLAGS),
1401
1402         GATE(SCLK_MIPIDPHY_CFG, "clk_mipidphy_cfg", "xin24m", 0, RK3399_CLKGATE_CON(11), 15, GFLAGS),
1403         GATE(SCLK_DPHY_TX0_CFG, "clk_dphy_tx0_cfg", "clk_mipidphy_cfg", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 1, GFLAGS),
1404         GATE(SCLK_DPHY_TX1RX1_CFG, "clk_dphy_tx1rx1_cfg", "clk_mipidphy_cfg", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 2, GFLAGS),
1405         GATE(SCLK_DPHY_RX0_CFG, "clk_dphy_rx0_cfg", "clk_mipidphy_cfg", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 3, GFLAGS),
1406
1407         /* testout */
1408         MUX(0, "clk_test_pre", mux_pll_src_cpll_gpll_p, CLK_SET_RATE_PARENT,
1409                         RK3399_CLKSEL_CON(58), 7, 1, MFLAGS),
1410         COMPOSITE_FRAC(0, "clk_test_frac", "clk_test_pre", CLK_SET_RATE_PARENT,
1411                         RK3399_CLKSEL_CON(105), 0,
1412                         RK3399_CLKGATE_CON(13), 9, GFLAGS),
1413
1414         DIV(0, "clk_test_24m", "xin24m", 0,
1415                         RK3399_CLKSEL_CON(57), 6, 10, DFLAGS),
1416
1417         /* spi */
1418         COMPOSITE(SCLK_SPI0, "clk_spi0", mux_pll_src_cpll_gpll_p, 0,
1419                         RK3399_CLKSEL_CON(59), 7, 1, MFLAGS, 0, 7, DFLAGS,
1420                         RK3399_CLKGATE_CON(9), 12, GFLAGS),
1421
1422         COMPOSITE(SCLK_SPI1, "clk_spi1", mux_pll_src_cpll_gpll_p, 0,
1423                         RK3399_CLKSEL_CON(59), 15, 1, MFLAGS, 8, 7, DFLAGS,
1424                         RK3399_CLKGATE_CON(9), 13, GFLAGS),
1425
1426         COMPOSITE(SCLK_SPI2, "clk_spi2", mux_pll_src_cpll_gpll_p, 0,
1427                         RK3399_CLKSEL_CON(60), 7, 1, MFLAGS, 0, 7, DFLAGS,
1428                         RK3399_CLKGATE_CON(9), 14, GFLAGS),
1429
1430         COMPOSITE(SCLK_SPI4, "clk_spi4", mux_pll_src_cpll_gpll_p, 0,
1431                         RK3399_CLKSEL_CON(60), 15, 1, MFLAGS, 8, 7, DFLAGS,
1432                         RK3399_CLKGATE_CON(9), 15, GFLAGS),
1433
1434         COMPOSITE(SCLK_SPI5, "clk_spi5", mux_pll_src_cpll_gpll_p, 0,
1435                         RK3399_CLKSEL_CON(58), 15, 1, MFLAGS, 8, 7, DFLAGS,
1436                         RK3399_CLKGATE_CON(13), 13, GFLAGS),
1437
1438         /* i2c */
1439         COMPOSITE(SCLK_I2C1, "clk_i2c1", mux_pll_src_cpll_gpll_p, 0,
1440                         RK3399_CLKSEL_CON(61), 7, 1, MFLAGS, 0, 7, DFLAGS,
1441                         RK3399_CLKGATE_CON(10), 0, GFLAGS),
1442
1443         COMPOSITE(SCLK_I2C2, "clk_i2c2", mux_pll_src_cpll_gpll_p, 0,
1444                         RK3399_CLKSEL_CON(62), 7, 1, MFLAGS, 0, 7, DFLAGS,
1445                         RK3399_CLKGATE_CON(10), 2, GFLAGS),
1446
1447         COMPOSITE(SCLK_I2C3, "clk_i2c3", mux_pll_src_cpll_gpll_p, 0,
1448                         RK3399_CLKSEL_CON(63), 7, 1, MFLAGS, 0, 7, DFLAGS,
1449                         RK3399_CLKGATE_CON(10), 4, GFLAGS),
1450
1451         COMPOSITE(SCLK_I2C5, "clk_i2c5", mux_pll_src_cpll_gpll_p, 0,
1452                         RK3399_CLKSEL_CON(61), 15, 1, MFLAGS, 8, 7, DFLAGS,
1453                         RK3399_CLKGATE_CON(10), 1, GFLAGS),
1454
1455         COMPOSITE(SCLK_I2C6, "clk_i2c6", mux_pll_src_cpll_gpll_p, 0,
1456                         RK3399_CLKSEL_CON(62), 15, 1, MFLAGS, 8, 7, DFLAGS,
1457                         RK3399_CLKGATE_CON(10), 3, GFLAGS),
1458
1459         COMPOSITE(SCLK_I2C7, "clk_i2c7", mux_pll_src_cpll_gpll_p, 0,
1460                         RK3399_CLKSEL_CON(63), 15, 1, MFLAGS, 8, 7, DFLAGS,
1461                         RK3399_CLKGATE_CON(10), 5, GFLAGS),
1462
1463         /* timer */
1464         GATE(SCLK_TIMER00, "clk_timer00", "xin24m", 0, RK3399_CLKGATE_CON(26), 0, GFLAGS),
1465         GATE(SCLK_TIMER01, "clk_timer01", "xin24m", 0, RK3399_CLKGATE_CON(26), 1, GFLAGS),
1466         GATE(SCLK_TIMER02, "clk_timer02", "xin24m", 0, RK3399_CLKGATE_CON(26), 2, GFLAGS),
1467         GATE(SCLK_TIMER03, "clk_timer03", "xin24m", 0, RK3399_CLKGATE_CON(26), 3, GFLAGS),
1468         GATE(SCLK_TIMER04, "clk_timer04", "xin24m", 0, RK3399_CLKGATE_CON(26), 4, GFLAGS),
1469         GATE(SCLK_TIMER05, "clk_timer05", "xin24m", 0, RK3399_CLKGATE_CON(26), 5, GFLAGS),
1470         GATE(SCLK_TIMER06, "clk_timer06", "xin24m", 0, RK3399_CLKGATE_CON(26), 6, GFLAGS),
1471         GATE(SCLK_TIMER07, "clk_timer07", "xin24m", 0, RK3399_CLKGATE_CON(26), 7, GFLAGS),
1472         GATE(SCLK_TIMER08, "clk_timer08", "xin24m", 0, RK3399_CLKGATE_CON(26), 8, GFLAGS),
1473         GATE(SCLK_TIMER09, "clk_timer09", "xin24m", 0, RK3399_CLKGATE_CON(26), 9, GFLAGS),
1474         GATE(SCLK_TIMER10, "clk_timer10", "xin24m", 0, RK3399_CLKGATE_CON(26), 10, GFLAGS),
1475         GATE(SCLK_TIMER11, "clk_timer11", "xin24m", 0, RK3399_CLKGATE_CON(26), 11, GFLAGS),
1476
1477         /* clk_test */
1478         /* clk_test_pre is controlled by CRU_MISC_CON[3] */
1479         COMPOSITE_NOMUX(0, "clk_test", "clk_test_pre", CLK_IGNORE_UNUSED,
1480                         RK3399_CLKSEL_CON(58), 0, 5, DFLAGS,
1481                         RK3399_CLKGATE_CON(13), 11, GFLAGS),
1482
1483         /* ddrc */
1484         GATE(0, "clk_ddrc_lpll_src", "lpll", 0, RK3399_CLKGATE_CON(3),
1485              0, GFLAGS),
1486         GATE(0, "clk_ddrc_bpll_src", "bpll", 0, RK3399_CLKGATE_CON(3),
1487              1, GFLAGS),
1488         GATE(0, "clk_ddrc_dpll_src", "dpll", 0, RK3399_CLKGATE_CON(3),
1489              2, GFLAGS),
1490         GATE(0, "clk_ddrc_gpll_src", "gpll", 0, RK3399_CLKGATE_CON(3),
1491              3, GFLAGS),
1492         COMPOSITE_DDRCLK(SCLK_DDRCLK, "sclk_ddrc", mux_ddrclk_p, 0,
1493                        RK3399_CLKSEL_CON(6), 4, 2, 0, 0, ROCKCHIP_DDRCLK_SIP),
1494 };
1495
1496 static struct rockchip_clk_branch rk3399_clk_pmu_branches[] __initdata = {
1497         /*
1498          * PMU CRU Clock-Architecture
1499          */
1500
1501         GATE(0, "fclk_cm0s_pmu_ppll_src", "ppll", 0,
1502                         RK3399_PMU_CLKGATE_CON(0), 1, GFLAGS),
1503
1504         COMPOSITE_NOGATE(FCLK_CM0S_SRC_PMU, "fclk_cm0s_src_pmu", mux_fclk_cm0s_pmu_ppll_p, 0,
1505                         RK3399_PMU_CLKSEL_CON(0), 15, 1, MFLAGS, 8, 5, DFLAGS),
1506
1507         COMPOSITE(SCLK_SPI3_PMU, "clk_spi3_pmu", mux_24m_ppll_p, 0,
1508                         RK3399_PMU_CLKSEL_CON(1), 7, 1, MFLAGS, 0, 7, DFLAGS,
1509                         RK3399_PMU_CLKGATE_CON(0), 2, GFLAGS),
1510
1511         COMPOSITE(0, "clk_wifi_div", mux_ppll_24m_p, CLK_IGNORE_UNUSED,
1512                         RK3399_PMU_CLKSEL_CON(1), 13, 1, MFLAGS, 8, 5, DFLAGS,
1513                         RK3399_PMU_CLKGATE_CON(0), 8, GFLAGS),
1514
1515         COMPOSITE_FRACMUX_NOGATE(0, "clk_wifi_frac", "clk_wifi_div", CLK_SET_RATE_PARENT,
1516                         RK3399_PMU_CLKSEL_CON(7), 0,
1517                         &rk3399_pmuclk_wifi_fracmux),
1518
1519         MUX(0, "clk_timer_src_pmu", mux_pll_p, CLK_IGNORE_UNUSED,
1520                         RK3399_PMU_CLKSEL_CON(1), 15, 1, MFLAGS),
1521
1522         COMPOSITE_NOMUX(SCLK_I2C0_PMU, "clk_i2c0_pmu", "ppll", 0,
1523                         RK3399_PMU_CLKSEL_CON(2), 0, 7, DFLAGS,
1524                         RK3399_PMU_CLKGATE_CON(0), 9, GFLAGS),
1525
1526         COMPOSITE_NOMUX(SCLK_I2C4_PMU, "clk_i2c4_pmu", "ppll", 0,
1527                         RK3399_PMU_CLKSEL_CON(3), 0, 7, DFLAGS,
1528                         RK3399_PMU_CLKGATE_CON(0), 10, GFLAGS),
1529
1530         COMPOSITE_NOMUX(SCLK_I2C8_PMU, "clk_i2c8_pmu", "ppll", 0,
1531                         RK3399_PMU_CLKSEL_CON(2), 8, 7, DFLAGS,
1532                         RK3399_PMU_CLKGATE_CON(0), 11, GFLAGS),
1533
1534         DIV(0, "clk_32k_suspend_pmu", "xin24m", CLK_IGNORE_UNUSED,
1535                         RK3399_PMU_CLKSEL_CON(4), 0, 10, DFLAGS),
1536         MUX(0, "clk_testout_2io", mux_clk_testout2_2io_p, CLK_IGNORE_UNUSED,
1537                         RK3399_PMU_CLKSEL_CON(4), 15, 1, MFLAGS),
1538
1539         COMPOSITE(0, "clk_uart4_div", mux_24m_ppll_p, 0,
1540                         RK3399_PMU_CLKSEL_CON(5), 10, 1, MFLAGS, 0, 7, DFLAGS,
1541                         RK3399_PMU_CLKGATE_CON(0), 5, GFLAGS),
1542
1543         COMPOSITE_FRACMUX(0, "clk_uart4_frac", "clk_uart4_div", CLK_SET_RATE_PARENT,
1544                         RK3399_PMU_CLKSEL_CON(6), 0,
1545                         RK3399_PMU_CLKGATE_CON(0), 6, GFLAGS,
1546                         &rk3399_uart4_pmu_fracmux),
1547
1548         DIV(PCLK_SRC_PMU, "pclk_pmu_src", "ppll", CLK_IGNORE_UNUSED,
1549                         RK3399_PMU_CLKSEL_CON(0), 0, 5, DFLAGS),
1550
1551         /* pmu clock gates */
1552         GATE(SCLK_TIMER12_PMU, "clk_timer0_pmu", "clk_timer_src_pmu", 0, RK3399_PMU_CLKGATE_CON(0), 3, GFLAGS),
1553         GATE(SCLK_TIMER13_PMU, "clk_timer1_pmu", "clk_timer_src_pmu", 0, RK3399_PMU_CLKGATE_CON(0), 4, GFLAGS),
1554
1555         GATE(SCLK_PVTM_PMU, "clk_pvtm_pmu", "xin24m", 0, RK3399_PMU_CLKGATE_CON(0), 7, GFLAGS),
1556
1557         GATE(PCLK_PMU, "pclk_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1), 0, GFLAGS),
1558         GATE(PCLK_PMUGRF_PMU, "pclk_pmugrf_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1), 1, GFLAGS),
1559         GATE(PCLK_INTMEM1_PMU, "pclk_intmem1_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1), 2, GFLAGS),
1560         GATE(PCLK_GPIO0_PMU, "pclk_gpio0_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 3, GFLAGS),
1561         GATE(PCLK_GPIO1_PMU, "pclk_gpio1_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 4, GFLAGS),
1562         GATE(PCLK_SGRF_PMU, "pclk_sgrf_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1), 5, GFLAGS),
1563         GATE(PCLK_NOC_PMU, "pclk_noc_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1), 6, GFLAGS),
1564         GATE(PCLK_I2C0_PMU, "pclk_i2c0_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 7, GFLAGS),
1565         GATE(PCLK_I2C4_PMU, "pclk_i2c4_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 8, GFLAGS),
1566         GATE(PCLK_I2C8_PMU, "pclk_i2c8_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 9, GFLAGS),
1567         GATE(PCLK_RKPWM_PMU, "pclk_rkpwm_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 10, GFLAGS),
1568         GATE(PCLK_SPI3_PMU, "pclk_spi3_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 11, GFLAGS),
1569         GATE(PCLK_TIMER_PMU, "pclk_timer_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 12, GFLAGS),
1570         GATE(PCLK_MAILBOX_PMU, "pclk_mailbox_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 13, GFLAGS),
1571         GATE(PCLK_UART4_PMU, "pclk_uart4_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 14, GFLAGS),
1572         GATE(PCLK_WDT_M0_PMU, "pclk_wdt_m0_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 15, GFLAGS),
1573
1574         GATE(FCLK_CM0S_PMU, "fclk_cm0s_pmu", "fclk_cm0s_src_pmu", 0, RK3399_PMU_CLKGATE_CON(2), 0, GFLAGS),
1575         GATE(SCLK_CM0S_PMU, "sclk_cm0s_pmu", "fclk_cm0s_src_pmu", 0, RK3399_PMU_CLKGATE_CON(2), 1, GFLAGS),
1576         GATE(HCLK_CM0S_PMU, "hclk_cm0s_pmu", "fclk_cm0s_src_pmu", 0, RK3399_PMU_CLKGATE_CON(2), 2, GFLAGS),
1577         GATE(DCLK_CM0S_PMU, "dclk_cm0s_pmu", "fclk_cm0s_src_pmu", 0, RK3399_PMU_CLKGATE_CON(2), 3, GFLAGS),
1578         GATE(HCLK_NOC_PMU, "hclk_noc_pmu", "fclk_cm0s_src_pmu", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(2), 5, GFLAGS),
1579 };
1580
1581 static const char *const rk3399_cru_critical_clocks[] __initconst = {
1582         /*
1583          * We need to declare that we enable all NOCs which are critical clocks
1584          * always and clearly and explicitly show that we have enabled them at
1585          * clk_summary.
1586          */
1587         "aclk_usb3_noc",
1588         "aclk_gmac_noc",
1589         "pclk_gmac_noc",
1590         "pclk_center_main_noc",
1591         "aclk_cci_noc0",
1592         "aclk_cci_noc1",
1593         "clk_dbg_noc",
1594         "hclk_vcodec_noc",
1595         "aclk_vcodec_noc",
1596         "hclk_vdu_noc",
1597         "aclk_vdu_noc",
1598         "hclk_iep_noc",
1599         "aclk_iep_noc",
1600         "hclk_rga_noc",
1601         "aclk_rga_noc",
1602         "aclk_center_main_noc",
1603         "aclk_center_peri_noc",
1604         "aclk_perihp_noc",
1605         "hclk_perihp_noc",
1606         "pclk_perihp_noc",
1607         "hclk_sdmmc_noc",
1608         "aclk_emmc_noc",
1609         "aclk_perilp0_noc",
1610         "hclk_perilp0_noc",
1611         "hclk_m0_perilp_noc",
1612         "hclk_perilp1_noc",
1613         "hclk_sdio_noc",
1614         "hclk_sdioaudio_noc",
1615         "pclk_perilp1_noc",
1616         "aclk_vio_noc",
1617         "aclk_hdcp_noc",
1618         "hclk_hdcp_noc",
1619         "pclk_hdcp_noc",
1620         "pclk_edp_noc",
1621         "aclk_vop0_noc",
1622         "hclk_vop0_noc",
1623         "aclk_vop1_noc",
1624         "hclk_vop1_noc",
1625         "aclk_isp0_noc",
1626         "hclk_isp0_noc",
1627         "aclk_isp1_noc",
1628         "hclk_isp1_noc",
1629         "aclk_gic_noc",
1630
1631         /* ddrc */
1632         "sclk_ddrc",
1633
1634         /* other critical clocks */
1635         "pclk_perilp0",
1636         "pclk_perilp0",
1637         "hclk_perilp0",
1638         "pclk_perilp1",
1639         "pclk_perihp",
1640         "hclk_perihp",
1641         "aclk_perihp",
1642         "aclk_perilp0",
1643         "hclk_perilp1",
1644         "aclk_dmac1_perilp",
1645         "gpll_aclk_perilp0_src",
1646         "gpll_aclk_perihp_src",
1647         "pclk_vio",
1648         "pclk_vio_grf",
1649         "pclk_perihp_grf",
1650 };
1651
1652 static const char *const rk3399_pmucru_critical_clocks[] __initconst = {
1653         /*
1654          * We need to declare that we enable all NOCs which are critical clocks
1655          * always and clearly and explicitly show that we have enabled them at
1656          * clk_summary.
1657          */
1658         "pclk_noc_pmu",
1659         "hclk_noc_pmu",
1660
1661         /* other critical clocks */
1662         "ppll",
1663         "pclk_pmu_src",
1664         "fclk_cm0s_src_pmu",
1665         "clk_timer_src_pmu",
1666         "pclk_rkpwm_pmu",
1667 };
1668
1669 static void __iomem *rk3399_cru_base;
1670 static void __iomem *rk3399_pmucru_base;
1671
1672 void rk3399_dump_cru(void)
1673 {
1674         if (rk3399_cru_base) {
1675                 pr_warn("CRU:\n");
1676                 print_hex_dump(KERN_WARNING, "", DUMP_PREFIX_OFFSET,
1677                                32, 4, rk3399_cru_base,
1678                                0x594, false);
1679         }
1680         if (rk3399_pmucru_base) {
1681                 pr_warn("PMU CRU:\n");
1682                 print_hex_dump(KERN_WARNING, "", DUMP_PREFIX_OFFSET,
1683                                32, 4, rk3399_pmucru_base,
1684                                0x134, false);
1685         }
1686 }
1687 EXPORT_SYMBOL_GPL(rk3399_dump_cru);
1688
1689 static int rk3399_clk_panic(struct notifier_block *this,
1690                             unsigned long ev, void *ptr)
1691 {
1692         rk3399_dump_cru();
1693         return NOTIFY_DONE;
1694 }
1695
1696 static struct notifier_block rk3399_clk_panic_block = {
1697         .notifier_call = rk3399_clk_panic,
1698 };
1699
1700 static void __init rk3399_clk_init(struct device_node *np)
1701 {
1702         struct rockchip_clk_provider *ctx;
1703         void __iomem *reg_base;
1704         struct clk *clk;
1705
1706         reg_base = of_iomap(np, 0);
1707         if (!reg_base) {
1708                 pr_err("%s: could not map cru region\n", __func__);
1709                 return;
1710         }
1711
1712         rk3399_cru_base = reg_base;
1713
1714         ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
1715         if (IS_ERR(ctx)) {
1716                 pr_err("%s: rockchip clk init failed\n", __func__);
1717                 return;
1718         }
1719
1720         /* Watchdog pclk is controlled by RK3399 SECURE_GRF_SOC_CON3[8]. */
1721         clk = clk_register_fixed_factor(NULL, "pclk_wdt", "pclk_alive", 0, 1, 1);
1722         if (IS_ERR(clk))
1723                 pr_warn("%s: could not register clock pclk_wdt: %ld\n",
1724                         __func__, PTR_ERR(clk));
1725         else
1726                 rockchip_clk_add_lookup(ctx, clk, PCLK_WDT);
1727
1728         rockchip_clk_register_plls(ctx, rk3399_pll_clks,
1729                                    ARRAY_SIZE(rk3399_pll_clks), -1);
1730
1731         rockchip_clk_register_branches(ctx, rk3399_clk_branches,
1732                                   ARRAY_SIZE(rk3399_clk_branches));
1733
1734         rockchip_clk_protect_critical(rk3399_cru_critical_clocks,
1735                                       ARRAY_SIZE(rk3399_cru_critical_clocks));
1736
1737         rockchip_clk_register_armclk(ctx, ARMCLKL, "armclkl",
1738                         mux_armclkl_p, ARRAY_SIZE(mux_armclkl_p),
1739                         &rk3399_cpuclkl_data, rk3399_cpuclkl_rates,
1740                         ARRAY_SIZE(rk3399_cpuclkl_rates));
1741
1742         rockchip_clk_register_armclk(ctx, ARMCLKB, "armclkb",
1743                         mux_armclkb_p, ARRAY_SIZE(mux_armclkb_p),
1744                         &rk3399_cpuclkb_data, rk3399_cpuclkb_rates,
1745                         ARRAY_SIZE(rk3399_cpuclkb_rates));
1746
1747         rockchip_register_softrst(np, 21, reg_base + RK3399_SOFTRST_CON(0),
1748                                   ROCKCHIP_SOFTRST_HIWORD_MASK);
1749
1750         rockchip_register_restart_notifier(ctx, RK3399_GLB_SRST_FST, NULL);
1751
1752         rockchip_clk_of_add_provider(np, ctx);
1753 }
1754 CLK_OF_DECLARE(rk3399_cru, "rockchip,rk3399-cru", rk3399_clk_init);
1755
1756 static void __init rk3399_pmu_clk_init(struct device_node *np)
1757 {
1758         struct rockchip_clk_provider *ctx;
1759         void __iomem *reg_base;
1760
1761         reg_base = of_iomap(np, 0);
1762         if (!reg_base) {
1763                 pr_err("%s: could not map cru pmu region\n", __func__);
1764                 return;
1765         }
1766
1767         rk3399_pmucru_base = reg_base;
1768
1769         ctx = rockchip_clk_init(np, reg_base, CLKPMU_NR_CLKS);
1770         if (IS_ERR(ctx)) {
1771                 pr_err("%s: rockchip pmu clk init failed\n", __func__);
1772                 return;
1773         }
1774
1775         rockchip_clk_register_plls(ctx, rk3399_pmu_pll_clks,
1776                                    ARRAY_SIZE(rk3399_pmu_pll_clks), -1);
1777
1778         rockchip_clk_register_branches(ctx, rk3399_clk_pmu_branches,
1779                                   ARRAY_SIZE(rk3399_clk_pmu_branches));
1780
1781         rockchip_clk_protect_critical(rk3399_pmucru_critical_clocks,
1782                                       ARRAY_SIZE(rk3399_pmucru_critical_clocks));
1783
1784         rockchip_register_softrst(np, 2, reg_base + RK3399_PMU_SOFTRST_CON(0),
1785                                   ROCKCHIP_SOFTRST_HIWORD_MASK);
1786
1787         rockchip_clk_of_add_provider(np, ctx);
1788
1789         atomic_notifier_chain_register(&panic_notifier_list,
1790                                        &rk3399_clk_panic_block);
1791 }
1792 CLK_OF_DECLARE(rk3399_cru_pmu, "rockchip,rk3399-pmucru", rk3399_pmu_clk_init);