2 * Copyright (c) 2016 Rockchip Electronics Co. Ltd.
3 * Author: Xing Zheng <zhengxing@rock-chips.com>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
16 #include <linux/clk-provider.h>
18 #include <linux/of_address.h>
19 #include <linux/platform_device.h>
20 #include <linux/regmap.h>
21 #include <dt-bindings/clock/rk3399-cru.h>
25 lpll, bpll, dpll, cpll, gpll, npll, vpll,
28 enum rk3399_pmu_plls {
32 static struct rockchip_pll_rate_table rk3399_pll_rates[] = {
33 /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
34 RK3036_PLL_RATE(2208000000, 1, 92, 1, 1, 1, 0),
35 RK3036_PLL_RATE(2184000000, 1, 91, 1, 1, 1, 0),
36 RK3036_PLL_RATE(2160000000, 1, 90, 1, 1, 1, 0),
37 RK3036_PLL_RATE(2136000000, 1, 89, 1, 1, 1, 0),
38 RK3036_PLL_RATE(2112000000, 1, 88, 1, 1, 1, 0),
39 RK3036_PLL_RATE(2088000000, 1, 87, 1, 1, 1, 0),
40 RK3036_PLL_RATE(2064000000, 1, 86, 1, 1, 1, 0),
41 RK3036_PLL_RATE(2040000000, 1, 85, 1, 1, 1, 0),
42 RK3036_PLL_RATE(2016000000, 1, 84, 1, 1, 1, 0),
43 RK3036_PLL_RATE(1992000000, 1, 83, 1, 1, 1, 0),
44 RK3036_PLL_RATE(1968000000, 1, 82, 1, 1, 1, 0),
45 RK3036_PLL_RATE(1944000000, 1, 81, 1, 1, 1, 0),
46 RK3036_PLL_RATE(1920000000, 1, 80, 1, 1, 1, 0),
47 RK3036_PLL_RATE(1896000000, 1, 79, 1, 1, 1, 0),
48 RK3036_PLL_RATE(1872000000, 1, 78, 1, 1, 1, 0),
49 RK3036_PLL_RATE(1848000000, 1, 77, 1, 1, 1, 0),
50 RK3036_PLL_RATE(1824000000, 1, 76, 1, 1, 1, 0),
51 RK3036_PLL_RATE(1800000000, 1, 75, 1, 1, 1, 0),
52 RK3036_PLL_RATE(1776000000, 1, 74, 1, 1, 1, 0),
53 RK3036_PLL_RATE(1752000000, 1, 73, 1, 1, 1, 0),
54 RK3036_PLL_RATE(1728000000, 1, 72, 1, 1, 1, 0),
55 RK3036_PLL_RATE(1704000000, 1, 71, 1, 1, 1, 0),
56 RK3036_PLL_RATE(1680000000, 1, 70, 1, 1, 1, 0),
57 RK3036_PLL_RATE(1656000000, 1, 69, 1, 1, 1, 0),
58 RK3036_PLL_RATE(1632000000, 1, 68, 1, 1, 1, 0),
59 RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0),
60 RK3036_PLL_RATE(1584000000, 1, 66, 1, 1, 1, 0),
61 RK3036_PLL_RATE(1560000000, 1, 65, 1, 1, 1, 0),
62 RK3036_PLL_RATE(1536000000, 1, 64, 1, 1, 1, 0),
63 RK3036_PLL_RATE(1512000000, 1, 63, 1, 1, 1, 0),
64 RK3036_PLL_RATE(1488000000, 1, 62, 1, 1, 1, 0),
65 RK3036_PLL_RATE(1464000000, 1, 61, 1, 1, 1, 0),
66 RK3036_PLL_RATE(1440000000, 1, 60, 1, 1, 1, 0),
67 RK3036_PLL_RATE(1416000000, 1, 59, 1, 1, 1, 0),
68 RK3036_PLL_RATE(1392000000, 1, 58, 1, 1, 1, 0),
69 RK3036_PLL_RATE(1368000000, 1, 57, 1, 1, 1, 0),
70 RK3036_PLL_RATE(1344000000, 1, 56, 1, 1, 1, 0),
71 RK3036_PLL_RATE(1320000000, 1, 55, 1, 1, 1, 0),
72 RK3036_PLL_RATE(1296000000, 1, 54, 1, 1, 1, 0),
73 RK3036_PLL_RATE(1272000000, 1, 53, 1, 1, 1, 0),
74 RK3036_PLL_RATE(1248000000, 1, 52, 1, 1, 1, 0),
75 RK3036_PLL_RATE(1200000000, 1, 50, 1, 1, 1, 0),
76 RK3036_PLL_RATE(1188000000, 2, 99, 1, 1, 1, 0),
77 RK3036_PLL_RATE(1104000000, 1, 46, 1, 1, 1, 0),
78 RK3036_PLL_RATE(1100000000, 12, 550, 1, 1, 1, 0),
79 RK3036_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0),
80 RK3036_PLL_RATE(1000000000, 6, 500, 2, 1, 1, 0),
81 RK3036_PLL_RATE( 984000000, 1, 82, 2, 1, 1, 0),
82 RK3036_PLL_RATE( 960000000, 1, 80, 2, 1, 1, 0),
83 RK3036_PLL_RATE( 936000000, 1, 78, 2, 1, 1, 0),
84 RK3036_PLL_RATE( 912000000, 1, 76, 2, 1, 1, 0),
85 RK3036_PLL_RATE( 900000000, 4, 300, 2, 1, 1, 0),
86 RK3036_PLL_RATE( 888000000, 1, 74, 2, 1, 1, 0),
87 RK3036_PLL_RATE( 864000000, 1, 72, 2, 1, 1, 0),
88 RK3036_PLL_RATE( 840000000, 1, 70, 2, 1, 1, 0),
89 RK3036_PLL_RATE( 816000000, 1, 68, 2, 1, 1, 0),
90 RK3036_PLL_RATE( 800000000, 6, 400, 2, 1, 1, 0),
91 RK3036_PLL_RATE( 700000000, 6, 350, 2, 1, 1, 0),
92 RK3036_PLL_RATE( 696000000, 1, 58, 2, 1, 1, 0),
93 RK3036_PLL_RATE( 676000000, 3, 169, 2, 1, 1, 0),
94 RK3036_PLL_RATE( 600000000, 1, 75, 3, 1, 1, 0),
95 RK3036_PLL_RATE( 594000000, 1, 99, 4, 1, 1, 0),
96 RK3036_PLL_RATE( 504000000, 1, 63, 3, 1, 1, 0),
97 RK3036_PLL_RATE( 500000000, 6, 250, 2, 1, 1, 0),
98 RK3036_PLL_RATE( 408000000, 1, 68, 2, 2, 1, 0),
99 RK3036_PLL_RATE( 312000000, 1, 52, 2, 2, 1, 0),
100 RK3036_PLL_RATE( 297000000, 1, 99, 4, 2, 1, 0),
101 RK3036_PLL_RATE( 216000000, 1, 72, 4, 2, 1, 0),
102 RK3036_PLL_RATE( 148500000, 1, 99, 4, 4, 1, 0),
103 RK3036_PLL_RATE( 96000000, 1, 64, 4, 4, 1, 0),
104 RK3036_PLL_RATE( 74250000, 2, 99, 4, 4, 1, 0),
105 RK3036_PLL_RATE( 54000000, 1, 54, 6, 4, 1, 0),
106 RK3036_PLL_RATE( 27000000, 1, 27, 6, 4, 1, 0),
111 PNAME(mux_pll_p) = { "xin24m", "xin32k" };
113 PNAME(mux_armclkl_p) = { "clk_core_l_lpll_src",
114 "clk_core_l_bpll_src",
115 "clk_core_l_dpll_src",
116 "clk_core_l_gpll_src" };
117 PNAME(mux_armclkb_p) = { "clk_core_b_lpll_src",
118 "clk_core_b_bpll_src",
119 "clk_core_b_dpll_src",
120 "clk_core_b_gpll_src" };
121 PNAME(mux_aclk_cci_p) = { "cpll_aclk_cci_src",
124 "vpll_aclk_cci_src" };
125 PNAME(mux_cci_trace_p) = { "cpll_cci_trace",
127 PNAME(mux_cs_p) = { "cpll_cs", "gpll_cs",
129 PNAME(mux_aclk_perihp_p) = { "cpll_aclk_perihp_src",
130 "gpll_aclk_perihp_src" };
132 PNAME(mux_pll_src_cpll_gpll_p) = { "cpll", "gpll" };
133 PNAME(mux_pll_src_cpll_gpll_npll_p) = { "cpll", "gpll", "npll" };
134 PNAME(mux_pll_src_cpll_gpll_ppll_p) = { "cpll", "gpll", "ppll" };
135 PNAME(mux_pll_src_cpll_gpll_upll_p) = { "cpll", "gpll", "upll" };
136 PNAME(mux_pll_src_npll_cpll_gpll_p) = { "npll", "cpll", "gpll" };
137 PNAME(mux_pll_src_cpll_gpll_npll_ppll_p) = { "cpll", "gpll", "npll",
139 PNAME(mux_pll_src_cpll_gpll_npll_24m_p) = { "cpll", "gpll", "npll",
141 PNAME(mux_pll_src_cpll_gpll_npll_usbphy480m_p) = { "cpll", "gpll", "npll",
143 PNAME(mux_pll_src_ppll_cpll_gpll_npll_p) = { "ppll", "cpll", "gpll",
145 PNAME(mux_pll_src_cpll_gpll_npll_upll_24m_p) = { "cpll", "gpll", "npll",
147 PNAME(mux_pll_src_cpll_gpll_npll_ppll_upll_24m_p) = { "cpll", "gpll", "npll",
148 "ppll", "upll", "xin24m" };
150 PNAME(mux_pll_src_vpll_cpll_gpll_p) = { "vpll", "cpll", "gpll" };
152 * We hope to be able to HDMI/DP can obtain better signal quality,
153 * therefore, we move VOP pwm and aclk clocks to other PLLs, let
154 * HDMI/DP phyclock can monopolize VPLL.
156 PNAME(mux_pll_src_dmyvpll_cpll_gpll_npll_p) = { "dummy_vpll", "cpll", "gpll",
158 PNAME(mux_pll_src_dmyvpll_cpll_gpll_24m_p) = { "dummy_vpll", "cpll", "gpll",
161 PNAME(mux_dclk_vop0_p) = { "dclk_vop0_div",
162 "dummy_dclk_vop0_frac" };
163 PNAME(mux_dclk_vop1_p) = { "dclk_vop1_div",
164 "dummy_dclk_vop1_frac" };
166 PNAME(mux_clk_cif_p) = { "clk_cifout_src", "xin24m" };
168 PNAME(mux_pll_src_24m_usbphy480m_p) = { "xin24m", "clk_usbphy_480m" };
169 PNAME(mux_pll_src_24m_pciephy_p) = { "xin24m", "clk_pciephy_ref100m" };
170 PNAME(mux_pll_src_24m_32k_cpll_gpll_p) = { "xin24m", "xin32k",
172 PNAME(mux_pciecore_cru_phy_p) = { "clk_pcie_core_cru",
173 "clk_pcie_core_phy" };
175 PNAME(mux_aclk_emmc_p) = { "cpll_aclk_emmc_src",
176 "gpll_aclk_emmc_src" };
178 PNAME(mux_aclk_perilp0_p) = { "cpll_aclk_perilp0_src",
179 "gpll_aclk_perilp0_src" };
181 PNAME(mux_fclk_cm0s_p) = { "cpll_fclk_cm0s_src",
182 "gpll_fclk_cm0s_src" };
184 PNAME(mux_hclk_perilp1_p) = { "cpll_hclk_perilp1_src",
185 "gpll_hclk_perilp1_src" };
187 PNAME(mux_clk_testout1_p) = { "clk_testout1_pll_src", "xin24m" };
188 PNAME(mux_clk_testout2_p) = { "clk_testout2_pll_src", "xin24m" };
190 PNAME(mux_usbphy_480m_p) = { "clk_usbphy0_480m_src",
191 "clk_usbphy1_480m_src" };
192 PNAME(mux_aclk_gmac_p) = { "cpll_aclk_gmac_src",
193 "gpll_aclk_gmac_src" };
194 PNAME(mux_rmii_p) = { "clk_gmac", "clkin_gmac" };
195 PNAME(mux_spdif_p) = { "clk_spdif_div", "clk_spdif_frac",
196 "clkin_i2s", "xin12m" };
197 PNAME(mux_i2s0_p) = { "clk_i2s0_div", "clk_i2s0_frac",
198 "clkin_i2s", "xin12m" };
199 PNAME(mux_i2s1_p) = { "clk_i2s1_div", "clk_i2s1_frac",
200 "clkin_i2s", "xin12m" };
201 PNAME(mux_i2s2_p) = { "clk_i2s2_div", "clk_i2s2_frac",
202 "clkin_i2s", "xin12m" };
203 PNAME(mux_i2sch_p) = { "clk_i2s0", "clk_i2s1",
205 PNAME(mux_i2sout_p) = { "clk_i2sout_src", "xin12m" };
207 PNAME(mux_uart0_p) = { "clk_uart0_div", "clk_uart0_frac", "xin24m" };
208 PNAME(mux_uart1_p) = { "clk_uart1_div", "clk_uart1_frac", "xin24m" };
209 PNAME(mux_uart2_p) = { "clk_uart2_div", "clk_uart2_frac", "xin24m" };
210 PNAME(mux_uart3_p) = { "clk_uart3_div", "clk_uart3_frac", "xin24m" };
212 /* PMU CRU parents */
213 PNAME(mux_ppll_24m_p) = { "ppll", "xin24m" };
214 PNAME(mux_24m_ppll_p) = { "xin24m", "ppll" };
215 PNAME(mux_fclk_cm0s_pmu_ppll_p) = { "fclk_cm0s_pmu_ppll_src", "xin24m" };
216 PNAME(mux_wifi_pmu_p) = { "clk_wifi_div", "clk_wifi_frac" };
217 PNAME(mux_uart4_pmu_p) = { "clk_uart4_div", "clk_uart4_frac",
219 PNAME(mux_clk_testout2_2io_p) = { "clk_testout2", "clk_32k_suspend_pmu" };
221 static struct rockchip_pll_clock rk3399_pll_clks[] __initdata = {
222 [lpll] = PLL(pll_rk3399, PLL_APLLL, "lpll", mux_pll_p, 0, RK3399_PLL_CON(0),
223 RK3399_PLL_CON(3), 8, 31, 0, rk3399_pll_rates),
224 [bpll] = PLL(pll_rk3399, PLL_APLLB, "bpll", mux_pll_p, 0, RK3399_PLL_CON(8),
225 RK3399_PLL_CON(11), 8, 31, 0, rk3399_pll_rates),
226 [dpll] = PLL(pll_rk3399, PLL_DPLL, "dpll", mux_pll_p, 0, RK3399_PLL_CON(16),
227 RK3399_PLL_CON(19), 8, 31, 0, NULL),
228 [cpll] = PLL(pll_rk3399, PLL_CPLL, "cpll", mux_pll_p, 0, RK3399_PLL_CON(24),
229 RK3399_PLL_CON(27), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rk3399_pll_rates),
230 [gpll] = PLL(pll_rk3399, PLL_GPLL, "gpll", mux_pll_p, 0, RK3399_PLL_CON(32),
231 RK3399_PLL_CON(35), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rk3399_pll_rates),
232 [npll] = PLL(pll_rk3399, PLL_NPLL, "npll", mux_pll_p, 0, RK3399_PLL_CON(40),
233 RK3399_PLL_CON(43), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rk3399_pll_rates),
234 [vpll] = PLL(pll_rk3399, PLL_VPLL, "vpll", mux_pll_p, 0, RK3399_PLL_CON(48),
235 RK3399_PLL_CON(51), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rk3399_pll_rates),
238 static struct rockchip_pll_clock rk3399_pmu_pll_clks[] __initdata = {
239 [ppll] = PLL(pll_rk3399, PLL_PPLL, "ppll", mux_pll_p, 0, RK3399_PMU_PLL_CON(0),
240 RK3399_PMU_PLL_CON(3), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rk3399_pll_rates),
243 #define MFLAGS CLK_MUX_HIWORD_MASK
244 #define DFLAGS CLK_DIVIDER_HIWORD_MASK
245 #define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)
246 #define IFLAGS ROCKCHIP_INVERTER_HIWORD_MASK
248 static struct rockchip_clk_branch rk3399_spdif_fracmux __initdata =
249 MUX(0, "clk_spdif_mux", mux_spdif_p, CLK_SET_RATE_PARENT,
250 RK3399_CLKSEL_CON(32), 13, 2, MFLAGS);
252 static struct rockchip_clk_branch rk3399_i2s0_fracmux __initdata =
253 MUX(0, "clk_i2s0_mux", mux_i2s0_p, CLK_SET_RATE_PARENT,
254 RK3399_CLKSEL_CON(28), 8, 2, MFLAGS);
256 static struct rockchip_clk_branch rk3399_i2s1_fracmux __initdata =
257 MUX(0, "clk_i2s1_mux", mux_i2s1_p, CLK_SET_RATE_PARENT,
258 RK3399_CLKSEL_CON(29), 8, 2, MFLAGS);
260 static struct rockchip_clk_branch rk3399_i2s2_fracmux __initdata =
261 MUX(0, "clk_i2s2_mux", mux_i2s2_p, CLK_SET_RATE_PARENT,
262 RK3399_CLKSEL_CON(30), 8, 2, MFLAGS);
264 static struct rockchip_clk_branch rk3399_uart0_fracmux __initdata =
265 MUX(SCLK_UART0, "clk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT,
266 RK3399_CLKSEL_CON(33), 8, 2, MFLAGS);
268 static struct rockchip_clk_branch rk3399_uart1_fracmux __initdata =
269 MUX(SCLK_UART1, "clk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT,
270 RK3399_CLKSEL_CON(34), 8, 2, MFLAGS);
272 static struct rockchip_clk_branch rk3399_uart2_fracmux __initdata =
273 MUX(SCLK_UART2, "clk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT,
274 RK3399_CLKSEL_CON(35), 8, 2, MFLAGS);
276 static struct rockchip_clk_branch rk3399_uart3_fracmux __initdata =
277 MUX(SCLK_UART3, "clk_uart3", mux_uart3_p, CLK_SET_RATE_PARENT,
278 RK3399_CLKSEL_CON(36), 8, 2, MFLAGS);
280 static struct rockchip_clk_branch rk3399_uart4_pmu_fracmux __initdata =
281 MUX(SCLK_UART4_PMU, "clk_uart4_pmu", mux_uart4_pmu_p, CLK_SET_RATE_PARENT,
282 RK3399_PMU_CLKSEL_CON(5), 8, 2, MFLAGS);
284 static struct rockchip_clk_branch rk3399_dclk_vop0_fracmux __initdata =
285 MUX(DCLK_VOP0, "dclk_vop0", mux_dclk_vop0_p, CLK_SET_RATE_PARENT | CLK_KEEP_REQ_RATE,
286 RK3399_CLKSEL_CON(49), 11, 1, MFLAGS);
288 static struct rockchip_clk_branch rk3399_dclk_vop1_fracmux __initdata =
289 MUX(DCLK_VOP1, "dclk_vop1", mux_dclk_vop1_p, CLK_SET_RATE_PARENT | CLK_KEEP_REQ_RATE,
290 RK3399_CLKSEL_CON(50), 11, 1, MFLAGS);
292 static struct rockchip_clk_branch rk3399_pmuclk_wifi_fracmux __initdata =
293 MUX(SCLK_WIFI_PMU, "clk_wifi_pmu", mux_wifi_pmu_p, CLK_SET_RATE_PARENT,
294 RK3399_PMU_CLKSEL_CON(1), 14, 1, MFLAGS);
296 static const struct rockchip_cpuclk_reg_data rk3399_cpuclkl_data = {
297 .core_reg = RK3399_CLKSEL_CON(0),
299 .div_core_mask = 0x1f,
303 .mux_core_mask = 0x3,
306 static const struct rockchip_cpuclk_reg_data rk3399_cpuclkb_data = {
307 .core_reg = RK3399_CLKSEL_CON(2),
309 .div_core_mask = 0x1f,
313 .mux_core_mask = 0x3,
316 #define RK3399_DIV_ACLKM_MASK 0x1f
317 #define RK3399_DIV_ACLKM_SHIFT 8
318 #define RK3399_DIV_ATCLK_MASK 0x1f
319 #define RK3399_DIV_ATCLK_SHIFT 0
320 #define RK3399_DIV_PCLK_DBG_MASK 0x1f
321 #define RK3399_DIV_PCLK_DBG_SHIFT 8
323 #define RK3399_CLKSEL0(_offs, _aclkm) \
325 .reg = RK3399_CLKSEL_CON(0 + _offs), \
326 .val = HIWORD_UPDATE(_aclkm, RK3399_DIV_ACLKM_MASK, \
327 RK3399_DIV_ACLKM_SHIFT), \
329 #define RK3399_CLKSEL1(_offs, _atclk, _pdbg) \
331 .reg = RK3399_CLKSEL_CON(1 + _offs), \
332 .val = HIWORD_UPDATE(_atclk, RK3399_DIV_ATCLK_MASK, \
333 RK3399_DIV_ATCLK_SHIFT) | \
334 HIWORD_UPDATE(_pdbg, RK3399_DIV_PCLK_DBG_MASK, \
335 RK3399_DIV_PCLK_DBG_SHIFT), \
338 /* cluster_l: aclkm in clksel0, rest in clksel1 */
339 #define RK3399_CPUCLKL_RATE(_prate, _aclkm, _atclk, _pdbg) \
341 .prate = _prate##U, \
343 RK3399_CLKSEL0(0, _aclkm), \
344 RK3399_CLKSEL1(0, _atclk, _pdbg), \
348 /* cluster_b: aclkm in clksel2, rest in clksel3 */
349 #define RK3399_CPUCLKB_RATE(_prate, _aclkm, _atclk, _pdbg) \
351 .prate = _prate##U, \
353 RK3399_CLKSEL0(2, _aclkm), \
354 RK3399_CLKSEL1(2, _atclk, _pdbg), \
358 static struct rockchip_cpuclk_rate_table rk3399_cpuclkl_rates[] __initdata = {
359 RK3399_CPUCLKL_RATE(1800000000, 1, 8, 8),
360 RK3399_CPUCLKL_RATE(1704000000, 1, 8, 8),
361 RK3399_CPUCLKL_RATE(1608000000, 1, 7, 7),
362 RK3399_CPUCLKL_RATE(1512000000, 1, 7, 7),
363 RK3399_CPUCLKL_RATE(1488000000, 1, 6, 6),
364 RK3399_CPUCLKL_RATE(1416000000, 1, 6, 6),
365 RK3399_CPUCLKL_RATE(1200000000, 1, 5, 5),
366 RK3399_CPUCLKL_RATE(1008000000, 1, 5, 5),
367 RK3399_CPUCLKL_RATE( 816000000, 1, 4, 4),
368 RK3399_CPUCLKL_RATE( 696000000, 1, 3, 3),
369 RK3399_CPUCLKL_RATE( 600000000, 1, 3, 3),
370 RK3399_CPUCLKL_RATE( 408000000, 1, 2, 2),
371 RK3399_CPUCLKL_RATE( 312000000, 1, 1, 1),
372 RK3399_CPUCLKL_RATE( 216000000, 1, 1, 1),
373 RK3399_CPUCLKL_RATE( 96000000, 1, 1, 1),
376 static struct rockchip_cpuclk_rate_table rk3399_cpuclkb_rates[] __initdata = {
377 RK3399_CPUCLKB_RATE(2208000000, 1, 11, 11),
378 RK3399_CPUCLKB_RATE(2184000000, 1, 11, 11),
379 RK3399_CPUCLKB_RATE(2088000000, 1, 10, 10),
380 RK3399_CPUCLKB_RATE(2040000000, 1, 10, 10),
381 RK3399_CPUCLKB_RATE(1992000000, 1, 9, 9),
382 RK3399_CPUCLKB_RATE(1896000000, 1, 9, 9),
383 RK3399_CPUCLKB_RATE(1800000000, 1, 8, 8),
384 RK3399_CPUCLKB_RATE(1704000000, 1, 8, 8),
385 RK3399_CPUCLKB_RATE(1608000000, 1, 7, 7),
386 RK3399_CPUCLKB_RATE(1512000000, 1, 7, 7),
387 RK3399_CPUCLKB_RATE(1488000000, 1, 6, 6),
388 RK3399_CPUCLKB_RATE(1416000000, 1, 6, 6),
389 RK3399_CPUCLKB_RATE(1200000000, 1, 5, 5),
390 RK3399_CPUCLKB_RATE(1008000000, 1, 5, 5),
391 RK3399_CPUCLKB_RATE( 816000000, 1, 4, 4),
392 RK3399_CPUCLKB_RATE( 696000000, 1, 3, 3),
393 RK3399_CPUCLKB_RATE( 600000000, 1, 3, 3),
394 RK3399_CPUCLKB_RATE( 408000000, 1, 2, 2),
395 RK3399_CPUCLKB_RATE( 312000000, 1, 1, 1),
396 RK3399_CPUCLKB_RATE( 216000000, 1, 1, 1),
397 RK3399_CPUCLKB_RATE( 96000000, 1, 1, 1),
400 static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
402 * CRU Clock-Architecture
406 GATE(SCLK_USB2PHY0_REF, "clk_usb2phy0_ref", "xin24m", CLK_IGNORE_UNUSED,
407 RK3399_CLKGATE_CON(6), 5, GFLAGS),
408 GATE(SCLK_USB2PHY1_REF, "clk_usb2phy1_ref", "xin24m", CLK_IGNORE_UNUSED,
409 RK3399_CLKGATE_CON(6), 6, GFLAGS),
411 GATE(0, "clk_usbphy0_480m_src", "clk_usbphy0_480m", CLK_IGNORE_UNUSED,
412 RK3399_CLKGATE_CON(13), 12, GFLAGS),
413 GATE(0, "clk_usbphy1_480m_src", "clk_usbphy1_480m", CLK_IGNORE_UNUSED,
414 RK3399_CLKGATE_CON(13), 12, GFLAGS),
415 MUX(0, "clk_usbphy_480m", mux_usbphy_480m_p, CLK_IGNORE_UNUSED,
416 RK3399_CLKSEL_CON(14), 6, 1, MFLAGS),
418 MUX(0, "upll", mux_pll_src_24m_usbphy480m_p, 0,
419 RK3399_CLKSEL_CON(14), 15, 1, MFLAGS),
421 COMPOSITE_NODIV(SCLK_HSICPHY, "clk_hsicphy", mux_pll_src_cpll_gpll_npll_usbphy480m_p, 0,
422 RK3399_CLKSEL_CON(19), 0, 2, MFLAGS,
423 RK3399_CLKGATE_CON(6), 4, GFLAGS),
425 COMPOSITE(ACLK_USB3, "aclk_usb3", mux_pll_src_cpll_gpll_npll_p, 0,
426 RK3399_CLKSEL_CON(39), 6, 2, MFLAGS, 0, 5, DFLAGS,
427 RK3399_CLKGATE_CON(12), 0, GFLAGS),
428 GATE(ACLK_USB3OTG0, "aclk_usb3otg0", "aclk_usb3", 0,
429 RK3399_CLKGATE_CON(30), 1, GFLAGS),
430 GATE(ACLK_USB3OTG1, "aclk_usb3otg1", "aclk_usb3", 0,
431 RK3399_CLKGATE_CON(30), 2, GFLAGS),
432 GATE(ACLK_USB3_RKSOC_AXI_PERF, "aclk_usb3_rksoc_axi_perf", "aclk_usb3", 0,
433 RK3399_CLKGATE_CON(30), 3, GFLAGS),
435 GATE(SCLK_USB3OTG0_REF, "clk_usb3otg0_ref", "xin24m", 0,
436 RK3399_CLKGATE_CON(12), 1, GFLAGS),
437 GATE(SCLK_USB3OTG1_REF, "clk_usb3otg1_ref", "xin24m", 0,
438 RK3399_CLKGATE_CON(12), 2, GFLAGS),
440 COMPOSITE(SCLK_USB3OTG0_SUSPEND, "clk_usb3otg0_suspend", mux_pll_p, 0,
441 RK3399_CLKSEL_CON(40), 15, 1, MFLAGS, 0, 10, DFLAGS,
442 RK3399_CLKGATE_CON(12), 3, GFLAGS),
444 COMPOSITE(SCLK_USB3OTG1_SUSPEND, "clk_usb3otg1_suspend", mux_pll_p, 0,
445 RK3399_CLKSEL_CON(41), 15, 1, MFLAGS, 0, 10, DFLAGS,
446 RK3399_CLKGATE_CON(12), 4, GFLAGS),
448 COMPOSITE(SCLK_UPHY0_TCPDPHY_REF, "clk_uphy0_tcpdphy_ref", mux_pll_p, 0,
449 RK3399_CLKSEL_CON(64), 15, 1, MFLAGS, 8, 5, DFLAGS,
450 RK3399_CLKGATE_CON(13), 4, GFLAGS),
452 COMPOSITE(SCLK_UPHY0_TCPDCORE, "clk_uphy0_tcpdcore", mux_pll_src_24m_32k_cpll_gpll_p, 0,
453 RK3399_CLKSEL_CON(64), 6, 2, MFLAGS, 0, 5, DFLAGS,
454 RK3399_CLKGATE_CON(13), 5, GFLAGS),
456 COMPOSITE(SCLK_UPHY1_TCPDPHY_REF, "clk_uphy1_tcpdphy_ref", mux_pll_p, 0,
457 RK3399_CLKSEL_CON(65), 15, 1, MFLAGS, 8, 5, DFLAGS,
458 RK3399_CLKGATE_CON(13), 6, GFLAGS),
460 COMPOSITE(SCLK_UPHY1_TCPDCORE, "clk_uphy1_tcpdcore", mux_pll_src_24m_32k_cpll_gpll_p, 0,
461 RK3399_CLKSEL_CON(65), 6, 2, MFLAGS, 0, 5, DFLAGS,
462 RK3399_CLKGATE_CON(13), 7, GFLAGS),
465 GATE(0, "clk_core_l_lpll_src", "lpll", CLK_IGNORE_UNUSED,
466 RK3399_CLKGATE_CON(0), 0, GFLAGS),
467 GATE(0, "clk_core_l_bpll_src", "bpll", CLK_IGNORE_UNUSED,
468 RK3399_CLKGATE_CON(0), 1, GFLAGS),
469 GATE(0, "clk_core_l_dpll_src", "dpll", CLK_IGNORE_UNUSED,
470 RK3399_CLKGATE_CON(0), 2, GFLAGS),
471 GATE(0, "clk_core_l_gpll_src", "gpll", CLK_IGNORE_UNUSED,
472 RK3399_CLKGATE_CON(0), 3, GFLAGS),
474 COMPOSITE_NOMUX(0, "aclkm_core_l", "armclkl", CLK_IGNORE_UNUSED,
475 RK3399_CLKSEL_CON(0), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
476 RK3399_CLKGATE_CON(0), 4, GFLAGS),
477 COMPOSITE_NOMUX(0, "atclk_core_l", "armclkl", CLK_IGNORE_UNUSED,
478 RK3399_CLKSEL_CON(1), 0, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
479 RK3399_CLKGATE_CON(0), 5, GFLAGS),
480 COMPOSITE_NOMUX(0, "pclk_dbg_core_l", "armclkl", CLK_IGNORE_UNUSED,
481 RK3399_CLKSEL_CON(1), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
482 RK3399_CLKGATE_CON(0), 6, GFLAGS),
484 GATE(ACLK_CORE_ADB400_CORE_L_2_CCI500, "aclk_core_adb400_core_l_2_cci500", "aclkm_core_l", CLK_IGNORE_UNUSED,
485 RK3399_CLKGATE_CON(14), 12, GFLAGS),
486 GATE(ACLK_PERF_CORE_L, "aclk_perf_core_l", "aclkm_core_l", CLK_IGNORE_UNUSED,
487 RK3399_CLKGATE_CON(14), 13, GFLAGS),
489 GATE(0, "clk_dbg_pd_core_l", "armclkl", CLK_IGNORE_UNUSED,
490 RK3399_CLKGATE_CON(14), 9, GFLAGS),
491 GATE(ACLK_GIC_ADB400_GIC_2_CORE_L, "aclk_core_adb400_gic_2_core_l", "armclkl", CLK_IGNORE_UNUSED,
492 RK3399_CLKGATE_CON(14), 10, GFLAGS),
493 GATE(ACLK_GIC_ADB400_CORE_L_2_GIC, "aclk_core_adb400_core_l_2_gic", "armclkl", CLK_IGNORE_UNUSED,
494 RK3399_CLKGATE_CON(14), 11, GFLAGS),
495 GATE(SCLK_PVTM_CORE_L, "clk_pvtm_core_l", "xin24m", CLK_IGNORE_UNUSED,
496 RK3399_CLKGATE_CON(0), 7, GFLAGS),
499 GATE(0, "clk_core_b_lpll_src", "lpll", CLK_IGNORE_UNUSED,
500 RK3399_CLKGATE_CON(1), 0, GFLAGS),
501 GATE(0, "clk_core_b_bpll_src", "bpll", CLK_IGNORE_UNUSED,
502 RK3399_CLKGATE_CON(1), 1, GFLAGS),
503 GATE(0, "clk_core_b_dpll_src", "dpll", CLK_IGNORE_UNUSED,
504 RK3399_CLKGATE_CON(1), 2, GFLAGS),
505 GATE(0, "clk_core_b_gpll_src", "gpll", CLK_IGNORE_UNUSED,
506 RK3399_CLKGATE_CON(1), 3, GFLAGS),
508 COMPOSITE_NOMUX(0, "aclkm_core_b", "armclkb", CLK_IGNORE_UNUSED,
509 RK3399_CLKSEL_CON(2), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
510 RK3399_CLKGATE_CON(1), 4, GFLAGS),
511 COMPOSITE_NOMUX(0, "atclk_core_b", "armclkb", CLK_IGNORE_UNUSED,
512 RK3399_CLKSEL_CON(3), 0, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
513 RK3399_CLKGATE_CON(1), 5, GFLAGS),
514 COMPOSITE_NOMUX(0, "pclk_dbg_core_b", "armclkb", CLK_IGNORE_UNUSED,
515 RK3399_CLKSEL_CON(3), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
516 RK3399_CLKGATE_CON(1), 6, GFLAGS),
518 GATE(ACLK_CORE_ADB400_CORE_B_2_CCI500, "aclk_core_adb400_core_b_2_cci500", "aclkm_core_b", CLK_IGNORE_UNUSED,
519 RK3399_CLKGATE_CON(14), 5, GFLAGS),
520 GATE(ACLK_PERF_CORE_B, "aclk_perf_core_b", "aclkm_core_b", CLK_IGNORE_UNUSED,
521 RK3399_CLKGATE_CON(14), 6, GFLAGS),
523 GATE(0, "clk_dbg_pd_core_b", "armclkb", CLK_IGNORE_UNUSED,
524 RK3399_CLKGATE_CON(14), 1, GFLAGS),
525 GATE(ACLK_GIC_ADB400_GIC_2_CORE_B, "aclk_core_adb400_gic_2_core_b", "armclkb", CLK_IGNORE_UNUSED,
526 RK3399_CLKGATE_CON(14), 3, GFLAGS),
527 GATE(ACLK_GIC_ADB400_CORE_B_2_GIC, "aclk_core_adb400_core_b_2_gic", "armclkb", CLK_IGNORE_UNUSED,
528 RK3399_CLKGATE_CON(14), 4, GFLAGS),
530 DIV(0, "pclken_dbg_core_b", "pclk_dbg_core_b", CLK_IGNORE_UNUSED,
531 RK3399_CLKSEL_CON(3), 13, 2, DFLAGS | CLK_DIVIDER_READ_ONLY),
533 GATE(0, "pclk_dbg_cxcs_pd_core_b", "pclk_dbg_core_b", CLK_IGNORE_UNUSED,
534 RK3399_CLKGATE_CON(14), 2, GFLAGS),
536 GATE(SCLK_PVTM_CORE_B, "clk_pvtm_core_b", "xin24m", CLK_IGNORE_UNUSED,
537 RK3399_CLKGATE_CON(1), 7, GFLAGS),
540 GATE(0, "cpll_aclk_gmac_src", "cpll", CLK_IGNORE_UNUSED,
541 RK3399_CLKGATE_CON(6), 9, GFLAGS),
542 GATE(0, "gpll_aclk_gmac_src", "gpll", CLK_IGNORE_UNUSED,
543 RK3399_CLKGATE_CON(6), 8, GFLAGS),
544 COMPOSITE(0, "aclk_gmac_pre", mux_aclk_gmac_p, 0,
545 RK3399_CLKSEL_CON(20), 7, 1, MFLAGS, 0, 5, DFLAGS,
546 RK3399_CLKGATE_CON(6), 10, GFLAGS),
548 GATE(ACLK_GMAC, "aclk_gmac", "aclk_gmac_pre", 0,
549 RK3399_CLKGATE_CON(32), 0, GFLAGS),
550 GATE(ACLK_PERF_GMAC, "aclk_perf_gmac", "aclk_gmac_pre", 0,
551 RK3399_CLKGATE_CON(32), 4, GFLAGS),
553 COMPOSITE_NOMUX(0, "pclk_gmac_pre", "aclk_gmac_pre", 0,
554 RK3399_CLKSEL_CON(19), 8, 3, DFLAGS,
555 RK3399_CLKGATE_CON(6), 11, GFLAGS),
556 GATE(PCLK_GMAC, "pclk_gmac", "pclk_gmac_pre", 0,
557 RK3399_CLKGATE_CON(32), 2, GFLAGS),
559 COMPOSITE(SCLK_MAC, "clk_gmac", mux_pll_src_cpll_gpll_npll_p, 0,
560 RK3399_CLKSEL_CON(20), 14, 2, MFLAGS, 8, 5, DFLAGS,
561 RK3399_CLKGATE_CON(5), 5, GFLAGS),
563 MUX(SCLK_RMII_SRC, "clk_rmii_src", mux_rmii_p, CLK_SET_RATE_PARENT,
564 RK3399_CLKSEL_CON(19), 4, 1, MFLAGS),
565 GATE(SCLK_MACREF_OUT, "clk_mac_refout", "clk_rmii_src", 0,
566 RK3399_CLKGATE_CON(5), 6, GFLAGS),
567 GATE(SCLK_MACREF, "clk_mac_ref", "clk_rmii_src", 0,
568 RK3399_CLKGATE_CON(5), 7, GFLAGS),
569 GATE(SCLK_MAC_RX, "clk_rmii_rx", "clk_rmii_src", 0,
570 RK3399_CLKGATE_CON(5), 8, GFLAGS),
571 GATE(SCLK_MAC_TX, "clk_rmii_tx", "clk_rmii_src", 0,
572 RK3399_CLKGATE_CON(5), 9, GFLAGS),
575 COMPOSITE(0, "clk_spdif_div", mux_pll_src_cpll_gpll_p, 0,
576 RK3399_CLKSEL_CON(32), 7, 1, MFLAGS, 0, 7, DFLAGS,
577 RK3399_CLKGATE_CON(8), 13, GFLAGS),
578 COMPOSITE_FRACMUX(0, "clk_spdif_frac", "clk_spdif_div", CLK_SET_RATE_PARENT,
579 RK3399_CLKSEL_CON(99), 0,
580 RK3399_CLKGATE_CON(8), 14, GFLAGS,
581 &rk3399_spdif_fracmux),
582 GATE(SCLK_SPDIF_8CH, "clk_spdif", "clk_spdif_mux", CLK_SET_RATE_PARENT,
583 RK3399_CLKGATE_CON(8), 15, GFLAGS),
585 COMPOSITE(SCLK_SPDIF_REC_DPTX, "clk_spdif_rec_dptx", mux_pll_src_cpll_gpll_p, 0,
586 RK3399_CLKSEL_CON(32), 15, 1, MFLAGS, 8, 5, DFLAGS,
587 RK3399_CLKGATE_CON(10), 6, GFLAGS),
589 COMPOSITE(0, "clk_i2s0_div", mux_pll_src_cpll_gpll_p, 0,
590 RK3399_CLKSEL_CON(28), 7, 1, MFLAGS, 0, 7, DFLAGS,
591 RK3399_CLKGATE_CON(8), 3, GFLAGS),
592 COMPOSITE_FRACMUX(0, "clk_i2s0_frac", "clk_i2s0_div", CLK_SET_RATE_PARENT,
593 RK3399_CLKSEL_CON(96), 0,
594 RK3399_CLKGATE_CON(8), 4, GFLAGS,
595 &rk3399_i2s0_fracmux),
596 GATE(SCLK_I2S0_8CH, "clk_i2s0", "clk_i2s0_mux", CLK_SET_RATE_PARENT,
597 RK3399_CLKGATE_CON(8), 5, GFLAGS),
599 COMPOSITE(0, "clk_i2s1_div", mux_pll_src_cpll_gpll_p, 0,
600 RK3399_CLKSEL_CON(29), 7, 1, MFLAGS, 0, 7, DFLAGS,
601 RK3399_CLKGATE_CON(8), 6, GFLAGS),
602 COMPOSITE_FRACMUX(0, "clk_i2s1_frac", "clk_i2s1_div", CLK_SET_RATE_PARENT,
603 RK3399_CLKSEL_CON(97), 0,
604 RK3399_CLKGATE_CON(8), 7, GFLAGS,
605 &rk3399_i2s1_fracmux),
606 GATE(SCLK_I2S1_8CH, "clk_i2s1", "clk_i2s1_mux", CLK_SET_RATE_PARENT,
607 RK3399_CLKGATE_CON(8), 8, GFLAGS),
609 COMPOSITE(0, "clk_i2s2_div", mux_pll_src_cpll_gpll_p, 0,
610 RK3399_CLKSEL_CON(30), 7, 1, MFLAGS, 0, 7, DFLAGS,
611 RK3399_CLKGATE_CON(8), 9, GFLAGS),
612 COMPOSITE_FRACMUX(0, "clk_i2s2_frac", "clk_i2s2_div", CLK_SET_RATE_PARENT,
613 RK3399_CLKSEL_CON(98), 0,
614 RK3399_CLKGATE_CON(8), 10, GFLAGS,
615 &rk3399_i2s2_fracmux),
616 GATE(SCLK_I2S2_8CH, "clk_i2s2", "clk_i2s2_mux", CLK_SET_RATE_PARENT,
617 RK3399_CLKGATE_CON(8), 11, GFLAGS),
619 MUX(0, "clk_i2sout_src", mux_i2sch_p, CLK_SET_RATE_PARENT,
620 RK3399_CLKSEL_CON(31), 0, 2, MFLAGS),
621 COMPOSITE_NODIV(SCLK_I2S_8CH_OUT, "clk_i2sout", mux_i2sout_p, CLK_SET_RATE_PARENT,
622 RK3399_CLKSEL_CON(30), 8, 2, MFLAGS,
623 RK3399_CLKGATE_CON(8), 12, GFLAGS),
626 MUX(0, "clk_uart0_src", mux_pll_src_cpll_gpll_upll_p, 0,
627 RK3399_CLKSEL_CON(33), 12, 2, MFLAGS),
628 COMPOSITE_NOMUX(0, "clk_uart0_div", "clk_uart0_src", 0,
629 RK3399_CLKSEL_CON(33), 0, 7, DFLAGS,
630 RK3399_CLKGATE_CON(9), 0, GFLAGS),
631 COMPOSITE_FRACMUX(0, "clk_uart0_frac", "clk_uart0_div", CLK_SET_RATE_PARENT,
632 RK3399_CLKSEL_CON(100), 0,
633 RK3399_CLKGATE_CON(9), 1, GFLAGS,
634 &rk3399_uart0_fracmux),
636 MUX(0, "clk_uart_src", mux_pll_src_cpll_gpll_p, 0,
637 RK3399_CLKSEL_CON(33), 15, 1, MFLAGS),
638 COMPOSITE_NOMUX(0, "clk_uart1_div", "clk_uart_src", 0,
639 RK3399_CLKSEL_CON(34), 0, 7, DFLAGS,
640 RK3399_CLKGATE_CON(9), 2, GFLAGS),
641 COMPOSITE_FRACMUX(0, "clk_uart1_frac", "clk_uart1_div", CLK_SET_RATE_PARENT,
642 RK3399_CLKSEL_CON(101), 0,
643 RK3399_CLKGATE_CON(9), 3, GFLAGS,
644 &rk3399_uart1_fracmux),
646 COMPOSITE_NOMUX(0, "clk_uart2_div", "clk_uart_src", 0,
647 RK3399_CLKSEL_CON(35), 0, 7, DFLAGS,
648 RK3399_CLKGATE_CON(9), 4, GFLAGS),
649 COMPOSITE_FRACMUX(0, "clk_uart2_frac", "clk_uart2_div", CLK_SET_RATE_PARENT,
650 RK3399_CLKSEL_CON(102), 0,
651 RK3399_CLKGATE_CON(9), 5, GFLAGS,
652 &rk3399_uart2_fracmux),
654 COMPOSITE_NOMUX(0, "clk_uart3_div", "clk_uart_src", 0,
655 RK3399_CLKSEL_CON(36), 0, 7, DFLAGS,
656 RK3399_CLKGATE_CON(9), 6, GFLAGS),
657 COMPOSITE_FRACMUX(0, "clk_uart3_frac", "clk_uart3_div", CLK_SET_RATE_PARENT,
658 RK3399_CLKSEL_CON(103), 0,
659 RK3399_CLKGATE_CON(9), 7, GFLAGS,
660 &rk3399_uart3_fracmux),
662 COMPOSITE(0, "pclk_ddr", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED,
663 RK3399_CLKSEL_CON(6), 15, 1, MFLAGS, 8, 5, DFLAGS,
664 RK3399_CLKGATE_CON(3), 4, GFLAGS),
666 GATE(PCLK_DDR_MON, "pclk_ddr_mon", "pclk_ddr", CLK_IGNORE_UNUSED,
667 RK3399_CLKGATE_CON(18), 12, GFLAGS),
668 GATE(PCLK_CIC, "pclk_cic", "pclk_ddr", CLK_IGNORE_UNUSED,
669 RK3399_CLKGATE_CON(18), 15, GFLAGS),
671 GATE(SCLK_PVTM_DDR, "clk_pvtm_ddr", "xin24m", CLK_IGNORE_UNUSED,
672 RK3399_CLKGATE_CON(4), 11, GFLAGS),
673 GATE(SCLK_DFIMON0_TIMER, "clk_dfimon0_timer", "xin24m", CLK_IGNORE_UNUSED,
674 RK3399_CLKGATE_CON(3), 5, GFLAGS),
675 GATE(SCLK_DFIMON1_TIMER, "clk_dfimon1_timer", "xin24m", CLK_IGNORE_UNUSED,
676 RK3399_CLKGATE_CON(3), 6, GFLAGS),
679 GATE(0, "cpll_aclk_cci_src", "cpll", CLK_IGNORE_UNUSED,
680 RK3399_CLKGATE_CON(2), 0, GFLAGS),
681 GATE(0, "gpll_aclk_cci_src", "gpll", CLK_IGNORE_UNUSED,
682 RK3399_CLKGATE_CON(2), 1, GFLAGS),
683 GATE(0, "npll_aclk_cci_src", "npll", CLK_IGNORE_UNUSED,
684 RK3399_CLKGATE_CON(2), 2, GFLAGS),
685 GATE(0, "vpll_aclk_cci_src", "vpll", CLK_IGNORE_UNUSED,
686 RK3399_CLKGATE_CON(2), 3, GFLAGS),
688 COMPOSITE(0, "aclk_cci_pre", mux_aclk_cci_p, CLK_IGNORE_UNUSED,
689 RK3399_CLKSEL_CON(5), 6, 2, MFLAGS, 0, 5, DFLAGS,
690 RK3399_CLKGATE_CON(2), 4, GFLAGS),
692 GATE(ACLK_ADB400M_PD_CORE_L, "aclk_adb400m_pd_core_l", "aclk_cci_pre", CLK_IGNORE_UNUSED,
693 RK3399_CLKGATE_CON(15), 0, GFLAGS),
694 GATE(ACLK_ADB400M_PD_CORE_B, "aclk_adb400m_pd_core_b", "aclk_cci_pre", CLK_IGNORE_UNUSED,
695 RK3399_CLKGATE_CON(15), 1, GFLAGS),
696 GATE(ACLK_CCI, "aclk_cci", "aclk_cci_pre", CLK_IGNORE_UNUSED,
697 RK3399_CLKGATE_CON(15), 2, GFLAGS),
699 GATE(0, "cpll_cci_trace", "cpll", CLK_IGNORE_UNUSED,
700 RK3399_CLKGATE_CON(2), 5, GFLAGS),
701 GATE(0, "gpll_cci_trace", "gpll", CLK_IGNORE_UNUSED,
702 RK3399_CLKGATE_CON(2), 6, GFLAGS),
703 COMPOSITE(SCLK_CCI_TRACE, "clk_cci_trace", mux_cci_trace_p, CLK_IGNORE_UNUSED,
704 RK3399_CLKSEL_CON(5), 15, 2, MFLAGS, 8, 5, DFLAGS,
705 RK3399_CLKGATE_CON(2), 7, GFLAGS),
707 GATE(0, "cpll_cs", "cpll", CLK_IGNORE_UNUSED,
708 RK3399_CLKGATE_CON(2), 8, GFLAGS),
709 GATE(0, "gpll_cs", "gpll", CLK_IGNORE_UNUSED,
710 RK3399_CLKGATE_CON(2), 9, GFLAGS),
711 GATE(0, "npll_cs", "npll", CLK_IGNORE_UNUSED,
712 RK3399_CLKGATE_CON(2), 10, GFLAGS),
713 COMPOSITE_NOGATE(0, "clk_cs", mux_cs_p, CLK_IGNORE_UNUSED,
714 RK3399_CLKSEL_CON(4), 6, 2, MFLAGS, 0, 5, DFLAGS),
715 GATE(0, "clk_dbg_cxcs", "clk_cs", CLK_IGNORE_UNUSED,
716 RK3399_CLKGATE_CON(15), 5, GFLAGS),
719 COMPOSITE(0, "aclk_vcodec_pre", mux_pll_src_cpll_gpll_npll_ppll_p, 0,
720 RK3399_CLKSEL_CON(7), 6, 2, MFLAGS, 0, 5, DFLAGS,
721 RK3399_CLKGATE_CON(4), 0, GFLAGS),
722 COMPOSITE_NOMUX(0, "hclk_vcodec_pre", "aclk_vcodec_pre", 0,
723 RK3399_CLKSEL_CON(7), 8, 5, DFLAGS,
724 RK3399_CLKGATE_CON(4), 1, GFLAGS),
725 GATE(HCLK_VCODEC, "hclk_vcodec", "hclk_vcodec_pre", 0,
726 RK3399_CLKGATE_CON(17), 2, GFLAGS),
728 GATE(ACLK_VCODEC, "aclk_vcodec", "aclk_vcodec_pre", 0,
729 RK3399_CLKGATE_CON(17), 0, GFLAGS),
732 COMPOSITE(SCLK_VDU_CORE, "clk_vdu_core", mux_pll_src_cpll_gpll_npll_p, 0,
733 RK3399_CLKSEL_CON(9), 6, 2, MFLAGS, 0, 5, DFLAGS,
734 RK3399_CLKGATE_CON(4), 4, GFLAGS),
735 COMPOSITE(SCLK_VDU_CA, "clk_vdu_ca", mux_pll_src_cpll_gpll_npll_p, 0,
736 RK3399_CLKSEL_CON(9), 14, 2, MFLAGS, 8, 5, DFLAGS,
737 RK3399_CLKGATE_CON(4), 5, GFLAGS),
739 COMPOSITE(0, "aclk_vdu_pre", mux_pll_src_cpll_gpll_npll_ppll_p, 0,
740 RK3399_CLKSEL_CON(8), 6, 2, MFLAGS, 0, 5, DFLAGS,
741 RK3399_CLKGATE_CON(4), 2, GFLAGS),
742 COMPOSITE_NOMUX(0, "hclk_vdu_pre", "aclk_vdu_pre", 0,
743 RK3399_CLKSEL_CON(8), 8, 5, DFLAGS,
744 RK3399_CLKGATE_CON(4), 3, GFLAGS),
745 GATE(HCLK_VDU, "hclk_vdu", "hclk_vdu_pre", 0,
746 RK3399_CLKGATE_CON(17), 10, GFLAGS),
748 GATE(ACLK_VDU, "aclk_vdu", "aclk_vdu_pre", 0,
749 RK3399_CLKGATE_CON(17), 8, GFLAGS),
752 COMPOSITE(0, "aclk_iep_pre", mux_pll_src_cpll_gpll_npll_ppll_p, 0,
753 RK3399_CLKSEL_CON(10), 6, 2, MFLAGS, 0, 5, DFLAGS,
754 RK3399_CLKGATE_CON(4), 6, GFLAGS),
755 COMPOSITE_NOMUX(0, "hclk_iep_pre", "aclk_iep_pre", 0,
756 RK3399_CLKSEL_CON(10), 8, 5, DFLAGS,
757 RK3399_CLKGATE_CON(4), 7, GFLAGS),
758 GATE(HCLK_IEP, "hclk_iep", "hclk_iep_pre", 0,
759 RK3399_CLKGATE_CON(16), 2, GFLAGS),
761 GATE(ACLK_IEP, "aclk_iep", "aclk_iep_pre", 0,
762 RK3399_CLKGATE_CON(16), 0, GFLAGS),
765 COMPOSITE(SCLK_RGA_CORE, "clk_rga_core", mux_pll_src_cpll_gpll_npll_ppll_p, 0,
766 RK3399_CLKSEL_CON(12), 6, 2, MFLAGS, 0, 5, DFLAGS,
767 RK3399_CLKGATE_CON(4), 10, GFLAGS),
769 COMPOSITE(0, "aclk_rga_pre", mux_pll_src_cpll_gpll_npll_ppll_p, 0,
770 RK3399_CLKSEL_CON(11), 6, 2, MFLAGS, 0, 5, DFLAGS,
771 RK3399_CLKGATE_CON(4), 8, GFLAGS),
772 COMPOSITE_NOMUX(0, "hclk_rga_pre", "aclk_rga_pre", 0,
773 RK3399_CLKSEL_CON(11), 8, 5, DFLAGS,
774 RK3399_CLKGATE_CON(4), 9, GFLAGS),
775 GATE(HCLK_RGA, "hclk_rga", "hclk_rga_pre", 0,
776 RK3399_CLKGATE_CON(16), 10, GFLAGS),
778 GATE(ACLK_RGA, "aclk_rga", "aclk_rga_pre", 0,
779 RK3399_CLKGATE_CON(16), 8, GFLAGS),
782 COMPOSITE(0, "aclk_center", mux_pll_src_cpll_gpll_npll_p, CLK_IGNORE_UNUSED,
783 RK3399_CLKSEL_CON(12), 14, 2, MFLAGS, 8, 5, DFLAGS,
784 RK3399_CLKGATE_CON(3), 7, GFLAGS),
787 COMPOSITE(0, "aclk_gpu_pre", mux_pll_src_ppll_cpll_gpll_npll_p, CLK_IGNORE_UNUSED,
788 RK3399_CLKSEL_CON(13), 5, 3, MFLAGS, 0, 5, DFLAGS,
789 RK3399_CLKGATE_CON(13), 0, GFLAGS),
790 GATE(ACLK_GPU, "aclk_gpu", "aclk_gpu_pre", 0,
791 RK3399_CLKGATE_CON(30), 8, GFLAGS),
792 GATE(ACLK_PERF_GPU, "aclk_perf_gpu", "aclk_gpu_pre", 0,
793 RK3399_CLKGATE_CON(30), 10, GFLAGS),
794 GATE(SCLK_PVTM_GPU, "aclk_pvtm_gpu", "xin24m", 0,
795 RK3399_CLKGATE_CON(13), 1, GFLAGS),
798 GATE(0, "cpll_aclk_perihp_src", "cpll", CLK_IGNORE_UNUSED,
799 RK3399_CLKGATE_CON(5), 0, GFLAGS),
800 GATE(0, "gpll_aclk_perihp_src", "gpll", CLK_IGNORE_UNUSED,
801 RK3399_CLKGATE_CON(5), 1, GFLAGS),
802 COMPOSITE(ACLK_PERIHP, "aclk_perihp", mux_aclk_perihp_p, CLK_IGNORE_UNUSED,
803 RK3399_CLKSEL_CON(14), 7, 1, MFLAGS, 0, 5, DFLAGS,
804 RK3399_CLKGATE_CON(5), 2, GFLAGS),
805 COMPOSITE_NOMUX(HCLK_PERIHP, "hclk_perihp", "aclk_perihp", CLK_IGNORE_UNUSED,
806 RK3399_CLKSEL_CON(14), 8, 2, DFLAGS,
807 RK3399_CLKGATE_CON(5), 3, GFLAGS),
808 COMPOSITE_NOMUX(PCLK_PERIHP, "pclk_perihp", "aclk_perihp", CLK_IGNORE_UNUSED,
809 RK3399_CLKSEL_CON(14), 12, 2, DFLAGS,
810 RK3399_CLKGATE_CON(5), 4, GFLAGS),
812 GATE(ACLK_PERF_PCIE, "aclk_perf_pcie", "aclk_perihp", CLK_IGNORE_UNUSED,
813 RK3399_CLKGATE_CON(20), 2, GFLAGS),
814 GATE(ACLK_PCIE, "aclk_pcie", "aclk_perihp", CLK_IGNORE_UNUSED,
815 RK3399_CLKGATE_CON(20), 10, GFLAGS),
817 GATE(HCLK_HOST0, "hclk_host0", "hclk_perihp", 0,
818 RK3399_CLKGATE_CON(20), 5, GFLAGS),
819 GATE(HCLK_HOST0_ARB, "hclk_host0_arb", "hclk_perihp", 0,
820 RK3399_CLKGATE_CON(20), 6, GFLAGS),
821 GATE(HCLK_HOST1, "hclk_host1", "hclk_perihp", 0,
822 RK3399_CLKGATE_CON(20), 7, GFLAGS),
823 GATE(HCLK_HOST1_ARB, "hclk_host1_arb", "hclk_perihp", 0,
824 RK3399_CLKGATE_CON(20), 8, GFLAGS),
825 GATE(HCLK_HSIC, "hclk_hsic", "hclk_perihp", 0,
826 RK3399_CLKGATE_CON(20), 9, GFLAGS),
827 GATE(0, "hclk_ahb1tom", "hclk_perihp", CLK_IGNORE_UNUSED,
828 RK3399_CLKGATE_CON(20), 15, GFLAGS),
830 GATE(PCLK_PCIE, "pclk_pcie", "pclk_perihp", 0,
831 RK3399_CLKGATE_CON(20), 11, GFLAGS),
832 GATE(PCLK_HSICPHY, "pclk_hsicphy", "pclk_perihp", 0,
833 RK3399_CLKGATE_CON(31), 8, GFLAGS),
836 COMPOSITE(0, "hclk_sd", mux_pll_src_cpll_gpll_p, 0,
837 RK3399_CLKSEL_CON(13), 15, 1, MFLAGS, 8, 5, DFLAGS,
838 RK3399_CLKGATE_CON(12), 13, GFLAGS),
839 GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_sd", 0,
840 RK3399_CLKGATE_CON(33), 8, GFLAGS),
842 COMPOSITE(SCLK_SDIO, "clk_sdio", mux_pll_src_cpll_gpll_npll_ppll_upll_24m_p, 0,
843 RK3399_CLKSEL_CON(15), 8, 3, MFLAGS, 0, 7, DFLAGS,
844 RK3399_CLKGATE_CON(6), 0, GFLAGS),
846 COMPOSITE(SCLK_SDMMC, "clk_sdmmc", mux_pll_src_cpll_gpll_npll_ppll_upll_24m_p, 0,
847 RK3399_CLKSEL_CON(16), 8, 3, MFLAGS, 0, 7, DFLAGS,
848 RK3399_CLKGATE_CON(6), 1, GFLAGS),
850 MMC(SCLK_SDMMC_DRV, "sdmmc_drv", "clk_sdmmc", RK3399_SDMMC_CON0, 1),
851 MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "clk_sdmmc", RK3399_SDMMC_CON1, 1),
853 MMC(SCLK_SDIO_DRV, "sdio_drv", "clk_sdio", RK3399_SDIO_CON0, 1),
854 MMC(SCLK_SDIO_SAMPLE, "sdio_sample", "clk_sdio", RK3399_SDIO_CON1, 1),
857 COMPOSITE(SCLK_PCIE_PM, "clk_pcie_pm", mux_pll_src_cpll_gpll_npll_24m_p, 0,
858 RK3399_CLKSEL_CON(17), 8, 3, MFLAGS, 0, 7, DFLAGS,
859 RK3399_CLKGATE_CON(6), 2, GFLAGS),
861 COMPOSITE_NOMUX(SCLK_PCIEPHY_REF100M, "clk_pciephy_ref100m", "npll", 0,
862 RK3399_CLKSEL_CON(18), 11, 5, DFLAGS,
863 RK3399_CLKGATE_CON(12), 6, GFLAGS),
864 MUX(SCLK_PCIEPHY_REF, "clk_pciephy_ref", mux_pll_src_24m_pciephy_p, CLK_SET_RATE_PARENT,
865 RK3399_CLKSEL_CON(18), 10, 1, MFLAGS),
867 COMPOSITE(0, "clk_pcie_core_cru", mux_pll_src_cpll_gpll_npll_p, 0,
868 RK3399_CLKSEL_CON(18), 8, 2, MFLAGS, 0, 7, DFLAGS,
869 RK3399_CLKGATE_CON(6), 3, GFLAGS),
870 MUX(SCLK_PCIE_CORE, "clk_pcie_core", mux_pciecore_cru_phy_p, CLK_SET_RATE_PARENT,
871 RK3399_CLKSEL_CON(18), 7, 1, MFLAGS),
874 COMPOSITE(SCLK_EMMC, "clk_emmc", mux_pll_src_cpll_gpll_npll_upll_24m_p, 0,
875 RK3399_CLKSEL_CON(22), 8, 3, MFLAGS, 0, 7, DFLAGS,
876 RK3399_CLKGATE_CON(6), 14, GFLAGS),
878 GATE(0, "cpll_aclk_emmc_src", "cpll", CLK_IGNORE_UNUSED,
879 RK3399_CLKGATE_CON(6), 12, GFLAGS),
880 GATE(0, "gpll_aclk_emmc_src", "gpll", CLK_IGNORE_UNUSED,
881 RK3399_CLKGATE_CON(6), 13, GFLAGS),
882 COMPOSITE_NOGATE(ACLK_EMMC, "aclk_emmc", mux_aclk_emmc_p, CLK_IGNORE_UNUSED,
883 RK3399_CLKSEL_CON(21), 7, 1, MFLAGS, 0, 5, DFLAGS),
884 GATE(ACLK_EMMC_CORE, "aclk_emmccore", "aclk_emmc", CLK_IGNORE_UNUSED,
885 RK3399_CLKGATE_CON(32), 8, GFLAGS),
888 GATE(0, "cpll_aclk_perilp0_src", "cpll", CLK_IGNORE_UNUSED,
889 RK3399_CLKGATE_CON(7), 1, GFLAGS),
890 GATE(0, "gpll_aclk_perilp0_src", "gpll", CLK_IGNORE_UNUSED,
891 RK3399_CLKGATE_CON(7), 0, GFLAGS),
892 COMPOSITE(ACLK_PERILP0, "aclk_perilp0", mux_aclk_perilp0_p, CLK_IGNORE_UNUSED,
893 RK3399_CLKSEL_CON(23), 7, 1, MFLAGS, 0, 5, DFLAGS,
894 RK3399_CLKGATE_CON(7), 2, GFLAGS),
895 COMPOSITE_NOMUX(HCLK_PERILP0, "hclk_perilp0", "aclk_perilp0", CLK_IGNORE_UNUSED,
896 RK3399_CLKSEL_CON(23), 8, 2, DFLAGS,
897 RK3399_CLKGATE_CON(7), 3, GFLAGS),
898 COMPOSITE_NOMUX(PCLK_PERILP0, "pclk_perilp0", "aclk_perilp0", 0,
899 RK3399_CLKSEL_CON(23), 12, 3, DFLAGS,
900 RK3399_CLKGATE_CON(7), 4, GFLAGS),
902 /* aclk_perilp0 gates */
903 GATE(ACLK_INTMEM, "aclk_intmem", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 0, GFLAGS),
904 GATE(ACLK_TZMA, "aclk_tzma", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 1, GFLAGS),
905 GATE(SCLK_INTMEM0, "clk_intmem0", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 2, GFLAGS),
906 GATE(SCLK_INTMEM1, "clk_intmem1", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 3, GFLAGS),
907 GATE(SCLK_INTMEM2, "clk_intmem2", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 4, GFLAGS),
908 GATE(SCLK_INTMEM3, "clk_intmem3", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 5, GFLAGS),
909 GATE(SCLK_INTMEM4, "clk_intmem4", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 6, GFLAGS),
910 GATE(SCLK_INTMEM5, "clk_intmem5", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 7, GFLAGS),
911 GATE(ACLK_DCF, "aclk_dcf", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 8, GFLAGS),
912 GATE(ACLK_DMAC0_PERILP, "aclk_dmac0_perilp", "aclk_perilp0", 0, RK3399_CLKGATE_CON(25), 5, GFLAGS),
913 GATE(ACLK_DMAC1_PERILP, "aclk_dmac1_perilp", "aclk_perilp0", 0, RK3399_CLKGATE_CON(25), 6, GFLAGS),
915 /* hclk_perilp0 gates */
916 GATE(HCLK_ROM, "hclk_rom", "hclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(24), 4, GFLAGS),
917 GATE(HCLK_M_CRYPTO0, "hclk_m_crypto0", "hclk_perilp0", 0, RK3399_CLKGATE_CON(24), 5, GFLAGS),
918 GATE(HCLK_S_CRYPTO0, "hclk_s_crypto0", "hclk_perilp0", 0, RK3399_CLKGATE_CON(24), 6, GFLAGS),
919 GATE(HCLK_M_CRYPTO1, "hclk_m_crypto1", "hclk_perilp0", 0, RK3399_CLKGATE_CON(24), 14, GFLAGS),
920 GATE(HCLK_S_CRYPTO1, "hclk_s_crypto1", "hclk_perilp0", 0, RK3399_CLKGATE_CON(24), 15, GFLAGS),
922 /* pclk_perilp0 gates */
923 GATE(PCLK_DCF, "pclk_dcf", "pclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 9, GFLAGS),
926 COMPOSITE(SCLK_CRYPTO0, "clk_crypto0", mux_pll_src_cpll_gpll_ppll_p, 0,
927 RK3399_CLKSEL_CON(24), 6, 2, MFLAGS, 0, 5, DFLAGS,
928 RK3399_CLKGATE_CON(7), 7, GFLAGS),
930 COMPOSITE(SCLK_CRYPTO1, "clk_crypto1", mux_pll_src_cpll_gpll_ppll_p, 0,
931 RK3399_CLKSEL_CON(26), 6, 2, MFLAGS, 0, 5, DFLAGS,
932 RK3399_CLKGATE_CON(7), 8, GFLAGS),
935 GATE(0, "cpll_fclk_cm0s_src", "cpll", 0,
936 RK3399_CLKGATE_CON(7), 6, GFLAGS),
937 GATE(0, "gpll_fclk_cm0s_src", "gpll", 0,
938 RK3399_CLKGATE_CON(7), 5, GFLAGS),
939 COMPOSITE(FCLK_CM0S, "fclk_cm0s", mux_fclk_cm0s_p, 0,
940 RK3399_CLKSEL_CON(24), 15, 1, MFLAGS, 8, 5, DFLAGS,
941 RK3399_CLKGATE_CON(7), 9, GFLAGS),
943 /* fclk_cm0s gates */
944 GATE(SCLK_M0_PERILP, "sclk_m0_perilp", "fclk_cm0s", 0, RK3399_CLKGATE_CON(24), 8, GFLAGS),
945 GATE(HCLK_M0_PERILP, "hclk_m0_perilp", "fclk_cm0s", 0, RK3399_CLKGATE_CON(24), 9, GFLAGS),
946 GATE(DCLK_M0_PERILP, "dclk_m0_perilp", "fclk_cm0s", 0, RK3399_CLKGATE_CON(24), 10, GFLAGS),
947 GATE(SCLK_M0_PERILP_DEC, "clk_m0_perilp_dec", "fclk_cm0s", 0, RK3399_CLKGATE_CON(24), 11, GFLAGS),
950 GATE(0, "cpll_hclk_perilp1_src", "cpll", CLK_IGNORE_UNUSED,
951 RK3399_CLKGATE_CON(8), 1, GFLAGS),
952 GATE(0, "gpll_hclk_perilp1_src", "gpll", CLK_IGNORE_UNUSED,
953 RK3399_CLKGATE_CON(8), 0, GFLAGS),
954 COMPOSITE_NOGATE(HCLK_PERILP1, "hclk_perilp1", mux_hclk_perilp1_p, CLK_IGNORE_UNUSED,
955 RK3399_CLKSEL_CON(25), 7, 1, MFLAGS, 0, 5, DFLAGS),
956 COMPOSITE_NOMUX(PCLK_PERILP1, "pclk_perilp1", "hclk_perilp1", CLK_IGNORE_UNUSED,
957 RK3399_CLKSEL_CON(25), 8, 3, DFLAGS,
958 RK3399_CLKGATE_CON(8), 2, GFLAGS),
960 /* hclk_perilp1 gates */
961 GATE(HCLK_I2S0_8CH, "hclk_i2s0", "hclk_perilp1", 0, RK3399_CLKGATE_CON(34), 0, GFLAGS),
962 GATE(HCLK_I2S1_8CH, "hclk_i2s1", "hclk_perilp1", 0, RK3399_CLKGATE_CON(34), 1, GFLAGS),
963 GATE(HCLK_I2S2_8CH, "hclk_i2s2", "hclk_perilp1", 0, RK3399_CLKGATE_CON(34), 2, GFLAGS),
964 GATE(HCLK_SPDIF, "hclk_spdif", "hclk_perilp1", 0, RK3399_CLKGATE_CON(34), 3, GFLAGS),
965 GATE(HCLK_SDIO, "hclk_sdio", "hclk_perilp1", 0, RK3399_CLKGATE_CON(34), 4, GFLAGS),
966 GATE(PCLK_SPI5, "pclk_spi5", "hclk_perilp1", 0, RK3399_CLKGATE_CON(34), 5, GFLAGS),
968 /* pclk_perilp1 gates */
969 GATE(PCLK_UART0, "pclk_uart0", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 0, GFLAGS),
970 GATE(PCLK_UART1, "pclk_uart1", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 1, GFLAGS),
971 GATE(PCLK_UART2, "pclk_uart2", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 2, GFLAGS),
972 GATE(PCLK_UART3, "pclk_uart3", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 3, GFLAGS),
973 GATE(PCLK_I2C7, "pclk_rki2c7", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 5, GFLAGS),
974 GATE(PCLK_I2C1, "pclk_rki2c1", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 6, GFLAGS),
975 GATE(PCLK_I2C5, "pclk_rki2c5", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 7, GFLAGS),
976 GATE(PCLK_I2C6, "pclk_rki2c6", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 8, GFLAGS),
977 GATE(PCLK_I2C2, "pclk_rki2c2", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 9, GFLAGS),
978 GATE(PCLK_I2C3, "pclk_rki2c3", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 10, GFLAGS),
979 GATE(PCLK_MAILBOX0, "pclk_mailbox0", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 11, GFLAGS),
980 GATE(PCLK_SARADC, "pclk_saradc", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 12, GFLAGS),
981 GATE(PCLK_TSADC, "pclk_tsadc", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 13, GFLAGS),
982 GATE(PCLK_EFUSE1024NS, "pclk_efuse1024ns", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 14, GFLAGS),
983 GATE(PCLK_EFUSE1024S, "pclk_efuse1024s", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 15, GFLAGS),
984 GATE(PCLK_SPI0, "pclk_spi0", "pclk_perilp1", 0, RK3399_CLKGATE_CON(23), 10, GFLAGS),
985 GATE(PCLK_SPI1, "pclk_spi1", "pclk_perilp1", 0, RK3399_CLKGATE_CON(23), 11, GFLAGS),
986 GATE(PCLK_SPI2, "pclk_spi2", "pclk_perilp1", 0, RK3399_CLKGATE_CON(23), 12, GFLAGS),
987 GATE(PCLK_SPI4, "pclk_spi4", "pclk_perilp1", 0, RK3399_CLKGATE_CON(23), 13, GFLAGS),
990 COMPOSITE_NOMUX(SCLK_SARADC, "clk_saradc", "xin24m", 0,
991 RK3399_CLKSEL_CON(26), 8, 8, DFLAGS,
992 RK3399_CLKGATE_CON(9), 11, GFLAGS),
995 COMPOSITE(SCLK_TSADC, "clk_tsadc", mux_pll_p, 0,
996 RK3399_CLKSEL_CON(27), 15, 1, MFLAGS, 0, 10, DFLAGS,
997 RK3399_CLKGATE_CON(9), 10, GFLAGS),
1000 MUX(0, "clk_testout1_pll_src", mux_pll_src_cpll_gpll_npll_p, 0,
1001 RK3399_CLKSEL_CON(38), 6, 2, MFLAGS),
1002 COMPOSITE(0, "clk_testout1", mux_clk_testout1_p, 0,
1003 RK3399_CLKSEL_CON(38), 5, 1, MFLAGS, 0, 5, DFLAGS,
1004 RK3399_CLKGATE_CON(13), 14, GFLAGS),
1006 MUX(0, "clk_testout2_pll_src", mux_pll_src_cpll_gpll_npll_p, 0,
1007 RK3399_CLKSEL_CON(38), 14, 2, MFLAGS),
1008 COMPOSITE(0, "clk_testout2", mux_clk_testout2_p, 0,
1009 RK3399_CLKSEL_CON(38), 13, 1, MFLAGS, 8, 5, DFLAGS,
1010 RK3399_CLKGATE_CON(13), 15, GFLAGS),
1013 COMPOSITE(ACLK_VIO, "aclk_vio", mux_pll_src_cpll_gpll_ppll_p, CLK_IGNORE_UNUSED,
1014 RK3399_CLKSEL_CON(42), 6, 2, MFLAGS, 0, 5, DFLAGS,
1015 RK3399_CLKGATE_CON(11), 10, GFLAGS),
1016 COMPOSITE_NOMUX(PCLK_VIO, "pclk_vio", "aclk_vio", CLK_IGNORE_UNUSED,
1017 RK3399_CLKSEL_CON(43), 0, 5, DFLAGS,
1018 RK3399_CLKGATE_CON(11), 1, GFLAGS),
1020 GATE(PCLK_MIPI_DSI0, "pclk_mipi_dsi0", "pclk_vio", 0,
1021 RK3399_CLKGATE_CON(29), 1, GFLAGS),
1022 GATE(PCLK_MIPI_DSI1, "pclk_mipi_dsi1", "pclk_vio", 0,
1023 RK3399_CLKGATE_CON(29), 2, GFLAGS),
1026 COMPOSITE(ACLK_HDCP, "aclk_hdcp", mux_pll_src_cpll_gpll_ppll_p, 0,
1027 RK3399_CLKSEL_CON(42), 14, 2, MFLAGS, 8, 5, DFLAGS,
1028 RK3399_CLKGATE_CON(11), 12, GFLAGS),
1029 COMPOSITE_NOMUX(HCLK_HDCP, "hclk_hdcp", "aclk_hdcp", 0,
1030 RK3399_CLKSEL_CON(43), 5, 5, DFLAGS,
1031 RK3399_CLKGATE_CON(11), 3, GFLAGS),
1032 COMPOSITE_NOMUX(PCLK_HDCP, "pclk_hdcp", "aclk_hdcp", 0,
1033 RK3399_CLKSEL_CON(43), 10, 5, DFLAGS,
1034 RK3399_CLKGATE_CON(11), 10, GFLAGS),
1036 GATE(ACLK_HDCP22, "aclk_hdcp22", "aclk_hdcp", 0,
1037 RK3399_CLKGATE_CON(29), 10, GFLAGS),
1039 GATE(HCLK_HDCP22, "hclk_hdcp22", "hclk_hdcp", 0,
1040 RK3399_CLKGATE_CON(29), 9, GFLAGS),
1042 GATE(PCLK_HDMI_CTRL, "pclk_hdmi_ctrl", "pclk_hdcp", 0,
1043 RK3399_CLKGATE_CON(29), 6, GFLAGS),
1044 GATE(PCLK_DP_CTRL, "pclk_dp_ctrl", "pclk_hdcp", 0,
1045 RK3399_CLKGATE_CON(29), 7, GFLAGS),
1046 GATE(PCLK_HDCP22, "pclk_hdcp22", "pclk_hdcp", 0,
1047 RK3399_CLKGATE_CON(29), 8, GFLAGS),
1048 GATE(PCLK_GASKET, "pclk_gasket", "pclk_hdcp", 0,
1049 RK3399_CLKGATE_CON(29), 11, GFLAGS),
1052 COMPOSITE(SCLK_DP_CORE, "clk_dp_core", mux_pll_src_npll_cpll_gpll_p, 0,
1053 RK3399_CLKSEL_CON(46), 6, 2, MFLAGS, 0, 5, DFLAGS,
1054 RK3399_CLKGATE_CON(11), 8, GFLAGS),
1056 COMPOSITE(PCLK_EDP, "pclk_edp", mux_pll_src_cpll_gpll_p, 0,
1057 RK3399_CLKSEL_CON(44), 15, 1, MFLAGS, 8, 5, DFLAGS,
1058 RK3399_CLKGATE_CON(11), 11, GFLAGS),
1059 GATE(PCLK_EDP_CTRL, "pclk_edp_ctrl", "pclk_edp", 0,
1060 RK3399_CLKGATE_CON(32), 13, GFLAGS),
1063 GATE(SCLK_HDMI_SFR, "clk_hdmi_sfr", "xin24m", 0,
1064 RK3399_CLKGATE_CON(11), 6, GFLAGS),
1066 COMPOSITE(SCLK_HDMI_CEC, "clk_hdmi_cec", mux_pll_p, 0,
1067 RK3399_CLKSEL_CON(45), 15, 1, MFLAGS, 0, 10, DFLAGS,
1068 RK3399_CLKGATE_CON(11), 7, GFLAGS),
1071 COMPOSITE(ACLK_VOP0_PRE, "aclk_vop0_pre", mux_pll_src_dmyvpll_cpll_gpll_npll_p, 0,
1072 RK3399_CLKSEL_CON(47), 6, 2, MFLAGS, 0, 5, DFLAGS,
1073 RK3399_CLKGATE_CON(10), 8, GFLAGS),
1074 COMPOSITE_NOMUX(0, "hclk_vop0_pre", "aclk_vop0_pre", 0,
1075 RK3399_CLKSEL_CON(47), 8, 5, DFLAGS,
1076 RK3399_CLKGATE_CON(10), 9, GFLAGS),
1078 GATE(ACLK_VOP0, "aclk_vop0", "aclk_vop0_pre", 0,
1079 RK3399_CLKGATE_CON(28), 3, GFLAGS),
1081 GATE(HCLK_VOP0, "hclk_vop0", "hclk_vop0_pre", 0,
1082 RK3399_CLKGATE_CON(28), 2, GFLAGS),
1084 COMPOSITE(DCLK_VOP0_DIV, "dclk_vop0_div", mux_pll_src_vpll_cpll_gpll_p, CLK_SET_RATE_PARENT,
1085 RK3399_CLKSEL_CON(49), 8, 2, MFLAGS, 0, 8, DFLAGS,
1086 RK3399_CLKGATE_CON(10), 12, GFLAGS),
1088 /* The VOP0 is main screen, it is able to re-set parent rate. */
1089 COMPOSITE_FRACMUX_NOGATE(0, "dclk_vop0_frac", "dclk_vop0_div", CLK_SET_RATE_PARENT,
1090 RK3399_CLKSEL_CON(106), 0,
1091 &rk3399_dclk_vop0_fracmux),
1093 COMPOSITE(SCLK_VOP0_PWM, "clk_vop0_pwm", mux_pll_src_dmyvpll_cpll_gpll_24m_p, 0,
1094 RK3399_CLKSEL_CON(51), 6, 2, MFLAGS, 0, 5, DFLAGS,
1095 RK3399_CLKGATE_CON(10), 14, GFLAGS),
1098 COMPOSITE(ACLK_VOP1_PRE, "aclk_vop1_pre", mux_pll_src_dmyvpll_cpll_gpll_npll_p, 0,
1099 RK3399_CLKSEL_CON(48), 6, 2, MFLAGS, 0, 5, DFLAGS,
1100 RK3399_CLKGATE_CON(10), 10, GFLAGS),
1101 COMPOSITE_NOMUX(0, "hclk_vop1_pre", "aclk_vop1_pre", 0,
1102 RK3399_CLKSEL_CON(48), 8, 5, DFLAGS,
1103 RK3399_CLKGATE_CON(10), 11, GFLAGS),
1105 GATE(ACLK_VOP1, "aclk_vop1", "aclk_vop1_pre", 0,
1106 RK3399_CLKGATE_CON(28), 7, GFLAGS),
1108 GATE(HCLK_VOP1, "hclk_vop1", "hclk_vop1_pre", 0,
1109 RK3399_CLKGATE_CON(28), 6, GFLAGS),
1111 /* The VOP1 is sub screen, it is note able to re-set parent rate. */
1112 COMPOSITE(DCLK_VOP1_DIV, "dclk_vop1_div", mux_pll_src_vpll_cpll_gpll_p, 0,
1113 RK3399_CLKSEL_CON(50), 8, 2, MFLAGS, 0, 8, DFLAGS,
1114 RK3399_CLKGATE_CON(10), 13, GFLAGS),
1116 COMPOSITE_FRACMUX_NOGATE(0, "dclk_vop1_frac", "dclk_vop1_div", CLK_SET_RATE_PARENT,
1117 RK3399_CLKSEL_CON(107), 0,
1118 &rk3399_dclk_vop1_fracmux),
1120 COMPOSITE(SCLK_VOP1_PWM, "clk_vop1_pwm", mux_pll_src_dmyvpll_cpll_gpll_24m_p, 0,
1121 RK3399_CLKSEL_CON(52), 6, 2, MFLAGS, 0, 5, DFLAGS,
1122 RK3399_CLKGATE_CON(10), 15, GFLAGS),
1125 COMPOSITE(ACLK_ISP0, "aclk_isp0", mux_pll_src_cpll_gpll_ppll_p, 0,
1126 RK3399_CLKSEL_CON(53), 6, 2, MFLAGS, 0, 5, DFLAGS,
1127 RK3399_CLKGATE_CON(12), 8, GFLAGS),
1128 COMPOSITE_NOMUX(HCLK_ISP0, "hclk_isp0", "aclk_isp0", 0,
1129 RK3399_CLKSEL_CON(53), 8, 5, DFLAGS,
1130 RK3399_CLKGATE_CON(12), 9, GFLAGS),
1132 GATE(ACLK_ISP0_WRAPPER, "aclk_isp0_wrapper", "aclk_isp0", 0,
1133 RK3399_CLKGATE_CON(27), 5, GFLAGS),
1134 GATE(HCLK_ISP1_WRAPPER, "hclk_isp1_wrapper", "aclk_isp0", 0,
1135 RK3399_CLKGATE_CON(27), 7, GFLAGS),
1137 GATE(HCLK_ISP0_WRAPPER, "hclk_isp0_wrapper", "hclk_isp0", 0,
1138 RK3399_CLKGATE_CON(27), 4, GFLAGS),
1140 COMPOSITE(SCLK_ISP0, "clk_isp0", mux_pll_src_cpll_gpll_npll_p, 0,
1141 RK3399_CLKSEL_CON(55), 6, 2, MFLAGS, 0, 5, DFLAGS,
1142 RK3399_CLKGATE_CON(11), 4, GFLAGS),
1144 COMPOSITE(ACLK_ISP1, "aclk_isp1", mux_pll_src_cpll_gpll_ppll_p, 0,
1145 RK3399_CLKSEL_CON(54), 6, 2, MFLAGS, 0, 5, DFLAGS,
1146 RK3399_CLKGATE_CON(12), 10, GFLAGS),
1147 COMPOSITE_NOMUX(HCLK_ISP1, "hclk_isp1", "aclk_isp1", 0,
1148 RK3399_CLKSEL_CON(54), 8, 5, DFLAGS,
1149 RK3399_CLKGATE_CON(12), 11, GFLAGS),
1151 GATE(ACLK_ISP1_WRAPPER, "aclk_isp1_wrapper", "hclk_isp1", 0,
1152 RK3399_CLKGATE_CON(27), 8, GFLAGS),
1154 COMPOSITE(SCLK_ISP1, "clk_isp1", mux_pll_src_cpll_gpll_npll_p, 0,
1155 RK3399_CLKSEL_CON(55), 14, 2, MFLAGS, 8, 5, DFLAGS,
1156 RK3399_CLKGATE_CON(11), 5, GFLAGS),
1159 * We use pclkin_cifinv by default GRF_SOC_CON20[9] (GSC20_9) setting in system,
1160 * so we ignore the mux and make clocks nodes as following,
1162 * pclkin_cifinv --|-------\
1163 * |GSC20_9|-- pclkin_cifmux -- |G27_6| -- pclkin_isp1_wrapper
1164 * pclkin_cif --|-------/
1166 GATE(PCLK_ISP1_WRAPPER, "pclkin_isp1_wrapper", "pclkin_cif", 0,
1167 RK3399_CLKGATE_CON(27), 6, GFLAGS),
1170 COMPOSITE_NODIV(0, "clk_cifout_src", mux_pll_src_cpll_gpll_npll_p, 0,
1171 RK3399_CLKSEL_CON(56), 6, 2, MFLAGS,
1172 RK3399_CLKGATE_CON(10), 7, GFLAGS),
1174 COMPOSITE_NOGATE(SCLK_CIF_OUT, "clk_cifout", mux_clk_cif_p, 0,
1175 RK3399_CLKSEL_CON(56), 5, 1, MFLAGS, 0, 5, DFLAGS),
1178 COMPOSITE(ACLK_GIC_PRE, "aclk_gic_pre", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED,
1179 RK3399_CLKSEL_CON(56), 15, 1, MFLAGS, 8, 5, DFLAGS,
1180 RK3399_CLKGATE_CON(12), 12, GFLAGS),
1182 GATE(ACLK_GIC, "aclk_gic", "aclk_gic_pre", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(33), 0, GFLAGS),
1183 GATE(ACLK_GIC_ADB400_CORE_L_2_GIC, "aclk_gic_adb400_core_l_2_gic", "aclk_gic_pre", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(33), 2, GFLAGS),
1184 GATE(ACLK_GIC_ADB400_CORE_B_2_GIC, "aclk_gic_adb400_core_b_2_gic", "aclk_gic_pre", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(33), 3, GFLAGS),
1185 GATE(ACLK_GIC_ADB400_GIC_2_CORE_L, "aclk_gic_adb400_gic_2_core_l", "aclk_gic_pre", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(33), 4, GFLAGS),
1186 GATE(ACLK_GIC_ADB400_GIC_2_CORE_B, "aclk_gic_adb400_gic_2_core_b", "aclk_gic_pre", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(33), 5, GFLAGS),
1189 /* pclk_alive_gpll_src is controlled by PMUGRF_SOC_CON0[6] */
1190 DIV(PCLK_ALIVE, "pclk_alive", "gpll", 0,
1191 RK3399_CLKSEL_CON(57), 0, 5, DFLAGS),
1193 GATE(PCLK_USBPHY_MUX_G, "pclk_usbphy_mux_g", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 4, GFLAGS),
1194 GATE(PCLK_UPHY0_TCPHY_G, "pclk_uphy0_tcphy_g", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 5, GFLAGS),
1195 GATE(PCLK_UPHY0_TCPD_G, "pclk_uphy0_tcpd_g", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 6, GFLAGS),
1196 GATE(PCLK_UPHY1_TCPHY_G, "pclk_uphy1_tcphy_g", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 8, GFLAGS),
1197 GATE(PCLK_UPHY1_TCPD_G, "pclk_uphy1_tcpd_g", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 9, GFLAGS),
1199 GATE(PCLK_INTR_ARB, "pclk_intr_arb", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(31), 2, GFLAGS),
1200 GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_alive", 0, RK3399_CLKGATE_CON(31), 3, GFLAGS),
1201 GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_alive", 0, RK3399_CLKGATE_CON(31), 4, GFLAGS),
1202 GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_alive", 0, RK3399_CLKGATE_CON(31), 5, GFLAGS),
1203 GATE(PCLK_TIMER0, "pclk_timer0", "pclk_alive", 0, RK3399_CLKGATE_CON(31), 6, GFLAGS),
1204 GATE(PCLK_TIMER1, "pclk_timer1", "pclk_alive", 0, RK3399_CLKGATE_CON(31), 7, GFLAGS),
1205 GATE(PCLK_PMU_INTR_ARB, "pclk_pmu_intr_arb", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(31), 9, GFLAGS),
1207 GATE(SCLK_MIPIDPHY_REF, "clk_mipidphy_ref", "xin24m", 0, RK3399_CLKGATE_CON(11), 14, GFLAGS),
1208 GATE(SCLK_DPHY_PLL, "clk_dphy_pll", "clk_mipidphy_ref", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 0, GFLAGS),
1210 GATE(SCLK_MIPIDPHY_CFG, "clk_mipidphy_cfg", "xin24m", 0, RK3399_CLKGATE_CON(11), 15, GFLAGS),
1211 GATE(SCLK_DPHY_TX0_CFG, "clk_dphy_tx0_cfg", "clk_mipidphy_cfg", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 1, GFLAGS),
1212 GATE(SCLK_DPHY_TX1RX1_CFG, "clk_dphy_tx1rx1_cfg", "clk_mipidphy_cfg", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 2, GFLAGS),
1213 GATE(SCLK_DPHY_RX0_CFG, "clk_dphy_rx0_cfg", "clk_mipidphy_cfg", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 3, GFLAGS),
1216 MUX(0, "clk_test_pre", mux_pll_src_cpll_gpll_p, CLK_SET_RATE_PARENT,
1217 RK3399_CLKSEL_CON(58), 7, 1, MFLAGS),
1218 COMPOSITE_FRAC(0, "clk_test_frac", "clk_test_pre", CLK_SET_RATE_PARENT,
1219 RK3399_CLKSEL_CON(105), 0,
1220 RK3399_CLKGATE_CON(13), 9, GFLAGS),
1222 DIV(0, "clk_test_24m", "xin24m", 0,
1223 RK3399_CLKSEL_CON(57), 6, 10, DFLAGS),
1226 COMPOSITE(SCLK_SPI0, "clk_spi0", mux_pll_src_cpll_gpll_p, 0,
1227 RK3399_CLKSEL_CON(59), 7, 1, MFLAGS, 0, 7, DFLAGS,
1228 RK3399_CLKGATE_CON(9), 12, GFLAGS),
1230 COMPOSITE(SCLK_SPI1, "clk_spi1", mux_pll_src_cpll_gpll_p, 0,
1231 RK3399_CLKSEL_CON(59), 15, 1, MFLAGS, 8, 7, DFLAGS,
1232 RK3399_CLKGATE_CON(9), 13, GFLAGS),
1234 COMPOSITE(SCLK_SPI2, "clk_spi2", mux_pll_src_cpll_gpll_p, 0,
1235 RK3399_CLKSEL_CON(60), 7, 1, MFLAGS, 0, 7, DFLAGS,
1236 RK3399_CLKGATE_CON(9), 14, GFLAGS),
1238 COMPOSITE(SCLK_SPI4, "clk_spi4", mux_pll_src_cpll_gpll_p, 0,
1239 RK3399_CLKSEL_CON(60), 15, 1, MFLAGS, 8, 7, DFLAGS,
1240 RK3399_CLKGATE_CON(9), 15, GFLAGS),
1242 COMPOSITE(SCLK_SPI5, "clk_spi5", mux_pll_src_cpll_gpll_p, 0,
1243 RK3399_CLKSEL_CON(58), 15, 1, MFLAGS, 8, 7, DFLAGS,
1244 RK3399_CLKGATE_CON(13), 13, GFLAGS),
1247 COMPOSITE(SCLK_I2C1, "clk_i2c1", mux_pll_src_cpll_gpll_p, 0,
1248 RK3399_CLKSEL_CON(61), 7, 1, MFLAGS, 0, 7, DFLAGS,
1249 RK3399_CLKGATE_CON(10), 0, GFLAGS),
1251 COMPOSITE(SCLK_I2C2, "clk_i2c2", mux_pll_src_cpll_gpll_p, 0,
1252 RK3399_CLKSEL_CON(62), 7, 1, MFLAGS, 0, 7, DFLAGS,
1253 RK3399_CLKGATE_CON(10), 2, GFLAGS),
1255 COMPOSITE(SCLK_I2C3, "clk_i2c3", mux_pll_src_cpll_gpll_p, 0,
1256 RK3399_CLKSEL_CON(63), 7, 1, MFLAGS, 0, 7, DFLAGS,
1257 RK3399_CLKGATE_CON(10), 4, GFLAGS),
1259 COMPOSITE(SCLK_I2C5, "clk_i2c5", mux_pll_src_cpll_gpll_p, 0,
1260 RK3399_CLKSEL_CON(61), 15, 1, MFLAGS, 8, 7, DFLAGS,
1261 RK3399_CLKGATE_CON(10), 1, GFLAGS),
1263 COMPOSITE(SCLK_I2C6, "clk_i2c6", mux_pll_src_cpll_gpll_p, 0,
1264 RK3399_CLKSEL_CON(62), 15, 1, MFLAGS, 8, 7, DFLAGS,
1265 RK3399_CLKGATE_CON(10), 3, GFLAGS),
1267 COMPOSITE(SCLK_I2C7, "clk_i2c7", mux_pll_src_cpll_gpll_p, 0,
1268 RK3399_CLKSEL_CON(63), 15, 1, MFLAGS, 8, 7, DFLAGS,
1269 RK3399_CLKGATE_CON(10), 5, GFLAGS),
1272 GATE(SCLK_TIMER00, "clk_timer00", "xin24m", 0, RK3399_CLKGATE_CON(26), 0, GFLAGS),
1273 GATE(SCLK_TIMER01, "clk_timer01", "xin24m", 0, RK3399_CLKGATE_CON(26), 1, GFLAGS),
1274 GATE(SCLK_TIMER02, "clk_timer02", "xin24m", 0, RK3399_CLKGATE_CON(26), 2, GFLAGS),
1275 GATE(SCLK_TIMER03, "clk_timer03", "xin24m", 0, RK3399_CLKGATE_CON(26), 3, GFLAGS),
1276 GATE(SCLK_TIMER04, "clk_timer04", "xin24m", 0, RK3399_CLKGATE_CON(26), 4, GFLAGS),
1277 GATE(SCLK_TIMER05, "clk_timer05", "xin24m", 0, RK3399_CLKGATE_CON(26), 5, GFLAGS),
1278 GATE(SCLK_TIMER06, "clk_timer06", "xin24m", 0, RK3399_CLKGATE_CON(26), 6, GFLAGS),
1279 GATE(SCLK_TIMER07, "clk_timer07", "xin24m", 0, RK3399_CLKGATE_CON(26), 7, GFLAGS),
1280 GATE(SCLK_TIMER08, "clk_timer08", "xin24m", 0, RK3399_CLKGATE_CON(26), 8, GFLAGS),
1281 GATE(SCLK_TIMER09, "clk_timer09", "xin24m", 0, RK3399_CLKGATE_CON(26), 9, GFLAGS),
1282 GATE(SCLK_TIMER10, "clk_timer10", "xin24m", 0, RK3399_CLKGATE_CON(26), 10, GFLAGS),
1283 GATE(SCLK_TIMER11, "clk_timer11", "xin24m", 0, RK3399_CLKGATE_CON(26), 11, GFLAGS),
1286 /* clk_test_pre is controlled by CRU_MISC_CON[3] */
1287 COMPOSITE_NOMUX(0, "clk_test", "clk_test_pre", CLK_IGNORE_UNUSED,
1288 RK3368_CLKSEL_CON(58), 0, 5, DFLAGS,
1289 RK3368_CLKGATE_CON(13), 11, GFLAGS),
1292 static struct rockchip_clk_branch rk3399_clk_pmu_branches[] __initdata = {
1294 * PMU CRU Clock-Architecture
1297 GATE(0, "fclk_cm0s_pmu_ppll_src", "ppll", 0,
1298 RK3399_PMU_CLKGATE_CON(0), 1, GFLAGS),
1300 COMPOSITE_NOGATE(FCLK_CM0S_SRC_PMU, "fclk_cm0s_src_pmu", mux_fclk_cm0s_pmu_ppll_p, 0,
1301 RK3399_PMU_CLKSEL_CON(0), 15, 1, MFLAGS, 8, 5, DFLAGS),
1303 COMPOSITE(SCLK_SPI3_PMU, "clk_spi3_pmu", mux_24m_ppll_p, 0,
1304 RK3399_PMU_CLKSEL_CON(1), 7, 1, MFLAGS, 0, 7, DFLAGS,
1305 RK3399_PMU_CLKGATE_CON(0), 2, GFLAGS),
1307 COMPOSITE(0, "clk_wifi_div", mux_ppll_24m_p, CLK_IGNORE_UNUSED,
1308 RK3399_PMU_CLKSEL_CON(1), 13, 1, MFLAGS, 8, 5, DFLAGS,
1309 RK3399_PMU_CLKGATE_CON(0), 8, GFLAGS),
1311 COMPOSITE_FRACMUX_NOGATE(0, "clk_wifi_frac", "clk_wifi_div", CLK_SET_RATE_PARENT,
1312 RK3399_PMU_CLKSEL_CON(7), 0,
1313 &rk3399_pmuclk_wifi_fracmux),
1315 MUX(0, "clk_timer_src_pmu", mux_pll_p, CLK_IGNORE_UNUSED,
1316 RK3399_PMU_CLKSEL_CON(1), 15, 1, MFLAGS),
1318 COMPOSITE_NOMUX(SCLK_I2C0_PMU, "clk_i2c0_pmu", "ppll", 0,
1319 RK3399_PMU_CLKSEL_CON(2), 0, 7, DFLAGS,
1320 RK3399_PMU_CLKGATE_CON(0), 9, GFLAGS),
1322 COMPOSITE_NOMUX(SCLK_I2C4_PMU, "clk_i2c4_pmu", "ppll", 0,
1323 RK3399_PMU_CLKSEL_CON(3), 0, 7, DFLAGS,
1324 RK3399_PMU_CLKGATE_CON(0), 10, GFLAGS),
1326 COMPOSITE_NOMUX(SCLK_I2C8_PMU, "clk_i2c8_pmu", "ppll", 0,
1327 RK3399_PMU_CLKSEL_CON(2), 8, 7, DFLAGS,
1328 RK3399_PMU_CLKGATE_CON(0), 11, GFLAGS),
1330 DIV(0, "clk_32k_suspend_pmu", "xin24m", CLK_IGNORE_UNUSED,
1331 RK3399_PMU_CLKSEL_CON(4), 0, 10, DFLAGS),
1332 MUX(0, "clk_testout_2io", mux_clk_testout2_2io_p, CLK_IGNORE_UNUSED,
1333 RK3399_PMU_CLKSEL_CON(4), 15, 1, MFLAGS),
1335 COMPOSITE(0, "clk_uart4_div", mux_24m_ppll_p, 0,
1336 RK3399_PMU_CLKSEL_CON(5), 10, 1, MFLAGS, 0, 7, DFLAGS,
1337 RK3399_PMU_CLKGATE_CON(0), 5, GFLAGS),
1339 COMPOSITE_FRACMUX(0, "clk_uart4_frac", "clk_uart4_div", CLK_SET_RATE_PARENT,
1340 RK3399_PMU_CLKSEL_CON(6), 0,
1341 RK3399_PMU_CLKGATE_CON(0), 6, GFLAGS,
1342 &rk3399_uart4_pmu_fracmux),
1344 DIV(PCLK_SRC_PMU, "pclk_pmu_src", "ppll", CLK_IGNORE_UNUSED,
1345 RK3399_PMU_CLKSEL_CON(0), 0, 5, DFLAGS),
1347 /* pmu clock gates */
1348 GATE(SCLK_TIMER12_PMU, "clk_timer0_pmu", "clk_timer_src_pmu", 0, RK3399_PMU_CLKGATE_CON(0), 3, GFLAGS),
1349 GATE(SCLK_TIMER13_PMU, "clk_timer1_pmu", "clk_timer_src_pmu", 0, RK3399_PMU_CLKGATE_CON(0), 4, GFLAGS),
1351 GATE(SCLK_PVTM_PMU, "clk_pvtm_pmu", "xin24m", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(0), 7, GFLAGS),
1353 GATE(PCLK_PMU, "pclk_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1), 0, GFLAGS),
1354 GATE(PCLK_INTMEM1_PMU, "pclk_intmem1_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1), 2, GFLAGS),
1355 GATE(PCLK_GPIO0_PMU, "pclk_gpio0_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 3, GFLAGS),
1356 GATE(PCLK_GPIO1_PMU, "pclk_gpio1_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 4, GFLAGS),
1357 GATE(PCLK_I2C0_PMU, "pclk_i2c0_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 7, GFLAGS),
1358 GATE(PCLK_I2C4_PMU, "pclk_i2c4_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 8, GFLAGS),
1359 GATE(PCLK_I2C8_PMU, "pclk_i2c8_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 9, GFLAGS),
1360 GATE(PCLK_RKPWM_PMU, "pclk_rkpwm_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 10, GFLAGS),
1361 GATE(PCLK_SPI3_PMU, "pclk_spi3_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 11, GFLAGS),
1362 GATE(PCLK_TIMER_PMU, "pclk_timer_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 12, GFLAGS),
1363 GATE(PCLK_MAILBOX_PMU, "pclk_mailbox_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 13, GFLAGS),
1364 GATE(PCLK_UART4_PMU, "pclk_uart4_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 14, GFLAGS),
1365 GATE(PCLK_WDT_M0_PMU, "pclk_wdt_m0_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 15, GFLAGS),
1367 GATE(FCLK_CM0S_PMU, "fclk_cm0s_pmu", "fclk_cm0s_src_pmu", 0, RK3399_PMU_CLKGATE_CON(2), 0, GFLAGS),
1368 GATE(SCLK_CM0S_PMU, "sclk_cm0s_pmu", "fclk_cm0s_src_pmu", 0, RK3399_PMU_CLKGATE_CON(2), 1, GFLAGS),
1369 GATE(HCLK_CM0S_PMU, "hclk_cm0s_pmu", "fclk_cm0s_src_pmu", 0, RK3399_PMU_CLKGATE_CON(2), 2, GFLAGS),
1370 GATE(DCLK_CM0S_PMU, "dclk_cm0s_pmu", "fclk_cm0s_src_pmu", 0, RK3399_PMU_CLKGATE_CON(2), 3, GFLAGS),
1373 static const char *const rk3399_cru_critical_clocks[] __initconst = {
1383 "aclk_dmac1_perilp",
1384 "gpll_aclk_perilp0_src",
1385 "gpll_aclk_perihp_src",
1389 static const char *const rk3399_pmucru_critical_clocks[] __initconst = {
1392 "fclk_cm0s_src_pmu",
1393 "clk_timer_src_pmu",
1397 static void __init rk3399_clk_init(struct device_node *np)
1399 struct rockchip_clk_provider *ctx;
1400 void __iomem *reg_base;
1403 reg_base = of_iomap(np, 0);
1405 pr_err("%s: could not map cru region\n", __func__);
1409 ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
1411 pr_err("%s: rockchip clk init failed\n", __func__);
1415 /* Watchdog pclk is controlled by RK3399 SECURE_GRF_SOC_CON3[8]. */
1416 clk = clk_register_fixed_factor(NULL, "pclk_wdt", "pclk_alive", 0, 1, 1);
1418 pr_warn("%s: could not register clock pclk_wdt: %ld\n",
1419 __func__, PTR_ERR(clk));
1421 rockchip_clk_add_lookup(ctx, clk, PCLK_WDT);
1423 rockchip_clk_register_plls(ctx, rk3399_pll_clks,
1424 ARRAY_SIZE(rk3399_pll_clks), -1);
1426 rockchip_clk_register_branches(ctx, rk3399_clk_branches,
1427 ARRAY_SIZE(rk3399_clk_branches));
1429 rockchip_clk_protect_critical(rk3399_cru_critical_clocks,
1430 ARRAY_SIZE(rk3399_cru_critical_clocks));
1432 rockchip_clk_register_armclk(ctx, ARMCLKL, "armclkl",
1433 mux_armclkl_p, ARRAY_SIZE(mux_armclkl_p),
1434 &rk3399_cpuclkl_data, rk3399_cpuclkl_rates,
1435 ARRAY_SIZE(rk3399_cpuclkl_rates));
1437 rockchip_clk_register_armclk(ctx, ARMCLKB, "armclkb",
1438 mux_armclkb_p, ARRAY_SIZE(mux_armclkb_p),
1439 &rk3399_cpuclkb_data, rk3399_cpuclkb_rates,
1440 ARRAY_SIZE(rk3399_cpuclkb_rates));
1442 rockchip_register_softrst(np, 21, reg_base + RK3399_SOFTRST_CON(0),
1443 ROCKCHIP_SOFTRST_HIWORD_MASK);
1445 rockchip_register_restart_notifier(ctx, RK3399_GLB_SRST_FST, NULL);
1447 rockchip_clk_of_add_provider(np, ctx);
1449 CLK_OF_DECLARE(rk3399_cru, "rockchip,rk3399-cru", rk3399_clk_init);
1451 static void __init rk3399_pmu_clk_init(struct device_node *np)
1453 struct rockchip_clk_provider *ctx;
1454 void __iomem *reg_base;
1456 reg_base = of_iomap(np, 0);
1458 pr_err("%s: could not map cru pmu region\n", __func__);
1462 ctx = rockchip_clk_init(np, reg_base, CLKPMU_NR_CLKS);
1464 pr_err("%s: rockchip pmu clk init failed\n", __func__);
1468 rockchip_clk_register_plls(ctx, rk3399_pmu_pll_clks,
1469 ARRAY_SIZE(rk3399_pmu_pll_clks), -1);
1471 rockchip_clk_register_branches(ctx, rk3399_clk_pmu_branches,
1472 ARRAY_SIZE(rk3399_clk_pmu_branches));
1474 rockchip_clk_protect_critical(rk3399_pmucru_critical_clocks,
1475 ARRAY_SIZE(rk3399_pmucru_critical_clocks));
1477 rockchip_register_softrst(np, 2, reg_base + RK3399_PMU_SOFTRST_CON(0),
1478 ROCKCHIP_SOFTRST_HIWORD_MASK);
1480 rockchip_clk_of_add_provider(np, ctx);
1482 CLK_OF_DECLARE(rk3399_cru_pmu, "rockchip,rk3399-pmucru", rk3399_pmu_clk_init);
projects / firefly-linux-kernel-4.4.55.git / blob