2 * Copyright (c) 2016 Rockchip Electronics Co. Ltd.
3 * Author: Xing Zheng <zhengxing@rock-chips.com>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
16 #include <linux/clk-provider.h>
18 #include <linux/of_address.h>
19 #include <linux/platform_device.h>
20 #include <linux/regmap.h>
21 #include <dt-bindings/clock/rk3399-cru.h>
25 lpll, bpll, dpll, cpll, gpll, npll, vpll,
28 enum rk3399_pmu_plls {
32 static struct rockchip_pll_rate_table rk3399_pll_rates[] = {
33 /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
34 RK3036_PLL_RATE(2208000000, 1, 92, 1, 1, 1, 0),
35 RK3036_PLL_RATE(2184000000, 1, 91, 1, 1, 1, 0),
36 RK3036_PLL_RATE(2160000000, 1, 90, 1, 1, 1, 0),
37 RK3036_PLL_RATE(2136000000, 1, 89, 1, 1, 1, 0),
38 RK3036_PLL_RATE(2112000000, 1, 88, 1, 1, 1, 0),
39 RK3036_PLL_RATE(2088000000, 1, 87, 1, 1, 1, 0),
40 RK3036_PLL_RATE(2064000000, 1, 86, 1, 1, 1, 0),
41 RK3036_PLL_RATE(2040000000, 1, 85, 1, 1, 1, 0),
42 RK3036_PLL_RATE(2016000000, 1, 84, 1, 1, 1, 0),
43 RK3036_PLL_RATE(1992000000, 1, 83, 1, 1, 1, 0),
44 RK3036_PLL_RATE(1968000000, 1, 82, 1, 1, 1, 0),
45 RK3036_PLL_RATE(1944000000, 1, 81, 1, 1, 1, 0),
46 RK3036_PLL_RATE(1920000000, 1, 80, 1, 1, 1, 0),
47 RK3036_PLL_RATE(1896000000, 1, 79, 1, 1, 1, 0),
48 RK3036_PLL_RATE(1872000000, 1, 78, 1, 1, 1, 0),
49 RK3036_PLL_RATE(1848000000, 1, 77, 1, 1, 1, 0),
50 RK3036_PLL_RATE(1824000000, 1, 76, 1, 1, 1, 0),
51 RK3036_PLL_RATE(1800000000, 1, 75, 1, 1, 1, 0),
52 RK3036_PLL_RATE(1776000000, 1, 74, 1, 1, 1, 0),
53 RK3036_PLL_RATE(1752000000, 1, 73, 1, 1, 1, 0),
54 RK3036_PLL_RATE(1728000000, 1, 72, 1, 1, 1, 0),
55 RK3036_PLL_RATE(1704000000, 1, 71, 1, 1, 1, 0),
56 RK3036_PLL_RATE(1680000000, 1, 70, 1, 1, 1, 0),
57 RK3036_PLL_RATE(1656000000, 1, 69, 1, 1, 1, 0),
58 RK3036_PLL_RATE(1632000000, 1, 68, 1, 1, 1, 0),
59 RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0),
60 RK3036_PLL_RATE(1584000000, 1, 66, 1, 1, 1, 0),
61 RK3036_PLL_RATE(1560000000, 1, 65, 1, 1, 1, 0),
62 RK3036_PLL_RATE(1536000000, 1, 64, 1, 1, 1, 0),
63 RK3036_PLL_RATE(1512000000, 1, 63, 1, 1, 1, 0),
64 RK3036_PLL_RATE(1488000000, 1, 62, 1, 1, 1, 0),
65 RK3036_PLL_RATE(1464000000, 1, 61, 1, 1, 1, 0),
66 RK3036_PLL_RATE(1440000000, 1, 60, 1, 1, 1, 0),
67 RK3036_PLL_RATE(1416000000, 1, 59, 1, 1, 1, 0),
68 RK3036_PLL_RATE(1392000000, 1, 58, 1, 1, 1, 0),
69 RK3036_PLL_RATE(1368000000, 1, 57, 1, 1, 1, 0),
70 RK3036_PLL_RATE(1344000000, 1, 56, 1, 1, 1, 0),
71 RK3036_PLL_RATE(1320000000, 1, 55, 1, 1, 1, 0),
72 RK3036_PLL_RATE(1296000000, 1, 54, 1, 1, 1, 0),
73 RK3036_PLL_RATE(1272000000, 1, 53, 1, 1, 1, 0),
74 RK3036_PLL_RATE(1248000000, 1, 52, 1, 1, 1, 0),
75 RK3036_PLL_RATE(1200000000, 1, 50, 1, 1, 1, 0),
76 RK3036_PLL_RATE(1188000000, 2, 99, 1, 1, 1, 0),
77 RK3036_PLL_RATE(1104000000, 1, 46, 1, 1, 1, 0),
78 RK3036_PLL_RATE(1100000000, 12, 550, 1, 1, 1, 0),
79 RK3036_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0),
80 RK3036_PLL_RATE(1000000000, 6, 500, 2, 1, 1, 0),
81 RK3036_PLL_RATE( 984000000, 1, 82, 2, 1, 1, 0),
82 RK3036_PLL_RATE( 960000000, 1, 80, 2, 1, 1, 0),
83 RK3036_PLL_RATE( 936000000, 1, 78, 2, 1, 1, 0),
84 RK3036_PLL_RATE( 912000000, 1, 76, 2, 1, 1, 0),
85 RK3036_PLL_RATE( 900000000, 4, 300, 2, 1, 1, 0),
86 RK3036_PLL_RATE( 888000000, 1, 74, 2, 1, 1, 0),
87 RK3036_PLL_RATE( 864000000, 1, 72, 2, 1, 1, 0),
88 RK3036_PLL_RATE( 840000000, 1, 70, 2, 1, 1, 0),
89 RK3036_PLL_RATE( 816000000, 1, 68, 2, 1, 1, 0),
90 RK3036_PLL_RATE( 800000000, 6, 400, 2, 1, 1, 0),
91 RK3036_PLL_RATE( 700000000, 6, 350, 2, 1, 1, 0),
92 RK3036_PLL_RATE( 696000000, 1, 58, 2, 1, 1, 0),
93 RK3036_PLL_RATE( 676000000, 3, 169, 2, 1, 1, 0),
94 RK3036_PLL_RATE( 600000000, 1, 75, 3, 1, 1, 0),
95 RK3036_PLL_RATE( 594000000, 1, 99, 4, 1, 1, 0),
96 RK3036_PLL_RATE( 504000000, 1, 63, 3, 1, 1, 0),
97 RK3036_PLL_RATE( 500000000, 6, 250, 2, 1, 1, 0),
98 RK3036_PLL_RATE( 408000000, 1, 68, 2, 2, 1, 0),
99 RK3036_PLL_RATE( 312000000, 1, 52, 2, 2, 1, 0),
100 RK3036_PLL_RATE( 297000000, 1, 99, 4, 2, 1, 0),
101 RK3036_PLL_RATE( 216000000, 1, 72, 4, 2, 1, 0),
102 RK3036_PLL_RATE( 148500000, 1, 99, 4, 4, 1, 0),
103 RK3036_PLL_RATE( 96000000, 1, 64, 4, 4, 1, 0),
104 RK3036_PLL_RATE( 74250000, 2, 99, 4, 4, 1, 0),
105 RK3036_PLL_RATE( 54000000, 1, 54, 6, 4, 1, 0),
106 RK3036_PLL_RATE( 27000000, 1, 27, 6, 4, 1, 0),
111 PNAME(mux_pll_p) = { "xin24m", "xin32k" };
113 PNAME(mux_armclkl_p) = { "clk_core_l_lpll_src",
114 "clk_core_l_bpll_src",
115 "clk_core_l_dpll_src",
116 "clk_core_l_gpll_src" };
117 PNAME(mux_armclkb_p) = { "clk_core_b_lpll_src",
118 "clk_core_b_bpll_src",
119 "clk_core_b_dpll_src",
120 "clk_core_b_gpll_src" };
121 PNAME(mux_aclk_cci_p) = { "cpll_aclk_cci_src",
124 "vpll_aclk_cci_src" };
125 PNAME(mux_cci_trace_p) = { "cpll_cci_trace", "gpll_cci_trace" };
126 PNAME(mux_cs_p) = { "cpll_cs", "gpll_cs", "npll_cs"};
127 PNAME(mux_aclk_perihp_p) = { "cpll_aclk_perihp_src", "gpll_aclk_perihp_src" };
129 PNAME(mux_pll_src_cpll_gpll_p) = { "cpll", "gpll" };
130 PNAME(mux_pll_src_cpll_gpll_npll_p) = { "cpll", "gpll", "npll" };
131 PNAME(mux_pll_src_cpll_gpll_ppll_p) = { "cpll", "gpll", "ppll" };
132 PNAME(mux_pll_src_cpll_gpll_upll_p) = { "cpll", "gpll", "upll" };
133 PNAME(mux_pll_src_npll_cpll_gpll_p) = { "npll", "cpll", "gpll" };
134 PNAME(mux_pll_src_cpll_gpll_npll_ppll_p) = { "cpll", "gpll", "npll", "ppll" };
135 PNAME(mux_pll_src_cpll_gpll_npll_24m_p) = { "cpll", "gpll", "npll", "xin24m" };
136 PNAME(mux_pll_src_cpll_gpll_npll_usbphy480m_p) = { "cpll", "gpll", "npll", "clk_usbphy_480m" };
137 PNAME(mux_pll_src_ppll_cpll_gpll_npll_p) = { "ppll", "cpll", "gpll", "npll", "upll" };
138 PNAME(mux_pll_src_cpll_gpll_npll_upll_24m_p) = { "cpll", "gpll", "npll", "upll", "xin24m" };
139 PNAME(mux_pll_src_cpll_gpll_npll_ppll_upll_24m_p) = { "cpll", "gpll", "npll", "ppll", "upll", "xin24m" };
141 PNAME(mux_pll_src_vpll_cpll_gpll_p) = { "vpll", "cpll", "gpll" };
143 * We hope to be able to HDMI/DP can obtain better signal quality,
144 * therefore, we move VOP pwm and aclk clocks to other PLLs, let
145 * HDMI/DP phyclock can monopolize VPLL.
147 PNAME(mux_pll_src_dmyvpll_cpll_gpll_npll_p) = { "dummy_vpll", "cpll", "gpll", "npll" };
148 PNAME(mux_pll_src_dmyvpll_cpll_gpll_24m_p) = { "dummy_vpll", "cpll", "gpll", "xin24m" };
150 PNAME(mux_dclk_vop0_p) = { "dclk_vop0_div", "dummy_dclk_vop0_frac" };
151 PNAME(mux_dclk_vop1_p) = { "dclk_vop1_div", "dummy_dclk_vop1_frac" };
153 PNAME(mux_clk_cif_p) = { "clk_cifout_src", "xin24m" };
155 PNAME(mux_pll_src_24m_usbphy480m_p) = { "xin24m", "clk_usbphy_480m" };
156 PNAME(mux_pll_src_24m_pciephy_p) = { "xin24m", "clk_pciephy_ref100m" };
157 PNAME(mux_pll_src_24m_32k_cpll_gpll_p) = { "xin24m", "xin32k", "cpll", "gpll" };
158 PNAME(mux_pciecore_cru_phy_p) = { "clk_pcie_core_cru", "clk_pcie_core_phy" };
160 PNAME(mux_aclk_emmc_p) = { "cpll_aclk_emmc_src", "gpll_aclk_emmc_src" };
162 PNAME(mux_aclk_perilp0_p) = { "cpll_aclk_perilp0_src", "gpll_aclk_perilp0_src" };
164 PNAME(mux_fclk_cm0s_p) = { "cpll_fclk_cm0s_src", "gpll_fclk_cm0s_src" };
166 PNAME(mux_hclk_perilp1_p) = { "cpll_hclk_perilp1_src", "gpll_hclk_perilp1_src" };
168 PNAME(mux_clk_testout1_p) = { "clk_testout1_pll_src", "xin24m" };
169 PNAME(mux_clk_testout2_p) = { "clk_testout2_pll_src", "xin24m" };
171 PNAME(mux_usbphy_480m_p) = { "clk_usbphy0_480m_src", "clk_usbphy1_480m_src" };
172 PNAME(mux_aclk_gmac_p) = { "cpll_aclk_gmac_src", "gpll_aclk_gmac_src" };
173 PNAME(mux_rmii_p) = { "clk_gmac", "clkin_gmac" };
174 PNAME(mux_spdif_p) = { "clk_spdif_div", "clk_spdif_frac",
175 "clkin_i2s", "xin12m" };
176 PNAME(mux_i2s0_p) = { "clk_i2s0_div", "clk_i2s0_frac",
177 "clkin_i2s", "xin12m" };
178 PNAME(mux_i2s1_p) = { "clk_i2s1_div", "clk_i2s1_frac",
179 "clkin_i2s", "xin12m" };
180 PNAME(mux_i2s2_p) = { "clk_i2s2_div", "clk_i2s2_frac",
181 "clkin_i2s", "xin12m" };
182 PNAME(mux_i2sch_p) = { "clk_i2s0", "clk_i2s1", "clk_i2s2" };
183 PNAME(mux_i2sout_p) = { "clk_i2sout_src", "xin12m" };
185 PNAME(mux_uart0_p) = { "clk_uart0_div", "clk_uart0_frac", "xin24m" };
186 PNAME(mux_uart1_p) = { "clk_uart1_div", "clk_uart1_frac", "xin24m" };
187 PNAME(mux_uart2_p) = { "clk_uart2_div", "clk_uart2_frac", "xin24m" };
188 PNAME(mux_uart3_p) = { "clk_uart3_div", "clk_uart3_frac", "xin24m" };
190 /* PMU CRU parents */
191 PNAME(mux_ppll_24m_p) = { "ppll", "xin24m" };
192 PNAME(mux_24m_ppll_p) = { "xin24m", "ppll" };
193 PNAME(mux_fclk_cm0s_pmu_ppll_p) = { "fclk_cm0s_pmu_ppll_src", "xin24m" };
194 PNAME(mux_wifi_pmu_p) = { "clk_wifi_div", "clk_wifi_frac" };
195 PNAME(mux_uart4_pmu_p) = { "clk_uart4_div", "clk_uart4_frac", "xin24m" };
196 PNAME(mux_clk_testout2_2io_p) = { "clk_testout2", "clk_32k_suspend_pmu" };
198 static struct rockchip_pll_clock rk3399_pll_clks[] __initdata = {
199 [lpll] = PLL(pll_rk3399, PLL_APLLL, "lpll", mux_pll_p, 0, RK3399_PLL_CON(0),
200 RK3399_PLL_CON(3), 8, 31, 0, rk3399_pll_rates),
201 [bpll] = PLL(pll_rk3399, PLL_APLLB, "bpll", mux_pll_p, 0, RK3399_PLL_CON(8),
202 RK3399_PLL_CON(11), 8, 31, 0, rk3399_pll_rates),
203 [dpll] = PLL(pll_rk3399, PLL_DPLL, "dpll", mux_pll_p, 0, RK3399_PLL_CON(16),
204 RK3399_PLL_CON(19), 8, 31, 0, NULL),
205 [cpll] = PLL(pll_rk3399, PLL_CPLL, "cpll", mux_pll_p, 0, RK3399_PLL_CON(24),
206 RK3399_PLL_CON(27), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rk3399_pll_rates),
207 [gpll] = PLL(pll_rk3399, PLL_GPLL, "gpll", mux_pll_p, 0, RK3399_PLL_CON(32),
208 RK3399_PLL_CON(35), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rk3399_pll_rates),
209 [npll] = PLL(pll_rk3399, PLL_NPLL, "npll", mux_pll_p, 0, RK3399_PLL_CON(40),
210 RK3399_PLL_CON(43), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rk3399_pll_rates),
211 [vpll] = PLL(pll_rk3399, PLL_VPLL, "vpll", mux_pll_p, 0, RK3399_PLL_CON(48),
212 RK3399_PLL_CON(51), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rk3399_pll_rates),
215 static struct rockchip_pll_clock rk3399_pmu_pll_clks[] __initdata = {
216 [ppll] = PLL(pll_rk3399, PLL_PPLL, "ppll", mux_pll_p, 0, RK3399_PMU_PLL_CON(0),
217 RK3399_PMU_PLL_CON(3), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rk3399_pll_rates),
220 #define MFLAGS CLK_MUX_HIWORD_MASK
221 #define DFLAGS CLK_DIVIDER_HIWORD_MASK
222 #define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)
223 #define IFLAGS ROCKCHIP_INVERTER_HIWORD_MASK
225 static struct rockchip_clk_branch rk3399_spdif_fracmux __initdata =
226 MUX(0, "clk_spdif_mux", mux_spdif_p, CLK_SET_RATE_PARENT,
227 RK3399_CLKSEL_CON(32), 13, 2, MFLAGS);
229 static struct rockchip_clk_branch rk3399_i2s0_fracmux __initdata =
230 MUX(0, "clk_i2s0_mux", mux_i2s0_p, CLK_SET_RATE_PARENT,
231 RK3399_CLKSEL_CON(28), 8, 2, MFLAGS);
233 static struct rockchip_clk_branch rk3399_i2s1_fracmux __initdata =
234 MUX(0, "clk_i2s1_mux", mux_i2s1_p, CLK_SET_RATE_PARENT,
235 RK3399_CLKSEL_CON(29), 8, 2, MFLAGS);
237 static struct rockchip_clk_branch rk3399_i2s2_fracmux __initdata =
238 MUX(0, "clk_i2s2_mux", mux_i2s2_p, CLK_SET_RATE_PARENT,
239 RK3399_CLKSEL_CON(30), 8, 2, MFLAGS);
241 static struct rockchip_clk_branch rk3399_uart0_fracmux __initdata =
242 MUX(SCLK_UART0, "clk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT,
243 RK3399_CLKSEL_CON(33), 8, 2, MFLAGS);
245 static struct rockchip_clk_branch rk3399_uart1_fracmux __initdata =
246 MUX(SCLK_UART1, "clk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT,
247 RK3399_CLKSEL_CON(34), 8, 2, MFLAGS);
249 static struct rockchip_clk_branch rk3399_uart2_fracmux __initdata =
250 MUX(SCLK_UART2, "clk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT,
251 RK3399_CLKSEL_CON(35), 8, 2, MFLAGS);
253 static struct rockchip_clk_branch rk3399_uart3_fracmux __initdata =
254 MUX(SCLK_UART3, "clk_uart3", mux_uart3_p, CLK_SET_RATE_PARENT,
255 RK3399_CLKSEL_CON(36), 8, 2, MFLAGS);
257 static struct rockchip_clk_branch rk3399_uart4_pmu_fracmux __initdata =
258 MUX(SCLK_UART4_PMU, "clk_uart4_pmu", mux_uart4_pmu_p, CLK_SET_RATE_PARENT,
259 RK3399_PMU_CLKSEL_CON(5), 8, 2, MFLAGS);
261 static struct rockchip_clk_branch rk3399_dclk_vop0_fracmux __initdata =
262 MUX(DCLK_VOP0, "dclk_vop0", mux_dclk_vop0_p, CLK_SET_RATE_PARENT,
263 RK3399_CLKSEL_CON(49), 11, 1, MFLAGS);
265 static struct rockchip_clk_branch rk3399_dclk_vop1_fracmux __initdata =
266 MUX(DCLK_VOP1, "dclk_vop1", mux_dclk_vop1_p, CLK_SET_RATE_PARENT,
267 RK3399_CLKSEL_CON(50), 11, 1, MFLAGS);
269 static struct rockchip_clk_branch rk3399_pmuclk_wifi_fracmux __initdata =
270 MUX(SCLK_WIFI_PMU, "clk_wifi_pmu", mux_wifi_pmu_p, CLK_SET_RATE_PARENT,
271 RK3399_PMU_CLKSEL_CON(1), 14, 1, MFLAGS);
273 static const struct rockchip_cpuclk_reg_data rk3399_cpuclkl_data = {
274 .core_reg = RK3399_CLKSEL_CON(0),
276 .div_core_mask = 0x1f,
280 .mux_core_mask = 0x3,
283 static const struct rockchip_cpuclk_reg_data rk3399_cpuclkb_data = {
284 .core_reg = RK3399_CLKSEL_CON(2),
286 .div_core_mask = 0x1f,
290 .mux_core_mask = 0x3,
293 #define RK3399_DIV_ACLKM_MASK 0x1f
294 #define RK3399_DIV_ACLKM_SHIFT 8
295 #define RK3399_DIV_ATCLK_MASK 0x1f
296 #define RK3399_DIV_ATCLK_SHIFT 0
297 #define RK3399_DIV_PCLK_DBG_MASK 0x1f
298 #define RK3399_DIV_PCLK_DBG_SHIFT 8
300 #define RK3399_CLKSEL0(_offs, _aclkm) \
302 .reg = RK3399_CLKSEL_CON(0 + _offs), \
303 .val = HIWORD_UPDATE(_aclkm, RK3399_DIV_ACLKM_MASK, \
304 RK3399_DIV_ACLKM_SHIFT), \
306 #define RK3399_CLKSEL1(_offs, _atclk, _pdbg) \
308 .reg = RK3399_CLKSEL_CON(1 + _offs), \
309 .val = HIWORD_UPDATE(_atclk, RK3399_DIV_ATCLK_MASK, \
310 RK3399_DIV_ATCLK_SHIFT) | \
311 HIWORD_UPDATE(_pdbg, RK3399_DIV_PCLK_DBG_MASK, \
312 RK3399_DIV_PCLK_DBG_SHIFT), \
315 /* cluster_l: aclkm in clksel0, rest in clksel1 */
316 #define RK3399_CPUCLKL_RATE(_prate, _aclkm, _atclk, _pdbg) \
318 .prate = _prate##U, \
320 RK3399_CLKSEL0(0, _aclkm), \
321 RK3399_CLKSEL1(0, _atclk, _pdbg), \
325 /* cluster_b: aclkm in clksel2, rest in clksel3 */
326 #define RK3399_CPUCLKB_RATE(_prate, _aclkm, _atclk, _pdbg) \
328 .prate = _prate##U, \
330 RK3399_CLKSEL0(2, _aclkm), \
331 RK3399_CLKSEL1(2, _atclk, _pdbg), \
335 static struct rockchip_cpuclk_rate_table rk3399_cpuclkl_rates[] __initdata = {
336 RK3399_CPUCLKL_RATE(1800000000, 1, 8, 8),
337 RK3399_CPUCLKL_RATE(1704000000, 1, 8, 8),
338 RK3399_CPUCLKL_RATE(1608000000, 1, 7, 7),
339 RK3399_CPUCLKL_RATE(1512000000, 1, 7, 7),
340 RK3399_CPUCLKL_RATE(1488000000, 1, 6, 6),
341 RK3399_CPUCLKL_RATE(1416000000, 1, 6, 6),
342 RK3399_CPUCLKL_RATE(1200000000, 1, 5, 5),
343 RK3399_CPUCLKL_RATE(1008000000, 1, 5, 5),
344 RK3399_CPUCLKL_RATE( 816000000, 1, 4, 4),
345 RK3399_CPUCLKL_RATE( 696000000, 1, 3, 3),
346 RK3399_CPUCLKL_RATE( 600000000, 1, 3, 3),
347 RK3399_CPUCLKL_RATE( 408000000, 1, 2, 2),
348 RK3399_CPUCLKL_RATE( 312000000, 1, 1, 1),
351 static struct rockchip_cpuclk_rate_table rk3399_cpuclkb_rates[] __initdata = {
352 RK3399_CPUCLKB_RATE(2208000000, 1, 11, 11),
353 RK3399_CPUCLKB_RATE(2184000000, 1, 11, 11),
354 RK3399_CPUCLKB_RATE(2088000000, 1, 10, 10),
355 RK3399_CPUCLKB_RATE(2040000000, 1, 10, 10),
356 RK3399_CPUCLKB_RATE(1992000000, 1, 9, 9),
357 RK3399_CPUCLKB_RATE(1896000000, 1, 9, 9),
358 RK3399_CPUCLKB_RATE(1800000000, 1, 8, 8),
359 RK3399_CPUCLKB_RATE(1704000000, 1, 8, 8),
360 RK3399_CPUCLKB_RATE(1608000000, 1, 7, 7),
361 RK3399_CPUCLKB_RATE(1512000000, 1, 7, 7),
362 RK3399_CPUCLKB_RATE(1488000000, 1, 6, 6),
363 RK3399_CPUCLKB_RATE(1416000000, 1, 6, 6),
364 RK3399_CPUCLKB_RATE(1200000000, 1, 5, 5),
365 RK3399_CPUCLKB_RATE(1008000000, 1, 5, 5),
366 RK3399_CPUCLKB_RATE( 816000000, 1, 4, 4),
367 RK3399_CPUCLKB_RATE( 696000000, 1, 3, 3),
368 RK3399_CPUCLKB_RATE( 600000000, 1, 3, 3),
369 RK3399_CPUCLKB_RATE( 408000000, 1, 2, 2),
370 RK3399_CPUCLKB_RATE( 312000000, 1, 1, 1),
373 static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
375 * CRU Clock-Architecture
379 GATE(SCLK_USB2PHY0_REF, "clk_usb2phy0_ref", "xin24m", CLK_IGNORE_UNUSED,
380 RK3399_CLKGATE_CON(6), 5, GFLAGS),
381 GATE(SCLK_USB2PHY1_REF, "clk_usb2phy1_ref", "xin24m", CLK_IGNORE_UNUSED,
382 RK3399_CLKGATE_CON(6), 6, GFLAGS),
384 GATE(0, "clk_usbphy0_480m_src", "clk_usbphy0_480m", CLK_IGNORE_UNUSED,
385 RK3399_CLKGATE_CON(13), 12, GFLAGS),
386 GATE(0, "clk_usbphy1_480m_src", "clk_usbphy1_480m", CLK_IGNORE_UNUSED,
387 RK3399_CLKGATE_CON(13), 12, GFLAGS),
388 MUX(0, "clk_usbphy_480m", mux_usbphy_480m_p, CLK_IGNORE_UNUSED,
389 RK3399_CLKSEL_CON(14), 6, 1, MFLAGS),
391 MUX(0, "upll", mux_pll_src_24m_usbphy480m_p, 0,
392 RK3399_CLKSEL_CON(14), 15, 1, MFLAGS),
394 COMPOSITE_NODIV(SCLK_HSICPHY, "clk_hsicphy", mux_pll_src_cpll_gpll_npll_usbphy480m_p, 0,
395 RK3399_CLKSEL_CON(19), 0, 2, MFLAGS,
396 RK3399_CLKGATE_CON(6), 4, GFLAGS),
398 COMPOSITE(ACLK_USB3, "aclk_usb3", mux_pll_src_cpll_gpll_npll_p, 0,
399 RK3399_CLKSEL_CON(39), 6, 2, MFLAGS, 0, 5, DFLAGS,
400 RK3399_CLKGATE_CON(12), 0, GFLAGS),
401 GATE(ACLK_USB3_NOC, "aclk_usb3_noc", "aclk_usb3", CLK_IGNORE_UNUSED,
402 RK3399_CLKGATE_CON(30), 0, GFLAGS),
403 GATE(ACLK_USB3OTG0, "aclk_usb3otg0", "aclk_usb3", 0,
404 RK3399_CLKGATE_CON(30), 1, GFLAGS),
405 GATE(ACLK_USB3OTG1, "aclk_usb3otg1", "aclk_usb3", 0,
406 RK3399_CLKGATE_CON(30), 2, GFLAGS),
407 GATE(ACLK_USB3_RKSOC_AXI_PERF, "aclk_usb3_rksoc_axi_perf", "aclk_usb3", 0,
408 RK3399_CLKGATE_CON(30), 3, GFLAGS),
409 GATE(ACLK_USB3_GRF, "aclk_usb3_grf", "aclk_usb3", 0,
410 RK3399_CLKGATE_CON(30), 4, GFLAGS),
412 GATE(SCLK_USB3OTG0_REF, "clk_usb3otg0_ref", "xin24m", 0,
413 RK3399_CLKGATE_CON(12), 1, GFLAGS),
414 GATE(SCLK_USB3OTG1_REF, "clk_usb3otg1_ref", "xin24m", 0,
415 RK3399_CLKGATE_CON(12), 2, GFLAGS),
417 COMPOSITE(SCLK_USB3OTG0_SUSPEND, "clk_usb3otg0_suspend", mux_pll_p, 0,
418 RK3399_CLKSEL_CON(40), 15, 1, MFLAGS, 0, 10, DFLAGS,
419 RK3399_CLKGATE_CON(12), 3, GFLAGS),
421 COMPOSITE(SCLK_USB3OTG1_SUSPEND, "clk_usb3otg1_suspend", mux_pll_p, 0,
422 RK3399_CLKSEL_CON(41), 15, 1, MFLAGS, 0, 10, DFLAGS,
423 RK3399_CLKGATE_CON(12), 4, GFLAGS),
425 COMPOSITE(SCLK_UPHY0_TCPDPHY_REF, "clk_uphy0_tcpdphy_ref", mux_pll_p, 0,
426 RK3399_CLKSEL_CON(64), 15, 1, MFLAGS, 8, 5, DFLAGS,
427 RK3399_CLKGATE_CON(13), 4, GFLAGS),
429 COMPOSITE(SCLK_UPHY0_TCPDCORE, "clk_uphy0_tcpdcore", mux_pll_src_24m_32k_cpll_gpll_p, 0,
430 RK3399_CLKSEL_CON(64), 6, 2, MFLAGS, 0, 5, DFLAGS,
431 RK3399_CLKGATE_CON(13), 5, GFLAGS),
433 COMPOSITE(SCLK_UPHY1_TCPDPHY_REF, "clk_uphy1_tcpdphy_ref", mux_pll_p, 0,
434 RK3399_CLKSEL_CON(65), 15, 1, MFLAGS, 8, 5, DFLAGS,
435 RK3399_CLKGATE_CON(13), 6, GFLAGS),
437 COMPOSITE(SCLK_UPHY1_TCPDCORE, "clk_uphy1_tcpdcore", mux_pll_src_24m_32k_cpll_gpll_p, 0,
438 RK3399_CLKSEL_CON(65), 6, 2, MFLAGS, 0, 5, DFLAGS,
439 RK3399_CLKGATE_CON(13), 7, GFLAGS),
442 GATE(0, "clk_core_l_lpll_src", "lpll", CLK_IGNORE_UNUSED,
443 RK3399_CLKGATE_CON(0), 0, GFLAGS),
444 GATE(0, "clk_core_l_bpll_src", "bpll", CLK_IGNORE_UNUSED,
445 RK3399_CLKGATE_CON(0), 1, GFLAGS),
446 GATE(0, "clk_core_l_dpll_src", "dpll", CLK_IGNORE_UNUSED,
447 RK3399_CLKGATE_CON(0), 2, GFLAGS),
448 GATE(0, "clk_core_l_gpll_src", "gpll", CLK_IGNORE_UNUSED,
449 RK3399_CLKGATE_CON(0), 3, GFLAGS),
451 COMPOSITE_NOMUX(0, "aclkm_core_l", "armclkl", CLK_IGNORE_UNUSED,
452 RK3399_CLKSEL_CON(0), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
453 RK3399_CLKGATE_CON(0), 4, GFLAGS),
454 COMPOSITE_NOMUX(0, "atclk_core_l", "armclkl", CLK_IGNORE_UNUSED,
455 RK3399_CLKSEL_CON(1), 0, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
456 RK3399_CLKGATE_CON(0), 5, GFLAGS),
457 COMPOSITE_NOMUX(0, "pclk_dbg_core_l", "armclkl", CLK_IGNORE_UNUSED,
458 RK3399_CLKSEL_CON(1), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
459 RK3399_CLKGATE_CON(0), 6, GFLAGS),
461 GATE(ACLK_CORE_ADB400_CORE_L_2_CCI500, "aclk_core_adb400_core_l_2_cci500", "aclkm_core_l", CLK_IGNORE_UNUSED,
462 RK3399_CLKGATE_CON(14), 12, GFLAGS),
463 GATE(ACLK_PERF_CORE_L, "aclk_perf_core_l", "aclkm_core_l", CLK_IGNORE_UNUSED,
464 RK3399_CLKGATE_CON(14), 13, GFLAGS),
466 GATE(0, "clk_dbg_pd_core_l", "armclkl", CLK_IGNORE_UNUSED,
467 RK3399_CLKGATE_CON(14), 9, GFLAGS),
468 GATE(ACLK_GIC_ADB400_GIC_2_CORE_L, "aclk_core_adb400_gic_2_core_l", "armclkl", CLK_IGNORE_UNUSED,
469 RK3399_CLKGATE_CON(14), 10, GFLAGS),
470 GATE(ACLK_GIC_ADB400_CORE_L_2_GIC, "aclk_core_adb400_core_l_2_gic", "armclkl", CLK_IGNORE_UNUSED,
471 RK3399_CLKGATE_CON(14), 11, GFLAGS),
472 GATE(SCLK_PVTM_CORE_L, "clk_pvtm_core_l", "xin24m", CLK_IGNORE_UNUSED,
473 RK3399_CLKGATE_CON(0), 7, GFLAGS),
476 GATE(0, "clk_core_b_lpll_src", "lpll", CLK_IGNORE_UNUSED,
477 RK3399_CLKGATE_CON(1), 0, GFLAGS),
478 GATE(0, "clk_core_b_bpll_src", "bpll", CLK_IGNORE_UNUSED,
479 RK3399_CLKGATE_CON(1), 1, GFLAGS),
480 GATE(0, "clk_core_b_dpll_src", "dpll", CLK_IGNORE_UNUSED,
481 RK3399_CLKGATE_CON(1), 2, GFLAGS),
482 GATE(0, "clk_core_b_gpll_src", "gpll", CLK_IGNORE_UNUSED,
483 RK3399_CLKGATE_CON(1), 3, GFLAGS),
485 COMPOSITE_NOMUX(0, "aclkm_core_b", "armclkb", CLK_IGNORE_UNUSED,
486 RK3399_CLKSEL_CON(2), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
487 RK3399_CLKGATE_CON(1), 4, GFLAGS),
488 COMPOSITE_NOMUX(0, "atclk_core_b", "armclkb", CLK_IGNORE_UNUSED,
489 RK3399_CLKSEL_CON(3), 0, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
490 RK3399_CLKGATE_CON(1), 5, GFLAGS),
491 COMPOSITE_NOMUX(0, "pclk_dbg_core_b", "armclkb", CLK_IGNORE_UNUSED,
492 RK3399_CLKSEL_CON(3), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
493 RK3399_CLKGATE_CON(1), 6, GFLAGS),
495 GATE(ACLK_CORE_ADB400_CORE_B_2_CCI500, "aclk_core_adb400_core_b_2_cci500", "aclkm_core_b", CLK_IGNORE_UNUSED,
496 RK3399_CLKGATE_CON(14), 5, GFLAGS),
497 GATE(ACLK_PERF_CORE_B, "aclk_perf_core_b", "aclkm_core_b", CLK_IGNORE_UNUSED,
498 RK3399_CLKGATE_CON(14), 6, GFLAGS),
500 GATE(0, "clk_dbg_pd_core_b", "armclkb", CLK_IGNORE_UNUSED,
501 RK3399_CLKGATE_CON(14), 1, GFLAGS),
502 GATE(ACLK_GIC_ADB400_GIC_2_CORE_B, "aclk_core_adb400_gic_2_core_b", "armclkb", CLK_IGNORE_UNUSED,
503 RK3399_CLKGATE_CON(14), 3, GFLAGS),
504 GATE(ACLK_GIC_ADB400_CORE_B_2_GIC, "aclk_core_adb400_core_b_2_gic", "armclkb", CLK_IGNORE_UNUSED,
505 RK3399_CLKGATE_CON(14), 4, GFLAGS),
507 DIV(0, "pclken_dbg_core_b", "pclk_dbg_core_b", CLK_IGNORE_UNUSED,
508 RK3399_CLKSEL_CON(3), 13, 2, DFLAGS | CLK_DIVIDER_READ_ONLY),
510 GATE(0, "pclk_dbg_cxcs_pd_core_b", "pclk_dbg_core_b", CLK_IGNORE_UNUSED,
511 RK3399_CLKGATE_CON(14), 2, GFLAGS),
513 GATE(SCLK_PVTM_CORE_B, "clk_pvtm_core_b", "xin24m", CLK_IGNORE_UNUSED,
514 RK3399_CLKGATE_CON(1), 7, GFLAGS),
517 GATE(0, "cpll_aclk_gmac_src", "cpll", CLK_IGNORE_UNUSED,
518 RK3399_CLKGATE_CON(6), 9, GFLAGS),
519 GATE(0, "gpll_aclk_gmac_src", "gpll", CLK_IGNORE_UNUSED,
520 RK3399_CLKGATE_CON(6), 8, GFLAGS),
521 COMPOSITE(0, "aclk_gmac_pre", mux_aclk_gmac_p, 0,
522 RK3399_CLKSEL_CON(20), 7, 1, MFLAGS, 0, 5, DFLAGS,
523 RK3399_CLKGATE_CON(6), 10, GFLAGS),
525 GATE(ACLK_GMAC, "aclk_gmac", "aclk_gmac_pre", 0,
526 RK3399_CLKGATE_CON(32), 0, GFLAGS),
527 GATE(ACLK_GMAC_NOC, "aclk_gmac_noc", "aclk_gmac_pre", CLK_IGNORE_UNUSED,
528 RK3399_CLKGATE_CON(32), 1, GFLAGS),
529 GATE(ACLK_PERF_GMAC, "aclk_perf_gmac", "aclk_gmac_pre", 0,
530 RK3399_CLKGATE_CON(32), 4, GFLAGS),
532 COMPOSITE_NOMUX(0, "pclk_gmac_pre", "aclk_gmac_pre", 0,
533 RK3399_CLKSEL_CON(19), 8, 3, DFLAGS,
534 RK3399_CLKGATE_CON(6), 11, GFLAGS),
535 GATE(PCLK_GMAC, "pclk_gmac", "pclk_gmac_pre", 0,
536 RK3399_CLKGATE_CON(32), 2, GFLAGS),
537 GATE(PCLK_GMAC_NOC, "pclk_gmac_noc", "pclk_gmac_pre", CLK_IGNORE_UNUSED,
538 RK3399_CLKGATE_CON(32), 3, GFLAGS),
540 COMPOSITE(SCLK_MAC, "clk_gmac", mux_pll_src_cpll_gpll_npll_p, 0,
541 RK3399_CLKSEL_CON(20), 14, 2, MFLAGS, 8, 5, DFLAGS,
542 RK3399_CLKGATE_CON(5), 5, GFLAGS),
544 MUX(SCLK_RMII_SRC, "clk_rmii_src", mux_rmii_p, CLK_SET_RATE_PARENT,
545 RK3399_CLKSEL_CON(19), 4, 1, MFLAGS),
546 GATE(SCLK_MACREF_OUT, "clk_mac_refout", "clk_rmii_src", 0,
547 RK3399_CLKGATE_CON(5), 6, GFLAGS),
548 GATE(SCLK_MACREF, "clk_mac_ref", "clk_rmii_src", 0,
549 RK3399_CLKGATE_CON(5), 7, GFLAGS),
550 GATE(SCLK_MAC_RX, "clk_rmii_rx", "clk_rmii_src", 0,
551 RK3399_CLKGATE_CON(5), 8, GFLAGS),
552 GATE(SCLK_MAC_TX, "clk_rmii_tx", "clk_rmii_src", 0,
553 RK3399_CLKGATE_CON(5), 9, GFLAGS),
556 COMPOSITE(0, "clk_spdif_div", mux_pll_src_cpll_gpll_p, 0,
557 RK3399_CLKSEL_CON(32), 7, 1, MFLAGS, 0, 7, DFLAGS,
558 RK3399_CLKGATE_CON(8), 13, GFLAGS),
559 COMPOSITE_FRACMUX(0, "clk_spdif_frac", "clk_spdif_div", CLK_SET_RATE_PARENT,
560 RK3399_CLKSEL_CON(99), 0,
561 RK3399_CLKGATE_CON(8), 14, GFLAGS,
562 &rk3399_spdif_fracmux),
563 GATE(SCLK_SPDIF_8CH, "clk_spdif", "clk_spdif_mux", CLK_SET_RATE_PARENT,
564 RK3399_CLKGATE_CON(8), 15, GFLAGS),
566 COMPOSITE(SCLK_SPDIF_REC_DPTX, "clk_spdif_rec_dptx", mux_pll_src_cpll_gpll_p, 0,
567 RK3399_CLKSEL_CON(32), 15, 1, MFLAGS, 0, 5, DFLAGS,
568 RK3399_CLKGATE_CON(10), 6, GFLAGS),
570 COMPOSITE(0, "clk_i2s0_div", mux_pll_src_cpll_gpll_p, 0,
571 RK3399_CLKSEL_CON(28), 7, 1, MFLAGS, 0, 7, DFLAGS,
572 RK3399_CLKGATE_CON(8), 3, GFLAGS),
573 COMPOSITE_FRACMUX(0, "clk_i2s0_frac", "clk_i2s0_div", CLK_SET_RATE_PARENT,
574 RK3399_CLKSEL_CON(96), 0,
575 RK3399_CLKGATE_CON(8), 4, GFLAGS,
576 &rk3399_i2s0_fracmux),
577 GATE(SCLK_I2S0_8CH, "clk_i2s0", "clk_i2s0_mux", CLK_SET_RATE_PARENT,
578 RK3399_CLKGATE_CON(8), 5, GFLAGS),
580 COMPOSITE(0, "clk_i2s1_div", mux_pll_src_cpll_gpll_p, 0,
581 RK3399_CLKSEL_CON(29), 7, 1, MFLAGS, 0, 7, DFLAGS,
582 RK3399_CLKGATE_CON(8), 6, GFLAGS),
583 COMPOSITE_FRACMUX(0, "clk_i2s1_frac", "clk_i2s1_div", CLK_SET_RATE_PARENT,
584 RK3399_CLKSEL_CON(97), 0,
585 RK3399_CLKGATE_CON(8), 7, GFLAGS,
586 &rk3399_i2s1_fracmux),
587 GATE(SCLK_I2S1_8CH, "clk_i2s1", "clk_i2s1_mux", CLK_SET_RATE_PARENT,
588 RK3399_CLKGATE_CON(8), 8, GFLAGS),
590 COMPOSITE(0, "clk_i2s2_div", mux_pll_src_cpll_gpll_p, 0,
591 RK3399_CLKSEL_CON(30), 7, 1, MFLAGS, 0, 7, DFLAGS,
592 RK3399_CLKGATE_CON(8), 9, GFLAGS),
593 COMPOSITE_FRACMUX(0, "clk_i2s2_frac", "clk_i2s2_div", CLK_SET_RATE_PARENT,
594 RK3399_CLKSEL_CON(98), 0,
595 RK3399_CLKGATE_CON(8), 10, GFLAGS,
596 &rk3399_i2s2_fracmux),
597 GATE(SCLK_I2S2_8CH, "clk_i2s2", "clk_i2s2_mux", CLK_SET_RATE_PARENT,
598 RK3399_CLKGATE_CON(8), 11, GFLAGS),
600 MUX(0, "clk_i2sout_src", mux_i2sch_p, CLK_SET_RATE_PARENT,
601 RK3399_CLKSEL_CON(31), 0, 2, MFLAGS),
602 COMPOSITE_NODIV(SCLK_I2S_8CH_OUT, "clk_i2sout", mux_i2sout_p, CLK_SET_RATE_PARENT,
603 RK3399_CLKSEL_CON(30), 8, 2, MFLAGS,
604 RK3399_CLKGATE_CON(8), 12, GFLAGS),
607 MUX(0, "clk_uart0_src", mux_pll_src_cpll_gpll_upll_p, 0,
608 RK3399_CLKSEL_CON(33), 12, 2, MFLAGS),
609 COMPOSITE_NOMUX(0, "clk_uart0_div", "clk_uart0_src", 0,
610 RK3399_CLKSEL_CON(33), 0, 7, DFLAGS,
611 RK3399_CLKGATE_CON(9), 0, GFLAGS),
612 COMPOSITE_FRACMUX(0, "clk_uart0_frac", "clk_uart0_div", CLK_SET_RATE_PARENT,
613 RK3399_CLKSEL_CON(100), 0,
614 RK3399_CLKGATE_CON(9), 1, GFLAGS,
615 &rk3399_uart0_fracmux),
617 MUX(0, "clk_uart_src", mux_pll_src_cpll_gpll_p, 0,
618 RK3399_CLKSEL_CON(33), 15, 1, MFLAGS),
619 COMPOSITE_NOMUX(0, "clk_uart1_div", "clk_uart_src", 0,
620 RK3399_CLKSEL_CON(34), 0, 7, DFLAGS,
621 RK3399_CLKGATE_CON(9), 2, GFLAGS),
622 COMPOSITE_FRACMUX(0, "clk_uart1_frac", "clk_uart1_div", CLK_SET_RATE_PARENT,
623 RK3399_CLKSEL_CON(101), 0,
624 RK3399_CLKGATE_CON(9), 3, GFLAGS,
625 &rk3399_uart1_fracmux),
627 COMPOSITE_NOMUX(0, "clk_uart2_div", "clk_uart_src", 0,
628 RK3399_CLKSEL_CON(35), 0, 7, DFLAGS,
629 RK3399_CLKGATE_CON(9), 4, GFLAGS),
630 COMPOSITE_FRACMUX(0, "clk_uart2_frac", "clk_uart2_div", CLK_SET_RATE_PARENT,
631 RK3399_CLKSEL_CON(102), 0,
632 RK3399_CLKGATE_CON(9), 5, GFLAGS,
633 &rk3399_uart2_fracmux),
635 COMPOSITE_NOMUX(0, "clk_uart3_div", "clk_uart_src", 0,
636 RK3399_CLKSEL_CON(36), 0, 7, DFLAGS,
637 RK3399_CLKGATE_CON(9), 6, GFLAGS),
638 COMPOSITE_FRACMUX(0, "clk_uart3_frac", "clk_uart3_div", CLK_SET_RATE_PARENT,
639 RK3399_CLKSEL_CON(103), 0,
640 RK3399_CLKGATE_CON(9), 7, GFLAGS,
641 &rk3399_uart3_fracmux),
643 COMPOSITE(0, "pclk_ddr", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED,
644 RK3399_CLKSEL_CON(6), 15, 1, MFLAGS, 8, 5, DFLAGS,
645 RK3399_CLKGATE_CON(3), 4, GFLAGS),
647 GATE(PCLK_CENTER_MAIN_NOC, "pclk_center_main_noc", "pclk_ddr", CLK_IGNORE_UNUSED,
648 RK3399_CLKGATE_CON(18), 10, GFLAGS),
649 GATE(PCLK_DDR_MON, "pclk_ddr_mon", "pclk_ddr", CLK_IGNORE_UNUSED,
650 RK3399_CLKGATE_CON(18), 12, GFLAGS),
651 GATE(PCLK_CIC, "pclk_cic", "pclk_ddr", CLK_IGNORE_UNUSED,
652 RK3399_CLKGATE_CON(18), 15, GFLAGS),
653 GATE(PCLK_DDR_SGRF, "pclk_ddr_sgrf", "pclk_ddr", CLK_IGNORE_UNUSED,
654 RK3399_CLKGATE_CON(19), 2, GFLAGS),
656 GATE(SCLK_PVTM_DDR, "clk_pvtm_ddr", "xin24m", CLK_IGNORE_UNUSED,
657 RK3399_CLKGATE_CON(4), 11, GFLAGS),
658 GATE(SCLK_DFIMON0_TIMER, "clk_dfimon0_timer", "xin24m", CLK_IGNORE_UNUSED,
659 RK3399_CLKGATE_CON(3), 5, GFLAGS),
660 GATE(SCLK_DFIMON1_TIMER, "clk_dfimon1_timer", "xin24m", CLK_IGNORE_UNUSED,
661 RK3399_CLKGATE_CON(3), 6, GFLAGS),
664 GATE(0, "cpll_aclk_cci_src", "cpll", CLK_IGNORE_UNUSED,
665 RK3399_CLKGATE_CON(2), 0, GFLAGS),
666 GATE(0, "gpll_aclk_cci_src", "gpll", CLK_IGNORE_UNUSED,
667 RK3399_CLKGATE_CON(2), 1, GFLAGS),
668 GATE(0, "npll_aclk_cci_src", "npll", CLK_IGNORE_UNUSED,
669 RK3399_CLKGATE_CON(2), 2, GFLAGS),
670 GATE(0, "vpll_aclk_cci_src", "vpll", CLK_IGNORE_UNUSED,
671 RK3399_CLKGATE_CON(2), 3, GFLAGS),
673 COMPOSITE(0, "aclk_cci_pre", mux_aclk_cci_p, CLK_IGNORE_UNUSED,
674 RK3399_CLKSEL_CON(5), 6, 2, MFLAGS, 0, 5, DFLAGS,
675 RK3399_CLKGATE_CON(2), 4, GFLAGS),
677 GATE(ACLK_ADB400M_PD_CORE_L, "aclk_adb400m_pd_core_l", "aclk_cci_pre", CLK_IGNORE_UNUSED,
678 RK3399_CLKGATE_CON(15), 0, GFLAGS),
679 GATE(ACLK_ADB400M_PD_CORE_B, "aclk_adb400m_pd_core_b", "aclk_cci_pre", CLK_IGNORE_UNUSED,
680 RK3399_CLKGATE_CON(15), 1, GFLAGS),
681 GATE(ACLK_CCI, "aclk_cci", "aclk_cci_pre", CLK_IGNORE_UNUSED,
682 RK3399_CLKGATE_CON(15), 2, GFLAGS),
683 GATE(ACLK_CCI_NOC0, "aclk_cci_noc0", "aclk_cci_pre", CLK_IGNORE_UNUSED,
684 RK3399_CLKGATE_CON(15), 3, GFLAGS),
685 GATE(ACLK_CCI_NOC1, "aclk_cci_noc1", "aclk_cci_pre", CLK_IGNORE_UNUSED,
686 RK3399_CLKGATE_CON(15), 4, GFLAGS),
687 GATE(ACLK_CCI_GRF, "aclk_cci_grf", "aclk_cci_pre", CLK_IGNORE_UNUSED,
688 RK3399_CLKGATE_CON(15), 7, GFLAGS),
690 GATE(0, "cpll_cci_trace", "cpll", CLK_IGNORE_UNUSED,
691 RK3399_CLKGATE_CON(2), 5, GFLAGS),
692 GATE(0, "gpll_cci_trace", "gpll", CLK_IGNORE_UNUSED,
693 RK3399_CLKGATE_CON(2), 6, GFLAGS),
694 COMPOSITE(SCLK_CCI_TRACE, "clk_cci_trace", mux_cci_trace_p, CLK_IGNORE_UNUSED,
695 RK3399_CLKSEL_CON(5), 15, 2, MFLAGS, 8, 5, DFLAGS,
696 RK3399_CLKGATE_CON(2), 7, GFLAGS),
698 GATE(0, "cpll_cs", "cpll", CLK_IGNORE_UNUSED,
699 RK3399_CLKGATE_CON(2), 8, GFLAGS),
700 GATE(0, "gpll_cs", "gpll", CLK_IGNORE_UNUSED,
701 RK3399_CLKGATE_CON(2), 9, GFLAGS),
702 GATE(0, "npll_cs", "npll", CLK_IGNORE_UNUSED,
703 RK3399_CLKGATE_CON(2), 10, GFLAGS),
704 COMPOSITE_NOGATE(0, "clk_cs", mux_cs_p, CLK_IGNORE_UNUSED,
705 RK3399_CLKSEL_CON(4), 6, 2, MFLAGS, 0, 5, DFLAGS),
706 GATE(0, "clk_dbg_cxcs", "clk_cs", CLK_IGNORE_UNUSED,
707 RK3399_CLKGATE_CON(15), 5, GFLAGS),
708 GATE(0, "clk_dbg_noc", "clk_cs", CLK_IGNORE_UNUSED,
709 RK3399_CLKGATE_CON(15), 6, GFLAGS),
712 COMPOSITE(0, "aclk_vcodec_pre", mux_pll_src_cpll_gpll_npll_ppll_p, 0,
713 RK3399_CLKSEL_CON(7), 6, 2, MFLAGS, 0, 5, DFLAGS,
714 RK3399_CLKGATE_CON(4), 0, GFLAGS),
715 COMPOSITE_NOMUX(0, "hclk_vcodec_pre", "aclk_vcodec_pre", 0,
716 RK3399_CLKSEL_CON(7), 8, 5, DFLAGS,
717 RK3399_CLKGATE_CON(4), 1, GFLAGS),
718 GATE(HCLK_VCODEC, "hclk_vcodec", "hclk_vcodec_pre", 0,
719 RK3399_CLKGATE_CON(17), 2, GFLAGS),
720 GATE(0, "hclk_vcodec_noc", "hclk_vcodec_pre", CLK_IGNORE_UNUSED,
721 RK3399_CLKGATE_CON(17), 3, GFLAGS),
723 GATE(ACLK_VCODEC, "aclk_vcodec", "aclk_vcodec_pre", 0,
724 RK3399_CLKGATE_CON(17), 0, GFLAGS),
725 GATE(0, "aclk_vcodec_noc", "aclk_vcodec_pre", CLK_IGNORE_UNUSED,
726 RK3399_CLKGATE_CON(17), 1, GFLAGS),
729 COMPOSITE(SCLK_VDU_CORE, "clk_vdu_core", mux_pll_src_cpll_gpll_npll_p, 0,
730 RK3399_CLKSEL_CON(9), 6, 2, MFLAGS, 0, 5, DFLAGS,
731 RK3399_CLKGATE_CON(4), 4, GFLAGS),
732 COMPOSITE(SCLK_VDU_CA, "clk_vdu_ca", mux_pll_src_cpll_gpll_npll_p, 0,
733 RK3399_CLKSEL_CON(9), 14, 2, MFLAGS, 8, 5, DFLAGS,
734 RK3399_CLKGATE_CON(4), 5, GFLAGS),
736 COMPOSITE(0, "aclk_vdu_pre", mux_pll_src_cpll_gpll_npll_ppll_p, 0,
737 RK3399_CLKSEL_CON(8), 6, 2, MFLAGS, 0, 5, DFLAGS,
738 RK3399_CLKGATE_CON(4), 2, GFLAGS),
739 COMPOSITE_NOMUX(0, "hclk_vdu_pre", "aclk_vdu_pre", 0,
740 RK3399_CLKSEL_CON(8), 8, 5, DFLAGS,
741 RK3399_CLKGATE_CON(4), 3, GFLAGS),
742 GATE(HCLK_VDU, "hclk_vdu", "hclk_vdu_pre", 0,
743 RK3399_CLKGATE_CON(17), 10, GFLAGS),
744 GATE(HCLK_VDU_NOC, "hclk_vdu_noc", "hclk_vdu_pre", CLK_IGNORE_UNUSED,
745 RK3399_CLKGATE_CON(17), 11, GFLAGS),
747 GATE(ACLK_VDU, "aclk_vdu", "aclk_vdu_pre", 0,
748 RK3399_CLKGATE_CON(17), 8, GFLAGS),
749 GATE(ACLK_VDU_NOC, "aclk_vdu_noc", "aclk_vdu_pre", CLK_IGNORE_UNUSED,
750 RK3399_CLKGATE_CON(17), 9, GFLAGS),
753 COMPOSITE(0, "aclk_iep_pre", mux_pll_src_cpll_gpll_npll_ppll_p, 0,
754 RK3399_CLKSEL_CON(10), 6, 2, MFLAGS, 0, 5, DFLAGS,
755 RK3399_CLKGATE_CON(4), 6, GFLAGS),
756 COMPOSITE_NOMUX(0, "hclk_iep_pre", "aclk_iep_pre", 0,
757 RK3399_CLKSEL_CON(10), 8, 5, DFLAGS,
758 RK3399_CLKGATE_CON(4), 7, GFLAGS),
759 GATE(HCLK_IEP, "hclk_iep", "hclk_iep_pre", 0,
760 RK3399_CLKGATE_CON(16), 2, GFLAGS),
761 GATE(HCLK_IEP_NOC, "hclk_iep_noc", "hclk_iep_pre", CLK_IGNORE_UNUSED,
762 RK3399_CLKGATE_CON(16), 3, GFLAGS),
764 GATE(ACLK_IEP, "aclk_iep", "aclk_iep_pre", 0,
765 RK3399_CLKGATE_CON(16), 0, GFLAGS),
766 GATE(ACLK_IEP_NOC, "aclk_iep_noc", "aclk_iep_pre", CLK_IGNORE_UNUSED,
767 RK3399_CLKGATE_CON(16), 1, GFLAGS),
770 COMPOSITE(0, "clk_rga_core", mux_pll_src_cpll_gpll_npll_ppll_p, 0,
771 RK3399_CLKSEL_CON(12), 6, 2, MFLAGS, 0, 5, DFLAGS,
772 RK3399_CLKGATE_CON(4), 10, GFLAGS),
774 COMPOSITE(0, "aclk_rga_pre", mux_pll_src_cpll_gpll_npll_ppll_p, 0,
775 RK3399_CLKSEL_CON(11), 6, 2, MFLAGS, 0, 5, DFLAGS,
776 RK3399_CLKGATE_CON(4), 8, GFLAGS),
777 COMPOSITE_NOMUX(0, "hclk_rga_pre", "aclk_rga_pre", 0,
778 RK3399_CLKSEL_CON(11), 8, 5, DFLAGS,
779 RK3399_CLKGATE_CON(4), 9, GFLAGS),
780 GATE(HCLK_RGA, "hclk_rga", "hclk_rga_pre", 0,
781 RK3399_CLKGATE_CON(16), 10, GFLAGS),
782 GATE(HCLK_RGA_NOC, "hclk_rga_noc", "hclk_rga_pre", CLK_IGNORE_UNUSED,
783 RK3399_CLKGATE_CON(16), 11, GFLAGS),
785 GATE(ACLK_RGA, "aclk_rga", "aclk_rga_pre", 0,
786 RK3399_CLKGATE_CON(16), 8, GFLAGS),
787 GATE(ACLK_RGA_NOC, "aclk_rga_noc", "aclk_rga_pre", CLK_IGNORE_UNUSED,
788 RK3399_CLKGATE_CON(16), 9, GFLAGS),
791 COMPOSITE(0, "aclk_center", mux_pll_src_cpll_gpll_npll_p, CLK_IGNORE_UNUSED,
792 RK3399_CLKSEL_CON(12), 14, 2, MFLAGS, 8, 5, DFLAGS,
793 RK3399_CLKGATE_CON(3), 7, GFLAGS),
794 GATE(ACLK_CENTER_MAIN_NOC, "aclk_center_main_noc", "aclk_center", CLK_IGNORE_UNUSED,
795 RK3399_CLKGATE_CON(19), 0, GFLAGS),
796 GATE(ACLK_CENTER_PERI_NOC, "aclk_center_peri_noc", "aclk_center", CLK_IGNORE_UNUSED,
797 RK3399_CLKGATE_CON(19), 1, GFLAGS),
800 COMPOSITE(0, "aclk_gpu_pre", mux_pll_src_ppll_cpll_gpll_npll_p, CLK_IGNORE_UNUSED,
801 RK3399_CLKSEL_CON(13), 5, 3, MFLAGS, 0, 5, DFLAGS,
802 RK3399_CLKGATE_CON(13), 0, GFLAGS),
803 GATE(ACLK_GPU, "aclk_gpu", "aclk_gpu_pre", 0,
804 RK3399_CLKGATE_CON(30), 8, GFLAGS),
805 GATE(ACLK_PERF_GPU, "aclk_perf_gpu", "aclk_gpu_pre", 0,
806 RK3399_CLKGATE_CON(30), 10, GFLAGS),
807 GATE(ACLK_GPU_GRF, "aclk_gpu_grf", "aclk_gpu_pre", 0,
808 RK3399_CLKGATE_CON(30), 11, GFLAGS),
809 GATE(SCLK_PVTM_GPU, "aclk_pvtm_gpu", "xin24m", 0,
810 RK3399_CLKGATE_CON(13), 1, GFLAGS),
813 GATE(0, "cpll_aclk_perihp_src", "gpll", CLK_IGNORE_UNUSED,
814 RK3399_CLKGATE_CON(5), 0, GFLAGS),
815 GATE(0, "gpll_aclk_perihp_src", "cpll", CLK_IGNORE_UNUSED,
816 RK3399_CLKGATE_CON(5), 1, GFLAGS),
817 COMPOSITE(ACLK_PERIHP, "aclk_perihp", mux_aclk_perihp_p, CLK_IGNORE_UNUSED,
818 RK3399_CLKSEL_CON(14), 7, 1, MFLAGS, 0, 5, DFLAGS,
819 RK3399_CLKGATE_CON(5), 2, GFLAGS),
820 COMPOSITE_NOMUX(HCLK_PERIHP, "hclk_perihp", "aclk_perihp", CLK_IGNORE_UNUSED,
821 RK3399_CLKSEL_CON(14), 8, 2, DFLAGS,
822 RK3399_CLKGATE_CON(5), 3, GFLAGS),
823 COMPOSITE_NOMUX(PCLK_PERIHP, "pclk_perihp", "aclk_perihp", CLK_IGNORE_UNUSED,
824 RK3399_CLKSEL_CON(14), 12, 2, DFLAGS,
825 RK3399_CLKGATE_CON(5), 4, GFLAGS),
827 GATE(ACLK_PERF_PCIE, "aclk_perf_pcie", "aclk_perihp", CLK_IGNORE_UNUSED,
828 RK3399_CLKGATE_CON(20), 2, GFLAGS),
829 GATE(ACLK_PCIE, "aclk_pcie", "aclk_perihp", CLK_IGNORE_UNUSED,
830 RK3399_CLKGATE_CON(20), 10, GFLAGS),
831 GATE(0, "aclk_perihp_noc", "aclk_perihp", CLK_IGNORE_UNUSED,
832 RK3399_CLKGATE_CON(20), 12, GFLAGS),
834 GATE(HCLK_HOST0, "hclk_host0", "hclk_perihp", 0,
835 RK3399_CLKGATE_CON(20), 5, GFLAGS),
836 GATE(HCLK_HOST0_ARB, "hclk_host0_arb", "hclk_perihp", 0,
837 RK3399_CLKGATE_CON(20), 6, GFLAGS),
838 GATE(HCLK_HOST1, "hclk_host1", "hclk_perihp", 0,
839 RK3399_CLKGATE_CON(20), 7, GFLAGS),
840 GATE(HCLK_HOST1_ARB, "hclk_host1_arb", "hclk_perihp", 0,
841 RK3399_CLKGATE_CON(20), 8, GFLAGS),
842 GATE(HCLK_HSIC, "hclk_hsic", "hclk_perihp", 0,
843 RK3399_CLKGATE_CON(20), 9, GFLAGS),
844 GATE(0, "hclk_perihp_noc", "hclk_perihp", CLK_IGNORE_UNUSED,
845 RK3399_CLKGATE_CON(20), 13, GFLAGS),
846 GATE(0, "hclk_ahb1tom", "hclk_perihp", CLK_IGNORE_UNUSED,
847 RK3399_CLKGATE_CON(20), 15, GFLAGS),
849 GATE(PCLK_PERIHP_GRF, "pclk_perihp_grf", "pclk_perihp", CLK_IGNORE_UNUSED,
850 RK3399_CLKGATE_CON(20), 4, GFLAGS),
851 GATE(PCLK_PCIE, "pclk_pcie", "pclk_perihp", 0,
852 RK3399_CLKGATE_CON(20), 11, GFLAGS),
853 GATE(0, "pclk_perihp_noc", "pclk_perihp", CLK_IGNORE_UNUSED,
854 RK3399_CLKGATE_CON(20), 14, GFLAGS),
855 GATE(PCLK_HSICPHY, "pclk_hsicphy", "pclk_perihp", 0,
856 RK3399_CLKGATE_CON(31), 8, GFLAGS),
859 COMPOSITE(0, "hclk_sd", mux_pll_src_cpll_gpll_p, 0,
860 RK3399_CLKSEL_CON(13), 15, 1, MFLAGS, 8, 5, DFLAGS,
861 RK3399_CLKGATE_CON(12), 13, GFLAGS),
862 GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_sd", 0,
863 RK3399_CLKGATE_CON(33), 8, GFLAGS),
864 GATE(0, "hclk_sdmmc_noc", "hclk_sd", CLK_IGNORE_UNUSED,
865 RK3399_CLKGATE_CON(33), 9, GFLAGS),
867 COMPOSITE(SCLK_SDIO, "clk_sdio", mux_pll_src_cpll_gpll_npll_ppll_upll_24m_p, 0,
868 RK3399_CLKSEL_CON(15), 8, 3, MFLAGS, 0, 7, DFLAGS,
869 RK3399_CLKGATE_CON(6), 0, GFLAGS),
871 COMPOSITE(SCLK_SDMMC, "clk_sdmmc", mux_pll_src_cpll_gpll_npll_ppll_upll_24m_p, 0,
872 RK3399_CLKSEL_CON(16), 8, 3, MFLAGS, 0, 7, DFLAGS,
873 RK3399_CLKGATE_CON(6), 1, GFLAGS),
875 MMC(SCLK_SDMMC_DRV, "emmc_drv", "clk_sdmmc", RK3399_SDMMC_CON0, 1),
876 MMC(SCLK_SDMMC_SAMPLE, "emmc_sample", "clk_sdmmc", RK3399_SDMMC_CON1, 1),
878 MMC(SCLK_SDIO_DRV, "sdio_drv", "clk_sdio", RK3399_SDIO_CON0, 1),
879 MMC(SCLK_SDIO_SAMPLE, "sdio_sample", "clk_sdio", RK3399_SDIO_CON1, 1),
882 COMPOSITE(SCLK_PCIE_PM, "clk_pcie_pm", mux_pll_src_cpll_gpll_npll_24m_p, 0,
883 RK3399_CLKSEL_CON(17), 8, 3, MFLAGS, 0, 7, DFLAGS,
884 RK3399_CLKGATE_CON(6), 2, GFLAGS),
886 COMPOSITE_NOMUX(SCLK_PCIEPHY_REF100M, "clk_pciephy_ref100m", "npll", 0,
887 RK3399_CLKSEL_CON(18), 11, 5, DFLAGS,
888 RK3399_CLKGATE_CON(12), 6, GFLAGS),
889 MUX(SCLK_PCIEPHY_REF, "clk_pciephy_ref", mux_pll_src_24m_pciephy_p, CLK_SET_RATE_PARENT,
890 RK3399_CLKSEL_CON(18), 10, 1, MFLAGS),
892 COMPOSITE(0, "clk_pcie_core_cru", mux_pll_src_cpll_gpll_npll_p, 0,
893 RK3399_CLKSEL_CON(18), 8, 2, MFLAGS, 0, 7, DFLAGS,
894 RK3399_CLKGATE_CON(6), 3, GFLAGS),
895 MUX(SCLK_PCIE_CORE, "clk_pcie_core", mux_pciecore_cru_phy_p, CLK_SET_RATE_PARENT,
896 RK3399_CLKSEL_CON(18), 7, 1, MFLAGS),
899 COMPOSITE(SCLK_EMMC, "clk_emmc", mux_pll_src_cpll_gpll_npll_upll_24m_p, 0,
900 RK3399_CLKSEL_CON(22), 8, 3, MFLAGS, 0, 7, DFLAGS,
901 RK3399_CLKGATE_CON(6), 14, GFLAGS),
903 GATE(0, "cpll_aclk_emmc_src", "cpll", CLK_IGNORE_UNUSED,
904 RK3399_CLKGATE_CON(6), 12, GFLAGS),
905 GATE(0, "gpll_aclk_emmc_src", "gpll", CLK_IGNORE_UNUSED,
906 RK3399_CLKGATE_CON(6), 13, GFLAGS),
907 COMPOSITE_NOGATE(ACLK_EMMC, "aclk_emmc", mux_aclk_emmc_p, CLK_IGNORE_UNUSED,
908 RK3399_CLKSEL_CON(21), 7, 1, MFLAGS, 0, 5, DFLAGS),
909 GATE(ACLK_EMMC_CORE, "aclk_emmccore", "aclk_emmc", CLK_IGNORE_UNUSED,
910 RK3399_CLKGATE_CON(32), 8, GFLAGS),
911 GATE(ACLK_EMMC_NOC, "aclk_emmc_noc", "aclk_emmc", CLK_IGNORE_UNUSED,
912 RK3399_CLKGATE_CON(32), 9, GFLAGS),
913 GATE(ACLK_EMMC_GRF, "aclk_emmcgrf", "aclk_emmc", CLK_IGNORE_UNUSED,
914 RK3399_CLKGATE_CON(32), 10, GFLAGS),
917 GATE(0, "cpll_aclk_perilp0_src", "cpll", CLK_IGNORE_UNUSED,
918 RK3399_CLKGATE_CON(7), 1, GFLAGS),
919 GATE(0, "gpll_aclk_perilp0_src", "gpll", CLK_IGNORE_UNUSED,
920 RK3399_CLKGATE_CON(7), 0, GFLAGS),
921 COMPOSITE(ACLK_PERILP0, "aclk_perilp0", mux_aclk_perilp0_p, CLK_IGNORE_UNUSED,
922 RK3399_CLKSEL_CON(23), 7, 1, MFLAGS, 0, 5, DFLAGS,
923 RK3399_CLKGATE_CON(7), 2, GFLAGS),
924 COMPOSITE_NOMUX(HCLK_PERILP0, "hclk_perilp0", "aclk_perilp0", CLK_IGNORE_UNUSED,
925 RK3399_CLKSEL_CON(23), 8, 2, DFLAGS,
926 RK3399_CLKGATE_CON(7), 3, GFLAGS),
927 COMPOSITE_NOMUX(PCLK_PERILP0, "pclk_perilp0", "aclk_perilp0", 0,
928 RK3399_CLKSEL_CON(23), 12, 3, DFLAGS,
929 RK3399_CLKGATE_CON(7), 4, GFLAGS),
931 /* aclk_perilp0 gates */
932 GATE(ACLK_INTMEM, "aclk_intmem", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 0, GFLAGS),
933 GATE(ACLK_TZMA, "aclk_tzma", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 1, GFLAGS),
934 GATE(SCLK_INTMEM0, "clk_intmem0", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 2, GFLAGS),
935 GATE(SCLK_INTMEM1, "clk_intmem1", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 3, GFLAGS),
936 GATE(SCLK_INTMEM2, "clk_intmem2", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 4, GFLAGS),
937 GATE(SCLK_INTMEM3, "clk_intmem3", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 5, GFLAGS),
938 GATE(SCLK_INTMEM4, "clk_intmem4", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 6, GFLAGS),
939 GATE(SCLK_INTMEM5, "clk_intmem5", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 7, GFLAGS),
940 GATE(ACLK_DCF, "aclk_dcf", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 8, GFLAGS),
941 GATE(ACLK_DMAC0_PERILP, "aclk_dmac0_perilp", "aclk_perilp0", 0, RK3399_CLKGATE_CON(25), 5, GFLAGS),
942 GATE(ACLK_DMAC1_PERILP, "aclk_dmac1_perilp", "aclk_perilp0", 0, RK3399_CLKGATE_CON(25), 6, GFLAGS),
943 GATE(ACLK_PERILP0_NOC, "aclk_perilp0_noc", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(25), 7, GFLAGS),
945 /* hclk_perilp0 gates */
946 GATE(HCLK_ROM, "hclk_rom", "hclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(24), 4, GFLAGS),
947 GATE(HCLK_M_CRYPTO0, "hclk_m_crypto0", "hclk_perilp0", 0, RK3399_CLKGATE_CON(24), 5, GFLAGS),
948 GATE(HCLK_S_CRYPTO0, "hclk_s_crypto0", "hclk_perilp0", 0, RK3399_CLKGATE_CON(24), 6, GFLAGS),
949 GATE(HCLK_M_CRYPTO1, "hclk_m_crypto1", "hclk_perilp0", 0, RK3399_CLKGATE_CON(24), 14, GFLAGS),
950 GATE(HCLK_S_CRYPTO1, "hclk_s_crypto1", "hclk_perilp0", 0, RK3399_CLKGATE_CON(24), 15, GFLAGS),
951 GATE(HCLK_PERILP0_NOC, "hclk_perilp0_noc", "hclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(25), 8, GFLAGS),
953 /* pclk_perilp0 gates */
954 GATE(PCLK_DCF, "pclk_dcf", "pclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 9, GFLAGS),
957 COMPOSITE(SCLK_CRYPTO0, "clk_crypto0", mux_pll_src_cpll_gpll_ppll_p, 0,
958 RK3399_CLKSEL_CON(24), 6, 2, MFLAGS, 0, 5, DFLAGS,
959 RK3399_CLKGATE_CON(7), 7, GFLAGS),
961 COMPOSITE(SCLK_CRYPTO1, "clk_crypto1", mux_pll_src_cpll_gpll_ppll_p, 0,
962 RK3399_CLKSEL_CON(26), 6, 2, MFLAGS, 0, 5, DFLAGS,
963 RK3399_CLKGATE_CON(7), 8, GFLAGS),
966 GATE(0, "cpll_fclk_cm0s_src", "cpll", 0,
967 RK3399_CLKGATE_CON(7), 6, GFLAGS),
968 GATE(0, "gpll_fclk_cm0s_src", "gpll", 0,
969 RK3399_CLKGATE_CON(7), 5, GFLAGS),
970 COMPOSITE(FCLK_CM0S, "fclk_cm0s", mux_fclk_cm0s_p, 0,
971 RK3399_CLKSEL_CON(24), 15, 1, MFLAGS, 8, 5, DFLAGS,
972 RK3399_CLKGATE_CON(7), 9, GFLAGS),
974 /* fclk_cm0s gates */
975 GATE(SCLK_M0_PERILP, "sclk_m0_perilp", "fclk_cm0s", 0, RK3399_CLKGATE_CON(24), 8, GFLAGS),
976 GATE(HCLK_M0_PERILP, "hclk_m0_perilp", "fclk_cm0s", 0, RK3399_CLKGATE_CON(24), 9, GFLAGS),
977 GATE(DCLK_M0_PERILP, "dclk_m0_perilp", "fclk_cm0s", 0, RK3399_CLKGATE_CON(24), 10, GFLAGS),
978 GATE(SCLK_M0_PERILP_DEC, "clk_m0_perilp_dec", "fclk_cm0s", 0, RK3399_CLKGATE_CON(24), 11, GFLAGS),
979 GATE(HCLK_M0_PERILP_NOC, "hclk_m0_perilp_noc", "fclk_cm0s", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(25), 11, GFLAGS),
982 GATE(0, "cpll_hclk_perilp1_src", "cpll", CLK_IGNORE_UNUSED,
983 RK3399_CLKGATE_CON(8), 1, GFLAGS),
984 GATE(0, "gpll_hclk_perilp1_src", "gpll", CLK_IGNORE_UNUSED,
985 RK3399_CLKGATE_CON(8), 0, GFLAGS),
986 COMPOSITE_NOGATE(HCLK_PERILP1, "hclk_perilp1", mux_hclk_perilp1_p, CLK_IGNORE_UNUSED,
987 RK3399_CLKSEL_CON(25), 7, 1, MFLAGS, 0, 5, DFLAGS),
988 COMPOSITE_NOMUX(PCLK_PERILP1, "pclk_perilp1", "hclk_perilp1", CLK_IGNORE_UNUSED,
989 RK3399_CLKSEL_CON(25), 8, 3, DFLAGS,
990 RK3399_CLKGATE_CON(8), 2, GFLAGS),
992 /* hclk_perilp1 gates */
993 GATE(0, "hclk_perilp1_noc", "hclk_perilp1", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(25), 9, GFLAGS),
994 GATE(0, "hclk_sdio_noc", "hclk_perilp1", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(25), 12, GFLAGS),
995 GATE(HCLK_I2S0_8CH, "hclk_i2s0", "hclk_perilp1", 0, RK3399_CLKGATE_CON(34), 0, GFLAGS),
996 GATE(HCLK_I2S1_8CH, "hclk_i2s1", "hclk_perilp1", 0, RK3399_CLKGATE_CON(34), 1, GFLAGS),
997 GATE(HCLK_I2S2_8CH, "hclk_i2s2", "hclk_perilp1", 0, RK3399_CLKGATE_CON(34), 2, GFLAGS),
998 GATE(HCLK_SPDIF, "hclk_spdif", "hclk_perilp1", 0, RK3399_CLKGATE_CON(34), 3, GFLAGS),
999 GATE(HCLK_SDIO, "hclk_sdio", "hclk_perilp1", 0, RK3399_CLKGATE_CON(34), 4, GFLAGS),
1000 GATE(PCLK_SPI5, "pclk_spi5", "hclk_perilp1", 0, RK3399_CLKGATE_CON(34), 5, GFLAGS),
1001 GATE(0, "hclk_sdioaudio_noc", "hclk_perilp1", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(34), 6, GFLAGS),
1003 /* pclk_perilp1 gates */
1004 GATE(PCLK_UART0, "pclk_uart0", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 0, GFLAGS),
1005 GATE(PCLK_UART1, "pclk_uart1", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 1, GFLAGS),
1006 GATE(PCLK_UART2, "pclk_uart2", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 2, GFLAGS),
1007 GATE(PCLK_UART3, "pclk_uart3", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 3, GFLAGS),
1008 GATE(PCLK_I2C7, "pclk_rki2c7", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 5, GFLAGS),
1009 GATE(PCLK_I2C1, "pclk_rki2c1", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 6, GFLAGS),
1010 GATE(PCLK_I2C5, "pclk_rki2c5", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 7, GFLAGS),
1011 GATE(PCLK_I2C6, "pclk_rki2c6", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 8, GFLAGS),
1012 GATE(PCLK_I2C2, "pclk_rki2c2", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 9, GFLAGS),
1013 GATE(PCLK_I2C3, "pclk_rki2c3", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 10, GFLAGS),
1014 GATE(PCLK_MAILBOX0, "pclk_mailbox0", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 11, GFLAGS),
1015 GATE(PCLK_SARADC, "pclk_saradc", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 12, GFLAGS),
1016 GATE(PCLK_TSADC, "pclk_tsadc", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 13, GFLAGS),
1017 GATE(PCLK_EFUSE1024NS, "pclk_efuse1024ns", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 14, GFLAGS),
1018 GATE(PCLK_EFUSE1024S, "pclk_efuse1024s", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 15, GFLAGS),
1019 GATE(PCLK_SPI0, "pclk_spi0", "pclk_perilp1", 0, RK3399_CLKGATE_CON(23), 10, GFLAGS),
1020 GATE(PCLK_SPI1, "pclk_spi1", "pclk_perilp1", 0, RK3399_CLKGATE_CON(23), 11, GFLAGS),
1021 GATE(PCLK_SPI2, "pclk_spi2", "pclk_perilp1", 0, RK3399_CLKGATE_CON(23), 12, GFLAGS),
1022 GATE(PCLK_SPI4, "pclk_spi4", "pclk_perilp1", 0, RK3399_CLKGATE_CON(23), 13, GFLAGS),
1023 GATE(PCLK_PERIHP_GRF, "pclk_perilp_sgrf", "pclk_perilp1", 0, RK3399_CLKGATE_CON(24), 13, GFLAGS),
1024 GATE(0, "pclk_perilp1_noc", "pclk_perilp1", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(25), 10, GFLAGS),
1027 COMPOSITE_NOMUX(SCLK_SARADC, "clk_saradc", "xin24m", 0,
1028 RK3399_CLKSEL_CON(26), 8, 8, DFLAGS,
1029 RK3399_CLKGATE_CON(9), 11, GFLAGS),
1032 COMPOSITE(SCLK_TSADC, "clk_tsadc", mux_pll_p, 0,
1033 RK3399_CLKSEL_CON(27), 15, 1, MFLAGS, 0, 10, DFLAGS,
1034 RK3399_CLKGATE_CON(9), 10, GFLAGS),
1037 MUX(0, "clk_testout1_pll_src", mux_pll_src_cpll_gpll_npll_p, 0,
1038 RK3399_CLKSEL_CON(38), 6, 2, MFLAGS),
1039 COMPOSITE(0, "clk_testout1", mux_clk_testout1_p, 0,
1040 RK3399_CLKSEL_CON(38), 5, 1, MFLAGS, 0, 5, DFLAGS,
1041 RK3399_CLKGATE_CON(13), 14, GFLAGS),
1043 MUX(0, "clk_testout2_pll_src", mux_pll_src_cpll_gpll_npll_p, 0,
1044 RK3399_CLKSEL_CON(38), 14, 2, MFLAGS),
1045 COMPOSITE(0, "clk_testout2", mux_clk_testout2_p, 0,
1046 RK3399_CLKSEL_CON(38), 13, 1, MFLAGS, 8, 5, DFLAGS,
1047 RK3399_CLKGATE_CON(13), 15, GFLAGS),
1050 COMPOSITE(ACLK_VIO, "aclk_vio", mux_pll_src_cpll_gpll_ppll_p, CLK_IGNORE_UNUSED,
1051 RK3399_CLKSEL_CON(42), 6, 2, MFLAGS, 0, 5, DFLAGS,
1052 RK3399_CLKGATE_CON(11), 10, GFLAGS),
1053 COMPOSITE_NOMUX(PCLK_VIO, "pclk_vio", "aclk_vio", 0,
1054 RK3399_CLKSEL_CON(43), 0, 5, DFLAGS,
1055 RK3399_CLKGATE_CON(11), 1, GFLAGS),
1057 GATE(ACLK_VIO_NOC, "aclk_vio_noc", "aclk_vio", CLK_IGNORE_UNUSED,
1058 RK3399_CLKGATE_CON(29), 0, GFLAGS),
1060 GATE(PCLK_MIPI_DSI0, "pclk_mipi_dsi0", "pclk_vio", 0,
1061 RK3399_CLKGATE_CON(29), 1, GFLAGS),
1062 GATE(PCLK_MIPI_DSI1, "pclk_mipi_dsi1", "pclk_vio", 0,
1063 RK3399_CLKGATE_CON(29), 2, GFLAGS),
1064 GATE(PCLK_VIO_GRF, "pclk_vio_grf", "pclk_vio", CLK_IGNORE_UNUSED,
1065 RK3399_CLKGATE_CON(29), 12, GFLAGS),
1068 COMPOSITE(ACLK_HDCP, "aclk_hdcp", mux_pll_src_cpll_gpll_ppll_p, 0,
1069 RK3399_CLKSEL_CON(42), 14, 2, MFLAGS, 8, 5, DFLAGS,
1070 RK3399_CLKGATE_CON(11), 12, GFLAGS),
1071 COMPOSITE_NOMUX(HCLK_HDCP, "hclk_hdcp", "aclk_hdcp", 0,
1072 RK3399_CLKSEL_CON(43), 5, 5, DFLAGS,
1073 RK3399_CLKGATE_CON(11), 3, GFLAGS),
1074 COMPOSITE_NOMUX(PCLK_HDCP, "pclk_hdcp", "aclk_hdcp", 0,
1075 RK3399_CLKSEL_CON(43), 10, 5, DFLAGS,
1076 RK3399_CLKGATE_CON(11), 10, GFLAGS),
1078 GATE(ACLK_HDCP_NOC, "aclk_hdcp_noc", "aclk_hdcp", CLK_IGNORE_UNUSED,
1079 RK3399_CLKGATE_CON(29), 4, GFLAGS),
1080 GATE(ACLK_HDCP22, "aclk_hdcp22", "aclk_hdcp", 0,
1081 RK3399_CLKGATE_CON(29), 10, GFLAGS),
1083 GATE(HCLK_HDCP_NOC, "hclk_hdcp_noc", "hclk_hdcp", CLK_IGNORE_UNUSED,
1084 RK3399_CLKGATE_CON(29), 5, GFLAGS),
1085 GATE(HCLK_HDCP22, "hclk_hdcp22", "hclk_hdcp", 0,
1086 RK3399_CLKGATE_CON(29), 9, GFLAGS),
1088 GATE(PCLK_HDCP_NOC, "pclk_hdcp_noc", "pclk_hdcp", CLK_IGNORE_UNUSED,
1089 RK3399_CLKGATE_CON(29), 3, GFLAGS),
1090 GATE(PCLK_HDMI_CTRL, "pclk_hdmi_ctrl", "pclk_hdcp", 0,
1091 RK3399_CLKGATE_CON(29), 6, GFLAGS),
1092 GATE(PCLK_DP_CTRL, "pclk_dp_ctrl", "pclk_hdcp", 0,
1093 RK3399_CLKGATE_CON(29), 7, GFLAGS),
1094 GATE(PCLK_HDCP22, "pclk_hdcp22", "pclk_hdcp", 0,
1095 RK3399_CLKGATE_CON(29), 8, GFLAGS),
1096 GATE(PCLK_GASKET, "pclk_gasket", "pclk_hdcp", 0,
1097 RK3399_CLKGATE_CON(29), 11, GFLAGS),
1100 COMPOSITE(SCLK_DP_CORE, "clk_dp_core", mux_pll_src_npll_cpll_gpll_p, 0,
1101 RK3399_CLKSEL_CON(46), 6, 2, MFLAGS, 0, 5, DFLAGS,
1102 RK3399_CLKGATE_CON(11), 8, GFLAGS),
1104 COMPOSITE(PCLK_EDP, "pclk_edp", mux_pll_src_cpll_gpll_p, 0,
1105 RK3399_CLKSEL_CON(44), 15, 1, MFLAGS, 8, 5, DFLAGS,
1106 RK3399_CLKGATE_CON(11), 11, GFLAGS),
1107 GATE(PCLK_EDP_NOC, "pclk_edp_noc", "pclk_edp", CLK_IGNORE_UNUSED,
1108 RK3399_CLKGATE_CON(32), 12, GFLAGS),
1109 GATE(PCLK_EDP_CTRL, "pclk_edp_ctrl", "pclk_edp", 0,
1110 RK3399_CLKGATE_CON(32), 13, GFLAGS),
1113 GATE(SCLK_HDMI_SFR, "clk_hdmi_sfr", "xin24m", 0,
1114 RK3399_CLKGATE_CON(11), 6, GFLAGS),
1116 COMPOSITE(SCLK_HDMI_CEC, "clk_hdmi_cec", mux_pll_p, 0,
1117 RK3399_CLKSEL_CON(45), 15, 1, MFLAGS, 0, 10, DFLAGS,
1118 RK3399_CLKGATE_CON(11), 7, GFLAGS),
1121 COMPOSITE(ACLK_VOP0_PRE, "aclk_vop0_pre", mux_pll_src_dmyvpll_cpll_gpll_npll_p, 0,
1122 RK3399_CLKSEL_CON(47), 6, 2, MFLAGS, 0, 5, DFLAGS,
1123 RK3399_CLKGATE_CON(10), 8, GFLAGS),
1124 COMPOSITE_NOMUX(0, "hclk_vop0_pre", "aclk_vop0_pre", 0,
1125 RK3399_CLKSEL_CON(47), 8, 5, DFLAGS,
1126 RK3399_CLKGATE_CON(10), 9, GFLAGS),
1128 GATE(ACLK_VOP0, "aclk_vop0", "aclk_vop0_pre", 0,
1129 RK3399_CLKGATE_CON(28), 3, GFLAGS),
1130 GATE(ACLK_VOP0_NOC, "aclk_vop0_noc", "aclk_vop0_pre", CLK_IGNORE_UNUSED,
1131 RK3399_CLKGATE_CON(28), 1, GFLAGS),
1133 GATE(HCLK_VOP0, "hclk_vop0", "hclk_vop0_pre", 0,
1134 RK3399_CLKGATE_CON(28), 2, GFLAGS),
1135 GATE(HCLK_VOP0_NOC, "hclk_vop0_noc", "hclk_vop0_pre", CLK_IGNORE_UNUSED,
1136 RK3399_CLKGATE_CON(28), 0, GFLAGS),
1138 COMPOSITE(DCLK_VOP0_DIV, "dclk_vop0_div", mux_pll_src_vpll_cpll_gpll_p, CLK_SET_RATE_PARENT,
1139 RK3399_CLKSEL_CON(49), 8, 2, MFLAGS, 0, 8, DFLAGS,
1140 RK3399_CLKGATE_CON(10), 12, GFLAGS),
1142 /* The VOP0 is main screen, it is able to re-set parent rate. */
1143 COMPOSITE_FRACMUX_NOGATE(0, "dclk_vop0_frac", "dclk_vop0_div", CLK_SET_RATE_PARENT,
1144 RK3399_CLKSEL_CON(106), 0,
1145 &rk3399_dclk_vop0_fracmux),
1147 COMPOSITE(SCLK_VOP0_PWM, "clk_vop0_pwm", mux_pll_src_dmyvpll_cpll_gpll_24m_p, 0,
1148 RK3399_CLKSEL_CON(51), 6, 2, MFLAGS, 0, 5, DFLAGS,
1149 RK3399_CLKGATE_CON(10), 14, GFLAGS),
1152 COMPOSITE(ACLK_VOP1_PRE, "aclk_vop1_pre", mux_pll_src_dmyvpll_cpll_gpll_npll_p, 0,
1153 RK3399_CLKSEL_CON(48), 6, 2, MFLAGS, 0, 5, DFLAGS,
1154 RK3399_CLKGATE_CON(10), 10, GFLAGS),
1155 COMPOSITE_NOMUX(0, "hclk_vop1_pre", "aclk_vop1_pre", 0,
1156 RK3399_CLKSEL_CON(48), 8, 5, DFLAGS,
1157 RK3399_CLKGATE_CON(10), 11, GFLAGS),
1159 GATE(ACLK_VOP1, "aclk_vop1", "aclk_vop1_pre", 0,
1160 RK3399_CLKGATE_CON(28), 7, GFLAGS),
1161 GATE(ACLK_VOP1_NOC, "aclk_vop1_noc", "aclk_vop1_pre", CLK_IGNORE_UNUSED,
1162 RK3399_CLKGATE_CON(28), 5, GFLAGS),
1164 GATE(HCLK_VOP1, "hclk_vop1", "hclk_vop1_pre", 0,
1165 RK3399_CLKGATE_CON(28), 6, GFLAGS),
1166 GATE(HCLK_VOP1_NOC, "hclk_vop1_noc", "hclk_vop1_pre", CLK_IGNORE_UNUSED,
1167 RK3399_CLKGATE_CON(28), 4, GFLAGS),
1169 /* The VOP1 is sub screen, it is note able to re-set parent rate. */
1170 COMPOSITE(DCLK_VOP1_DIV, "dclk_vop1_div", mux_pll_src_vpll_cpll_gpll_p, 0,
1171 RK3399_CLKSEL_CON(50), 8, 2, MFLAGS, 0, 8, DFLAGS,
1172 RK3399_CLKGATE_CON(10), 13, GFLAGS),
1174 COMPOSITE_FRACMUX_NOGATE(0, "dclk_vop1_frac", "dclk_vop1_div", CLK_SET_RATE_PARENT,
1175 RK3399_CLKSEL_CON(107), 0,
1176 &rk3399_dclk_vop1_fracmux),
1178 COMPOSITE(SCLK_VOP1_PWM, "clk_vop1_pwm", mux_pll_src_dmyvpll_cpll_gpll_24m_p, 0,
1179 RK3399_CLKSEL_CON(52), 6, 2, MFLAGS, 0, 5, DFLAGS,
1180 RK3399_CLKGATE_CON(10), 15, GFLAGS),
1183 COMPOSITE(0, "aclk_isp0", mux_pll_src_cpll_gpll_ppll_p, 0,
1184 RK3399_CLKSEL_CON(53), 6, 2, MFLAGS, 0, 5, DFLAGS,
1185 RK3399_CLKGATE_CON(12), 8, GFLAGS),
1186 COMPOSITE_NOMUX(0, "hclk_isp0", "aclk_isp0", 0,
1187 RK3399_CLKSEL_CON(53), 8, 5, DFLAGS,
1188 RK3399_CLKGATE_CON(12), 9, GFLAGS),
1190 GATE(ACLK_ISP0_NOC, "aclk_isp0_noc", "aclk_isp0", CLK_IGNORE_UNUSED,
1191 RK3399_CLKGATE_CON(27), 1, GFLAGS),
1192 GATE(ACLK_ISP0_WRAPPER, "aclk_isp0_wrapper", "aclk_isp0", 0,
1193 RK3399_CLKGATE_CON(27), 5, GFLAGS),
1194 GATE(HCLK_ISP1_WRAPPER, "hclk_isp1_wrapper", "aclk_isp0", 0,
1195 RK3399_CLKGATE_CON(27), 7, GFLAGS),
1197 GATE(HCLK_ISP0_NOC, "hclk_isp0_noc", "hclk_isp0", CLK_IGNORE_UNUSED,
1198 RK3399_CLKGATE_CON(27), 0, GFLAGS),
1199 GATE(HCLK_ISP0_WRAPPER, "hclk_isp0_wrapper", "hclk_isp0", 0,
1200 RK3399_CLKGATE_CON(27), 4, GFLAGS),
1202 COMPOSITE(SCLK_ISP0, "clk_isp0", mux_pll_src_cpll_gpll_npll_p, 0,
1203 RK3399_CLKSEL_CON(55), 6, 2, MFLAGS, 0, 5, DFLAGS,
1204 RK3399_CLKGATE_CON(11), 4, GFLAGS),
1206 COMPOSITE(ACLK_ISP1, "aclk_isp1", mux_pll_src_cpll_gpll_ppll_p, 0,
1207 RK3399_CLKSEL_CON(54), 6, 2, MFLAGS, 0, 5, DFLAGS,
1208 RK3399_CLKGATE_CON(12), 10, GFLAGS),
1209 COMPOSITE_NOMUX(0, "hclk_isp1", "aclk_isp1", 0,
1210 RK3399_CLKSEL_CON(54), 8, 5, DFLAGS,
1211 RK3399_CLKGATE_CON(12), 11, GFLAGS),
1213 GATE(ACLK_ISP1_NOC, "aclk_isp1_noc", "aclk_isp1", CLK_IGNORE_UNUSED,
1214 RK3399_CLKGATE_CON(27), 3, GFLAGS),
1216 GATE(HCLK_ISP1_NOC, "hclk_isp1_noc", "hclk_isp1", CLK_IGNORE_UNUSED,
1217 RK3399_CLKGATE_CON(27), 2, GFLAGS),
1218 GATE(ACLK_ISP1_WRAPPER, "aclk_isp1_wrapper", "hclk_isp1", 0,
1219 RK3399_CLKGATE_CON(27), 8, GFLAGS),
1221 COMPOSITE(SCLK_ISP1, "clk_isp1", mux_pll_src_cpll_gpll_npll_p, 0,
1222 RK3399_CLKSEL_CON(55), 14, 2, MFLAGS, 8, 5, DFLAGS,
1223 RK3399_CLKGATE_CON(11), 5, GFLAGS),
1226 * We use pclkin_cifinv by default GRF_SOC_CON20[9] (GSC20_9) setting in system,
1227 * so we ignore the mux and make clocks nodes as following,
1229 * pclkin_cifinv --|-------\
1230 * |GSC20_9|-- pclkin_cifmux -- |G27_6| -- pclkin_isp1_wrapper
1231 * pclkin_cif --|-------/
1233 GATE(PCLK_ISP1_WRAPPER, "pclkin_isp1_wrapper", "pclkin_cif", 0,
1234 RK3399_CLKGATE_CON(27), 6, GFLAGS),
1237 COMPOSITE_NODIV(0, "clk_cifout_src", mux_pll_src_cpll_gpll_npll_p, 0,
1238 RK3399_CLKSEL_CON(56), 6, 2, MFLAGS,
1239 RK3399_CLKGATE_CON(10), 7, GFLAGS),
1241 COMPOSITE_NOGATE(SCLK_CIF_OUT, "clk_cifout", mux_clk_cif_p, 0,
1242 RK3399_CLKSEL_CON(56), 5, 1, MFLAGS, 0, 5, DFLAGS),
1245 COMPOSITE(ACLK_GIC_PRE, "aclk_gic_pre", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED,
1246 RK3399_CLKSEL_CON(56), 15, 1, MFLAGS, 8, 5, DFLAGS,
1247 RK3399_CLKGATE_CON(12), 12, GFLAGS),
1249 GATE(ACLK_GIC, "aclk_gic", "aclk_gic_pre", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(33), 0, GFLAGS),
1250 GATE(ACLK_GIC_NOC, "aclk_gic_noc", "aclk_gic_pre", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(33), 1, GFLAGS),
1251 GATE(ACLK_GIC_ADB400_CORE_L_2_GIC, "aclk_gic_adb400_core_l_2_gic", "aclk_gic_pre", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(33), 2, GFLAGS),
1252 GATE(ACLK_GIC_ADB400_CORE_B_2_GIC, "aclk_gic_adb400_core_b_2_gic", "aclk_gic_pre", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(33), 3, GFLAGS),
1253 GATE(ACLK_GIC_ADB400_GIC_2_CORE_L, "aclk_gic_adb400_gic_2_core_l", "aclk_gic_pre", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(33), 4, GFLAGS),
1254 GATE(ACLK_GIC_ADB400_GIC_2_CORE_B, "aclk_gic_adb400_gic_2_core_b", "aclk_gic_pre", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(33), 5, GFLAGS),
1257 /* pclk_alive_gpll_src is controlled by PMUGRF_SOC_CON0[6] */
1258 DIV(PCLK_ALIVE, "pclk_alive", "gpll", 0,
1259 RK3399_CLKSEL_CON(57), 0, 5, DFLAGS),
1261 GATE(PCLK_USBPHY_MUX_G, "pclk_usbphy_mux_g", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 4, GFLAGS),
1262 GATE(PCLK_UPHY0_TCPHY_G, "pclk_uphy0_tcphy_g", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 5, GFLAGS),
1263 GATE(PCLK_UPHY0_TCPD_G, "pclk_uphy0_tcpd_g", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 6, GFLAGS),
1264 GATE(PCLK_UPHY1_TCPHY_G, "pclk_uphy1_tcphy_g", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 8, GFLAGS),
1265 GATE(PCLK_UPHY1_TCPD_G, "pclk_uphy1_tcpd_g", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 9, GFLAGS),
1267 GATE(PCLK_GRF, "pclk_grf", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(31), 1, GFLAGS),
1268 GATE(PCLK_INTR_ARB, "pclk_intr_arb", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(31), 2, GFLAGS),
1269 GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_alive", 0, RK3399_CLKGATE_CON(31), 3, GFLAGS),
1270 GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_alive", 0, RK3399_CLKGATE_CON(31), 4, GFLAGS),
1271 GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_alive", 0, RK3399_CLKGATE_CON(31), 5, GFLAGS),
1272 GATE(PCLK_TIMER0, "pclk_timer0", "pclk_alive", 0, RK3399_CLKGATE_CON(31), 6, GFLAGS),
1273 GATE(PCLK_TIMER1, "pclk_timer1", "pclk_alive", 0, RK3399_CLKGATE_CON(31), 7, GFLAGS),
1274 GATE(PCLK_PMU_INTR_ARB, "pclk_pmu_intr_arb", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(31), 9, GFLAGS),
1275 GATE(PCLK_SGRF, "pclk_sgrf", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(31), 10, GFLAGS),
1277 GATE(SCLK_MIPIDPHY_REF, "clk_mipidphy_ref", "xin24m", 0, RK3399_CLKGATE_CON(11), 14, GFLAGS),
1278 GATE(SCLK_DPHY_PLL, "clk_dphy_pll", "clk_mipidphy_ref", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 0, GFLAGS),
1280 GATE(SCLK_MIPIDPHY_CFG, "clk_mipidphy_cfg", "xin24m", 0, RK3399_CLKGATE_CON(11), 15, GFLAGS),
1281 GATE(SCLK_DPHY_TX0_CFG, "clk_dphy_tx0_cfg", "clk_mipidphy_cfg", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 1, GFLAGS),
1282 GATE(SCLK_DPHY_TX1RX1_CFG, "clk_dphy_tx1rx1_cfg", "clk_mipidphy_cfg", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 2, GFLAGS),
1283 GATE(SCLK_DPHY_RX0_CFG, "clk_dphy_rx0_cfg", "clk_mipidphy_cfg", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 3, GFLAGS),
1286 MUX(0, "clk_test_pre", mux_pll_src_cpll_gpll_p, CLK_SET_RATE_PARENT,
1287 RK3399_CLKSEL_CON(58), 7, 1, MFLAGS),
1288 COMPOSITE_FRAC(0, "clk_test_frac", "clk_test_pre", CLK_SET_RATE_PARENT,
1289 RK3399_CLKSEL_CON(105), 0,
1290 RK3399_CLKGATE_CON(13), 9, GFLAGS),
1292 DIV(0, "clk_test_24m", "xin24m", 0,
1293 RK3399_CLKSEL_CON(57), 6, 10, DFLAGS),
1296 COMPOSITE(SCLK_SPI0, "clk_spi0", mux_pll_src_cpll_gpll_p, 0,
1297 RK3399_CLKSEL_CON(59), 7, 1, MFLAGS, 0, 7, DFLAGS,
1298 RK3399_CLKGATE_CON(9), 12, GFLAGS),
1300 COMPOSITE(SCLK_SPI1, "clk_spi1", mux_pll_src_cpll_gpll_p, 0,
1301 RK3399_CLKSEL_CON(59), 15, 1, MFLAGS, 8, 7, DFLAGS,
1302 RK3399_CLKGATE_CON(9), 13, GFLAGS),
1304 COMPOSITE(SCLK_SPI2, "clk_spi2", mux_pll_src_cpll_gpll_p, 0,
1305 RK3399_CLKSEL_CON(60), 7, 1, MFLAGS, 0, 7, DFLAGS,
1306 RK3399_CLKGATE_CON(9), 14, GFLAGS),
1308 COMPOSITE(SCLK_SPI4, "clk_spi4", mux_pll_src_cpll_gpll_p, 0,
1309 RK3399_CLKSEL_CON(60), 15, 1, MFLAGS, 8, 7, DFLAGS,
1310 RK3399_CLKGATE_CON(9), 15, GFLAGS),
1312 COMPOSITE(SCLK_SPI5, "clk_spi5", mux_pll_src_cpll_gpll_p, 0,
1313 RK3399_CLKSEL_CON(58), 15, 1, MFLAGS, 8, 7, DFLAGS,
1314 RK3399_CLKGATE_CON(13), 13, GFLAGS),
1317 COMPOSITE(SCLK_I2C1, "clk_i2c1", mux_pll_src_cpll_gpll_p, 0,
1318 RK3399_CLKSEL_CON(61), 7, 1, MFLAGS, 0, 7, DFLAGS,
1319 RK3399_CLKGATE_CON(10), 0, GFLAGS),
1321 COMPOSITE(SCLK_I2C2, "clk_i2c2", mux_pll_src_cpll_gpll_p, 0,
1322 RK3399_CLKSEL_CON(62), 7, 1, MFLAGS, 0, 7, DFLAGS,
1323 RK3399_CLKGATE_CON(10), 2, GFLAGS),
1325 COMPOSITE(SCLK_I2C3, "clk_i2c3", mux_pll_src_cpll_gpll_p, 0,
1326 RK3399_CLKSEL_CON(63), 7, 1, MFLAGS, 0, 7, DFLAGS,
1327 RK3399_CLKGATE_CON(10), 4, GFLAGS),
1329 COMPOSITE(SCLK_I2C5, "clk_i2c5", mux_pll_src_cpll_gpll_p, 0,
1330 RK3399_CLKSEL_CON(61), 15, 1, MFLAGS, 8, 7, DFLAGS,
1331 RK3399_CLKGATE_CON(10), 1, GFLAGS),
1333 COMPOSITE(SCLK_I2C6, "clk_i2c6", mux_pll_src_cpll_gpll_p, 0,
1334 RK3399_CLKSEL_CON(62), 15, 1, MFLAGS, 8, 7, DFLAGS,
1335 RK3399_CLKGATE_CON(10), 3, GFLAGS),
1337 COMPOSITE(SCLK_I2C7, "clk_i2c7", mux_pll_src_cpll_gpll_p, 0,
1338 RK3399_CLKSEL_CON(63), 15, 1, MFLAGS, 8, 7, DFLAGS,
1339 RK3399_CLKGATE_CON(10), 5, GFLAGS),
1342 GATE(SCLK_TIMER00, "clk_timer00", "xin24m", 0, RK3399_CLKGATE_CON(26), 0, GFLAGS),
1343 GATE(SCLK_TIMER01, "clk_timer01", "xin24m", 0, RK3399_CLKGATE_CON(26), 1, GFLAGS),
1344 GATE(SCLK_TIMER02, "clk_timer02", "xin24m", 0, RK3399_CLKGATE_CON(26), 2, GFLAGS),
1345 GATE(SCLK_TIMER03, "clk_timer03", "xin24m", 0, RK3399_CLKGATE_CON(26), 3, GFLAGS),
1346 GATE(SCLK_TIMER04, "clk_timer04", "xin24m", 0, RK3399_CLKGATE_CON(26), 4, GFLAGS),
1347 GATE(SCLK_TIMER05, "clk_timer05", "xin24m", 0, RK3399_CLKGATE_CON(26), 5, GFLAGS),
1348 GATE(SCLK_TIMER06, "clk_timer06", "xin24m", 0, RK3399_CLKGATE_CON(26), 6, GFLAGS),
1349 GATE(SCLK_TIMER07, "clk_timer07", "xin24m", 0, RK3399_CLKGATE_CON(26), 7, GFLAGS),
1350 GATE(SCLK_TIMER08, "clk_timer08", "xin24m", 0, RK3399_CLKGATE_CON(26), 8, GFLAGS),
1351 GATE(SCLK_TIMER09, "clk_timer09", "xin24m", 0, RK3399_CLKGATE_CON(26), 9, GFLAGS),
1352 GATE(SCLK_TIMER10, "clk_timer10", "xin24m", 0, RK3399_CLKGATE_CON(26), 10, GFLAGS),
1353 GATE(SCLK_TIMER11, "clk_timer11", "xin24m", 0, RK3399_CLKGATE_CON(26), 11, GFLAGS),
1356 /* clk_test_pre is controlled by CRU_MISC_CON[3] */
1357 COMPOSITE_NOMUX(0, "clk_test", "clk_test_pre", CLK_IGNORE_UNUSED,
1358 RK3368_CLKSEL_CON(58), 0, 5, DFLAGS,
1359 RK3368_CLKGATE_CON(13), 11, GFLAGS),
1362 static struct rockchip_clk_branch rk3399_clk_pmu_branches[] __initdata = {
1364 * PMU CRU Clock-Architecture
1367 GATE(0, "fclk_cm0s_pmu_ppll_src", "ppll", 0,
1368 RK3399_PMU_CLKGATE_CON(0), 1, GFLAGS),
1370 COMPOSITE_NOGATE(FCLK_CM0S_SRC_PMU, "fclk_cm0s_src_pmu", mux_fclk_cm0s_pmu_ppll_p, 0,
1371 RK3399_PMU_CLKSEL_CON(0), 15, 1, MFLAGS, 8, 5, DFLAGS),
1373 COMPOSITE(SCLK_SPI3_PMU, "clk_spi3_pmu", mux_24m_ppll_p, 0,
1374 RK3399_PMU_CLKSEL_CON(1), 7, 1, MFLAGS, 0, 7, DFLAGS,
1375 RK3399_PMU_CLKGATE_CON(0), 2, GFLAGS),
1377 COMPOSITE(0, "clk_wifi_div", mux_ppll_24m_p, CLK_IGNORE_UNUSED,
1378 RK3399_PMU_CLKSEL_CON(1), 13, 1, MFLAGS, 8, 5, DFLAGS,
1379 RK3399_PMU_CLKGATE_CON(0), 8, GFLAGS),
1381 COMPOSITE_FRACMUX_NOGATE(0, "clk_wifi_frac", "clk_wifi_div", CLK_SET_RATE_PARENT,
1382 RK3399_PMU_CLKSEL_CON(7), 0,
1383 &rk3399_pmuclk_wifi_fracmux),
1385 MUX(0, "clk_timer_src_pmu", mux_pll_p, CLK_IGNORE_UNUSED,
1386 RK3399_PMU_CLKSEL_CON(1), 15, 1, MFLAGS),
1388 COMPOSITE_NOMUX(SCLK_I2C0_PMU, "clk_i2c0_pmu", "ppll", 0,
1389 RK3399_PMU_CLKSEL_CON(2), 0, 7, DFLAGS,
1390 RK3399_PMU_CLKGATE_CON(0), 9, GFLAGS),
1392 COMPOSITE_NOMUX(SCLK_I2C4_PMU, "clk_i2c4_pmu", "ppll", 0,
1393 RK3399_PMU_CLKSEL_CON(3), 0, 7, DFLAGS,
1394 RK3399_PMU_CLKGATE_CON(0), 10, GFLAGS),
1396 COMPOSITE_NOMUX(SCLK_I2C8_PMU, "clk_i2c8_pmu", "ppll", 0,
1397 RK3399_PMU_CLKSEL_CON(2), 8, 7, DFLAGS,
1398 RK3399_PMU_CLKGATE_CON(0), 11, GFLAGS),
1400 DIV(0, "clk_32k_suspend_pmu", "xin24m", CLK_IGNORE_UNUSED,
1401 RK3399_PMU_CLKSEL_CON(4), 0, 10, DFLAGS),
1402 MUX(0, "clk_testout_2io", mux_clk_testout2_2io_p, CLK_IGNORE_UNUSED,
1403 RK3399_PMU_CLKSEL_CON(4), 15, 1, MFLAGS),
1405 COMPOSITE(0, "clk_uart4_div", mux_24m_ppll_p, 0,
1406 RK3399_PMU_CLKSEL_CON(5), 10, 1, MFLAGS, 0, 7, DFLAGS,
1407 RK3399_PMU_CLKGATE_CON(0), 5, GFLAGS),
1409 COMPOSITE_FRACMUX(0, "clk_uart4_frac", "clk_uart4_div", CLK_SET_RATE_PARENT,
1410 RK3399_PMU_CLKSEL_CON(6), 0,
1411 RK3399_PMU_CLKGATE_CON(0), 6, GFLAGS,
1412 &rk3399_uart4_pmu_fracmux),
1414 DIV(PCLK_SRC_PMU, "pclk_pmu_src", "ppll", CLK_IGNORE_UNUSED,
1415 RK3399_PMU_CLKSEL_CON(0), 0, 5, DFLAGS),
1417 /* pmu clock gates */
1418 GATE(SCLK_TIMER12_PMU, "clk_timer0_pmu", "clk_timer_src_pmu", 0, RK3399_PMU_CLKGATE_CON(0), 3, GFLAGS),
1419 GATE(SCLK_TIMER13_PMU, "clk_timer1_pmu", "clk_timer_src_pmu", 0, RK3399_PMU_CLKGATE_CON(0), 4, GFLAGS),
1421 GATE(SCLK_PVTM_PMU, "clk_pvtm_pmu", "xin24m", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(0), 7, GFLAGS),
1423 GATE(PCLK_PMU, "pclk_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1), 0, GFLAGS),
1424 GATE(PCLK_PMUGRF_PMU, "pclk_pmugrf_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1), 1, GFLAGS),
1425 GATE(PCLK_INTMEM1_PMU, "pclk_intmem1_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1), 2, GFLAGS),
1426 GATE(PCLK_GPIO0_PMU, "pclk_gpio0_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 3, GFLAGS),
1427 GATE(PCLK_GPIO1_PMU, "pclk_gpio1_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 4, GFLAGS),
1428 GATE(PCLK_SGRF_PMU, "pclk_sgrf_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1), 5, GFLAGS),
1429 GATE(PCLK_NOC_PMU, "pclk_noc_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1), 6, GFLAGS),
1430 GATE(PCLK_I2C0_PMU, "pclk_i2c0_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 7, GFLAGS),
1431 GATE(PCLK_I2C4_PMU, "pclk_i2c4_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 8, GFLAGS),
1432 GATE(PCLK_I2C8_PMU, "pclk_i2c8_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 9, GFLAGS),
1433 GATE(PCLK_RKPWM_PMU, "pclk_rkpwm_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 10, GFLAGS),
1434 GATE(PCLK_SPI3_PMU, "pclk_spi3_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 11, GFLAGS),
1435 GATE(PCLK_TIMER_PMU, "pclk_timer_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 12, GFLAGS),
1436 GATE(PCLK_MAILBOX_PMU, "pclk_mailbox_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 13, GFLAGS),
1437 GATE(PCLK_UART4_PMU, "pclk_uart4_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 14, GFLAGS),
1438 GATE(PCLK_WDT_M0_PMU, "pclk_wdt_m0_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 15, GFLAGS),
1440 GATE(FCLK_CM0S_PMU, "fclk_cm0s_pmu", "fclk_cm0s_src_pmu", 0, RK3399_PMU_CLKGATE_CON(2), 0, GFLAGS),
1441 GATE(SCLK_CM0S_PMU, "sclk_cm0s_pmu", "fclk_cm0s_src_pmu", 0, RK3399_PMU_CLKGATE_CON(2), 1, GFLAGS),
1442 GATE(HCLK_CM0S_PMU, "hclk_cm0s_pmu", "fclk_cm0s_src_pmu", 0, RK3399_PMU_CLKGATE_CON(2), 2, GFLAGS),
1443 GATE(DCLK_CM0S_PMU, "dclk_cm0s_pmu", "fclk_cm0s_src_pmu", 0, RK3399_PMU_CLKGATE_CON(2), 3, GFLAGS),
1444 GATE(HCLK_NOC_PMU, "hclk_noc_pmu", "fclk_cm0s_src_pmu", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(2), 5, GFLAGS),
1447 static const char *const rk3399_cru_critical_clocks[] __initconst = {
1449 * We need to declare that we enable all NOCs which are critical clocks
1450 * always and clearly and explicitly show that we have enabled them at
1456 "pclk_center_main_noc",
1468 "aclk_center_main_noc",
1469 "aclk_center_peri_noc",
1477 "hclk_m0_perilp_noc",
1480 "hclk_sdioaudio_noc",
1497 /* other critical clocks */
1507 "aclk_dmac1_perilp",
1508 "gpll_aclk_perilp0_src",
1509 "gpll_aclk_perihp_src",
1512 static const char *const rk3399_pmucru_critical_clocks[] __initconst = {
1514 * We need to declare that we enable all NOCs which are critical clocks
1515 * always and clearly and explicitly show that we have enabled them at
1521 /* other critical clocks */
1524 "fclk_cm0s_src_pmu",
1525 "clk_timer_src_pmu",
1529 static void __init rk3399_clk_init(struct device_node *np)
1531 struct rockchip_clk_provider *ctx;
1532 void __iomem *reg_base;
1534 reg_base = of_iomap(np, 0);
1536 pr_err("%s: could not map cru region\n", __func__);
1540 ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
1542 pr_err("%s: rockchip clk init failed\n", __func__);
1546 rockchip_clk_register_plls(ctx, rk3399_pll_clks,
1547 ARRAY_SIZE(rk3399_pll_clks), -1);
1549 rockchip_clk_register_branches(ctx, rk3399_clk_branches,
1550 ARRAY_SIZE(rk3399_clk_branches));
1552 rockchip_clk_protect_critical(rk3399_cru_critical_clocks,
1553 ARRAY_SIZE(rk3399_cru_critical_clocks));
1555 rockchip_clk_register_armclk(ctx, ARMCLKL, "armclkl",
1556 mux_armclkl_p, ARRAY_SIZE(mux_armclkl_p),
1557 &rk3399_cpuclkl_data, rk3399_cpuclkl_rates,
1558 ARRAY_SIZE(rk3399_cpuclkl_rates));
1560 rockchip_clk_register_armclk(ctx, ARMCLKB, "armclkb",
1561 mux_armclkb_p, ARRAY_SIZE(mux_armclkb_p),
1562 &rk3399_cpuclkb_data, rk3399_cpuclkb_rates,
1563 ARRAY_SIZE(rk3399_cpuclkb_rates));
1565 rockchip_register_softrst(np, 21, reg_base + RK3399_SOFTRST_CON(0),
1566 ROCKCHIP_SOFTRST_HIWORD_MASK);
1568 rockchip_register_restart_notifier(ctx, RK3399_GLB_SRST_FST, NULL);
1570 rockchip_clk_of_add_provider(np, ctx);
1572 CLK_OF_DECLARE(rk3399_cru, "rockchip,rk3399-cru", rk3399_clk_init);
1574 static void __init rk3399_pmu_clk_init(struct device_node *np)
1576 struct rockchip_clk_provider *ctx;
1577 void __iomem *reg_base;
1579 reg_base = of_iomap(np, 0);
1581 pr_err("%s: could not map cru pmu region\n", __func__);
1585 ctx = rockchip_clk_init(np, reg_base, CLKPMU_NR_CLKS);
1587 pr_err("%s: rockchip pmu clk init failed\n", __func__);
1591 rockchip_clk_register_plls(ctx, rk3399_pmu_pll_clks,
1592 ARRAY_SIZE(rk3399_pmu_pll_clks), -1);
1594 rockchip_clk_register_branches(ctx, rk3399_clk_pmu_branches,
1595 ARRAY_SIZE(rk3399_clk_pmu_branches));
1597 rockchip_clk_protect_critical(rk3399_pmucru_critical_clocks,
1598 ARRAY_SIZE(rk3399_pmucru_critical_clocks));
1600 rockchip_register_softrst(np, 2, reg_base + RK3399_PMU_SOFTRST_CON(0),
1601 ROCKCHIP_SOFTRST_HIWORD_MASK);
1603 rockchip_clk_of_add_provider(np, ctx);
1605 CLK_OF_DECLARE(rk3399_cru_pmu, "rockchip,rk3399-pmucru", rk3399_pmu_clk_init);
projects / firefly-linux-kernel-4.4.55.git / blob