2 * Copyright (c) 2014 MundoReader S.L.
3 * Author: Heiko Stuebner <heiko@sntech.de>
5 * Copyright (c) 2015 Rockchip Electronics Co. Ltd.
6 * Author: Xing Zheng <zhengxing@rock-chips.com>
11 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
12 * Copyright (c) 2013 Linaro Ltd.
13 * Author: Thomas Abraham <thomas.ab@samsung.com>
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2 of the License, or
18 * (at your option) any later version.
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
26 #ifndef CLK_ROCKCHIP_CLK_H
27 #define CLK_ROCKCHIP_CLK_H
30 #include <linux/clk-provider.h>
34 #define HIWORD_UPDATE(val, mask, shift) \
35 ((val) << (shift) | (mask) << ((shift) + 16))
37 /* register positions shared by RK2928, RK3036, RK3066, RK3188 and RK3228 */
38 #define RK2928_PLL_CON(x) ((x) * 0x4)
39 #define RK2928_MODE_CON 0x40
40 #define RK2928_CLKSEL_CON(x) ((x) * 0x4 + 0x44)
41 #define RK2928_CLKGATE_CON(x) ((x) * 0x4 + 0xd0)
42 #define RK2928_GLB_SRST_FST 0x100
43 #define RK2928_GLB_SRST_SND 0x104
44 #define RK2928_SOFTRST_CON(x) ((x) * 0x4 + 0x110)
45 #define RK2928_MISC_CON 0x134
47 #define RK3036_SDMMC_CON0 0x144
48 #define RK3036_SDMMC_CON1 0x148
49 #define RK3036_SDIO_CON0 0x14c
50 #define RK3036_SDIO_CON1 0x150
51 #define RK3036_EMMC_CON0 0x154
52 #define RK3036_EMMC_CON1 0x158
54 #define RK3228_GLB_SRST_FST 0x1f0
55 #define RK3228_GLB_SRST_SND 0x1f4
56 #define RK3228_SDMMC_CON0 0x1c0
57 #define RK3228_SDMMC_CON1 0x1c4
58 #define RK3228_SDIO_CON0 0x1c8
59 #define RK3228_SDIO_CON1 0x1cc
60 #define RK3228_EMMC_CON0 0x1d8
61 #define RK3228_EMMC_CON1 0x1dc
63 #define RK3288_PLL_CON(x) RK2928_PLL_CON(x)
64 #define RK3288_MODE_CON 0x50
65 #define RK3288_CLKSEL_CON(x) ((x) * 0x4 + 0x60)
66 #define RK3288_CLKGATE_CON(x) ((x) * 0x4 + 0x160)
67 #define RK3288_GLB_SRST_FST 0x1b0
68 #define RK3288_GLB_SRST_SND 0x1b4
69 #define RK3288_SOFTRST_CON(x) ((x) * 0x4 + 0x1b8)
70 #define RK3288_MISC_CON 0x1e8
71 #define RK3288_SDMMC_CON0 0x200
72 #define RK3288_SDMMC_CON1 0x204
73 #define RK3288_SDIO0_CON0 0x208
74 #define RK3288_SDIO0_CON1 0x20c
75 #define RK3288_SDIO1_CON0 0x210
76 #define RK3288_SDIO1_CON1 0x214
77 #define RK3288_EMMC_CON0 0x218
78 #define RK3288_EMMC_CON1 0x21c
80 #define RK3328_PLL_CON(x) RK2928_PLL_CON(x)
81 #define RK3328_CLKSEL_CON(x) ((x) * 0x4 + 0x100)
82 #define RK3328_CLKGATE_CON(x) ((x) * 0x4 + 0x200)
83 #define RK3328_GRFCLKSEL_CON(x) ((x) * 0x4 + 0x100)
84 #define RK3328_GLB_SRST_FST 0x9c
85 #define RK3328_GLB_SRST_SND 0x98
86 #define RK3328_SOFTRST_CON(x) ((x) * 0x4 + 0x300)
87 #define RK3328_MODE_CON 0x80
88 #define RK3328_MISC_CON 0x84
89 #define RK3328_SDMMC_CON0 0x380
90 #define RK3328_SDMMC_CON1 0x384
91 #define RK3328_SDIO_CON0 0x388
92 #define RK3328_SDIO_CON1 0x38c
93 #define RK3328_EMMC_CON0 0x390
94 #define RK3328_EMMC_CON1 0x394
95 #define RK3328_SDMMC_EXT_CON0 0x398
96 #define RK3328_SDMMC_EXT_CON1 0x39C
98 #define RK3368_PLL_CON(x) RK2928_PLL_CON(x)
99 #define RK3368_CLKSEL_CON(x) ((x) * 0x4 + 0x100)
100 #define RK3368_CLKGATE_CON(x) ((x) * 0x4 + 0x200)
101 #define RK3368_GLB_SRST_FST 0x280
102 #define RK3368_GLB_SRST_SND 0x284
103 #define RK3368_SOFTRST_CON(x) ((x) * 0x4 + 0x300)
104 #define RK3368_MISC_CON 0x380
105 #define RK3368_SDMMC_CON0 0x400
106 #define RK3368_SDMMC_CON1 0x404
107 #define RK3368_SDIO0_CON0 0x408
108 #define RK3368_SDIO0_CON1 0x40c
109 #define RK3368_SDIO1_CON0 0x410
110 #define RK3368_SDIO1_CON1 0x414
111 #define RK3368_EMMC_CON0 0x418
112 #define RK3368_EMMC_CON1 0x41c
114 #define RK3399_PLL_CON(x) RK2928_PLL_CON(x)
115 #define RK3399_CLKSEL_CON(x) ((x) * 0x4 + 0x100)
116 #define RK3399_CLKGATE_CON(x) ((x) * 0x4 + 0x300)
117 #define RK3399_SOFTRST_CON(x) ((x) * 0x4 + 0x400)
118 #define RK3399_GLB_SRST_FST 0x500
119 #define RK3399_GLB_SRST_SND 0x504
120 #define RK3399_GLB_CNT_TH 0x508
121 #define RK3399_MISC_CON 0x50c
122 #define RK3399_RST_CON 0x510
123 #define RK3399_RST_ST 0x514
124 #define RK3399_SDMMC_CON0 0x580
125 #define RK3399_SDMMC_CON1 0x584
126 #define RK3399_SDIO_CON0 0x588
127 #define RK3399_SDIO_CON1 0x58c
129 #define RK3399_PMU_PLL_CON(x) RK2928_PLL_CON(x)
130 #define RK3399_PMU_CLKSEL_CON(x) ((x) * 0x4 + 0x80)
131 #define RK3399_PMU_CLKGATE_CON(x) ((x) * 0x4 + 0x100)
132 #define RK3399_PMU_SOFTRST_CON(x) ((x) * 0x4 + 0x110)
133 #define RK3399_PMU_RSTNHOLD_CON(x) ((x) * 0x4 + 0x120)
134 #define RK3399_PMU_GATEDIS_CON(x) ((x) * 0x4 + 0x130)
136 enum rockchip_pll_type {
144 #define RK3036_PLL_RATE(_rate, _refdiv, _fbdiv, _postdiv1, \
145 _postdiv2, _dsmpd, _frac) \
149 .postdiv1 = _postdiv1, \
151 .postdiv2 = _postdiv2, \
156 #define RK3066_PLL_RATE(_rate, _nr, _nf, _no) \
162 .nb = ((_nf) < 2) ? 1 : (_nf) >> 1, \
165 #define RK3066_PLL_RATE_NB(_rate, _nr, _nf, _no, _nb) \
175 * struct rockchip_clk_provider - information about clock provider
176 * @reg_base: virtual address for the register base.
177 * @clk_data: holds clock related data like clk* and number of clocks.
178 * @cru_node: device-node of the clock-provider
179 * @grf: regmap of the general-register-files syscon
180 * @lock: maintains exclusion between callbacks for a given clock-provider.
182 struct rockchip_clk_provider {
183 void __iomem *reg_base;
184 struct clk_onecell_data clk_data;
185 struct device_node *cru_node;
190 struct rockchip_pll_rate_table {
196 /* for RK3036/RK3399 */
198 unsigned int postdiv1;
200 unsigned int postdiv2;
206 * struct rockchip_pll_clock - information about pll clock
207 * @id: platform specific id of the clock.
208 * @name: name of this pll clock.
209 * @parent_names: name of the parent clock.
210 * @num_parents: number of parents
211 * @flags: optional flags for basic clock.
212 * @con_offset: offset of the register for configuring the PLL.
213 * @mode_offset: offset of the register for configuring the PLL-mode.
214 * @mode_shift: offset inside the mode-register for the mode of this pll.
215 * @lock_shift: offset inside the lock register for the lock status.
216 * @type: Type of PLL to be registered.
217 * @pll_flags: hardware-specific flags
218 * @rate_table: Table of usable pll rates
221 * ROCKCHIP_PLL_SYNC_RATE - check rate parameters to match against the
222 * rate_table parameters and ajust them if necessary.
224 struct rockchip_pll_clock {
227 const char *const *parent_names;
234 enum rockchip_pll_type type;
236 struct rockchip_pll_rate_table *rate_table;
239 #define ROCKCHIP_PLL_SYNC_RATE BIT(0)
241 #define PLL(_type, _id, _name, _pnames, _flags, _con, _mode, _mshift, \
242 _lshift, _pflags, _rtable) \
247 .parent_names = _pnames, \
248 .num_parents = ARRAY_SIZE(_pnames), \
249 .flags = CLK_GET_RATE_NOCACHE | _flags, \
250 .con_offset = _con, \
251 .mode_offset = _mode, \
252 .mode_shift = _mshift, \
253 .lock_shift = _lshift, \
254 .pll_flags = _pflags, \
255 .rate_table = _rtable, \
258 struct clk *rockchip_clk_register_pll(struct rockchip_clk_provider *ctx,
259 enum rockchip_pll_type pll_type,
260 const char *name, const char *const *parent_names,
261 u8 num_parents, int con_offset, int grf_lock_offset,
262 int lock_shift, int mode_offset, int mode_shift,
263 struct rockchip_pll_rate_table *rate_table,
264 unsigned long flags, u8 clk_pll_flags);
266 struct rockchip_cpuclk_clksel {
271 #define ROCKCHIP_CPUCLK_NUM_DIVIDERS 2
272 struct rockchip_cpuclk_rate_table {
274 struct rockchip_cpuclk_clksel divs[ROCKCHIP_CPUCLK_NUM_DIVIDERS];
278 * struct rockchip_cpuclk_reg_data - describes register offsets and masks of the cpuclock
279 * @core_reg: register offset of the core settings register
280 * @div_core_shift: core divider offset used to divide the pll value
281 * @div_core_mask: core divider mask
282 * @mux_core_alt: mux value to select alternate parent
283 * @mux_core_main: mux value to select main parent of core
284 * @mux_core_shift: offset of the core multiplexer
285 * @mux_core_mask: core multiplexer mask
287 struct rockchip_cpuclk_reg_data {
297 struct clk *rockchip_clk_register_cpuclk(const char *name,
298 const char *const *parent_names, u8 num_parents,
299 const struct rockchip_cpuclk_reg_data *reg_data,
300 const struct rockchip_cpuclk_rate_table *rates,
301 int nrates, void __iomem *reg_base, spinlock_t *lock);
303 struct clk *rockchip_clk_register_mmc(const char *name,
304 const char *const *parent_names, u8 num_parents,
305 void __iomem *reg, int shift);
308 * for COMPOSITE_DDRCLK div_flag,
309 * there may have serval ways to set ddr clock, use
310 * this flag to distinguish them.
311 * ROCKCHIP_DDRCLK_SIP: use SIP call to bl31 to change ddrclk rate.
312 * ROCKCHIP_DDRCLK_SCPI: use SCPI APIs to let mcu change ddrclk rate.
314 #define ROCKCHIP_DDRCLK_SIP 0x01
315 #define ROCKCHIP_DDRCLK_SCPI 0x02
317 struct clk *rockchip_clk_register_ddrclk(const char *name, int flags,
318 const char *const *parent_names,
319 u8 num_parents, int mux_offset,
320 int mux_shift, int mux_width,
321 int div_shift, int div_width,
322 int ddr_flags, void __iomem *reg_base,
325 #define ROCKCHIP_INVERTER_HIWORD_MASK BIT(0)
327 struct clk *rockchip_clk_register_inverter(const char *name,
328 const char *const *parent_names, u8 num_parents,
329 void __iomem *reg, int shift, int flags,
332 struct clk *rockchip_clk_register_muxgrf(const char *name,
333 const char *const *parent_names, u8 num_parents,
334 int flags, struct regmap *grf, int reg,
335 int shift, int width, int mux_flags);
337 #define PNAME(x) static const char *const x[] __initconst
339 enum rockchip_clk_branch_type {
344 branch_fraction_divider,
352 struct rockchip_clk_branch {
354 enum rockchip_clk_branch_type branch_type;
356 const char *const *parent_names;
366 struct clk_div_table *div_table;
370 struct rockchip_clk_branch *child;
373 #define COMPOSITE(_id, cname, pnames, f, mo, ms, mw, mf, ds, dw,\
377 .branch_type = branch_composite, \
379 .parent_names = pnames, \
380 .num_parents = ARRAY_SIZE(pnames), \
382 .muxdiv_offset = mo, \
394 #define COMPOSITE_NOMUX(_id, cname, pname, f, mo, ds, dw, df, \
398 .branch_type = branch_composite, \
400 .parent_names = (const char *[]){ pname }, \
403 .muxdiv_offset = mo, \
412 #define COMPOSITE_NOMUX_DIVTBL(_id, cname, pname, f, mo, ds, dw,\
413 df, dt, go, gs, gf) \
416 .branch_type = branch_composite, \
418 .parent_names = (const char *[]){ pname }, \
421 .muxdiv_offset = mo, \
431 #define COMPOSITE_NODIV(_id, cname, pnames, f, mo, ms, mw, mf, \
435 .branch_type = branch_composite, \
437 .parent_names = pnames, \
438 .num_parents = ARRAY_SIZE(pnames), \
440 .muxdiv_offset = mo, \
449 #define COMPOSITE_NOGATE(_id, cname, pnames, f, mo, ms, mw, mf, \
453 .branch_type = branch_composite, \
455 .parent_names = pnames, \
456 .num_parents = ARRAY_SIZE(pnames), \
458 .muxdiv_offset = mo, \
468 #define COMPOSITE_NOGATE_DIVTBL(_id, cname, pnames, f, mo, ms, \
469 mw, mf, ds, dw, df, dt) \
472 .branch_type = branch_composite, \
474 .parent_names = pnames, \
475 .num_parents = ARRAY_SIZE(pnames), \
477 .muxdiv_offset = mo, \
488 #define COMPOSITE_FRAC(_id, cname, pname, f, mo, df, go, gs, gf)\
491 .branch_type = branch_fraction_divider, \
493 .parent_names = (const char *[]){ pname }, \
496 .muxdiv_offset = mo, \
505 #define COMPOSITE_FRACMUX(_id, cname, pname, f, mo, df, go, gs, gf, ch) \
508 .branch_type = branch_fraction_divider, \
510 .parent_names = (const char *[]){ pname }, \
513 .muxdiv_offset = mo, \
523 #define COMPOSITE_FRACMUX_NOGATE(_id, cname, pname, f, mo, df, ch) \
526 .branch_type = branch_fraction_divider, \
528 .parent_names = (const char *[]){ pname }, \
531 .muxdiv_offset = mo, \
539 #define COMPOSITE_DDRCLK(_id, cname, pnames, f, mo, ms, mw, \
543 .branch_type = branch_ddrc, \
545 .parent_names = pnames, \
546 .num_parents = ARRAY_SIZE(pnames), \
548 .muxdiv_offset = mo, \
557 #define MUX(_id, cname, pnames, f, o, s, w, mf) \
560 .branch_type = branch_mux, \
562 .parent_names = pnames, \
563 .num_parents = ARRAY_SIZE(pnames), \
565 .muxdiv_offset = o, \
572 #define MUXGRF(_id, cname, pnames, f, o, s, w, mf) \
575 .branch_type = branch_muxgrf, \
577 .parent_names = pnames, \
578 .num_parents = ARRAY_SIZE(pnames), \
580 .muxdiv_offset = o, \
587 #define DIV(_id, cname, pname, f, o, s, w, df) \
590 .branch_type = branch_divider, \
592 .parent_names = (const char *[]){ pname }, \
595 .muxdiv_offset = o, \
602 #define DIVTBL(_id, cname, pname, f, o, s, w, df, dt) \
605 .branch_type = branch_divider, \
607 .parent_names = (const char *[]){ pname }, \
610 .muxdiv_offset = o, \
617 #define GATE(_id, cname, pname, f, o, b, gf) \
620 .branch_type = branch_gate, \
622 .parent_names = (const char *[]){ pname }, \
630 #define MMC(_id, cname, pname, offset, shift) \
633 .branch_type = branch_mmc, \
635 .parent_names = (const char *[]){ pname }, \
637 .muxdiv_offset = offset, \
638 .div_shift = shift, \
641 #define INVERTER(_id, cname, pname, io, is, if) \
644 .branch_type = branch_inverter, \
646 .parent_names = (const char *[]){ pname }, \
648 .muxdiv_offset = io, \
653 #define FACTOR(_id, cname, pname, f, fm, fd) \
656 .branch_type = branch_factor, \
658 .parent_names = (const char *[]){ pname }, \
665 #define FACTOR_GATE(_id, cname, pname, f, fm, fd, go, gb, gf) \
668 .branch_type = branch_factor, \
670 .parent_names = (const char *[]){ pname }, \
680 struct rockchip_clk_provider *rockchip_clk_init(struct device_node *np,
681 void __iomem *base, unsigned long nr_clks);
682 void rockchip_clk_of_add_provider(struct device_node *np,
683 struct rockchip_clk_provider *ctx);
684 struct regmap *rockchip_clk_get_grf(struct rockchip_clk_provider *ctx);
685 void rockchip_clk_add_lookup(struct rockchip_clk_provider *ctx,
686 struct clk *clk, unsigned int id);
687 void rockchip_clk_register_branches(struct rockchip_clk_provider *ctx,
688 struct rockchip_clk_branch *list,
689 unsigned int nr_clk);
690 void rockchip_clk_register_plls(struct rockchip_clk_provider *ctx,
691 struct rockchip_pll_clock *pll_list,
692 unsigned int nr_pll, int grf_lock_offset);
693 void rockchip_clk_register_armclk(struct rockchip_clk_provider *ctx,
694 unsigned int lookup_id, const char *name,
695 const char *const *parent_names, u8 num_parents,
696 const struct rockchip_cpuclk_reg_data *reg_data,
697 const struct rockchip_cpuclk_rate_table *rates,
699 void rockchip_clk_protect_critical(const char *const clocks[], int nclocks);
700 void rockchip_register_restart_notifier(struct rockchip_clk_provider *ctx,
701 unsigned int reg, void (*cb)(void));
703 #define ROCKCHIP_SOFTRST_HIWORD_MASK BIT(0)
705 #ifdef CONFIG_RESET_CONTROLLER
706 void rockchip_register_softrst(struct device_node *np,
707 unsigned int num_regs,
708 void __iomem *base, u8 flags);
710 static inline void rockchip_register_softrst(struct device_node *np,
711 unsigned int num_regs,
712 void __iomem *base, u8 flags)