drivers/clk/samsung/clk-exynos5433.c

   1 /*
   2  * Copyright (c) 2014 Samsung Electronics Co., Ltd.
   3  * Author: Chanwoo Choi <cw00.choi@samsung.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  *
   9  * Common Clock Framework support for Exynos5443 SoC.
  10  */
  11
  12 #include <linux/clk.h>
  13 #include <linux/clkdev.h>
  14 #include <linux/clk-provider.h>
  15 #include <linux/of.h>
  16
  17 #include <dt-bindings/clock/exynos5433.h>
  18
  19 #include "clk.h"
  20 #include "clk-pll.h"
  21
  22 /*
  23  * Register offset definitions for CMU_TOP
  24  */
  25 #define ISP_PLL_LOCK                    0x0000
  26 #define AUD_PLL_LOCK                    0x0004
  27 #define ISP_PLL_CON0                    0x0100
  28 #define ISP_PLL_CON1                    0x0104
  29 #define ISP_PLL_FREQ_DET                0x0108
  30 #define AUD_PLL_CON0                    0x0110
  31 #define AUD_PLL_CON1                    0x0114
  32 #define AUD_PLL_CON2                    0x0118
  33 #define AUD_PLL_FREQ_DET                0x011c
  34 #define MUX_SEL_TOP0                    0x0200
  35 #define MUX_SEL_TOP1                    0x0204
  36 #define MUX_SEL_TOP2                    0x0208
  37 #define MUX_SEL_TOP3                    0x020c
  38 #define MUX_SEL_TOP4                    0x0210
  39 #define MUX_SEL_TOP_MSCL                0x0220
  40 #define MUX_SEL_TOP_CAM1                0x0224
  41 #define MUX_SEL_TOP_DISP                0x0228
  42 #define MUX_SEL_TOP_FSYS0               0x0230
  43 #define MUX_SEL_TOP_FSYS1               0x0234
  44 #define MUX_SEL_TOP_PERIC0              0x0238
  45 #define MUX_SEL_TOP_PERIC1              0x023c
  46 #define MUX_ENABLE_TOP0                 0x0300
  47 #define MUX_ENABLE_TOP1                 0x0304
  48 #define MUX_ENABLE_TOP2                 0x0308
  49 #define MUX_ENABLE_TOP3                 0x030c
  50 #define MUX_ENABLE_TOP4                 0x0310
  51 #define MUX_ENABLE_TOP_MSCL             0x0320
  52 #define MUX_ENABLE_TOP_CAM1             0x0324
  53 #define MUX_ENABLE_TOP_DISP             0x0328
  54 #define MUX_ENABLE_TOP_FSYS0            0x0330
  55 #define MUX_ENABLE_TOP_FSYS1            0x0334
  56 #define MUX_ENABLE_TOP_PERIC0           0x0338
  57 #define MUX_ENABLE_TOP_PERIC1           0x033c
  58 #define MUX_STAT_TOP0                   0x0400
  59 #define MUX_STAT_TOP1                   0x0404
  60 #define MUX_STAT_TOP2                   0x0408
  61 #define MUX_STAT_TOP3                   0x040c
  62 #define MUX_STAT_TOP4                   0x0410
  63 #define MUX_STAT_TOP_MSCL               0x0420
  64 #define MUX_STAT_TOP_CAM1               0x0424
  65 #define MUX_STAT_TOP_FSYS0              0x0430
  66 #define MUX_STAT_TOP_FSYS1              0x0434
  67 #define MUX_STAT_TOP_PERIC0             0x0438
  68 #define MUX_STAT_TOP_PERIC1             0x043c
  69 #define DIV_TOP0                        0x0600
  70 #define DIV_TOP1                        0x0604
  71 #define DIV_TOP2                        0x0608
  72 #define DIV_TOP3                        0x060c
  73 #define DIV_TOP4                        0x0610
  74 #define DIV_TOP_MSCL                    0x0618
  75 #define DIV_TOP_CAM10                   0x061c
  76 #define DIV_TOP_CAM11                   0x0620
  77 #define DIV_TOP_FSYS0                   0x062c
  78 #define DIV_TOP_FSYS1                   0x0630
  79 #define DIV_TOP_FSYS2                   0x0634
  80 #define DIV_TOP_PERIC0                  0x0638
  81 #define DIV_TOP_PERIC1                  0x063c
  82 #define DIV_TOP_PERIC2                  0x0640
  83 #define DIV_TOP_PERIC3                  0x0644
  84 #define DIV_TOP_PERIC4                  0x0648
  85 #define DIV_TOP_PLL_FREQ_DET            0x064c
  86 #define DIV_STAT_TOP0                   0x0700
  87 #define DIV_STAT_TOP1                   0x0704
  88 #define DIV_STAT_TOP2                   0x0708
  89 #define DIV_STAT_TOP3                   0x070c
  90 #define DIV_STAT_TOP4                   0x0710
  91 #define DIV_STAT_TOP_MSCL               0x0718
  92 #define DIV_STAT_TOP_CAM10              0x071c
  93 #define DIV_STAT_TOP_CAM11              0x0720
  94 #define DIV_STAT_TOP_FSYS0              0x072c
  95 #define DIV_STAT_TOP_FSYS1              0x0730
  96 #define DIV_STAT_TOP_FSYS2              0x0734
  97 #define DIV_STAT_TOP_PERIC0             0x0738
  98 #define DIV_STAT_TOP_PERIC1             0x073c
  99 #define DIV_STAT_TOP_PERIC2             0x0740
 100 #define DIV_STAT_TOP_PERIC3             0x0744
 101 #define DIV_STAT_TOP_PLL_FREQ_DET       0x074c
 102 #define ENABLE_ACLK_TOP                 0x0800
 103 #define ENABLE_SCLK_TOP                 0x0a00
 104 #define ENABLE_SCLK_TOP_MSCL            0x0a04
 105 #define ENABLE_SCLK_TOP_CAM1            0x0a08
 106 #define ENABLE_SCLK_TOP_DISP            0x0a0c
 107 #define ENABLE_SCLK_TOP_FSYS            0x0a10
 108 #define ENABLE_SCLK_TOP_PERIC           0x0a14
 109 #define ENABLE_IP_TOP                   0x0b00
 110 #define ENABLE_CMU_TOP                  0x0c00
 111 #define ENABLE_CMU_TOP_DIV_STAT         0x0c04
 112
 113 static unsigned long top_clk_regs[] __initdata = {
 114         ISP_PLL_LOCK,
 115         AUD_PLL_LOCK,
 116         ISP_PLL_CON0,
 117         ISP_PLL_CON1,
 118         ISP_PLL_FREQ_DET,
 119         AUD_PLL_CON0,
 120         AUD_PLL_CON1,
 121         AUD_PLL_CON2,
 122         AUD_PLL_FREQ_DET,
 123         MUX_SEL_TOP0,
 124         MUX_SEL_TOP1,
 125         MUX_SEL_TOP2,
 126         MUX_SEL_TOP3,
 127         MUX_SEL_TOP4,
 128         MUX_SEL_TOP_MSCL,
 129         MUX_SEL_TOP_CAM1,
 130         MUX_SEL_TOP_DISP,
 131         MUX_SEL_TOP_FSYS0,
 132         MUX_SEL_TOP_FSYS1,
 133         MUX_SEL_TOP_PERIC0,
 134         MUX_SEL_TOP_PERIC1,
 135         MUX_ENABLE_TOP0,
 136         MUX_ENABLE_TOP1,
 137         MUX_ENABLE_TOP2,
 138         MUX_ENABLE_TOP3,
 139         MUX_ENABLE_TOP4,
 140         MUX_ENABLE_TOP_MSCL,
 141         MUX_ENABLE_TOP_CAM1,
 142         MUX_ENABLE_TOP_DISP,
 143         MUX_ENABLE_TOP_FSYS0,
 144         MUX_ENABLE_TOP_FSYS1,
 145         MUX_ENABLE_TOP_PERIC0,
 146         MUX_ENABLE_TOP_PERIC1,
 147         MUX_STAT_TOP0,
 148         MUX_STAT_TOP1,
 149         MUX_STAT_TOP2,
 150         MUX_STAT_TOP3,
 151         MUX_STAT_TOP4,
 152         MUX_STAT_TOP_MSCL,
 153         MUX_STAT_TOP_CAM1,
 154         MUX_STAT_TOP_FSYS0,
 155         MUX_STAT_TOP_FSYS1,
 156         MUX_STAT_TOP_PERIC0,
 157         MUX_STAT_TOP_PERIC1,
 158         DIV_TOP0,
 159         DIV_TOP1,
 160         DIV_TOP2,
 161         DIV_TOP3,
 162         DIV_TOP4,
 163         DIV_TOP_MSCL,
 164         DIV_TOP_CAM10,
 165         DIV_TOP_CAM11,
 166         DIV_TOP_FSYS0,
 167         DIV_TOP_FSYS1,
 168         DIV_TOP_FSYS2,
 169         DIV_TOP_PERIC0,
 170         DIV_TOP_PERIC1,
 171         DIV_TOP_PERIC2,
 172         DIV_TOP_PERIC3,
 173         DIV_TOP_PERIC4,
 174         DIV_TOP_PLL_FREQ_DET,
 175         DIV_STAT_TOP0,
 176         DIV_STAT_TOP1,
 177         DIV_STAT_TOP2,
 178         DIV_STAT_TOP3,
 179         DIV_STAT_TOP4,
 180         DIV_STAT_TOP_MSCL,
 181         DIV_STAT_TOP_CAM10,
 182         DIV_STAT_TOP_CAM11,
 183         DIV_STAT_TOP_FSYS0,
 184         DIV_STAT_TOP_FSYS1,
 185         DIV_STAT_TOP_FSYS2,
 186         DIV_STAT_TOP_PERIC0,
 187         DIV_STAT_TOP_PERIC1,
 188         DIV_STAT_TOP_PERIC2,
 189         DIV_STAT_TOP_PERIC3,
 190         DIV_STAT_TOP_PLL_FREQ_DET,
 191         ENABLE_ACLK_TOP,
 192         ENABLE_SCLK_TOP,
 193         ENABLE_SCLK_TOP_MSCL,
 194         ENABLE_SCLK_TOP_CAM1,
 195         ENABLE_SCLK_TOP_DISP,
 196         ENABLE_SCLK_TOP_FSYS,
 197         ENABLE_SCLK_TOP_PERIC,
 198         ENABLE_IP_TOP,
 199         ENABLE_CMU_TOP,
 200         ENABLE_CMU_TOP_DIV_STAT,
 201 };
 202
 203 /* list of all parent clock list */
 204 PNAME(mout_aud_pll_p)           = { "oscclk", "fout_aud_pll", };
 205 PNAME(mout_isp_pll_p)           = { "oscclk", "fout_isp_pll", };
 206 PNAME(mout_aud_pll_user_p)      = { "oscclk", "mout_aud_pll", };
 207 PNAME(mout_mphy_pll_user_p)     = { "oscclk", "sclk_mphy_pll", };
 208 PNAME(mout_mfc_pll_user_p)      = { "oscclk", "sclk_mfc_pll", };
 209 PNAME(mout_bus_pll_user_p)      = { "oscclk", "sclk_bus_pll", };
 210 PNAME(mout_bus_pll_user_t_p)    = { "oscclk", "mout_bus_pll_user", };
 211 PNAME(mout_mphy_pll_user_t_p)   = { "oscclk", "mout_mphy_pll_user", };
 212
 213 PNAME(mout_bus_mfc_pll_user_p)  = { "mout_bus_pll_user", "mout_mfc_pll_user",};
 214 PNAME(mout_mfc_bus_pll_user_p)  = { "mout_mfc_pll_user", "mout_bus_pll_user",};
 215 PNAME(mout_aclk_cam1_552_b_p)   = { "mout_aclk_cam1_552_a",
 216                                     "mout_mfc_pll_user", };
 217 PNAME(mout_aclk_cam1_552_a_p)   = { "mout_isp_pll", "mout_bus_pll_user", };
 218
 219 PNAME(mout_aclk_mfc_400_c_p)    = { "mout_aclk_mfc_400_b",
 220                                     "mout_mphy_pll_user", };
 221 PNAME(mout_aclk_mfc_400_b_p)    = { "mout_aclk_mfc_400_a",
 222                                     "mout_bus_pll_user", };
 223 PNAME(mout_aclk_mfc_400_a_p)    = { "mout_mfc_pll_user", "mout_isp_pll", };
 224
 225 PNAME(mout_bus_mphy_pll_user_p) = { "mout_bus_pll_user",
 226                                     "mout_mphy_pll_user", };
 227 PNAME(mout_aclk_mscl_b_p)       = { "mout_aclk_mscl_400_a",
 228                                     "mout_mphy_pll_user", };
 229 PNAME(mout_aclk_g2d_400_b_p)    = { "mout_aclk_g2d_400_a",
 230                                     "mout_mphy_pll_user", };
 231
 232 PNAME(mout_sclk_jpeg_c_p)       = { "mout_sclk_jpeg_b", "mout_mphy_pll_user",};
 233 PNAME(mout_sclk_jpeg_b_p)       = { "mout_sclk_jpeg_a", "mout_mfc_pll_user", };
 234
 235 PNAME(mout_sclk_mmc2_b_p)       = { "mout_sclk_mmc2_a", "mout_mfc_pll_user",};
 236 PNAME(mout_sclk_mmc1_b_p)       = { "mout_sclk_mmc1_a", "mout_mfc_pll_user",};
 237 PNAME(mout_sclk_mmc0_d_p)       = { "mout_sclk_mmc0_c", "mout_isp_pll", };
 238 PNAME(mout_sclk_mmc0_c_p)       = { "mout_sclk_mmc0_b", "mout_mphy_pll_user",};
 239 PNAME(mout_sclk_mmc0_b_p)       = { "mout_sclk_mmc0_a", "mout_mfc_pll_user", };
 240
 241 PNAME(mout_sclk_spdif_p)        = { "sclk_audio0", "sclk_audio1",
 242                                     "oscclk", "ioclk_spdif_extclk", };
 243 PNAME(mout_sclk_audio1_p)       = { "ioclk_audiocdclk1", "oscclk",
 244                                     "mout_aud_pll_user_t",};
 245 PNAME(mout_sclk_audio0_p)       = { "ioclk_audiocdclk0", "oscclk",
 246                                     "mout_aud_pll_user_t",};
 247
 248 static struct samsung_fixed_rate_clock top_fixed_clks[] __initdata = {
 249         /* Xi2s{0|1}CDCLK input clock for I2S/PCM */
 250         FRATE(0, "ioclk_audiocdclk1", NULL, CLK_IS_ROOT, 100000000),
 251         FRATE(0, "ioclk_audiocdclk0", NULL, CLK_IS_ROOT, 100000000),
 252         /* Xi2s1SDI input clock for SPDIF */
 253         FRATE(0, "ioclk_spdif_extclk", NULL, CLK_IS_ROOT, 100000000),
 254         /* XspiCLK[4:0] input clock for SPI */
 255         FRATE(0, "ioclk_spi4_clk_in", NULL, CLK_IS_ROOT, 50000000),
 256         FRATE(0, "ioclk_spi3_clk_in", NULL, CLK_IS_ROOT, 50000000),
 257         FRATE(0, "ioclk_spi2_clk_in", NULL, CLK_IS_ROOT, 50000000),
 258         FRATE(0, "ioclk_spi1_clk_in", NULL, CLK_IS_ROOT, 50000000),
 259         FRATE(0, "ioclk_spi0_clk_in", NULL, CLK_IS_ROOT, 50000000),
 260         /* Xi2s1SCLK input clock for I2S1_BCLK */
 261         FRATE(0, "ioclk_i2s1_bclk_in", NULL, CLK_IS_ROOT, 12288000),
 262 };
 263
 264 static struct samsung_mux_clock top_mux_clks[] __initdata = {
 265         /* MUX_SEL_TOP0 */
 266         MUX(CLK_MOUT_AUD_PLL, "mout_aud_pll", mout_aud_pll_p, MUX_SEL_TOP0,
 267                         4, 1),
 268         MUX(CLK_MOUT_ISP_PLL, "mout_isp_pll", mout_isp_pll_p, MUX_SEL_TOP0,
 269                         0, 1),
 270
 271         /* MUX_SEL_TOP1 */
 272         MUX(CLK_MOUT_AUD_PLL_USER_T, "mout_aud_pll_user_t",
 273                         mout_aud_pll_user_p, MUX_SEL_TOP1, 12, 1),
 274         MUX(CLK_MOUT_MPHY_PLL_USER, "mout_mphy_pll_user", mout_mphy_pll_user_p,
 275                         MUX_SEL_TOP1, 8, 1),
 276         MUX(CLK_MOUT_MFC_PLL_USER, "mout_mfc_pll_user", mout_mfc_pll_user_p,
 277                         MUX_SEL_TOP1, 4, 1),
 278         MUX(CLK_MOUT_BUS_PLL_USER, "mout_bus_pll_user", mout_bus_pll_user_p,
 279                         MUX_SEL_TOP1, 0, 1),
 280
 281         /* MUX_SEL_TOP2 */
 282         MUX(CLK_MOUT_ACLK_HEVC_400, "mout_aclk_hevc_400",
 283                         mout_bus_mfc_pll_user_p, MUX_SEL_TOP2, 28, 1),
 284         MUX(CLK_MOUT_ACLK_CAM1_333, "mout_aclk_cam1_333",
 285                         mout_mfc_bus_pll_user_p, MUX_SEL_TOP2, 16, 1),
 286         MUX(CLK_MOUT_ACLK_CAM1_552_B, "mout_aclk_cam1_552_b",
 287                         mout_aclk_cam1_552_b_p, MUX_SEL_TOP2, 12, 1),
 288         MUX(CLK_MOUT_ACLK_CAM1_552_A, "mout_aclk_cam1_552_a",
 289                         mout_aclk_cam1_552_a_p, MUX_SEL_TOP2, 8, 1),
 290         MUX(CLK_MOUT_ACLK_ISP_DIS_400, "mout_aclk_isp_dis_400",
 291                         mout_bus_mfc_pll_user_p, MUX_SEL_TOP2, 4, 1),
 292         MUX(CLK_MOUT_ACLK_ISP_400, "mout_aclk_isp_400",
 293                         mout_bus_mfc_pll_user_p, MUX_SEL_TOP2, 0, 1),
 294
 295         /* MUX_SEL_TOP3 */
 296         MUX(CLK_MOUT_ACLK_BUS0_400, "mout_aclk_bus0_400",
 297                         mout_bus_mphy_pll_user_p, MUX_SEL_TOP3, 20, 1),
 298         MUX(CLK_MOUT_ACLK_MSCL_400_B, "mout_aclk_mscl_400_b",
 299                         mout_aclk_mscl_b_p, MUX_SEL_TOP3, 16, 1),
 300         MUX(CLK_MOUT_ACLK_MSCL_400_A, "mout_aclk_mscl_400_a",
 301                         mout_bus_mfc_pll_user_p, MUX_SEL_TOP3, 12, 1),
 302         MUX(CLK_MOUT_ACLK_GSCL_333, "mout_aclk_gscl_333",
 303                         mout_mfc_bus_pll_user_p, MUX_SEL_TOP3, 8, 1),
 304         MUX(CLK_MOUT_ACLK_G2D_400_B, "mout_aclk_g2d_400_b",
 305                         mout_aclk_g2d_400_b_p, MUX_SEL_TOP3, 4, 1),
 306         MUX(CLK_MOUT_ACLK_G2D_400_A, "mout_aclk_g2d_400_a",
 307                         mout_bus_mfc_pll_user_p, MUX_SEL_TOP3, 0, 1),
 308
 309         /* MUX_SEL_TOP4 */
 310         MUX(CLK_MOUT_ACLK_MFC_400_C, "mout_aclk_mfc_400_c",
 311                         mout_aclk_mfc_400_c_p, MUX_SEL_TOP4, 8, 1),
 312         MUX(CLK_MOUT_ACLK_MFC_400_B, "mout_aclk_mfc_400_b",
 313                         mout_aclk_mfc_400_b_p, MUX_SEL_TOP4, 4, 1),
 314         MUX(CLK_MOUT_ACLK_MFC_400_A, "mout_aclk_mfc_400_a",
 315                         mout_aclk_mfc_400_a_p, MUX_SEL_TOP4, 0, 1),
 316
 317         /* MUX_SEL_TOP_MSCL */
 318         MUX(CLK_MOUT_SCLK_JPEG_C, "mout_sclk_jpeg_c", mout_sclk_jpeg_c_p,
 319                         MUX_SEL_TOP_MSCL, 8, 1),
 320         MUX(CLK_MOUT_SCLK_JPEG_B, "mout_sclk_jpeg_b", mout_sclk_jpeg_b_p,
 321                         MUX_SEL_TOP_MSCL, 4, 1),
 322         MUX(CLK_MOUT_SCLK_JPEG_A, "mout_sclk_jpeg_a", mout_bus_pll_user_t_p,
 323                         MUX_SEL_TOP_MSCL, 0, 1),
 324
 325         /* MUX_SEL_TOP_CAM1 */
 326         MUX(CLK_MOUT_SCLK_ISP_SENSOR2, "mout_sclk_isp_sensor2",
 327                         mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 24, 1),
 328         MUX(CLK_MOUT_SCLK_ISP_SENSOR1, "mout_sclk_isp_sensor1",
 329                         mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 20, 1),
 330         MUX(CLK_MOUT_SCLK_ISP_SENSOR0, "mout_sclk_isp_sensor0",
 331                         mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 16, 1),
 332         MUX(CLK_MOUT_SCLK_ISP_UART, "mout_sclk_isp_uart",
 333                         mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 8, 1),
 334         MUX(CLK_MOUT_SCLK_ISP_SPI1, "mout_sclk_isp_spi1",
 335                         mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 4, 1),
 336         MUX(CLK_MOUT_SCLK_ISP_SPI0, "mout_sclk_isp_spi0",
 337                         mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 0, 1),
 338
 339         /* MUX_SEL_TOP_FSYS0 */
 340         MUX(CLK_MOUT_SCLK_MMC2_B, "mout_sclk_mmc2_b", mout_sclk_mmc2_b_p,
 341                         MUX_SEL_TOP_FSYS0, 28, 1),
 342         MUX(CLK_MOUT_SCLK_MMC2_A, "mout_sclk_mmc2_a", mout_bus_pll_user_t_p,
 343                         MUX_SEL_TOP_FSYS0, 24, 1),
 344         MUX(CLK_MOUT_SCLK_MMC1_B, "mout_sclk_mmc1_b", mout_sclk_mmc1_b_p,
 345                         MUX_SEL_TOP_FSYS0, 20, 1),
 346         MUX(CLK_MOUT_SCLK_MMC1_A, "mout_sclk_mmc1_a", mout_bus_pll_user_t_p,
 347                         MUX_SEL_TOP_FSYS0, 16, 1),
 348         MUX(CLK_MOUT_SCLK_MMC0_D, "mout_sclk_mmc0_d", mout_sclk_mmc0_d_p,
 349                         MUX_SEL_TOP_FSYS0, 12, 1),
 350         MUX(CLK_MOUT_SCLK_MMC0_C, "mout_sclk_mmc0_c", mout_sclk_mmc0_c_p,
 351                         MUX_SEL_TOP_FSYS0, 8, 1),
 352         MUX(CLK_MOUT_SCLK_MMC0_B, "mout_sclk_mmc0_b", mout_sclk_mmc0_b_p,
 353                         MUX_SEL_TOP_FSYS0, 4, 1),
 354         MUX(CLK_MOUT_SCLK_MMC0_A, "mout_sclk_mmc0_a", mout_bus_pll_user_t_p,
 355                         MUX_SEL_TOP_FSYS0, 0, 1),
 356
 357         /* MUX_SEL_TOP_FSYS1 */
 358         MUX(CLK_MOUT_SCLK_PCIE_100, "mout_sclk_pcie_100", mout_bus_pll_user_t_p,
 359                         MUX_SEL_TOP_FSYS1, 12, 1),
 360         MUX(CLK_MOUT_SCLK_UFSUNIPRO, "mout_sclk_ufsunipro",
 361                         mout_mphy_pll_user_t_p, MUX_SEL_TOP_FSYS1, 8, 1),
 362         MUX(CLK_MOUT_SCLK_USBHOST30, "mout_sclk_usbhost30",
 363                         mout_bus_pll_user_t_p, MUX_SEL_TOP_FSYS1, 4, 1),
 364         MUX(CLK_MOUT_SCLK_USBDRD30, "mout_sclk_usbdrd30",
 365                         mout_bus_pll_user_t_p, MUX_SEL_TOP_FSYS1, 0, 1),
 366
 367         /* MUX_SEL_TOP_PERIC0 */
 368         MUX(CLK_MOUT_SCLK_SPI4, "mout_sclk_spi4", mout_bus_pll_user_t_p,
 369                         MUX_SEL_TOP_PERIC0, 28, 1),
 370         MUX(CLK_MOUT_SCLK_SPI3, "mout_sclk_spi3", mout_bus_pll_user_t_p,
 371                         MUX_SEL_TOP_PERIC0, 24, 1),
 372         MUX(CLK_MOUT_SCLK_UART2, "mout_sclk_uart2", mout_bus_pll_user_t_p,
 373                         MUX_SEL_TOP_PERIC0, 20, 1),
 374         MUX(CLK_MOUT_SCLK_UART1, "mout_sclk_uart1", mout_bus_pll_user_t_p,
 375                         MUX_SEL_TOP_PERIC0, 16, 1),
 376         MUX(CLK_MOUT_SCLK_UART0, "mout_sclk_uart0", mout_bus_pll_user_t_p,
 377                         MUX_SEL_TOP_PERIC0, 12, 1),
 378         MUX(CLK_MOUT_SCLK_SPI2, "mout_sclk_spi2", mout_bus_pll_user_t_p,
 379                         MUX_SEL_TOP_PERIC0, 8, 1),
 380         MUX(CLK_MOUT_SCLK_SPI1, "mout_sclk_spi1", mout_bus_pll_user_t_p,
 381                         MUX_SEL_TOP_PERIC0, 4, 1),
 382         MUX(CLK_MOUT_SCLK_SPI0, "mout_sclk_spi0", mout_bus_pll_user_t_p,
 383                         MUX_SEL_TOP_PERIC0, 0, 1),
 384
 385         /* MUX_SEL_TOP_PERIC1 */
 386         MUX(CLK_MOUT_SCLK_SLIMBUS, "mout_sclk_slimbus", mout_aud_pll_user_p,
 387                         MUX_SEL_TOP_PERIC1, 16, 1),
 388         MUX(CLK_MOUT_SCLK_SPDIF, "mout_sclk_spdif", mout_sclk_spdif_p,
 389                         MUX_SEL_TOP_PERIC1, 12, 2),
 390         MUX(CLK_MOUT_SCLK_AUDIO1, "mout_sclk_audio1", mout_sclk_audio1_p,
 391                         MUX_SEL_TOP_PERIC1, 4, 2),
 392         MUX(CLK_MOUT_SCLK_AUDIO0, "mout_sclk_audio0", mout_sclk_audio0_p,
 393                         MUX_SEL_TOP_PERIC1, 0, 2),
 394 };
 395
 396 static struct samsung_div_clock top_div_clks[] __initdata = {
 397         /* DIV_TOP2 */
 398         DIV(CLK_DIV_ACLK_FSYS_200, "div_aclk_fsys_200", "mout_bus_pll_user",
 399                         DIV_TOP2, 0, 3),
 400
 401         /* DIV_TOP3 */
 402         DIV(CLK_DIV_ACLK_IMEM_SSSX_266, "div_aclk_imem_sssx_266",
 403                         "mout_bus_pll_user", DIV_TOP3, 24, 3),
 404         DIV(CLK_DIV_ACLK_IMEM_200, "div_aclk_imem_200",
 405                         "mout_bus_pll_user", DIV_TOP3, 20, 3),
 406         DIV(CLK_DIV_ACLK_IMEM_266, "div_aclk_imem_266",
 407                         "mout_bus_pll_user", DIV_TOP3, 16, 3),
 408         DIV(CLK_DIV_ACLK_PERIC_66_B, "div_aclk_peric_66_b",
 409                         "div_aclk_peric_66_a", DIV_TOP3, 12, 3),
 410         DIV(CLK_DIV_ACLK_PERIC_66_A, "div_aclk_peric_66_a",
 411                         "mout_bus_pll_user", DIV_TOP3, 8, 3),
 412         DIV(CLK_DIV_ACLK_PERIS_66_B, "div_aclk_peris_66_b",
 413                         "div_aclk_peris_66_a", DIV_TOP3, 4, 3),
 414         DIV(CLK_DIV_ACLK_PERIS_66_A, "div_aclk_peris_66_a",
 415                         "mout_bus_pll_user", DIV_TOP3, 0, 3),
 416
 417         /* DIV_TOP_FSYS0 */
 418         DIV(CLK_DIV_SCLK_MMC1_B, "div_sclk_mmc1_b", "div_sclk_mmc1_a",
 419                         DIV_TOP_FSYS0, 16, 8),
 420         DIV(CLK_DIV_SCLK_MMC1_A, "div_sclk_mmc1_a", "mout_sclk_mmc1_b",
 421                         DIV_TOP_FSYS0, 12, 4),
 422         DIV_F(CLK_DIV_SCLK_MMC0_B, "div_sclk_mmc0_b", "div_sclk_mmc0_a",
 423                         DIV_TOP_FSYS0, 4, 8, CLK_SET_RATE_PARENT, 0),
 424         DIV_F(CLK_DIV_SCLK_MMC0_A, "div_sclk_mmc0_a", "mout_sclk_mmc0_d",
 425                         DIV_TOP_FSYS0, 0, 4, CLK_SET_RATE_PARENT, 0),
 426
 427         /* DIV_TOP_FSYS1 */
 428         DIV(CLK_DIV_SCLK_MMC2_B, "div_sclk_mmc2_b", "div_sclk_mmc2_a",
 429                         DIV_TOP_FSYS1, 4, 8),
 430         DIV(CLK_DIV_SCLK_MMC2_A, "div_sclk_mmc2_a", "mout_sclk_mmc2_b",
 431                         DIV_TOP_FSYS1, 0, 4),
 432
 433         /* DIV_TOP_PERIC0 */
 434         DIV(CLK_DIV_SCLK_SPI1_B, "div_sclk_spi1_b", "div_sclk_spi1_a",
 435                         DIV_TOP_PERIC0, 16, 8),
 436         DIV(CLK_DIV_SCLK_SPI1_A, "div_sclk_spi1_a", "mout_sclk_spi1",
 437                         DIV_TOP_PERIC0, 12, 4),
 438         DIV(CLK_DIV_SCLK_SPI0_B, "div_sclk_spi0_b", "div_sclk_spi0_a",
 439                         DIV_TOP_PERIC0, 4, 8),
 440         DIV(CLK_DIV_SCLK_SPI0_A, "div_sclk_spi0_a", "mout_sclk_spi0",
 441                         DIV_TOP_PERIC0, 0, 4),
 442
 443         /* DIV_TOP_PERIC1 */
 444         DIV(CLK_DIV_SCLK_SPI2_B, "div_sclk_spi2_b", "div_sclk_spi2_a",
 445                         DIV_TOP_PERIC1, 4, 8),
 446         DIV(CLK_DIV_SCLK_SPI2_A, "div_sclk_spi2_a", "mout_sclk_spi2",
 447                         DIV_TOP_PERIC1, 0, 4),
 448
 449         /* DIV_TOP_PERIC2 */
 450         DIV(CLK_DIV_SCLK_UART2, "div_sclk_uart2", "mout_sclk_uart2",
 451                         DIV_TOP_PERIC2, 8, 4),
 452         DIV(CLK_DIV_SCLK_UART1, "div_sclk_uart1", "mout_sclk_uart0",
 453                         DIV_TOP_PERIC2, 4, 4),
 454         DIV(CLK_DIV_SCLK_UART0, "div_sclk_uart0", "mout_sclk_uart1",
 455                         DIV_TOP_PERIC2, 0, 4),
 456
 457         /* DIV_TOP_PERIC3 */
 458         DIV(CLK_DIV_SCLK_I2S1, "div_sclk_i2s1", "sclk_audio1",
 459                         DIV_TOP_PERIC3, 16, 6),
 460         DIV(CLK_DIV_SCLK_PCM1, "div_sclk_pcm1", "sclk_audio1",
 461                         DIV_TOP_PERIC3, 8, 8),
 462         DIV(CLK_DIV_SCLK_AUDIO1, "div_sclk_audio1", "mout_sclk_audio1",
 463                         DIV_TOP_PERIC3, 4, 4),
 464         DIV(CLK_DIV_SCLK_AUDIO0, "div_sclk_audio0", "mout_sclk_audio0",
 465                         DIV_TOP_PERIC3, 0, 4),
 466
 467         /* DIV_TOP_PERIC4 */
 468         DIV(CLK_DIV_SCLK_SPI4_B, "div_sclk_spi4_b", "div_sclk_spi4_a",
 469                         DIV_TOP_PERIC4, 16, 8),
 470         DIV(CLK_DIV_SCLK_SPI4_A, "div_sclk_spi4_a", "mout_sclk_spi4",
 471                         DIV_TOP_PERIC4, 12, 4),
 472         DIV(CLK_DIV_SCLK_SPI3_B, "div_sclk_spi3_b", "div_sclk_spi3_a",
 473                         DIV_TOP_PERIC4, 4, 8),
 474         DIV(CLK_DIV_SCLK_SPI3_A, "div_sclk_spi3_a", "mout_sclk_spi3",
 475                         DIV_TOP_PERIC4, 0, 4),
 476 };
 477
 478 static struct samsung_gate_clock top_gate_clks[] __initdata = {
 479         /* ENABLE_ACLK_TOP */
 480         GATE(CLK_ACLK_PERIC_66, "aclk_peric_66", "div_aclk_peric_66_b",
 481                         ENABLE_ACLK_TOP, 22,
 482                         CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
 483         GATE(CLK_ACLK_PERIS_66, "aclk_peris_66", "div_aclk_peris_66_b",
 484                         ENABLE_ACLK_TOP, 21,
 485                         CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
 486         GATE(CLK_ACLK_FSYS_200, "aclk_fsys_200", "div_aclk_fsys_200",
 487                         ENABLE_ACLK_TOP, 18,
 488                         CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
 489
 490         /* ENABLE_SCLK_TOP_FSYS */
 491         GATE(CLK_SCLK_MMC2_FSYS, "sclk_mmc2_fsys", "div_sclk_mmc2_b",
 492                         ENABLE_SCLK_TOP_FSYS, 6, CLK_SET_RATE_PARENT, 0),
 493         GATE(CLK_SCLK_MMC1_FSYS, "sclk_mmc1_fsys", "div_sclk_mmc1_b",
 494                         ENABLE_SCLK_TOP_FSYS, 5, CLK_SET_RATE_PARENT, 0),
 495         GATE(CLK_SCLK_MMC0_FSYS, "sclk_mmc0_fsys", "div_sclk_mmc0_b",
 496                         ENABLE_SCLK_TOP_FSYS, 4, CLK_SET_RATE_PARENT, 0),
 497
 498         /* ENABLE_SCLK_TOP_PERIC */
 499         GATE(CLK_SCLK_SPI4_PERIC, "sclk_spi4_peric", "div_sclk_spi4_b",
 500                         ENABLE_SCLK_TOP_PERIC, 12, CLK_SET_RATE_PARENT, 0),
 501         GATE(CLK_SCLK_SPI3_PERIC, "sclk_spi3_peric", "div_sclk_spi3_b",
 502                         ENABLE_SCLK_TOP_PERIC, 11, CLK_SET_RATE_PARENT, 0),
 503         GATE(CLK_SCLK_SPDIF_PERIC, "sclk_spdif_peric", "mout_sclk_spdif",
 504                         ENABLE_SCLK_TOP_PERIC, 9, CLK_SET_RATE_PARENT, 0),
 505         GATE(CLK_SCLK_I2S1_PERIC, "sclk_i2s1_peric", "div_sclk_i2s1",
 506                         ENABLE_SCLK_TOP_PERIC, 8, CLK_SET_RATE_PARENT, 0),
 507         GATE(CLK_SCLK_PCM1_PERIC, "sclk_pcm1_peric", "div_sclk_pcm1",
 508                         ENABLE_SCLK_TOP_PERIC, 7, CLK_SET_RATE_PARENT, 0),
 509         GATE(CLK_SCLK_UART2_PERIC, "sclk_uart2_peric", "div_sclk_uart2",
 510                         ENABLE_SCLK_TOP_PERIC, 5, CLK_SET_RATE_PARENT, 0),
 511         GATE(CLK_SCLK_UART1_PERIC, "sclk_uart1_peric", "div_sclk_uart1",
 512                         ENABLE_SCLK_TOP_PERIC, 4, CLK_SET_RATE_PARENT, 0),
 513         GATE(CLK_SCLK_UART0_PERIC, "sclk_uart0_peric", "div_sclk_uart0",
 514                         ENABLE_SCLK_TOP_PERIC, 3, CLK_SET_RATE_PARENT, 0),
 515         GATE(CLK_SCLK_SPI2_PERIC, "sclk_spi2_peric", "div_sclk_spi2_b",
 516                         ENABLE_SCLK_TOP_PERIC, 2, CLK_SET_RATE_PARENT, 0),
 517         GATE(CLK_SCLK_SPI1_PERIC, "sclk_spi1_peric", "div_sclk_spi1_b",
 518                         ENABLE_SCLK_TOP_PERIC, 1, CLK_SET_RATE_PARENT, 0),
 519         GATE(CLK_SCLK_SPI0_PERIC, "sclk_spi0_peric", "div_sclk_spi0_b",
 520                         ENABLE_SCLK_TOP_PERIC, 0, CLK_SET_RATE_PARENT, 0),
 521
 522         /* MUX_ENABLE_TOP_PERIC1 */
 523         GATE(CLK_SCLK_SLIMBUS, "sclk_slimbus", "mout_sclk_slimbus",
 524                         MUX_ENABLE_TOP_PERIC1, 16, 0, 0),
 525         GATE(CLK_SCLK_AUDIO1, "sclk_audio1", "div_sclk_audio1",
 526                         MUX_ENABLE_TOP_PERIC1, 4, 0, 0),
 527         GATE(CLK_SCLK_AUDIO0, "sclk_audio0", "div_sclk_audio0",
 528                         MUX_ENABLE_TOP_PERIC1, 0, 0, 0),
 529 };
 530
 531 /*
 532  * ATLAS_PLL & APOLLO_PLL & MEM0_PLL & MEM1_PLL & BUS_PLL & MFC_PLL
 533  * & MPHY_PLL & G3D_PLL & DISP_PLL & ISP_PLL
 534  */
 535 static struct samsung_pll_rate_table exynos5443_pll_rates[] = {
 536         PLL_35XX_RATE(2500000000U, 625, 6,  0),
 537         PLL_35XX_RATE(2400000000U, 500, 5,  0),
 538         PLL_35XX_RATE(2300000000U, 575, 6,  0),
 539         PLL_35XX_RATE(2200000000U, 550, 6,  0),
 540         PLL_35XX_RATE(2100000000U, 350, 4,  0),
 541         PLL_35XX_RATE(2000000000U, 500, 6,  0),
 542         PLL_35XX_RATE(1900000000U, 475, 6,  0),
 543         PLL_35XX_RATE(1800000000U, 375, 5,  0),
 544         PLL_35XX_RATE(1700000000U, 425, 6,  0),
 545         PLL_35XX_RATE(1600000000U, 400, 6,  0),
 546         PLL_35XX_RATE(1500000000U, 250, 4,  0),
 547         PLL_35XX_RATE(1400000000U, 350, 6,  0),
 548         PLL_35XX_RATE(1332000000U, 222, 4,  0),
 549         PLL_35XX_RATE(1300000000U, 325, 6,  0),
 550         PLL_35XX_RATE(1200000000U, 500, 5,  1),
 551         PLL_35XX_RATE(1100000000U, 550, 6,  1),
 552         PLL_35XX_RATE(1086000000U, 362, 4,  1),
 553         PLL_35XX_RATE(1066000000U, 533, 6,  1),
 554         PLL_35XX_RATE(1000000000U, 500, 6,  1),
 555         PLL_35XX_RATE(933000000U,  311, 4,  1),
 556         PLL_35XX_RATE(921000000U,  307, 4,  1),
 557         PLL_35XX_RATE(900000000U,  375, 5,  1),
 558         PLL_35XX_RATE(825000000U,  275, 4,  1),
 559         PLL_35XX_RATE(800000000U,  400, 6,  1),
 560         PLL_35XX_RATE(733000000U,  733, 12, 1),
 561         PLL_35XX_RATE(700000000U,  360, 6,  1),
 562         PLL_35XX_RATE(667000000U,  222, 4,  1),
 563         PLL_35XX_RATE(633000000U,  211, 4,  1),
 564         PLL_35XX_RATE(600000000U,  500, 5,  2),
 565         PLL_35XX_RATE(552000000U,  460, 5,  2),
 566         PLL_35XX_RATE(550000000U,  550, 6,  2),
 567         PLL_35XX_RATE(543000000U,  362, 4,  2),
 568         PLL_35XX_RATE(533000000U,  533, 6,  2),
 569         PLL_35XX_RATE(500000000U,  500, 6,  2),
 570         PLL_35XX_RATE(444000000U,  370, 5,  2),
 571         PLL_35XX_RATE(420000000U,  350, 5,  2),
 572         PLL_35XX_RATE(400000000U,  400, 6,  2),
 573         PLL_35XX_RATE(350000000U,  360, 6,  2),
 574         PLL_35XX_RATE(333000000U,  222, 4,  2),
 575         PLL_35XX_RATE(300000000U,  500, 5,  3),
 576         PLL_35XX_RATE(266000000U,  532, 6,  3),
 577         PLL_35XX_RATE(200000000U,  400, 6,  3),
 578         PLL_35XX_RATE(166000000U,  332, 6,  3),
 579         PLL_35XX_RATE(160000000U,  320, 6,  3),
 580         PLL_35XX_RATE(133000000U,  552, 6,  4),
 581         PLL_35XX_RATE(100000000U,  400, 6,  4),
 582         { /* sentinel */ }
 583 };
 584
 585 /* AUD_PLL */
 586 static struct samsung_pll_rate_table exynos5443_aud_pll_rates[] = {
 587         PLL_36XX_RATE(400000000U, 200, 3, 2,      0),
 588         PLL_36XX_RATE(393216000U, 197, 3, 2, -25690),
 589         PLL_36XX_RATE(384000000U, 128, 2, 2,      0),
 590         PLL_36XX_RATE(368640000U, 246, 4, 2, -15729),
 591         PLL_36XX_RATE(361507200U, 181, 3, 2, -16148),
 592         PLL_36XX_RATE(338688000U, 113, 2, 2,  -6816),
 593         PLL_36XX_RATE(294912000U,  98, 1, 3,  19923),
 594         PLL_36XX_RATE(288000000U,  96, 1, 3,      0),
 595         PLL_36XX_RATE(252000000U,  84, 1, 3,      0),
 596         { /* sentinel */ }
 597 };
 598
 599 static struct samsung_pll_clock top_pll_clks[] __initdata = {
 600         PLL(pll_35xx, CLK_FOUT_ISP_PLL, "fout_isp_pll", "oscclk",
 601                 ISP_PLL_LOCK, ISP_PLL_CON0, exynos5443_pll_rates),
 602         PLL(pll_36xx, CLK_FOUT_AUD_PLL, "fout_aud_pll", "oscclk",
 603                 AUD_PLL_LOCK, AUD_PLL_CON0, exynos5443_aud_pll_rates),
 604 };
 605
 606 static struct samsung_cmu_info top_cmu_info __initdata = {
 607         .pll_clks               = top_pll_clks,
 608         .nr_pll_clks            = ARRAY_SIZE(top_pll_clks),
 609         .mux_clks               = top_mux_clks,
 610         .nr_mux_clks            = ARRAY_SIZE(top_mux_clks),
 611         .div_clks               = top_div_clks,
 612         .nr_div_clks            = ARRAY_SIZE(top_div_clks),
 613         .gate_clks              = top_gate_clks,
 614         .nr_gate_clks           = ARRAY_SIZE(top_gate_clks),
 615         .fixed_clks             = top_fixed_clks,
 616         .nr_fixed_clks          = ARRAY_SIZE(top_fixed_clks),
 617         .nr_clk_ids             = TOP_NR_CLK,
 618         .clk_regs               = top_clk_regs,
 619         .nr_clk_regs            = ARRAY_SIZE(top_clk_regs),
 620 };
 621
 622 static void __init exynos5433_cmu_top_init(struct device_node *np)
 623 {
 624         samsung_cmu_register_one(np, &top_cmu_info);
 625 }
 626 CLK_OF_DECLARE(exynos5433_cmu_top, "samsung,exynos5433-cmu-top",
 627                 exynos5433_cmu_top_init);
 628
 629 /*
 630  * Register offset definitions for CMU_CPIF
 631  */
 632 #define MPHY_PLL_LOCK           0x0000
 633 #define MPHY_PLL_CON0           0x0100
 634 #define MPHY_PLL_CON1           0x0104
 635 #define MPHY_PLL_FREQ_DET       0x010c
 636 #define MUX_SEL_CPIF0           0x0200
 637 #define DIV_CPIF                0x0600
 638 #define ENABLE_SCLK_CPIF        0x0a00
 639
 640 static unsigned long cpif_clk_regs[] __initdata = {
 641         MPHY_PLL_LOCK,
 642         MPHY_PLL_CON0,
 643         MPHY_PLL_CON1,
 644         MPHY_PLL_FREQ_DET,
 645         MUX_SEL_CPIF0,
 646         ENABLE_SCLK_CPIF,
 647 };
 648
 649 /* list of all parent clock list */
 650 PNAME(mout_mphy_pll_p)          = { "oscclk", "fout_mphy_pll", };
 651
 652 static struct samsung_pll_clock cpif_pll_clks[] __initdata = {
 653         PLL(pll_35xx, CLK_FOUT_MPHY_PLL, "fout_mphy_pll", "oscclk",
 654                 MPHY_PLL_LOCK, MPHY_PLL_CON0, exynos5443_pll_rates),
 655 };
 656
 657 static struct samsung_mux_clock cpif_mux_clks[] __initdata = {
 658         /* MUX_SEL_CPIF0 */
 659         MUX(CLK_MOUT_MPHY_PLL, "mout_mphy_pll", mout_mphy_pll_p, MUX_SEL_CPIF0,
 660                         0, 1),
 661 };
 662
 663 static struct samsung_div_clock cpif_div_clks[] __initdata = {
 664         /* DIV_CPIF */
 665         DIV(CLK_DIV_SCLK_MPHY, "div_sclk_mphy", "mout_mphy_pll", DIV_CPIF,
 666                         0, 6),
 667 };
 668
 669 static struct samsung_gate_clock cpif_gate_clks[] __initdata = {
 670         /* ENABLE_SCLK_CPIF */
 671         GATE(CLK_SCLK_MPHY_PLL, "sclk_mphy_pll", "mout_mphy_pll",
 672                         ENABLE_SCLK_CPIF, 9, 0, 0),
 673         GATE(CLK_SCLK_UFS_MPHY, "sclk_ufs_mphy", "div_sclk_mphy",
 674                         ENABLE_SCLK_CPIF, 4, 0, 0),
 675 };
 676
 677 static struct samsung_cmu_info cpif_cmu_info __initdata = {
 678         .pll_clks               = cpif_pll_clks,
 679         .nr_pll_clks            = ARRAY_SIZE(cpif_pll_clks),
 680         .mux_clks               = cpif_mux_clks,
 681         .nr_mux_clks            = ARRAY_SIZE(cpif_mux_clks),
 682         .div_clks               = cpif_div_clks,
 683         .nr_div_clks            = ARRAY_SIZE(cpif_div_clks),
 684         .gate_clks              = cpif_gate_clks,
 685         .nr_gate_clks           = ARRAY_SIZE(cpif_gate_clks),
 686         .nr_clk_ids             = CPIF_NR_CLK,
 687         .clk_regs               = cpif_clk_regs,
 688         .nr_clk_regs            = ARRAY_SIZE(cpif_clk_regs),
 689 };
 690
 691 static void __init exynos5433_cmu_cpif_init(struct device_node *np)
 692 {
 693         samsung_cmu_register_one(np, &cpif_cmu_info);
 694 }
 695 CLK_OF_DECLARE(exynos5433_cmu_cpif, "samsung,exynos5433-cmu-cpif",
 696                 exynos5433_cmu_cpif_init);
 697
 698 /*
 699  * Register offset definitions for CMU_MIF
 700  */
 701 #define MEM0_PLL_LOCK                   0x0000
 702 #define MEM1_PLL_LOCK                   0x0004
 703 #define BUS_PLL_LOCK                    0x0008
 704 #define MFC_PLL_LOCK                    0x000c
 705 #define MEM0_PLL_CON0                   0x0100
 706 #define MEM0_PLL_CON1                   0x0104
 707 #define MEM0_PLL_FREQ_DET               0x010c
 708 #define MEM1_PLL_CON0                   0x0110
 709 #define MEM1_PLL_CON1                   0x0114
 710 #define MEM1_PLL_FREQ_DET               0x011c
 711 #define BUS_PLL_CON0                    0x0120
 712 #define BUS_PLL_CON1                    0x0124
 713 #define BUS_PLL_FREQ_DET                0x012c
 714 #define MFC_PLL_CON0                    0x0130
 715 #define MFC_PLL_CON1                    0x0134
 716 #define MFC_PLL_FREQ_DET                0x013c
 717
 718 static unsigned long mif_clk_regs[] __initdata = {
 719         MEM0_PLL_LOCK,
 720         MEM1_PLL_LOCK,
 721         BUS_PLL_LOCK,
 722         MFC_PLL_LOCK,
 723         MEM0_PLL_CON0,
 724         MEM0_PLL_CON1,
 725         MEM0_PLL_FREQ_DET,
 726         MEM1_PLL_CON0,
 727         MEM1_PLL_CON1,
 728         MEM1_PLL_FREQ_DET,
 729         BUS_PLL_CON0,
 730         BUS_PLL_CON1,
 731         BUS_PLL_FREQ_DET,
 732         MFC_PLL_CON0,
 733         MFC_PLL_CON1,
 734         MFC_PLL_FREQ_DET,
 735 };
 736
 737 static struct samsung_pll_clock mif_pll_clks[] __initdata = {
 738         PLL(pll_35xx, CLK_FOUT_MEM0_PLL, "fout_mem0_pll", "oscclk",
 739                 MEM0_PLL_LOCK, MEM0_PLL_CON0, exynos5443_pll_rates),
 740         PLL(pll_35xx, CLK_FOUT_MEM1_PLL, "fout_mem1_pll", "oscclk",
 741                 MEM1_PLL_LOCK, MEM1_PLL_CON0, exynos5443_pll_rates),
 742         PLL(pll_35xx, CLK_FOUT_BUS_PLL, "fout_bus_pll", "oscclk",
 743                 BUS_PLL_LOCK, BUS_PLL_CON0, exynos5443_pll_rates),
 744         PLL(pll_35xx, CLK_FOUT_MFC_PLL, "fout_mfc_pll", "oscclk",
 745                 MFC_PLL_LOCK, MFC_PLL_CON0, exynos5443_pll_rates),
 746 };
 747
 748 static struct samsung_cmu_info mif_cmu_info __initdata = {
 749         .pll_clks               = mif_pll_clks,
 750         .nr_pll_clks            = ARRAY_SIZE(mif_pll_clks),
 751         .nr_clk_ids             = MIF_NR_CLK,
 752         .clk_regs               = mif_clk_regs,
 753         .nr_clk_regs            = ARRAY_SIZE(mif_clk_regs),
 754 };
 755
 756 static void __init exynos5433_cmu_mif_init(struct device_node *np)
 757 {
 758         samsung_cmu_register_one(np, &mif_cmu_info);
 759 }
 760 CLK_OF_DECLARE(exynos5433_cmu_mif, "samsung,exynos5433-cmu-mif",
 761                 exynos5433_cmu_mif_init);
 762
 763 /*
 764  * Register offset definitions for CMU_PERIC
 765  */
 766 #define DIV_PERIC                       0x0600
 767 #define DIV_STAT_PERIC                  0x0700
 768 #define ENABLE_ACLK_PERIC               0x0800
 769 #define ENABLE_PCLK_PERIC0              0x0900
 770 #define ENABLE_PCLK_PERIC1              0x0904
 771 #define ENABLE_SCLK_PERIC               0x0A00
 772 #define ENABLE_IP_PERIC0                0x0B00
 773 #define ENABLE_IP_PERIC1                0x0B04
 774 #define ENABLE_IP_PERIC2                0x0B08
 775
 776 static unsigned long peric_clk_regs[] __initdata = {
 777         DIV_PERIC,
 778         DIV_STAT_PERIC,
 779         ENABLE_ACLK_PERIC,
 780         ENABLE_PCLK_PERIC0,
 781         ENABLE_PCLK_PERIC1,
 782         ENABLE_SCLK_PERIC,
 783         ENABLE_IP_PERIC0,
 784         ENABLE_IP_PERIC1,
 785         ENABLE_IP_PERIC2,
 786 };
 787
 788 static struct samsung_div_clock peric_div_clks[] __initdata = {
 789         /* DIV_PERIC */
 790         DIV(CLK_DIV_SCLK_SCI, "div_sclk_sci", "oscclk", DIV_PERIC, 4, 4),
 791         DIV(CLK_DIV_SCLK_SC_IN, "div_sclk_sc_in", "oscclk", DIV_PERIC, 0, 4),
 792 };
 793
 794 static struct samsung_gate_clock peric_gate_clks[] __initdata = {
 795         /* ENABLE_ACLK_PERIC */
 796         GATE(CLK_ACLK_AHB2APB_PERIC2P, "aclk_ahb2apb_peric2p", "aclk_peric_66",
 797                         ENABLE_ACLK_PERIC, 3, CLK_IGNORE_UNUSED, 0),
 798         GATE(CLK_ACLK_AHB2APB_PERIC1P, "aclk_ahb2apb_peric1p", "aclk_peric_66",
 799                         ENABLE_ACLK_PERIC, 2, CLK_IGNORE_UNUSED, 0),
 800         GATE(CLK_ACLK_AHB2APB_PERIC0P, "aclk_ahb2apb_peric0p", "aclk_peric_66",
 801                         ENABLE_ACLK_PERIC, 1, CLK_IGNORE_UNUSED, 0),
 802         GATE(CLK_ACLK_PERICNP_66, "aclk_pericnp_66", "aclk_peric_66",
 803                         ENABLE_ACLK_PERIC, 0, CLK_IGNORE_UNUSED, 0),
 804
 805         /* ENABLE_PCLK_PERIC0 */
 806         GATE(CLK_PCLK_SCI, "pclk_sci", "aclk_peric_66", ENABLE_PCLK_PERIC0,
 807                         31, CLK_SET_RATE_PARENT, 0),
 808         GATE(CLK_PCLK_GPIO_FINGER, "pclk_gpio_finger", "aclk_peric_66",
 809                         ENABLE_PCLK_PERIC0, 30, CLK_IGNORE_UNUSED, 0),
 810         GATE(CLK_PCLK_GPIO_ESE, "pclk_gpio_ese", "aclk_peric_66",
 811                         ENABLE_PCLK_PERIC0, 29, CLK_IGNORE_UNUSED, 0),
 812         GATE(CLK_PCLK_PWM, "pclk_pwm", "aclk_peric_66", ENABLE_PCLK_PERIC0,
 813                         28, CLK_SET_RATE_PARENT, 0),
 814         GATE(CLK_PCLK_SPDIF, "pclk_spdif", "aclk_peric_66", ENABLE_PCLK_PERIC0,
 815                         26, CLK_SET_RATE_PARENT, 0),
 816         GATE(CLK_PCLK_PCM1, "pclk_pcm1", "aclk_peric_66", ENABLE_PCLK_PERIC0,
 817                         25, CLK_SET_RATE_PARENT, 0),
 818         GATE(CLK_PCLK_I2S1, "pclk_i2s", "aclk_peric_66", ENABLE_PCLK_PERIC0,
 819                         24, CLK_SET_RATE_PARENT, 0),
 820         GATE(CLK_PCLK_SPI2, "pclk_spi2", "aclk_peric_66", ENABLE_PCLK_PERIC0,
 821                         23, CLK_SET_RATE_PARENT, 0),
 822         GATE(CLK_PCLK_SPI1, "pclk_spi1", "aclk_peric_66", ENABLE_PCLK_PERIC0,
 823                         22, CLK_SET_RATE_PARENT, 0),
 824         GATE(CLK_PCLK_SPI0, "pclk_spi0", "aclk_peric_66", ENABLE_PCLK_PERIC0,
 825                         21, CLK_SET_RATE_PARENT, 0),
 826         GATE(CLK_PCLK_ADCIF, "pclk_adcif", "aclk_peric_66", ENABLE_PCLK_PERIC0,
 827                         20, CLK_SET_RATE_PARENT, 0),
 828         GATE(CLK_PCLK_GPIO_TOUCH, "pclk_gpio_touch", "aclk_peric_66",
 829                         ENABLE_PCLK_PERIC0, 19, CLK_IGNORE_UNUSED, 0),
 830         GATE(CLK_PCLK_GPIO_NFC, "pclk_gpio_nfc", "aclk_peric_66",
 831                         ENABLE_PCLK_PERIC0, 18, CLK_IGNORE_UNUSED, 0),
 832         GATE(CLK_PCLK_GPIO_PERIC, "pclk_gpio_peric", "aclk_peric_66",
 833                         ENABLE_PCLK_PERIC0, 17, CLK_IGNORE_UNUSED, 0),
 834         GATE(CLK_PCLK_PMU_PERIC, "pclk_pmu_peric", "aclk_peric_66",
 835                         ENABLE_PCLK_PERIC0, 16, CLK_SET_RATE_PARENT, 0),
 836         GATE(CLK_PCLK_SYSREG_PERIC, "pclk_sysreg_peric", "aclk_peric_66",
 837                         ENABLE_PCLK_PERIC0, 15,
 838                         CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
 839         GATE(CLK_PCLK_UART2, "pclk_uart2", "aclk_peric_66", ENABLE_PCLK_PERIC0,
 840                         14, CLK_SET_RATE_PARENT, 0),
 841         GATE(CLK_PCLK_UART1, "pclk_uart1", "aclk_peric_66", ENABLE_PCLK_PERIC0,
 842                         13, CLK_SET_RATE_PARENT, 0),
 843         GATE(CLK_PCLK_UART0, "pclk_uart0", "aclk_peric_66", ENABLE_PCLK_PERIC0,
 844                         12, CLK_SET_RATE_PARENT, 0),
 845         GATE(CLK_PCLK_HSI2C3, "pclk_hsi2c3", "aclk_peric_66",
 846                         ENABLE_PCLK_PERIC0, 11, CLK_SET_RATE_PARENT, 0),
 847         GATE(CLK_PCLK_HSI2C2, "pclk_hsi2c2", "aclk_peric_66",
 848                         ENABLE_PCLK_PERIC0, 10, CLK_SET_RATE_PARENT, 0),
 849         GATE(CLK_PCLK_HSI2C1, "pclk_hsi2c1", "aclk_peric_66",
 850                         ENABLE_PCLK_PERIC0, 9, CLK_SET_RATE_PARENT, 0),
 851         GATE(CLK_PCLK_HSI2C0, "pclk_hsi2c0", "aclk_peric_66",
 852                         ENABLE_PCLK_PERIC0, 8, CLK_SET_RATE_PARENT, 0),
 853         GATE(CLK_PCLK_I2C7, "pclk_i2c7", "aclk_peric_66", ENABLE_PCLK_PERIC0,
 854                         7, CLK_SET_RATE_PARENT, 0),
 855         GATE(CLK_PCLK_I2C6, "pclk_i2c6", "aclk_peric_66", ENABLE_PCLK_PERIC0,
 856                         6, CLK_SET_RATE_PARENT, 0),
 857         GATE(CLK_PCLK_I2C5, "pclk_i2c5", "aclk_peric_66", ENABLE_PCLK_PERIC0,
 858                         5, CLK_SET_RATE_PARENT, 0),
 859         GATE(CLK_PCLK_I2C4, "pclk_i2c4", "aclk_peric_66", ENABLE_PCLK_PERIC0,
 860                         4, CLK_SET_RATE_PARENT, 0),
 861         GATE(CLK_PCLK_I2C3, "pclk_i2c3", "aclk_peric_66", ENABLE_PCLK_PERIC0,
 862                         3, CLK_SET_RATE_PARENT, 0),
 863         GATE(CLK_PCLK_I2C2, "pclk_i2c2", "aclk_peric_66", ENABLE_PCLK_PERIC0,
 864                         2, CLK_SET_RATE_PARENT, 0),
 865         GATE(CLK_PCLK_I2C1, "pclk_i2c1", "aclk_peric_66", ENABLE_PCLK_PERIC0,
 866                         1, CLK_SET_RATE_PARENT, 0),
 867         GATE(CLK_PCLK_I2C0, "pclk_i2c0", "aclk_peric_66", ENABLE_PCLK_PERIC0,
 868                         0, CLK_SET_RATE_PARENT, 0),
 869
 870         /* ENABLE_PCLK_PERIC1 */
 871         GATE(CLK_PCLK_SPI4, "pclk_spi4", "aclk_peric_66", ENABLE_PCLK_PERIC1,
 872                         9, CLK_SET_RATE_PARENT, 0),
 873         GATE(CLK_PCLK_SPI3, "pclk_spi3", "aclk_peric_66", ENABLE_PCLK_PERIC1,
 874                         8, CLK_SET_RATE_PARENT, 0),
 875         GATE(CLK_PCLK_HSI2C11, "pclk_hsi2c11", "aclk_peric_66",
 876                         ENABLE_PCLK_PERIC1, 7, CLK_SET_RATE_PARENT, 0),
 877         GATE(CLK_PCLK_HSI2C10, "pclk_hsi2c10", "aclk_peric_66",
 878                         ENABLE_PCLK_PERIC1, 6, CLK_SET_RATE_PARENT, 0),
 879         GATE(CLK_PCLK_HSI2C9, "pclk_hsi2c9", "aclk_peric_66",
 880                         ENABLE_PCLK_PERIC1, 5, CLK_SET_RATE_PARENT, 0),
 881         GATE(CLK_PCLK_HSI2C8, "pclk_hsi2c8", "aclk_peric_66",
 882                         ENABLE_PCLK_PERIC1, 4, CLK_SET_RATE_PARENT, 0),
 883         GATE(CLK_PCLK_HSI2C7, "pclk_hsi2c7", "aclk_peric_66",
 884                         ENABLE_PCLK_PERIC1, 3, CLK_SET_RATE_PARENT, 0),
 885         GATE(CLK_PCLK_HSI2C6, "pclk_hsi2c6", "aclk_peric_66",
 886                         ENABLE_PCLK_PERIC1, 2, CLK_SET_RATE_PARENT, 0),
 887         GATE(CLK_PCLK_HSI2C5, "pclk_hsi2c5", "aclk_peric_66",
 888                         ENABLE_PCLK_PERIC1, 1, CLK_SET_RATE_PARENT, 0),
 889         GATE(CLK_PCLK_HSI2C4, "pclk_hsi2c4", "aclk_peric_66",
 890                         ENABLE_PCLK_PERIC1, 0, CLK_SET_RATE_PARENT, 0),
 891
 892         /* ENABLE_SCLK_PERIC */
 893         GATE(CLK_SCLK_IOCLK_SPI4, "sclk_ioclk_spi4", "ioclk_spi4_clk_in",
 894                         ENABLE_SCLK_PERIC, 21, CLK_SET_RATE_PARENT, 0),
 895         GATE(CLK_SCLK_IOCLK_SPI3, "sclk_ioclk_spi3", "ioclk_spi3_clk_in",
 896                         ENABLE_SCLK_PERIC, 20, CLK_SET_RATE_PARENT, 0),
 897         GATE(CLK_SCLK_SPI4, "sclk_spi4", "sclk_spi4_peric", ENABLE_SCLK_PERIC,
 898                         19, CLK_SET_RATE_PARENT, 0),
 899         GATE(CLK_SCLK_SPI3, "sclk_spi3", "sclk_spi3_peric", ENABLE_SCLK_PERIC,
 900                         18, CLK_SET_RATE_PARENT, 0),
 901         GATE(CLK_SCLK_SCI, "sclk_sci", "div_sclk_sci", ENABLE_SCLK_PERIC,
 902                         17, 0, 0),
 903         GATE(CLK_SCLK_SC_IN, "sclk_sc_in", "div_sclk_sc_in", ENABLE_SCLK_PERIC,
 904                         16, 0, 0),
 905         GATE(CLK_SCLK_PWM, "sclk_pwm", "oscclk", ENABLE_SCLK_PERIC, 15, 0, 0),
 906         GATE(CLK_SCLK_IOCLK_SPI2, "sclk_ioclk_spi2", "ioclk_spi2_clk_in",
 907                         ENABLE_SCLK_PERIC, 13, CLK_SET_RATE_PARENT, 0),
 908         GATE(CLK_SCLK_IOCLK_SPI1, "sclk_ioclk_spi1", "ioclk_spi1_clk_in",
 909                         ENABLE_SCLK_PERIC, 12,
 910                         CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
 911         GATE(CLK_SCLK_IOCLK_SPI0, "sclk_ioclk_spi0", "ioclk_spi0_clk_in",
 912                         ENABLE_SCLK_PERIC, 11, CLK_SET_RATE_PARENT, 0),
 913         GATE(CLK_SCLK_IOCLK_I2S1_BCLK, "sclk_ioclk_i2s1_bclk",
 914                         "ioclk_i2s1_bclk_in", ENABLE_SCLK_PERIC, 10,
 915                         CLK_SET_RATE_PARENT, 0),
 916         GATE(CLK_SCLK_SPDIF, "sclk_spdif", "sclk_spdif_peric",
 917                         ENABLE_SCLK_PERIC, 8, CLK_SET_RATE_PARENT, 0),
 918         GATE(CLK_SCLK_PCM1, "sclk_pcm1", "sclk_pcm1_peric",
 919                         ENABLE_SCLK_PERIC, 7, CLK_SET_RATE_PARENT, 0),
 920         GATE(CLK_SCLK_I2S1, "sclk_i2s1", "sclk_i2s1_peric",
 921                         ENABLE_SCLK_PERIC, 6, CLK_SET_RATE_PARENT, 0),
 922         GATE(CLK_SCLK_SPI2, "sclk_spi2", "sclk_spi2_peric", ENABLE_SCLK_PERIC,
 923                         5, CLK_SET_RATE_PARENT, 0),
 924         GATE(CLK_SCLK_SPI1, "sclk_spi1", "sclk_spi1_peric", ENABLE_SCLK_PERIC,
 925                         4, CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
 926         GATE(CLK_SCLK_SPI0, "sclk_spi0", "sclk_spi0_peric", ENABLE_SCLK_PERIC,
 927                         3, CLK_SET_RATE_PARENT, 0),
 928         GATE(CLK_SCLK_UART2, "sclk_uart2", "sclk_uart2_peric",
 929                         ENABLE_SCLK_PERIC, 2, CLK_SET_RATE_PARENT, 0),
 930         GATE(CLK_SCLK_UART1, "sclk_uart1", "sclk_uart1_peric",
 931                         ENABLE_SCLK_PERIC, 1, CLK_SET_RATE_PARENT, 0),
 932         GATE(CLK_SCLK_UART0, "sclk_uart0", "sclk_uart0_peric",
 933                         ENABLE_SCLK_PERIC, 0, CLK_SET_RATE_PARENT, 0),
 934 };
 935
 936 static struct samsung_cmu_info peric_cmu_info __initdata = {
 937         .div_clks               = peric_div_clks,
 938         .nr_div_clks            = ARRAY_SIZE(peric_div_clks),
 939         .gate_clks              = peric_gate_clks,
 940         .nr_gate_clks           = ARRAY_SIZE(peric_gate_clks),
 941         .nr_clk_ids             = PERIC_NR_CLK,
 942         .clk_regs               = peric_clk_regs,
 943         .nr_clk_regs            = ARRAY_SIZE(peric_clk_regs),
 944 };
 945
 946 static void __init exynos5433_cmu_peric_init(struct device_node *np)
 947 {
 948         samsung_cmu_register_one(np, &peric_cmu_info);
 949 }
 950
 951 CLK_OF_DECLARE(exynos5433_cmu_peric, "samsung,exynos5433-cmu-peric",
 952                 exynos5433_cmu_peric_init);
 953
 954 /*
 955  * Register offset definitions for CMU_PERIS
 956  */
 957 #define ENABLE_ACLK_PERIS               0x0800
 958 #define ENABLE_PCLK_PERIS               0x0900
 959
 960 static unsigned long peris_clk_regs[] __initdata = {
 961         ENABLE_ACLK_PERIS,
 962         ENABLE_PCLK_PERIS,
 963 };
 964
 965 static struct samsung_gate_clock peris_gate_clks[] __initdata = {
 966         /* ENABLE_PCLK_PERIS */
 967         GATE(CLK_PCLK_HPM_APBIF, "pclk_hpm_apbif", "aclk_peris_66",
 968                         ENABLE_PCLK_PERIS, 30, CLK_IGNORE_UNUSED, 0),
 969         GATE(CLK_PCLK_TMU1_APBIF, "pclk_tmu1_apbif", "aclk_peris_66",
 970                         ENABLE_PCLK_PERIS, 24, CLK_IGNORE_UNUSED, 0),
 971         GATE(CLK_PCLK_TMU0_APBIF, "pclk_tmu0_apbif", "aclk_peris_66",
 972                         ENABLE_PCLK_PERIS, 23, CLK_IGNORE_UNUSED, 0),
 973         GATE(CLK_PCLK_PMU_PERIS, "pclk_pmu_peris", "aclk_peris_66",
 974                         ENABLE_PCLK_PERIS, 22, CLK_IGNORE_UNUSED, 0),
 975         GATE(CLK_PCLK_SYSREG_PERIS, "pclk_sysreg_peris", "aclk_peris_66",
 976                         ENABLE_PCLK_PERIS, 21, CLK_IGNORE_UNUSED, 0),
 977         GATE(CLK_PCLK_CMU_TOP_APBIF, "pclk_cmu_top_apbif", "aclk_peris_66",
 978                         ENABLE_PCLK_PERIS, 20, CLK_IGNORE_UNUSED, 0),
 979         GATE(CLK_PCLK_WDT_APOLLO, "pclk_wdt_apollo", "aclk_peris_66",
 980                         ENABLE_PCLK_PERIS, 17, CLK_IGNORE_UNUSED, 0),
 981         GATE(CLK_PCLK_WDT_ATLAS, "pclk_wdt_atlas", "aclk_peris_66",
 982                         ENABLE_PCLK_PERIS, 16, CLK_IGNORE_UNUSED, 0),
 983         GATE(CLK_PCLK_MCT, "pclk_mct", "aclk_peris_66",
 984                         ENABLE_PCLK_PERIS, 15, CLK_IGNORE_UNUSED, 0),
 985         GATE(CLK_PCLK_HDMI_CEC, "pclk_hdmi_cec", "aclk_peris_66",
 986                         ENABLE_PCLK_PERIS, 14, CLK_IGNORE_UNUSED, 0),
 987 };
 988
 989 static struct samsung_cmu_info peris_cmu_info __initdata = {
 990         .gate_clks              = peris_gate_clks,
 991         .nr_gate_clks           = ARRAY_SIZE(peris_gate_clks),
 992         .nr_clk_ids             = PERIS_NR_CLK,
 993         .clk_regs               = peris_clk_regs,
 994         .nr_clk_regs            = ARRAY_SIZE(peris_clk_regs),
 995 };
 996
 997 static void __init exynos5433_cmu_peris_init(struct device_node *np)
 998 {
 999         samsung_cmu_register_one(np, &peris_cmu_info);
1000 }
1001
1002 CLK_OF_DECLARE(exynos5433_cmu_peris, "samsung,exynos5433-cmu-peris",
1003                 exynos5433_cmu_peris_init);
1004
1005 /*
1006  * Register offset definitions for CMU_FSYS
1007  */
1008 #define MUX_SEL_FSYS0                   0x0200
1009 #define MUX_SEL_FSYS1                   0x0204
1010 #define MUX_SEL_FSYS2                   0x0208
1011 #define MUX_SEL_FSYS3                   0x020c
1012 #define MUX_SEL_FSYS4                   0x0210
1013 #define MUX_ENABLE_FSYS0                0x0300
1014 #define MUX_ENABLE_FSYS1                0x0304
1015 #define MUX_ENABLE_FSYS2                0x0308
1016 #define MUX_ENABLE_FSYS3                0x030c
1017 #define MUX_ENABLE_FSYS4                0x0310
1018 #define MUX_STAT_FSYS0                  0x0400
1019 #define MUX_STAT_FSYS1                  0x0404
1020 #define MUX_STAT_FSYS2                  0x0408
1021 #define MUX_STAT_FSYS3                  0x040c
1022 #define MUX_STAT_FSYS4                  0x0410
1023 #define MUX_IGNORE_FSYS2                0x0508
1024 #define MUX_IGNORE_FSYS3                0x050c
1025 #define ENABLE_ACLK_FSYS0               0x0800
1026 #define ENABLE_ACLK_FSYS1               0x0804
1027 #define ENABLE_PCLK_FSYS                0x0900
1028 #define ENABLE_SCLK_FSYS                0x0a00
1029 #define ENABLE_IP_FSYS0                 0x0b00
1030 #define ENABLE_IP_FSYS1                 0x0b04
1031
1032 /* list of all parent clock list */
1033 PNAME(mout_aclk_fsys_200_user_p)        = { "oscclk", "div_aclk_fsys_200", };
1034 PNAME(mout_sclk_mmc2_user_p)            = { "oscclk", "sclk_mmc2_fsys", };
1035 PNAME(mout_sclk_mmc1_user_p)            = { "oscclk", "sclk_mmc1_fsys", };
1036 PNAME(mout_sclk_mmc0_user_p)            = { "oscclk", "sclk_mmc0_fsys", };
1037
1038 static unsigned long fsys_clk_regs[] __initdata = {
1039         MUX_SEL_FSYS0,
1040         MUX_SEL_FSYS1,
1041         MUX_SEL_FSYS2,
1042         MUX_SEL_FSYS3,
1043         MUX_SEL_FSYS4,
1044         MUX_ENABLE_FSYS0,
1045         MUX_ENABLE_FSYS1,
1046         MUX_ENABLE_FSYS2,
1047         MUX_ENABLE_FSYS3,
1048         MUX_ENABLE_FSYS4,
1049         MUX_STAT_FSYS0,
1050         MUX_STAT_FSYS1,
1051         MUX_STAT_FSYS2,
1052         MUX_STAT_FSYS3,
1053         MUX_STAT_FSYS4,
1054         MUX_IGNORE_FSYS2,
1055         MUX_IGNORE_FSYS3,
1056         ENABLE_ACLK_FSYS0,
1057         ENABLE_ACLK_FSYS1,
1058         ENABLE_PCLK_FSYS,
1059         ENABLE_SCLK_FSYS,
1060         ENABLE_IP_FSYS0,
1061         ENABLE_IP_FSYS1,
1062 };
1063
1064 static struct samsung_mux_clock fsys_mux_clks[] __initdata = {
1065         /* MUX_SEL_FSYS0 */
1066         MUX(CLK_MOUT_ACLK_FSYS_200_USER, "mout_aclk_fsys_200_user",
1067                         mout_aclk_fsys_200_user_p, MUX_SEL_FSYS0, 0, 1),
1068
1069         /* MUX_SEL_FSYS1 */
1070         MUX(CLK_MOUT_SCLK_MMC2_USER, "mout_sclk_mmc2_user",
1071                         mout_sclk_mmc2_user_p, MUX_SEL_FSYS1, 20, 1),
1072         MUX(CLK_MOUT_SCLK_MMC1_USER, "mout_sclk_mmc1_user",
1073                         mout_sclk_mmc1_user_p, MUX_SEL_FSYS1, 16, 1),
1074         MUX(CLK_MOUT_SCLK_MMC0_USER, "mout_sclk_mmc0_user",
1075                         mout_sclk_mmc0_user_p, MUX_SEL_FSYS1, 12, 1),
1076 };
1077
1078 static struct samsung_gate_clock fsys_gate_clks[] __initdata = {
1079         /* ENABLE_ACLK_FSYS0 */
1080         GATE(CLK_ACLK_PCIE, "aclk_pcie", "mout_aclk_fsys_200_user",
1081                         ENABLE_ACLK_FSYS0, 13, CLK_IGNORE_UNUSED, 0),
1082         GATE(CLK_ACLK_PDMA1, "aclk_pdma1", "mout_aclk_fsys_200_user",
1083                         ENABLE_ACLK_FSYS0, 11, CLK_IGNORE_UNUSED, 0),
1084         GATE(CLK_ACLK_TSI, "aclk_tsi", "mout_aclk_fsys_200_user",
1085                         ENABLE_ACLK_FSYS0, 10, CLK_IGNORE_UNUSED, 0),
1086         GATE(CLK_ACLK_MMC2, "aclk_mmc2", "mout_aclk_fsys_200_user",
1087                         ENABLE_ACLK_FSYS0, 8, CLK_IGNORE_UNUSED, 0),
1088         GATE(CLK_ACLK_MMC1, "aclk_mmc1", "mout_aclk_fsys_200_user",
1089                         ENABLE_ACLK_FSYS0, 7, CLK_IGNORE_UNUSED, 0),
1090         GATE(CLK_ACLK_MMC0, "aclk_mmc0", "mout_aclk_fsys_200_user",
1091                         ENABLE_ACLK_FSYS0, 6, CLK_IGNORE_UNUSED, 0),
1092         GATE(CLK_ACLK_UFS, "aclk_ufs", "mout_aclk_fsys_200_user",
1093                         ENABLE_ACLK_FSYS0, 5, CLK_IGNORE_UNUSED, 0),
1094         GATE(CLK_ACLK_USBHOST20, "aclk_usbhost20", "mout_aclk_fsys_200_user",
1095                         ENABLE_ACLK_FSYS0, 3, CLK_IGNORE_UNUSED, 0),
1096         GATE(CLK_ACLK_USBHOST30, "aclk_usbhost30", "mout_aclk_fsys_200_user",
1097                         ENABLE_ACLK_FSYS0, 2, CLK_IGNORE_UNUSED, 0),
1098         GATE(CLK_ACLK_USBDRD30, "aclk_usbdrd30", "mout_aclk_fsys_200_user",
1099                         ENABLE_ACLK_FSYS0, 1, CLK_IGNORE_UNUSED, 0),
1100         GATE(CLK_ACLK_PDMA0, "aclk_pdma0", "mout_aclk_fsys_200_user",
1101                         ENABLE_ACLK_FSYS0, 0, CLK_IGNORE_UNUSED, 0),
1102
1103         /* ENABLE_SCLK_FSYS */
1104         GATE(CLK_SCLK_MMC2, "sclk_mmc2", "mout_sclk_mmc2_user",
1105                         ENABLE_SCLK_FSYS, 4, CLK_SET_RATE_PARENT, 0),
1106         GATE(CLK_SCLK_MMC1, "sclk_mmc1", "mout_sclk_mmc1_user",
1107                         ENABLE_SCLK_FSYS, 3, CLK_SET_RATE_PARENT, 0),
1108         GATE(CLK_SCLK_MMC0, "sclk_mmc0", "mout_sclk_mmc0_user",
1109                         ENABLE_SCLK_FSYS, 2, CLK_SET_RATE_PARENT, 0),
1110
1111         /* ENABLE_IP_FSYS0 */
1112         GATE(CLK_PDMA1, "pdma1", "aclk_pdma1", ENABLE_IP_FSYS0, 15, 0, 0),
1113         GATE(CLK_PDMA0, "pdma0", "aclk_pdma0", ENABLE_IP_FSYS0, 0, 0, 0),
1114 };
1115
1116 static struct samsung_cmu_info fsys_cmu_info __initdata = {
1117         .mux_clks               = fsys_mux_clks,
1118         .nr_mux_clks            = ARRAY_SIZE(fsys_mux_clks),
1119         .gate_clks              = fsys_gate_clks,
1120         .nr_gate_clks           = ARRAY_SIZE(fsys_gate_clks),
1121         .nr_clk_ids             = FSYS_NR_CLK,
1122         .clk_regs               = fsys_clk_regs,
1123         .nr_clk_regs            = ARRAY_SIZE(fsys_clk_regs),
1124 };
1125
1126 static void __init exynos5433_cmu_fsys_init(struct device_node *np)
1127 {
1128         samsung_cmu_register_one(np, &fsys_cmu_info);
1129 }
1130
1131 CLK_OF_DECLARE(exynos5433_cmu_fsys, "samsung,exynos5433-cmu-fsys",
1132                 exynos5433_cmu_fsys_init);