2 * Copyright (c) 2014 Samsung Electronics Co., Ltd.
3 * Author: Chanwoo Choi <cw00.choi@samsung.com>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
9 * Common Clock Framework support for Exynos5443 SoC.
12 #include <linux/clk.h>
13 #include <linux/clkdev.h>
14 #include <linux/clk-provider.h>
17 #include <dt-bindings/clock/exynos5433.h>
23 * Register offset definitions for CMU_TOP
25 #define ISP_PLL_LOCK 0x0000
26 #define AUD_PLL_LOCK 0x0004
27 #define ISP_PLL_CON0 0x0100
28 #define ISP_PLL_CON1 0x0104
29 #define ISP_PLL_FREQ_DET 0x0108
30 #define AUD_PLL_CON0 0x0110
31 #define AUD_PLL_CON1 0x0114
32 #define AUD_PLL_CON2 0x0118
33 #define AUD_PLL_FREQ_DET 0x011c
34 #define MUX_SEL_TOP0 0x0200
35 #define MUX_SEL_TOP1 0x0204
36 #define MUX_SEL_TOP2 0x0208
37 #define MUX_SEL_TOP3 0x020c
38 #define MUX_SEL_TOP4 0x0210
39 #define MUX_SEL_TOP_MSCL 0x0220
40 #define MUX_SEL_TOP_CAM1 0x0224
41 #define MUX_SEL_TOP_DISP 0x0228
42 #define MUX_SEL_TOP_FSYS0 0x0230
43 #define MUX_SEL_TOP_FSYS1 0x0234
44 #define MUX_SEL_TOP_PERIC0 0x0238
45 #define MUX_SEL_TOP_PERIC1 0x023c
46 #define MUX_ENABLE_TOP0 0x0300
47 #define MUX_ENABLE_TOP1 0x0304
48 #define MUX_ENABLE_TOP2 0x0308
49 #define MUX_ENABLE_TOP3 0x030c
50 #define MUX_ENABLE_TOP4 0x0310
51 #define MUX_ENABLE_TOP_MSCL 0x0320
52 #define MUX_ENABLE_TOP_CAM1 0x0324
53 #define MUX_ENABLE_TOP_DISP 0x0328
54 #define MUX_ENABLE_TOP_FSYS0 0x0330
55 #define MUX_ENABLE_TOP_FSYS1 0x0334
56 #define MUX_ENABLE_TOP_PERIC0 0x0338
57 #define MUX_ENABLE_TOP_PERIC1 0x033c
58 #define MUX_STAT_TOP0 0x0400
59 #define MUX_STAT_TOP1 0x0404
60 #define MUX_STAT_TOP2 0x0408
61 #define MUX_STAT_TOP3 0x040c
62 #define MUX_STAT_TOP4 0x0410
63 #define MUX_STAT_TOP_MSCL 0x0420
64 #define MUX_STAT_TOP_CAM1 0x0424
65 #define MUX_STAT_TOP_FSYS0 0x0430
66 #define MUX_STAT_TOP_FSYS1 0x0434
67 #define MUX_STAT_TOP_PERIC0 0x0438
68 #define MUX_STAT_TOP_PERIC1 0x043c
69 #define DIV_TOP0 0x0600
70 #define DIV_TOP1 0x0604
71 #define DIV_TOP2 0x0608
72 #define DIV_TOP3 0x060c
73 #define DIV_TOP4 0x0610
74 #define DIV_TOP_MSCL 0x0618
75 #define DIV_TOP_CAM10 0x061c
76 #define DIV_TOP_CAM11 0x0620
77 #define DIV_TOP_FSYS0 0x062c
78 #define DIV_TOP_FSYS1 0x0630
79 #define DIV_TOP_FSYS2 0x0634
80 #define DIV_TOP_PERIC0 0x0638
81 #define DIV_TOP_PERIC1 0x063c
82 #define DIV_TOP_PERIC2 0x0640
83 #define DIV_TOP_PERIC3 0x0644
84 #define DIV_TOP_PERIC4 0x0648
85 #define DIV_TOP_PLL_FREQ_DET 0x064c
86 #define DIV_STAT_TOP0 0x0700
87 #define DIV_STAT_TOP1 0x0704
88 #define DIV_STAT_TOP2 0x0708
89 #define DIV_STAT_TOP3 0x070c
90 #define DIV_STAT_TOP4 0x0710
91 #define DIV_STAT_TOP_MSCL 0x0718
92 #define DIV_STAT_TOP_CAM10 0x071c
93 #define DIV_STAT_TOP_CAM11 0x0720
94 #define DIV_STAT_TOP_FSYS0 0x072c
95 #define DIV_STAT_TOP_FSYS1 0x0730
96 #define DIV_STAT_TOP_FSYS2 0x0734
97 #define DIV_STAT_TOP_PERIC0 0x0738
98 #define DIV_STAT_TOP_PERIC1 0x073c
99 #define DIV_STAT_TOP_PERIC2 0x0740
100 #define DIV_STAT_TOP_PERIC3 0x0744
101 #define DIV_STAT_TOP_PLL_FREQ_DET 0x074c
102 #define ENABLE_ACLK_TOP 0x0800
103 #define ENABLE_SCLK_TOP 0x0a00
104 #define ENABLE_SCLK_TOP_MSCL 0x0a04
105 #define ENABLE_SCLK_TOP_CAM1 0x0a08
106 #define ENABLE_SCLK_TOP_DISP 0x0a0c
107 #define ENABLE_SCLK_TOP_FSYS 0x0a10
108 #define ENABLE_SCLK_TOP_PERIC 0x0a14
109 #define ENABLE_IP_TOP 0x0b00
110 #define ENABLE_CMU_TOP 0x0c00
111 #define ENABLE_CMU_TOP_DIV_STAT 0x0c04
113 static unsigned long top_clk_regs[] __initdata = {
143 MUX_ENABLE_TOP_FSYS0,
144 MUX_ENABLE_TOP_FSYS1,
145 MUX_ENABLE_TOP_PERIC0,
146 MUX_ENABLE_TOP_PERIC1,
174 DIV_TOP_PLL_FREQ_DET,
190 DIV_STAT_TOP_PLL_FREQ_DET,
193 ENABLE_SCLK_TOP_MSCL,
194 ENABLE_SCLK_TOP_CAM1,
195 ENABLE_SCLK_TOP_DISP,
196 ENABLE_SCLK_TOP_FSYS,
197 ENABLE_SCLK_TOP_PERIC,
200 ENABLE_CMU_TOP_DIV_STAT,
203 /* list of all parent clock list */
204 PNAME(mout_aud_pll_p) = { "oscclk", "fout_aud_pll", };
205 PNAME(mout_isp_pll_p) = { "oscclk", "fout_isp_pll", };
206 PNAME(mout_aud_pll_user_p) = { "oscclk", "mout_aud_pll", };
207 PNAME(mout_mphy_pll_user_p) = { "oscclk", "sclk_mphy_pll", };
208 PNAME(mout_mfc_pll_user_p) = { "oscclk", "sclk_mfc_pll", };
209 PNAME(mout_bus_pll_user_p) = { "oscclk", "sclk_bus_pll", };
210 PNAME(mout_bus_pll_user_t_p) = { "oscclk", "mout_bus_pll_user", };
211 PNAME(mout_mphy_pll_user_t_p) = { "oscclk", "mout_mphy_pll_user", };
213 PNAME(mout_bus_mfc_pll_user_p) = { "mout_bus_pll_user", "mout_mfc_pll_user",};
214 PNAME(mout_mfc_bus_pll_user_p) = { "mout_mfc_pll_user", "mout_bus_pll_user",};
215 PNAME(mout_aclk_cam1_552_b_p) = { "mout_aclk_cam1_552_a",
216 "mout_mfc_pll_user", };
217 PNAME(mout_aclk_cam1_552_a_p) = { "mout_isp_pll", "mout_bus_pll_user", };
219 PNAME(mout_aclk_mfc_400_c_p) = { "mout_aclk_mfc_400_b",
220 "mout_mphy_pll_user", };
221 PNAME(mout_aclk_mfc_400_b_p) = { "mout_aclk_mfc_400_a",
222 "mout_bus_pll_user", };
223 PNAME(mout_aclk_mfc_400_a_p) = { "mout_mfc_pll_user", "mout_isp_pll", };
225 PNAME(mout_bus_mphy_pll_user_p) = { "mout_bus_pll_user",
226 "mout_mphy_pll_user", };
227 PNAME(mout_aclk_mscl_b_p) = { "mout_aclk_mscl_400_a",
228 "mout_mphy_pll_user", };
229 PNAME(mout_aclk_g2d_400_b_p) = { "mout_aclk_g2d_400_a",
230 "mout_mphy_pll_user", };
232 PNAME(mout_sclk_jpeg_c_p) = { "mout_sclk_jpeg_b", "mout_mphy_pll_user",};
233 PNAME(mout_sclk_jpeg_b_p) = { "mout_sclk_jpeg_a", "mout_mfc_pll_user", };
235 PNAME(mout_sclk_mmc2_b_p) = { "mout_sclk_mmc2_a", "mout_mfc_pll_user",};
236 PNAME(mout_sclk_mmc1_b_p) = { "mout_sclk_mmc1_a", "mout_mfc_pll_user",};
237 PNAME(mout_sclk_mmc0_d_p) = { "mout_sclk_mmc0_c", "mout_isp_pll", };
238 PNAME(mout_sclk_mmc0_c_p) = { "mout_sclk_mmc0_b", "mout_mphy_pll_user",};
239 PNAME(mout_sclk_mmc0_b_p) = { "mout_sclk_mmc0_a", "mout_mfc_pll_user", };
241 PNAME(mout_sclk_spdif_p) = { "sclk_audio0", "sclk_audio1",
242 "oscclk", "ioclk_spdif_extclk", };
243 PNAME(mout_sclk_audio1_p) = { "ioclk_audiocdclk1", "oscclk",
244 "mout_aud_pll_user_t",};
245 PNAME(mout_sclk_audio0_p) = { "ioclk_audiocdclk0", "oscclk",
246 "mout_aud_pll_user_t",};
248 static struct samsung_fixed_factor_clock top_fixed_factor_clks[] __initdata = {
249 FFACTOR(0, "oscclk_efuse_common", "oscclk", 1, 1, 0),
252 static struct samsung_fixed_rate_clock top_fixed_clks[] __initdata = {
253 /* Xi2s{0|1}CDCLK input clock for I2S/PCM */
254 FRATE(0, "ioclk_audiocdclk1", NULL, CLK_IS_ROOT, 100000000),
255 FRATE(0, "ioclk_audiocdclk0", NULL, CLK_IS_ROOT, 100000000),
256 /* Xi2s1SDI input clock for SPDIF */
257 FRATE(0, "ioclk_spdif_extclk", NULL, CLK_IS_ROOT, 100000000),
258 /* XspiCLK[4:0] input clock for SPI */
259 FRATE(0, "ioclk_spi4_clk_in", NULL, CLK_IS_ROOT, 50000000),
260 FRATE(0, "ioclk_spi3_clk_in", NULL, CLK_IS_ROOT, 50000000),
261 FRATE(0, "ioclk_spi2_clk_in", NULL, CLK_IS_ROOT, 50000000),
262 FRATE(0, "ioclk_spi1_clk_in", NULL, CLK_IS_ROOT, 50000000),
263 FRATE(0, "ioclk_spi0_clk_in", NULL, CLK_IS_ROOT, 50000000),
264 /* Xi2s1SCLK input clock for I2S1_BCLK */
265 FRATE(0, "ioclk_i2s1_bclk_in", NULL, CLK_IS_ROOT, 12288000),
268 static struct samsung_mux_clock top_mux_clks[] __initdata = {
270 MUX(CLK_MOUT_AUD_PLL, "mout_aud_pll", mout_aud_pll_p, MUX_SEL_TOP0,
272 MUX(CLK_MOUT_ISP_PLL, "mout_isp_pll", mout_isp_pll_p, MUX_SEL_TOP0,
276 MUX(CLK_MOUT_AUD_PLL_USER_T, "mout_aud_pll_user_t",
277 mout_aud_pll_user_p, MUX_SEL_TOP1, 12, 1),
278 MUX(CLK_MOUT_MPHY_PLL_USER, "mout_mphy_pll_user", mout_mphy_pll_user_p,
280 MUX(CLK_MOUT_MFC_PLL_USER, "mout_mfc_pll_user", mout_mfc_pll_user_p,
282 MUX(CLK_MOUT_BUS_PLL_USER, "mout_bus_pll_user", mout_bus_pll_user_p,
286 MUX(CLK_MOUT_ACLK_HEVC_400, "mout_aclk_hevc_400",
287 mout_bus_mfc_pll_user_p, MUX_SEL_TOP2, 28, 1),
288 MUX(CLK_MOUT_ACLK_CAM1_333, "mout_aclk_cam1_333",
289 mout_mfc_bus_pll_user_p, MUX_SEL_TOP2, 16, 1),
290 MUX(CLK_MOUT_ACLK_CAM1_552_B, "mout_aclk_cam1_552_b",
291 mout_aclk_cam1_552_b_p, MUX_SEL_TOP2, 12, 1),
292 MUX(CLK_MOUT_ACLK_CAM1_552_A, "mout_aclk_cam1_552_a",
293 mout_aclk_cam1_552_a_p, MUX_SEL_TOP2, 8, 1),
294 MUX(CLK_MOUT_ACLK_ISP_DIS_400, "mout_aclk_isp_dis_400",
295 mout_bus_mfc_pll_user_p, MUX_SEL_TOP2, 4, 1),
296 MUX(CLK_MOUT_ACLK_ISP_400, "mout_aclk_isp_400",
297 mout_bus_mfc_pll_user_p, MUX_SEL_TOP2, 0, 1),
300 MUX(CLK_MOUT_ACLK_BUS0_400, "mout_aclk_bus0_400",
301 mout_bus_mphy_pll_user_p, MUX_SEL_TOP3, 20, 1),
302 MUX(CLK_MOUT_ACLK_MSCL_400_B, "mout_aclk_mscl_400_b",
303 mout_aclk_mscl_b_p, MUX_SEL_TOP3, 16, 1),
304 MUX(CLK_MOUT_ACLK_MSCL_400_A, "mout_aclk_mscl_400_a",
305 mout_bus_mfc_pll_user_p, MUX_SEL_TOP3, 12, 1),
306 MUX(CLK_MOUT_ACLK_GSCL_333, "mout_aclk_gscl_333",
307 mout_mfc_bus_pll_user_p, MUX_SEL_TOP3, 8, 1),
308 MUX(CLK_MOUT_ACLK_G2D_400_B, "mout_aclk_g2d_400_b",
309 mout_aclk_g2d_400_b_p, MUX_SEL_TOP3, 4, 1),
310 MUX(CLK_MOUT_ACLK_G2D_400_A, "mout_aclk_g2d_400_a",
311 mout_bus_mfc_pll_user_p, MUX_SEL_TOP3, 0, 1),
314 MUX(CLK_MOUT_ACLK_MFC_400_C, "mout_aclk_mfc_400_c",
315 mout_aclk_mfc_400_c_p, MUX_SEL_TOP4, 8, 1),
316 MUX(CLK_MOUT_ACLK_MFC_400_B, "mout_aclk_mfc_400_b",
317 mout_aclk_mfc_400_b_p, MUX_SEL_TOP4, 4, 1),
318 MUX(CLK_MOUT_ACLK_MFC_400_A, "mout_aclk_mfc_400_a",
319 mout_aclk_mfc_400_a_p, MUX_SEL_TOP4, 0, 1),
321 /* MUX_SEL_TOP_MSCL */
322 MUX(CLK_MOUT_SCLK_JPEG_C, "mout_sclk_jpeg_c", mout_sclk_jpeg_c_p,
323 MUX_SEL_TOP_MSCL, 8, 1),
324 MUX(CLK_MOUT_SCLK_JPEG_B, "mout_sclk_jpeg_b", mout_sclk_jpeg_b_p,
325 MUX_SEL_TOP_MSCL, 4, 1),
326 MUX(CLK_MOUT_SCLK_JPEG_A, "mout_sclk_jpeg_a", mout_bus_pll_user_t_p,
327 MUX_SEL_TOP_MSCL, 0, 1),
329 /* MUX_SEL_TOP_CAM1 */
330 MUX(CLK_MOUT_SCLK_ISP_SENSOR2, "mout_sclk_isp_sensor2",
331 mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 24, 1),
332 MUX(CLK_MOUT_SCLK_ISP_SENSOR1, "mout_sclk_isp_sensor1",
333 mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 20, 1),
334 MUX(CLK_MOUT_SCLK_ISP_SENSOR0, "mout_sclk_isp_sensor0",
335 mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 16, 1),
336 MUX(CLK_MOUT_SCLK_ISP_UART, "mout_sclk_isp_uart",
337 mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 8, 1),
338 MUX(CLK_MOUT_SCLK_ISP_SPI1, "mout_sclk_isp_spi1",
339 mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 4, 1),
340 MUX(CLK_MOUT_SCLK_ISP_SPI0, "mout_sclk_isp_spi0",
341 mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 0, 1),
343 /* MUX_SEL_TOP_FSYS0 */
344 MUX(CLK_MOUT_SCLK_MMC2_B, "mout_sclk_mmc2_b", mout_sclk_mmc2_b_p,
345 MUX_SEL_TOP_FSYS0, 28, 1),
346 MUX(CLK_MOUT_SCLK_MMC2_A, "mout_sclk_mmc2_a", mout_bus_pll_user_t_p,
347 MUX_SEL_TOP_FSYS0, 24, 1),
348 MUX(CLK_MOUT_SCLK_MMC1_B, "mout_sclk_mmc1_b", mout_sclk_mmc1_b_p,
349 MUX_SEL_TOP_FSYS0, 20, 1),
350 MUX(CLK_MOUT_SCLK_MMC1_A, "mout_sclk_mmc1_a", mout_bus_pll_user_t_p,
351 MUX_SEL_TOP_FSYS0, 16, 1),
352 MUX(CLK_MOUT_SCLK_MMC0_D, "mout_sclk_mmc0_d", mout_sclk_mmc0_d_p,
353 MUX_SEL_TOP_FSYS0, 12, 1),
354 MUX(CLK_MOUT_SCLK_MMC0_C, "mout_sclk_mmc0_c", mout_sclk_mmc0_c_p,
355 MUX_SEL_TOP_FSYS0, 8, 1),
356 MUX(CLK_MOUT_SCLK_MMC0_B, "mout_sclk_mmc0_b", mout_sclk_mmc0_b_p,
357 MUX_SEL_TOP_FSYS0, 4, 1),
358 MUX(CLK_MOUT_SCLK_MMC0_A, "mout_sclk_mmc0_a", mout_bus_pll_user_t_p,
359 MUX_SEL_TOP_FSYS0, 0, 1),
361 /* MUX_SEL_TOP_FSYS1 */
362 MUX(CLK_MOUT_SCLK_PCIE_100, "mout_sclk_pcie_100", mout_bus_pll_user_t_p,
363 MUX_SEL_TOP_FSYS1, 12, 1),
364 MUX(CLK_MOUT_SCLK_UFSUNIPRO, "mout_sclk_ufsunipro",
365 mout_mphy_pll_user_t_p, MUX_SEL_TOP_FSYS1, 8, 1),
366 MUX(CLK_MOUT_SCLK_USBHOST30, "mout_sclk_usbhost30",
367 mout_bus_pll_user_t_p, MUX_SEL_TOP_FSYS1, 4, 1),
368 MUX(CLK_MOUT_SCLK_USBDRD30, "mout_sclk_usbdrd30",
369 mout_bus_pll_user_t_p, MUX_SEL_TOP_FSYS1, 0, 1),
371 /* MUX_SEL_TOP_PERIC0 */
372 MUX(CLK_MOUT_SCLK_SPI4, "mout_sclk_spi4", mout_bus_pll_user_t_p,
373 MUX_SEL_TOP_PERIC0, 28, 1),
374 MUX(CLK_MOUT_SCLK_SPI3, "mout_sclk_spi3", mout_bus_pll_user_t_p,
375 MUX_SEL_TOP_PERIC0, 24, 1),
376 MUX(CLK_MOUT_SCLK_UART2, "mout_sclk_uart2", mout_bus_pll_user_t_p,
377 MUX_SEL_TOP_PERIC0, 20, 1),
378 MUX(CLK_MOUT_SCLK_UART1, "mout_sclk_uart1", mout_bus_pll_user_t_p,
379 MUX_SEL_TOP_PERIC0, 16, 1),
380 MUX(CLK_MOUT_SCLK_UART0, "mout_sclk_uart0", mout_bus_pll_user_t_p,
381 MUX_SEL_TOP_PERIC0, 12, 1),
382 MUX(CLK_MOUT_SCLK_SPI2, "mout_sclk_spi2", mout_bus_pll_user_t_p,
383 MUX_SEL_TOP_PERIC0, 8, 1),
384 MUX(CLK_MOUT_SCLK_SPI1, "mout_sclk_spi1", mout_bus_pll_user_t_p,
385 MUX_SEL_TOP_PERIC0, 4, 1),
386 MUX(CLK_MOUT_SCLK_SPI0, "mout_sclk_spi0", mout_bus_pll_user_t_p,
387 MUX_SEL_TOP_PERIC0, 0, 1),
389 /* MUX_SEL_TOP_PERIC1 */
390 MUX(CLK_MOUT_SCLK_SLIMBUS, "mout_sclk_slimbus", mout_aud_pll_user_p,
391 MUX_SEL_TOP_PERIC1, 16, 1),
392 MUX(CLK_MOUT_SCLK_SPDIF, "mout_sclk_spdif", mout_sclk_spdif_p,
393 MUX_SEL_TOP_PERIC1, 12, 2),
394 MUX(CLK_MOUT_SCLK_AUDIO1, "mout_sclk_audio1", mout_sclk_audio1_p,
395 MUX_SEL_TOP_PERIC1, 4, 2),
396 MUX(CLK_MOUT_SCLK_AUDIO0, "mout_sclk_audio0", mout_sclk_audio0_p,
397 MUX_SEL_TOP_PERIC1, 0, 2),
400 static struct samsung_div_clock top_div_clks[] __initdata = {
402 DIV(CLK_DIV_ACLK_FSYS_200, "div_aclk_fsys_200", "mout_bus_pll_user",
406 DIV(CLK_DIV_ACLK_IMEM_SSSX_266, "div_aclk_imem_sssx_266",
407 "mout_bus_pll_user", DIV_TOP3, 24, 3),
408 DIV(CLK_DIV_ACLK_IMEM_200, "div_aclk_imem_200",
409 "mout_bus_pll_user", DIV_TOP3, 20, 3),
410 DIV(CLK_DIV_ACLK_IMEM_266, "div_aclk_imem_266",
411 "mout_bus_pll_user", DIV_TOP3, 16, 3),
412 DIV(CLK_DIV_ACLK_PERIC_66_B, "div_aclk_peric_66_b",
413 "div_aclk_peric_66_a", DIV_TOP3, 12, 3),
414 DIV(CLK_DIV_ACLK_PERIC_66_A, "div_aclk_peric_66_a",
415 "mout_bus_pll_user", DIV_TOP3, 8, 3),
416 DIV(CLK_DIV_ACLK_PERIS_66_B, "div_aclk_peris_66_b",
417 "div_aclk_peris_66_a", DIV_TOP3, 4, 3),
418 DIV(CLK_DIV_ACLK_PERIS_66_A, "div_aclk_peris_66_a",
419 "mout_bus_pll_user", DIV_TOP3, 0, 3),
422 DIV(CLK_DIV_SCLK_MMC1_B, "div_sclk_mmc1_b", "div_sclk_mmc1_a",
423 DIV_TOP_FSYS0, 16, 8),
424 DIV(CLK_DIV_SCLK_MMC1_A, "div_sclk_mmc1_a", "mout_sclk_mmc1_b",
425 DIV_TOP_FSYS0, 12, 4),
426 DIV_F(CLK_DIV_SCLK_MMC0_B, "div_sclk_mmc0_b", "div_sclk_mmc0_a",
427 DIV_TOP_FSYS0, 4, 8, CLK_SET_RATE_PARENT, 0),
428 DIV_F(CLK_DIV_SCLK_MMC0_A, "div_sclk_mmc0_a", "mout_sclk_mmc0_d",
429 DIV_TOP_FSYS0, 0, 4, CLK_SET_RATE_PARENT, 0),
432 DIV(CLK_DIV_SCLK_MMC2_B, "div_sclk_mmc2_b", "div_sclk_mmc2_a",
433 DIV_TOP_FSYS1, 4, 8),
434 DIV(CLK_DIV_SCLK_MMC2_A, "div_sclk_mmc2_a", "mout_sclk_mmc2_b",
435 DIV_TOP_FSYS1, 0, 4),
438 DIV(CLK_DIV_SCLK_SPI1_B, "div_sclk_spi1_b", "div_sclk_spi1_a",
439 DIV_TOP_PERIC0, 16, 8),
440 DIV(CLK_DIV_SCLK_SPI1_A, "div_sclk_spi1_a", "mout_sclk_spi1",
441 DIV_TOP_PERIC0, 12, 4),
442 DIV(CLK_DIV_SCLK_SPI0_B, "div_sclk_spi0_b", "div_sclk_spi0_a",
443 DIV_TOP_PERIC0, 4, 8),
444 DIV(CLK_DIV_SCLK_SPI0_A, "div_sclk_spi0_a", "mout_sclk_spi0",
445 DIV_TOP_PERIC0, 0, 4),
448 DIV(CLK_DIV_SCLK_SPI2_B, "div_sclk_spi2_b", "div_sclk_spi2_a",
449 DIV_TOP_PERIC1, 4, 8),
450 DIV(CLK_DIV_SCLK_SPI2_A, "div_sclk_spi2_a", "mout_sclk_spi2",
451 DIV_TOP_PERIC1, 0, 4),
454 DIV(CLK_DIV_SCLK_UART2, "div_sclk_uart2", "mout_sclk_uart2",
455 DIV_TOP_PERIC2, 8, 4),
456 DIV(CLK_DIV_SCLK_UART1, "div_sclk_uart1", "mout_sclk_uart0",
457 DIV_TOP_PERIC2, 4, 4),
458 DIV(CLK_DIV_SCLK_UART0, "div_sclk_uart0", "mout_sclk_uart1",
459 DIV_TOP_PERIC2, 0, 4),
462 DIV(CLK_DIV_SCLK_I2S1, "div_sclk_i2s1", "sclk_audio1",
463 DIV_TOP_PERIC3, 16, 6),
464 DIV(CLK_DIV_SCLK_PCM1, "div_sclk_pcm1", "sclk_audio1",
465 DIV_TOP_PERIC3, 8, 8),
466 DIV(CLK_DIV_SCLK_AUDIO1, "div_sclk_audio1", "mout_sclk_audio1",
467 DIV_TOP_PERIC3, 4, 4),
468 DIV(CLK_DIV_SCLK_AUDIO0, "div_sclk_audio0", "mout_sclk_audio0",
469 DIV_TOP_PERIC3, 0, 4),
472 DIV(CLK_DIV_SCLK_SPI4_B, "div_sclk_spi4_b", "div_sclk_spi4_a",
473 DIV_TOP_PERIC4, 16, 8),
474 DIV(CLK_DIV_SCLK_SPI4_A, "div_sclk_spi4_a", "mout_sclk_spi4",
475 DIV_TOP_PERIC4, 12, 4),
476 DIV(CLK_DIV_SCLK_SPI3_B, "div_sclk_spi3_b", "div_sclk_spi3_a",
477 DIV_TOP_PERIC4, 4, 8),
478 DIV(CLK_DIV_SCLK_SPI3_A, "div_sclk_spi3_a", "mout_sclk_spi3",
479 DIV_TOP_PERIC4, 0, 4),
482 static struct samsung_gate_clock top_gate_clks[] __initdata = {
483 /* ENABLE_ACLK_TOP */
484 GATE(CLK_ACLK_PERIC_66, "aclk_peric_66", "div_aclk_peric_66_b",
486 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
487 GATE(CLK_ACLK_PERIS_66, "aclk_peris_66", "div_aclk_peris_66_b",
489 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
490 GATE(CLK_ACLK_FSYS_200, "aclk_fsys_200", "div_aclk_fsys_200",
492 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
494 /* ENABLE_SCLK_TOP_FSYS */
495 GATE(CLK_SCLK_MMC2_FSYS, "sclk_mmc2_fsys", "div_sclk_mmc2_b",
496 ENABLE_SCLK_TOP_FSYS, 6, CLK_SET_RATE_PARENT, 0),
497 GATE(CLK_SCLK_MMC1_FSYS, "sclk_mmc1_fsys", "div_sclk_mmc1_b",
498 ENABLE_SCLK_TOP_FSYS, 5, CLK_SET_RATE_PARENT, 0),
499 GATE(CLK_SCLK_MMC0_FSYS, "sclk_mmc0_fsys", "div_sclk_mmc0_b",
500 ENABLE_SCLK_TOP_FSYS, 4, CLK_SET_RATE_PARENT, 0),
502 /* ENABLE_SCLK_TOP_PERIC */
503 GATE(CLK_SCLK_SPI4_PERIC, "sclk_spi4_peric", "div_sclk_spi4_b",
504 ENABLE_SCLK_TOP_PERIC, 12, CLK_SET_RATE_PARENT, 0),
505 GATE(CLK_SCLK_SPI3_PERIC, "sclk_spi3_peric", "div_sclk_spi3_b",
506 ENABLE_SCLK_TOP_PERIC, 11, CLK_SET_RATE_PARENT, 0),
507 GATE(CLK_SCLK_SPDIF_PERIC, "sclk_spdif_peric", "mout_sclk_spdif",
508 ENABLE_SCLK_TOP_PERIC, 9, CLK_SET_RATE_PARENT, 0),
509 GATE(CLK_SCLK_I2S1_PERIC, "sclk_i2s1_peric", "div_sclk_i2s1",
510 ENABLE_SCLK_TOP_PERIC, 8, CLK_SET_RATE_PARENT, 0),
511 GATE(CLK_SCLK_PCM1_PERIC, "sclk_pcm1_peric", "div_sclk_pcm1",
512 ENABLE_SCLK_TOP_PERIC, 7, CLK_SET_RATE_PARENT, 0),
513 GATE(CLK_SCLK_UART2_PERIC, "sclk_uart2_peric", "div_sclk_uart2",
514 ENABLE_SCLK_TOP_PERIC, 5, CLK_SET_RATE_PARENT, 0),
515 GATE(CLK_SCLK_UART1_PERIC, "sclk_uart1_peric", "div_sclk_uart1",
516 ENABLE_SCLK_TOP_PERIC, 4, CLK_SET_RATE_PARENT, 0),
517 GATE(CLK_SCLK_UART0_PERIC, "sclk_uart0_peric", "div_sclk_uart0",
518 ENABLE_SCLK_TOP_PERIC, 3, CLK_SET_RATE_PARENT, 0),
519 GATE(CLK_SCLK_SPI2_PERIC, "sclk_spi2_peric", "div_sclk_spi2_b",
520 ENABLE_SCLK_TOP_PERIC, 2, CLK_SET_RATE_PARENT, 0),
521 GATE(CLK_SCLK_SPI1_PERIC, "sclk_spi1_peric", "div_sclk_spi1_b",
522 ENABLE_SCLK_TOP_PERIC, 1, CLK_SET_RATE_PARENT, 0),
523 GATE(CLK_SCLK_SPI0_PERIC, "sclk_spi0_peric", "div_sclk_spi0_b",
524 ENABLE_SCLK_TOP_PERIC, 0, CLK_SET_RATE_PARENT, 0),
526 /* MUX_ENABLE_TOP_PERIC1 */
527 GATE(CLK_SCLK_SLIMBUS, "sclk_slimbus", "mout_sclk_slimbus",
528 MUX_ENABLE_TOP_PERIC1, 16, 0, 0),
529 GATE(CLK_SCLK_AUDIO1, "sclk_audio1", "div_sclk_audio1",
530 MUX_ENABLE_TOP_PERIC1, 4, 0, 0),
531 GATE(CLK_SCLK_AUDIO0, "sclk_audio0", "div_sclk_audio0",
532 MUX_ENABLE_TOP_PERIC1, 0, 0, 0),
536 * ATLAS_PLL & APOLLO_PLL & MEM0_PLL & MEM1_PLL & BUS_PLL & MFC_PLL
537 * & MPHY_PLL & G3D_PLL & DISP_PLL & ISP_PLL
539 static struct samsung_pll_rate_table exynos5443_pll_rates[] = {
540 PLL_35XX_RATE(2500000000U, 625, 6, 0),
541 PLL_35XX_RATE(2400000000U, 500, 5, 0),
542 PLL_35XX_RATE(2300000000U, 575, 6, 0),
543 PLL_35XX_RATE(2200000000U, 550, 6, 0),
544 PLL_35XX_RATE(2100000000U, 350, 4, 0),
545 PLL_35XX_RATE(2000000000U, 500, 6, 0),
546 PLL_35XX_RATE(1900000000U, 475, 6, 0),
547 PLL_35XX_RATE(1800000000U, 375, 5, 0),
548 PLL_35XX_RATE(1700000000U, 425, 6, 0),
549 PLL_35XX_RATE(1600000000U, 400, 6, 0),
550 PLL_35XX_RATE(1500000000U, 250, 4, 0),
551 PLL_35XX_RATE(1400000000U, 350, 6, 0),
552 PLL_35XX_RATE(1332000000U, 222, 4, 0),
553 PLL_35XX_RATE(1300000000U, 325, 6, 0),
554 PLL_35XX_RATE(1200000000U, 500, 5, 1),
555 PLL_35XX_RATE(1100000000U, 550, 6, 1),
556 PLL_35XX_RATE(1086000000U, 362, 4, 1),
557 PLL_35XX_RATE(1066000000U, 533, 6, 1),
558 PLL_35XX_RATE(1000000000U, 500, 6, 1),
559 PLL_35XX_RATE(933000000U, 311, 4, 1),
560 PLL_35XX_RATE(921000000U, 307, 4, 1),
561 PLL_35XX_RATE(900000000U, 375, 5, 1),
562 PLL_35XX_RATE(825000000U, 275, 4, 1),
563 PLL_35XX_RATE(800000000U, 400, 6, 1),
564 PLL_35XX_RATE(733000000U, 733, 12, 1),
565 PLL_35XX_RATE(700000000U, 360, 6, 1),
566 PLL_35XX_RATE(667000000U, 222, 4, 1),
567 PLL_35XX_RATE(633000000U, 211, 4, 1),
568 PLL_35XX_RATE(600000000U, 500, 5, 2),
569 PLL_35XX_RATE(552000000U, 460, 5, 2),
570 PLL_35XX_RATE(550000000U, 550, 6, 2),
571 PLL_35XX_RATE(543000000U, 362, 4, 2),
572 PLL_35XX_RATE(533000000U, 533, 6, 2),
573 PLL_35XX_RATE(500000000U, 500, 6, 2),
574 PLL_35XX_RATE(444000000U, 370, 5, 2),
575 PLL_35XX_RATE(420000000U, 350, 5, 2),
576 PLL_35XX_RATE(400000000U, 400, 6, 2),
577 PLL_35XX_RATE(350000000U, 360, 6, 2),
578 PLL_35XX_RATE(333000000U, 222, 4, 2),
579 PLL_35XX_RATE(300000000U, 500, 5, 3),
580 PLL_35XX_RATE(266000000U, 532, 6, 3),
581 PLL_35XX_RATE(200000000U, 400, 6, 3),
582 PLL_35XX_RATE(166000000U, 332, 6, 3),
583 PLL_35XX_RATE(160000000U, 320, 6, 3),
584 PLL_35XX_RATE(133000000U, 552, 6, 4),
585 PLL_35XX_RATE(100000000U, 400, 6, 4),
590 static struct samsung_pll_rate_table exynos5443_aud_pll_rates[] = {
591 PLL_36XX_RATE(400000000U, 200, 3, 2, 0),
592 PLL_36XX_RATE(393216000U, 197, 3, 2, -25690),
593 PLL_36XX_RATE(384000000U, 128, 2, 2, 0),
594 PLL_36XX_RATE(368640000U, 246, 4, 2, -15729),
595 PLL_36XX_RATE(361507200U, 181, 3, 2, -16148),
596 PLL_36XX_RATE(338688000U, 113, 2, 2, -6816),
597 PLL_36XX_RATE(294912000U, 98, 1, 3, 19923),
598 PLL_36XX_RATE(288000000U, 96, 1, 3, 0),
599 PLL_36XX_RATE(252000000U, 84, 1, 3, 0),
603 static struct samsung_pll_clock top_pll_clks[] __initdata = {
604 PLL(pll_35xx, CLK_FOUT_ISP_PLL, "fout_isp_pll", "oscclk",
605 ISP_PLL_LOCK, ISP_PLL_CON0, exynos5443_pll_rates),
606 PLL(pll_36xx, CLK_FOUT_AUD_PLL, "fout_aud_pll", "oscclk",
607 AUD_PLL_LOCK, AUD_PLL_CON0, exynos5443_aud_pll_rates),
610 static struct samsung_cmu_info top_cmu_info __initdata = {
611 .pll_clks = top_pll_clks,
612 .nr_pll_clks = ARRAY_SIZE(top_pll_clks),
613 .mux_clks = top_mux_clks,
614 .nr_mux_clks = ARRAY_SIZE(top_mux_clks),
615 .div_clks = top_div_clks,
616 .nr_div_clks = ARRAY_SIZE(top_div_clks),
617 .gate_clks = top_gate_clks,
618 .nr_gate_clks = ARRAY_SIZE(top_gate_clks),
619 .fixed_clks = top_fixed_clks,
620 .nr_fixed_clks = ARRAY_SIZE(top_fixed_clks),
621 .fixed_factor_clks = top_fixed_factor_clks,
622 .nr_fixed_factor_clks = ARRAY_SIZE(top_fixed_factor_clks),
623 .nr_clk_ids = TOP_NR_CLK,
624 .clk_regs = top_clk_regs,
625 .nr_clk_regs = ARRAY_SIZE(top_clk_regs),
628 static void __init exynos5433_cmu_top_init(struct device_node *np)
630 samsung_cmu_register_one(np, &top_cmu_info);
632 CLK_OF_DECLARE(exynos5433_cmu_top, "samsung,exynos5433-cmu-top",
633 exynos5433_cmu_top_init);
636 * Register offset definitions for CMU_CPIF
638 #define MPHY_PLL_LOCK 0x0000
639 #define MPHY_PLL_CON0 0x0100
640 #define MPHY_PLL_CON1 0x0104
641 #define MPHY_PLL_FREQ_DET 0x010c
642 #define MUX_SEL_CPIF0 0x0200
643 #define DIV_CPIF 0x0600
644 #define ENABLE_SCLK_CPIF 0x0a00
646 static unsigned long cpif_clk_regs[] __initdata = {
655 /* list of all parent clock list */
656 PNAME(mout_mphy_pll_p) = { "oscclk", "fout_mphy_pll", };
658 static struct samsung_pll_clock cpif_pll_clks[] __initdata = {
659 PLL(pll_35xx, CLK_FOUT_MPHY_PLL, "fout_mphy_pll", "oscclk",
660 MPHY_PLL_LOCK, MPHY_PLL_CON0, exynos5443_pll_rates),
663 static struct samsung_mux_clock cpif_mux_clks[] __initdata = {
665 MUX(CLK_MOUT_MPHY_PLL, "mout_mphy_pll", mout_mphy_pll_p, MUX_SEL_CPIF0,
669 static struct samsung_div_clock cpif_div_clks[] __initdata = {
671 DIV(CLK_DIV_SCLK_MPHY, "div_sclk_mphy", "mout_mphy_pll", DIV_CPIF,
675 static struct samsung_gate_clock cpif_gate_clks[] __initdata = {
676 /* ENABLE_SCLK_CPIF */
677 GATE(CLK_SCLK_MPHY_PLL, "sclk_mphy_pll", "mout_mphy_pll",
678 ENABLE_SCLK_CPIF, 9, 0, 0),
679 GATE(CLK_SCLK_UFS_MPHY, "sclk_ufs_mphy", "div_sclk_mphy",
680 ENABLE_SCLK_CPIF, 4, 0, 0),
683 static struct samsung_cmu_info cpif_cmu_info __initdata = {
684 .pll_clks = cpif_pll_clks,
685 .nr_pll_clks = ARRAY_SIZE(cpif_pll_clks),
686 .mux_clks = cpif_mux_clks,
687 .nr_mux_clks = ARRAY_SIZE(cpif_mux_clks),
688 .div_clks = cpif_div_clks,
689 .nr_div_clks = ARRAY_SIZE(cpif_div_clks),
690 .gate_clks = cpif_gate_clks,
691 .nr_gate_clks = ARRAY_SIZE(cpif_gate_clks),
692 .nr_clk_ids = CPIF_NR_CLK,
693 .clk_regs = cpif_clk_regs,
694 .nr_clk_regs = ARRAY_SIZE(cpif_clk_regs),
697 static void __init exynos5433_cmu_cpif_init(struct device_node *np)
699 samsung_cmu_register_one(np, &cpif_cmu_info);
701 CLK_OF_DECLARE(exynos5433_cmu_cpif, "samsung,exynos5433-cmu-cpif",
702 exynos5433_cmu_cpif_init);
705 * Register offset definitions for CMU_MIF
707 #define MEM0_PLL_LOCK 0x0000
708 #define MEM1_PLL_LOCK 0x0004
709 #define BUS_PLL_LOCK 0x0008
710 #define MFC_PLL_LOCK 0x000c
711 #define MEM0_PLL_CON0 0x0100
712 #define MEM0_PLL_CON1 0x0104
713 #define MEM0_PLL_FREQ_DET 0x010c
714 #define MEM1_PLL_CON0 0x0110
715 #define MEM1_PLL_CON1 0x0114
716 #define MEM1_PLL_FREQ_DET 0x011c
717 #define BUS_PLL_CON0 0x0120
718 #define BUS_PLL_CON1 0x0124
719 #define BUS_PLL_FREQ_DET 0x012c
720 #define MFC_PLL_CON0 0x0130
721 #define MFC_PLL_CON1 0x0134
722 #define MFC_PLL_FREQ_DET 0x013c
724 static unsigned long mif_clk_regs[] __initdata = {
743 static struct samsung_pll_clock mif_pll_clks[] __initdata = {
744 PLL(pll_35xx, CLK_FOUT_MEM0_PLL, "fout_mem0_pll", "oscclk",
745 MEM0_PLL_LOCK, MEM0_PLL_CON0, exynos5443_pll_rates),
746 PLL(pll_35xx, CLK_FOUT_MEM1_PLL, "fout_mem1_pll", "oscclk",
747 MEM1_PLL_LOCK, MEM1_PLL_CON0, exynos5443_pll_rates),
748 PLL(pll_35xx, CLK_FOUT_BUS_PLL, "fout_bus_pll", "oscclk",
749 BUS_PLL_LOCK, BUS_PLL_CON0, exynos5443_pll_rates),
750 PLL(pll_35xx, CLK_FOUT_MFC_PLL, "fout_mfc_pll", "oscclk",
751 MFC_PLL_LOCK, MFC_PLL_CON0, exynos5443_pll_rates),
754 static struct samsung_cmu_info mif_cmu_info __initdata = {
755 .pll_clks = mif_pll_clks,
756 .nr_pll_clks = ARRAY_SIZE(mif_pll_clks),
757 .nr_clk_ids = MIF_NR_CLK,
758 .clk_regs = mif_clk_regs,
759 .nr_clk_regs = ARRAY_SIZE(mif_clk_regs),
762 static void __init exynos5433_cmu_mif_init(struct device_node *np)
764 samsung_cmu_register_one(np, &mif_cmu_info);
766 CLK_OF_DECLARE(exynos5433_cmu_mif, "samsung,exynos5433-cmu-mif",
767 exynos5433_cmu_mif_init);
770 * Register offset definitions for CMU_PERIC
772 #define DIV_PERIC 0x0600
773 #define DIV_STAT_PERIC 0x0700
774 #define ENABLE_ACLK_PERIC 0x0800
775 #define ENABLE_PCLK_PERIC0 0x0900
776 #define ENABLE_PCLK_PERIC1 0x0904
777 #define ENABLE_SCLK_PERIC 0x0A00
778 #define ENABLE_IP_PERIC0 0x0B00
779 #define ENABLE_IP_PERIC1 0x0B04
780 #define ENABLE_IP_PERIC2 0x0B08
782 static unsigned long peric_clk_regs[] __initdata = {
794 static struct samsung_div_clock peric_div_clks[] __initdata = {
796 DIV(CLK_DIV_SCLK_SCI, "div_sclk_sci", "oscclk", DIV_PERIC, 4, 4),
797 DIV(CLK_DIV_SCLK_SC_IN, "div_sclk_sc_in", "oscclk", DIV_PERIC, 0, 4),
800 static struct samsung_gate_clock peric_gate_clks[] __initdata = {
801 /* ENABLE_ACLK_PERIC */
802 GATE(CLK_ACLK_AHB2APB_PERIC2P, "aclk_ahb2apb_peric2p", "aclk_peric_66",
803 ENABLE_ACLK_PERIC, 3, CLK_IGNORE_UNUSED, 0),
804 GATE(CLK_ACLK_AHB2APB_PERIC1P, "aclk_ahb2apb_peric1p", "aclk_peric_66",
805 ENABLE_ACLK_PERIC, 2, CLK_IGNORE_UNUSED, 0),
806 GATE(CLK_ACLK_AHB2APB_PERIC0P, "aclk_ahb2apb_peric0p", "aclk_peric_66",
807 ENABLE_ACLK_PERIC, 1, CLK_IGNORE_UNUSED, 0),
808 GATE(CLK_ACLK_PERICNP_66, "aclk_pericnp_66", "aclk_peric_66",
809 ENABLE_ACLK_PERIC, 0, CLK_IGNORE_UNUSED, 0),
811 /* ENABLE_PCLK_PERIC0 */
812 GATE(CLK_PCLK_SCI, "pclk_sci", "aclk_peric_66", ENABLE_PCLK_PERIC0,
813 31, CLK_SET_RATE_PARENT, 0),
814 GATE(CLK_PCLK_GPIO_FINGER, "pclk_gpio_finger", "aclk_peric_66",
815 ENABLE_PCLK_PERIC0, 30, CLK_IGNORE_UNUSED, 0),
816 GATE(CLK_PCLK_GPIO_ESE, "pclk_gpio_ese", "aclk_peric_66",
817 ENABLE_PCLK_PERIC0, 29, CLK_IGNORE_UNUSED, 0),
818 GATE(CLK_PCLK_PWM, "pclk_pwm", "aclk_peric_66", ENABLE_PCLK_PERIC0,
819 28, CLK_SET_RATE_PARENT, 0),
820 GATE(CLK_PCLK_SPDIF, "pclk_spdif", "aclk_peric_66", ENABLE_PCLK_PERIC0,
821 26, CLK_SET_RATE_PARENT, 0),
822 GATE(CLK_PCLK_PCM1, "pclk_pcm1", "aclk_peric_66", ENABLE_PCLK_PERIC0,
823 25, CLK_SET_RATE_PARENT, 0),
824 GATE(CLK_PCLK_I2S1, "pclk_i2s", "aclk_peric_66", ENABLE_PCLK_PERIC0,
825 24, CLK_SET_RATE_PARENT, 0),
826 GATE(CLK_PCLK_SPI2, "pclk_spi2", "aclk_peric_66", ENABLE_PCLK_PERIC0,
827 23, CLK_SET_RATE_PARENT, 0),
828 GATE(CLK_PCLK_SPI1, "pclk_spi1", "aclk_peric_66", ENABLE_PCLK_PERIC0,
829 22, CLK_SET_RATE_PARENT, 0),
830 GATE(CLK_PCLK_SPI0, "pclk_spi0", "aclk_peric_66", ENABLE_PCLK_PERIC0,
831 21, CLK_SET_RATE_PARENT, 0),
832 GATE(CLK_PCLK_ADCIF, "pclk_adcif", "aclk_peric_66", ENABLE_PCLK_PERIC0,
833 20, CLK_SET_RATE_PARENT, 0),
834 GATE(CLK_PCLK_GPIO_TOUCH, "pclk_gpio_touch", "aclk_peric_66",
835 ENABLE_PCLK_PERIC0, 19, CLK_IGNORE_UNUSED, 0),
836 GATE(CLK_PCLK_GPIO_NFC, "pclk_gpio_nfc", "aclk_peric_66",
837 ENABLE_PCLK_PERIC0, 18, CLK_IGNORE_UNUSED, 0),
838 GATE(CLK_PCLK_GPIO_PERIC, "pclk_gpio_peric", "aclk_peric_66",
839 ENABLE_PCLK_PERIC0, 17, CLK_IGNORE_UNUSED, 0),
840 GATE(CLK_PCLK_PMU_PERIC, "pclk_pmu_peric", "aclk_peric_66",
841 ENABLE_PCLK_PERIC0, 16, CLK_SET_RATE_PARENT, 0),
842 GATE(CLK_PCLK_SYSREG_PERIC, "pclk_sysreg_peric", "aclk_peric_66",
843 ENABLE_PCLK_PERIC0, 15,
844 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
845 GATE(CLK_PCLK_UART2, "pclk_uart2", "aclk_peric_66", ENABLE_PCLK_PERIC0,
846 14, CLK_SET_RATE_PARENT, 0),
847 GATE(CLK_PCLK_UART1, "pclk_uart1", "aclk_peric_66", ENABLE_PCLK_PERIC0,
848 13, CLK_SET_RATE_PARENT, 0),
849 GATE(CLK_PCLK_UART0, "pclk_uart0", "aclk_peric_66", ENABLE_PCLK_PERIC0,
850 12, CLK_SET_RATE_PARENT, 0),
851 GATE(CLK_PCLK_HSI2C3, "pclk_hsi2c3", "aclk_peric_66",
852 ENABLE_PCLK_PERIC0, 11, CLK_SET_RATE_PARENT, 0),
853 GATE(CLK_PCLK_HSI2C2, "pclk_hsi2c2", "aclk_peric_66",
854 ENABLE_PCLK_PERIC0, 10, CLK_SET_RATE_PARENT, 0),
855 GATE(CLK_PCLK_HSI2C1, "pclk_hsi2c1", "aclk_peric_66",
856 ENABLE_PCLK_PERIC0, 9, CLK_SET_RATE_PARENT, 0),
857 GATE(CLK_PCLK_HSI2C0, "pclk_hsi2c0", "aclk_peric_66",
858 ENABLE_PCLK_PERIC0, 8, CLK_SET_RATE_PARENT, 0),
859 GATE(CLK_PCLK_I2C7, "pclk_i2c7", "aclk_peric_66", ENABLE_PCLK_PERIC0,
860 7, CLK_SET_RATE_PARENT, 0),
861 GATE(CLK_PCLK_I2C6, "pclk_i2c6", "aclk_peric_66", ENABLE_PCLK_PERIC0,
862 6, CLK_SET_RATE_PARENT, 0),
863 GATE(CLK_PCLK_I2C5, "pclk_i2c5", "aclk_peric_66", ENABLE_PCLK_PERIC0,
864 5, CLK_SET_RATE_PARENT, 0),
865 GATE(CLK_PCLK_I2C4, "pclk_i2c4", "aclk_peric_66", ENABLE_PCLK_PERIC0,
866 4, CLK_SET_RATE_PARENT, 0),
867 GATE(CLK_PCLK_I2C3, "pclk_i2c3", "aclk_peric_66", ENABLE_PCLK_PERIC0,
868 3, CLK_SET_RATE_PARENT, 0),
869 GATE(CLK_PCLK_I2C2, "pclk_i2c2", "aclk_peric_66", ENABLE_PCLK_PERIC0,
870 2, CLK_SET_RATE_PARENT, 0),
871 GATE(CLK_PCLK_I2C1, "pclk_i2c1", "aclk_peric_66", ENABLE_PCLK_PERIC0,
872 1, CLK_SET_RATE_PARENT, 0),
873 GATE(CLK_PCLK_I2C0, "pclk_i2c0", "aclk_peric_66", ENABLE_PCLK_PERIC0,
874 0, CLK_SET_RATE_PARENT, 0),
876 /* ENABLE_PCLK_PERIC1 */
877 GATE(CLK_PCLK_SPI4, "pclk_spi4", "aclk_peric_66", ENABLE_PCLK_PERIC1,
878 9, CLK_SET_RATE_PARENT, 0),
879 GATE(CLK_PCLK_SPI3, "pclk_spi3", "aclk_peric_66", ENABLE_PCLK_PERIC1,
880 8, CLK_SET_RATE_PARENT, 0),
881 GATE(CLK_PCLK_HSI2C11, "pclk_hsi2c11", "aclk_peric_66",
882 ENABLE_PCLK_PERIC1, 7, CLK_SET_RATE_PARENT, 0),
883 GATE(CLK_PCLK_HSI2C10, "pclk_hsi2c10", "aclk_peric_66",
884 ENABLE_PCLK_PERIC1, 6, CLK_SET_RATE_PARENT, 0),
885 GATE(CLK_PCLK_HSI2C9, "pclk_hsi2c9", "aclk_peric_66",
886 ENABLE_PCLK_PERIC1, 5, CLK_SET_RATE_PARENT, 0),
887 GATE(CLK_PCLK_HSI2C8, "pclk_hsi2c8", "aclk_peric_66",
888 ENABLE_PCLK_PERIC1, 4, CLK_SET_RATE_PARENT, 0),
889 GATE(CLK_PCLK_HSI2C7, "pclk_hsi2c7", "aclk_peric_66",
890 ENABLE_PCLK_PERIC1, 3, CLK_SET_RATE_PARENT, 0),
891 GATE(CLK_PCLK_HSI2C6, "pclk_hsi2c6", "aclk_peric_66",
892 ENABLE_PCLK_PERIC1, 2, CLK_SET_RATE_PARENT, 0),
893 GATE(CLK_PCLK_HSI2C5, "pclk_hsi2c5", "aclk_peric_66",
894 ENABLE_PCLK_PERIC1, 1, CLK_SET_RATE_PARENT, 0),
895 GATE(CLK_PCLK_HSI2C4, "pclk_hsi2c4", "aclk_peric_66",
896 ENABLE_PCLK_PERIC1, 0, CLK_SET_RATE_PARENT, 0),
898 /* ENABLE_SCLK_PERIC */
899 GATE(CLK_SCLK_IOCLK_SPI4, "sclk_ioclk_spi4", "ioclk_spi4_clk_in",
900 ENABLE_SCLK_PERIC, 21, CLK_SET_RATE_PARENT, 0),
901 GATE(CLK_SCLK_IOCLK_SPI3, "sclk_ioclk_spi3", "ioclk_spi3_clk_in",
902 ENABLE_SCLK_PERIC, 20, CLK_SET_RATE_PARENT, 0),
903 GATE(CLK_SCLK_SPI4, "sclk_spi4", "sclk_spi4_peric", ENABLE_SCLK_PERIC,
904 19, CLK_SET_RATE_PARENT, 0),
905 GATE(CLK_SCLK_SPI3, "sclk_spi3", "sclk_spi3_peric", ENABLE_SCLK_PERIC,
906 18, CLK_SET_RATE_PARENT, 0),
907 GATE(CLK_SCLK_SCI, "sclk_sci", "div_sclk_sci", ENABLE_SCLK_PERIC,
909 GATE(CLK_SCLK_SC_IN, "sclk_sc_in", "div_sclk_sc_in", ENABLE_SCLK_PERIC,
911 GATE(CLK_SCLK_PWM, "sclk_pwm", "oscclk", ENABLE_SCLK_PERIC, 15, 0, 0),
912 GATE(CLK_SCLK_IOCLK_SPI2, "sclk_ioclk_spi2", "ioclk_spi2_clk_in",
913 ENABLE_SCLK_PERIC, 13, CLK_SET_RATE_PARENT, 0),
914 GATE(CLK_SCLK_IOCLK_SPI1, "sclk_ioclk_spi1", "ioclk_spi1_clk_in",
915 ENABLE_SCLK_PERIC, 12,
916 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
917 GATE(CLK_SCLK_IOCLK_SPI0, "sclk_ioclk_spi0", "ioclk_spi0_clk_in",
918 ENABLE_SCLK_PERIC, 11, CLK_SET_RATE_PARENT, 0),
919 GATE(CLK_SCLK_IOCLK_I2S1_BCLK, "sclk_ioclk_i2s1_bclk",
920 "ioclk_i2s1_bclk_in", ENABLE_SCLK_PERIC, 10,
921 CLK_SET_RATE_PARENT, 0),
922 GATE(CLK_SCLK_SPDIF, "sclk_spdif", "sclk_spdif_peric",
923 ENABLE_SCLK_PERIC, 8, CLK_SET_RATE_PARENT, 0),
924 GATE(CLK_SCLK_PCM1, "sclk_pcm1", "sclk_pcm1_peric",
925 ENABLE_SCLK_PERIC, 7, CLK_SET_RATE_PARENT, 0),
926 GATE(CLK_SCLK_I2S1, "sclk_i2s1", "sclk_i2s1_peric",
927 ENABLE_SCLK_PERIC, 6, CLK_SET_RATE_PARENT, 0),
928 GATE(CLK_SCLK_SPI2, "sclk_spi2", "sclk_spi2_peric", ENABLE_SCLK_PERIC,
929 5, CLK_SET_RATE_PARENT, 0),
930 GATE(CLK_SCLK_SPI1, "sclk_spi1", "sclk_spi1_peric", ENABLE_SCLK_PERIC,
931 4, CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
932 GATE(CLK_SCLK_SPI0, "sclk_spi0", "sclk_spi0_peric", ENABLE_SCLK_PERIC,
933 3, CLK_SET_RATE_PARENT, 0),
934 GATE(CLK_SCLK_UART2, "sclk_uart2", "sclk_uart2_peric",
935 ENABLE_SCLK_PERIC, 2, CLK_SET_RATE_PARENT, 0),
936 GATE(CLK_SCLK_UART1, "sclk_uart1", "sclk_uart1_peric",
937 ENABLE_SCLK_PERIC, 1, CLK_SET_RATE_PARENT, 0),
938 GATE(CLK_SCLK_UART0, "sclk_uart0", "sclk_uart0_peric",
939 ENABLE_SCLK_PERIC, 0, CLK_SET_RATE_PARENT, 0),
942 static struct samsung_cmu_info peric_cmu_info __initdata = {
943 .div_clks = peric_div_clks,
944 .nr_div_clks = ARRAY_SIZE(peric_div_clks),
945 .gate_clks = peric_gate_clks,
946 .nr_gate_clks = ARRAY_SIZE(peric_gate_clks),
947 .nr_clk_ids = PERIC_NR_CLK,
948 .clk_regs = peric_clk_regs,
949 .nr_clk_regs = ARRAY_SIZE(peric_clk_regs),
952 static void __init exynos5433_cmu_peric_init(struct device_node *np)
954 samsung_cmu_register_one(np, &peric_cmu_info);
957 CLK_OF_DECLARE(exynos5433_cmu_peric, "samsung,exynos5433-cmu-peric",
958 exynos5433_cmu_peric_init);
961 * Register offset definitions for CMU_PERIS
963 #define ENABLE_ACLK_PERIS 0x0800
964 #define ENABLE_PCLK_PERIS 0x0900
965 #define ENABLE_PCLK_PERIS_SECURE_TZPC 0x0904
966 #define ENABLE_PCLK_PERIS_SECURE_SECKEY_APBIF 0x0908
967 #define ENABLE_PCLK_PERIS_SECURE_CHIPID_APBIF 0x090c
968 #define ENABLE_PCLK_PERIS_SECURE_TOPRTC 0x0910
969 #define ENABLE_PCLK_PERIS_SECURE_CUSTOM_EFUSE_APBIF 0x0914
970 #define ENABLE_PCLK_PERIS_SECURE_ANTIRBK_CNT_APBIF 0x0918
971 #define ENABLE_PCLK_PERIS_SECURE_OTP_CON_APBIF 0x091c
972 #define ENABLE_SCLK_PERIS 0x0a00
973 #define ENABLE_SCLK_PERIS_SECURE_SECKEY 0x0a04
974 #define ENABLE_SCLK_PERIS_SECURE_CHIPID 0x0a08
975 #define ENABLE_SCLK_PERIS_SECURE_TOPRTC 0x0a0c
976 #define ENABLE_SCLK_PERIS_SECURE_CUSTOM_EFUSE 0x0a10
977 #define ENABLE_SCLK_PERIS_SECURE_ANTIRBK_CNT 0x0a14
978 #define ENABLE_SCLK_PERIS_SECURE_OTP_CON 0x0a18
979 #define ENABLE_IP_PERIS0 0x0b00
980 #define ENABLE_IP_PERIS1 0x0b04
981 #define ENABLE_IP_PERIS_SECURE_TZPC 0x0b08
982 #define ENABLE_IP_PERIS_SECURE_SECKEY 0x0b0c
983 #define ENABLE_IP_PERIS_SECURE_CHIPID 0x0b10
984 #define ENABLE_IP_PERIS_SECURE_TOPRTC 0x0b14
985 #define ENABLE_IP_PERIS_SECURE_CUSTOM_EFUSE 0x0b18
986 #define ENABLE_IP_PERIS_SECURE_ANTIBRK_CNT 0x0b1c
987 #define ENABLE_IP_PERIS_SECURE_OTP_CON 0x0b20
989 static unsigned long peris_clk_regs[] __initdata = {
992 ENABLE_PCLK_PERIS_SECURE_TZPC,
993 ENABLE_PCLK_PERIS_SECURE_SECKEY_APBIF,
994 ENABLE_PCLK_PERIS_SECURE_CHIPID_APBIF,
995 ENABLE_PCLK_PERIS_SECURE_TOPRTC,
996 ENABLE_PCLK_PERIS_SECURE_CUSTOM_EFUSE_APBIF,
997 ENABLE_PCLK_PERIS_SECURE_ANTIRBK_CNT_APBIF,
998 ENABLE_PCLK_PERIS_SECURE_OTP_CON_APBIF,
1000 ENABLE_SCLK_PERIS_SECURE_SECKEY,
1001 ENABLE_SCLK_PERIS_SECURE_CHIPID,
1002 ENABLE_SCLK_PERIS_SECURE_TOPRTC,
1003 ENABLE_SCLK_PERIS_SECURE_CUSTOM_EFUSE,
1004 ENABLE_SCLK_PERIS_SECURE_ANTIRBK_CNT,
1005 ENABLE_SCLK_PERIS_SECURE_OTP_CON,
1008 ENABLE_IP_PERIS_SECURE_TZPC,
1009 ENABLE_IP_PERIS_SECURE_SECKEY,
1010 ENABLE_IP_PERIS_SECURE_CHIPID,
1011 ENABLE_IP_PERIS_SECURE_TOPRTC,
1012 ENABLE_IP_PERIS_SECURE_CUSTOM_EFUSE,
1013 ENABLE_IP_PERIS_SECURE_ANTIBRK_CNT,
1014 ENABLE_IP_PERIS_SECURE_OTP_CON,
1017 static struct samsung_gate_clock peris_gate_clks[] __initdata = {
1018 /* ENABLE_ACLK_PERIS */
1019 GATE(CLK_ACLK_AHB2APB_PERIS1P, "aclk_ahb2apb_peris1p", "aclk_peris_66",
1020 ENABLE_ACLK_PERIS, 2, CLK_IGNORE_UNUSED, 0),
1021 GATE(CLK_ACLK_AHB2APB_PERIS0P, "aclk_ahb2apb_peris0p", "aclk_peris_66",
1022 ENABLE_ACLK_PERIS, 1, CLK_IGNORE_UNUSED, 0),
1023 GATE(CLK_ACLK_PERISNP_66, "aclk_perisnp_66", "aclk_peris_66",
1024 ENABLE_ACLK_PERIS, 0, CLK_IGNORE_UNUSED, 0),
1026 /* ENABLE_PCLK_PERIS */
1027 GATE(CLK_PCLK_HPM_APBIF, "pclk_hpm_apbif", "aclk_peris_66",
1028 ENABLE_PCLK_PERIS, 30, CLK_IGNORE_UNUSED, 0),
1029 GATE(CLK_PCLK_TMU1_APBIF, "pclk_tmu1_apbif", "aclk_peris_66",
1030 ENABLE_PCLK_PERIS, 24, CLK_IGNORE_UNUSED, 0),
1031 GATE(CLK_PCLK_TMU0_APBIF, "pclk_tmu0_apbif", "aclk_peris_66",
1032 ENABLE_PCLK_PERIS, 23, CLK_IGNORE_UNUSED, 0),
1033 GATE(CLK_PCLK_PMU_PERIS, "pclk_pmu_peris", "aclk_peris_66",
1034 ENABLE_PCLK_PERIS, 22, CLK_IGNORE_UNUSED, 0),
1035 GATE(CLK_PCLK_SYSREG_PERIS, "pclk_sysreg_peris", "aclk_peris_66",
1036 ENABLE_PCLK_PERIS, 21, CLK_IGNORE_UNUSED, 0),
1037 GATE(CLK_PCLK_CMU_TOP_APBIF, "pclk_cmu_top_apbif", "aclk_peris_66",
1038 ENABLE_PCLK_PERIS, 20, CLK_IGNORE_UNUSED, 0),
1039 GATE(CLK_PCLK_WDT_APOLLO, "pclk_wdt_apollo", "aclk_peris_66",
1040 ENABLE_PCLK_PERIS, 17, CLK_IGNORE_UNUSED, 0),
1041 GATE(CLK_PCLK_WDT_ATLAS, "pclk_wdt_atlas", "aclk_peris_66",
1042 ENABLE_PCLK_PERIS, 16, CLK_IGNORE_UNUSED, 0),
1043 GATE(CLK_PCLK_MCT, "pclk_mct", "aclk_peris_66",
1044 ENABLE_PCLK_PERIS, 15, CLK_IGNORE_UNUSED, 0),
1045 GATE(CLK_PCLK_HDMI_CEC, "pclk_hdmi_cec", "aclk_peris_66",
1046 ENABLE_PCLK_PERIS, 14, CLK_IGNORE_UNUSED, 0),
1048 /* ENABLE_PCLK_PERIS_SECURE_TZPC */
1049 GATE(CLK_PCLK_TZPC12, "pclk_tzpc12", "aclk_peris_66",
1050 ENABLE_PCLK_PERIS_SECURE_TZPC, 12, 0, 0),
1051 GATE(CLK_PCLK_TZPC11, "pclk_tzpc11", "aclk_peris_66",
1052 ENABLE_PCLK_PERIS_SECURE_TZPC, 11, 0, 0),
1053 GATE(CLK_PCLK_TZPC10, "pclk_tzpc10", "aclk_peris_66",
1054 ENABLE_PCLK_PERIS_SECURE_TZPC, 10, 0, 0),
1055 GATE(CLK_PCLK_TZPC9, "pclk_tzpc9", "aclk_peris_66",
1056 ENABLE_PCLK_PERIS_SECURE_TZPC, 9, 0, 0),
1057 GATE(CLK_PCLK_TZPC8, "pclk_tzpc8", "aclk_peris_66",
1058 ENABLE_PCLK_PERIS_SECURE_TZPC, 8, 0, 0),
1059 GATE(CLK_PCLK_TZPC7, "pclk_tzpc7", "aclk_peris_66",
1060 ENABLE_PCLK_PERIS_SECURE_TZPC, 7, 0, 0),
1061 GATE(CLK_PCLK_TZPC6, "pclk_tzpc6", "aclk_peris_66",
1062 ENABLE_PCLK_PERIS_SECURE_TZPC, 6, 0, 0),
1063 GATE(CLK_PCLK_TZPC5, "pclk_tzpc5", "aclk_peris_66",
1064 ENABLE_PCLK_PERIS_SECURE_TZPC, 5, 0, 0),
1065 GATE(CLK_PCLK_TZPC4, "pclk_tzpc4", "aclk_peris_66",
1066 ENABLE_PCLK_PERIS_SECURE_TZPC, 4, 0, 0),
1067 GATE(CLK_PCLK_TZPC3, "pclk_tzpc3", "aclk_peris_66",
1068 ENABLE_PCLK_PERIS_SECURE_TZPC, 3, 0, 0),
1069 GATE(CLK_PCLK_TZPC2, "pclk_tzpc2", "aclk_peris_66",
1070 ENABLE_PCLK_PERIS_SECURE_TZPC, 2, 0, 0),
1071 GATE(CLK_PCLK_TZPC1, "pclk_tzpc1", "aclk_peris_66",
1072 ENABLE_PCLK_PERIS_SECURE_TZPC, 1, 0, 0),
1073 GATE(CLK_PCLK_TZPC0, "pclk_tzpc0", "aclk_peris_66",
1074 ENABLE_PCLK_PERIS_SECURE_TZPC, 0, 0, 0),
1076 /* ENABLE_PCLK_PERIS_SECURE_SECKEY_APBIF */
1077 GATE(CLK_PCLK_SECKEY_APBIF, "pclk_seckey_apbif", "aclk_peris_66",
1078 ENABLE_PCLK_PERIS_SECURE_SECKEY_APBIF, 0, 0, 0),
1080 /* ENABLE_PCLK_PERIS_SECURE_CHIPID_APBIF */
1081 GATE(CLK_PCLK_CHIPID_APBIF, "pclk_chipid_apbif", "aclk_peris_66",
1082 ENABLE_PCLK_PERIS_SECURE_CHIPID_APBIF, 0, 0, 0),
1084 /* ENABLE_PCLK_PERIS_SECURE_TOPRTC */
1085 GATE(CLK_PCLK_TOPRTC, "pclk_toprtc", "aclk_peris_66",
1086 ENABLE_PCLK_PERIS_SECURE_TOPRTC, 0, 0, 0),
1088 /* ENABLE_PCLK_PERIS_SECURE_CUSTOM_EFUSE_APBIF */
1089 GATE(CLK_PCLK_CUSTOM_EFUSE_APBIF, "pclk_custom_efuse_apbif",
1091 ENABLE_PCLK_PERIS_SECURE_CUSTOM_EFUSE_APBIF, 0, 0, 0),
1093 /* ENABLE_PCLK_PERIS_SECURE_ANTIRBK_CNT_APBIF */
1094 GATE(CLK_PCLK_ANTIRBK_CNT_APBIF, "pclk_antirbk_cnt_apbif",
1096 ENABLE_PCLK_PERIS_SECURE_ANTIRBK_CNT_APBIF, 0, 0, 0),
1098 /* ENABLE_PCLK_PERIS_SECURE_OTP_CON_APBIF */
1099 GATE(CLK_PCLK_OTP_CON_APBIF, "pclk_otp_con_apbif",
1101 ENABLE_PCLK_PERIS_SECURE_OTP_CON_APBIF, 0, 0, 0),
1103 /* ENABLE_SCLK_PERIS */
1104 GATE(CLK_SCLK_ASV_TB, "sclk_asv_tb", "oscclk_efuse_common",
1105 ENABLE_SCLK_PERIS, 10, 0, 0),
1106 GATE(CLK_SCLK_TMU1, "sclk_tmu1", "oscclk_efuse_common",
1107 ENABLE_SCLK_PERIS, 4, 0, 0),
1108 GATE(CLK_SCLK_TMU0, "sclk_tmu0", "oscclk_efuse_common",
1109 ENABLE_SCLK_PERIS, 3, 0, 0),
1111 /* ENABLE_SCLK_PERIS_SECURE_SECKEY */
1112 GATE(CLK_SCLK_SECKEY, "sclk_seckey", "oscclk_efuse_common",
1113 ENABLE_SCLK_PERIS_SECURE_SECKEY, 0, 0, 0),
1115 /* ENABLE_SCLK_PERIS_SECURE_CHIPID */
1116 GATE(CLK_SCLK_CHIPID, "sclk_chipid", "oscclk_efuse_common",
1117 ENABLE_SCLK_PERIS_SECURE_CHIPID, 0, 0, 0),
1119 /* ENABLE_SCLK_PERIS_SECURE_TOPRTC */
1120 GATE(CLK_SCLK_TOPRTC, "sclk_toprtc", "oscclk_efuse_common",
1121 ENABLE_SCLK_PERIS_SECURE_TOPRTC, 0, 0, 0),
1123 /* ENABLE_SCLK_PERIS_SECURE_CUSTOM_EFUSE */
1124 GATE(CLK_SCLK_CUSTOM_EFUSE, "sclk_custom_efuse", "oscclk_efuse_common",
1125 ENABLE_SCLK_PERIS_SECURE_CUSTOM_EFUSE, 0, 0, 0),
1127 /* ENABLE_SCLK_PERIS_SECURE_ANTIRBK_CNT */
1128 GATE(CLK_SCLK_ANTIRBK_CNT, "sclk_antirbk_cnt", "oscclk_efuse_common",
1129 ENABLE_SCLK_PERIS_SECURE_ANTIRBK_CNT, 0, 0, 0),
1131 /* ENABLE_SCLK_PERIS_SECURE_OTP_CON */
1132 GATE(CLK_SCLK_OTP_CON, "sclk_otp_con", "oscclk_efuse_common",
1133 ENABLE_SCLK_PERIS_SECURE_OTP_CON, 0, 0, 0),
1136 static struct samsung_cmu_info peris_cmu_info __initdata = {
1137 .gate_clks = peris_gate_clks,
1138 .nr_gate_clks = ARRAY_SIZE(peris_gate_clks),
1139 .nr_clk_ids = PERIS_NR_CLK,
1140 .clk_regs = peris_clk_regs,
1141 .nr_clk_regs = ARRAY_SIZE(peris_clk_regs),
1144 static void __init exynos5433_cmu_peris_init(struct device_node *np)
1146 samsung_cmu_register_one(np, &peris_cmu_info);
1149 CLK_OF_DECLARE(exynos5433_cmu_peris, "samsung,exynos5433-cmu-peris",
1150 exynos5433_cmu_peris_init);
1153 * Register offset definitions for CMU_FSYS
1155 #define MUX_SEL_FSYS0 0x0200
1156 #define MUX_SEL_FSYS1 0x0204
1157 #define MUX_SEL_FSYS2 0x0208
1158 #define MUX_SEL_FSYS3 0x020c
1159 #define MUX_SEL_FSYS4 0x0210
1160 #define MUX_ENABLE_FSYS0 0x0300
1161 #define MUX_ENABLE_FSYS1 0x0304
1162 #define MUX_ENABLE_FSYS2 0x0308
1163 #define MUX_ENABLE_FSYS3 0x030c
1164 #define MUX_ENABLE_FSYS4 0x0310
1165 #define MUX_STAT_FSYS0 0x0400
1166 #define MUX_STAT_FSYS1 0x0404
1167 #define MUX_STAT_FSYS2 0x0408
1168 #define MUX_STAT_FSYS3 0x040c
1169 #define MUX_STAT_FSYS4 0x0410
1170 #define MUX_IGNORE_FSYS2 0x0508
1171 #define MUX_IGNORE_FSYS3 0x050c
1172 #define ENABLE_ACLK_FSYS0 0x0800
1173 #define ENABLE_ACLK_FSYS1 0x0804
1174 #define ENABLE_PCLK_FSYS 0x0900
1175 #define ENABLE_SCLK_FSYS 0x0a00
1176 #define ENABLE_IP_FSYS0 0x0b00
1177 #define ENABLE_IP_FSYS1 0x0b04
1179 /* list of all parent clock list */
1180 PNAME(mout_aclk_fsys_200_user_p) = { "oscclk", "div_aclk_fsys_200", };
1181 PNAME(mout_sclk_mmc2_user_p) = { "oscclk", "sclk_mmc2_fsys", };
1182 PNAME(mout_sclk_mmc1_user_p) = { "oscclk", "sclk_mmc1_fsys", };
1183 PNAME(mout_sclk_mmc0_user_p) = { "oscclk", "sclk_mmc0_fsys", };
1185 static unsigned long fsys_clk_regs[] __initdata = {
1211 static struct samsung_mux_clock fsys_mux_clks[] __initdata = {
1213 MUX(CLK_MOUT_ACLK_FSYS_200_USER, "mout_aclk_fsys_200_user",
1214 mout_aclk_fsys_200_user_p, MUX_SEL_FSYS0, 0, 1),
1217 MUX(CLK_MOUT_SCLK_MMC2_USER, "mout_sclk_mmc2_user",
1218 mout_sclk_mmc2_user_p, MUX_SEL_FSYS1, 20, 1),
1219 MUX(CLK_MOUT_SCLK_MMC1_USER, "mout_sclk_mmc1_user",
1220 mout_sclk_mmc1_user_p, MUX_SEL_FSYS1, 16, 1),
1221 MUX(CLK_MOUT_SCLK_MMC0_USER, "mout_sclk_mmc0_user",
1222 mout_sclk_mmc0_user_p, MUX_SEL_FSYS1, 12, 1),
1225 static struct samsung_gate_clock fsys_gate_clks[] __initdata = {
1226 /* ENABLE_ACLK_FSYS0 */
1227 GATE(CLK_ACLK_PCIE, "aclk_pcie", "mout_aclk_fsys_200_user",
1228 ENABLE_ACLK_FSYS0, 13, CLK_IGNORE_UNUSED, 0),
1229 GATE(CLK_ACLK_PDMA1, "aclk_pdma1", "mout_aclk_fsys_200_user",
1230 ENABLE_ACLK_FSYS0, 11, CLK_IGNORE_UNUSED, 0),
1231 GATE(CLK_ACLK_TSI, "aclk_tsi", "mout_aclk_fsys_200_user",
1232 ENABLE_ACLK_FSYS0, 10, CLK_IGNORE_UNUSED, 0),
1233 GATE(CLK_ACLK_MMC2, "aclk_mmc2", "mout_aclk_fsys_200_user",
1234 ENABLE_ACLK_FSYS0, 8, CLK_IGNORE_UNUSED, 0),
1235 GATE(CLK_ACLK_MMC1, "aclk_mmc1", "mout_aclk_fsys_200_user",
1236 ENABLE_ACLK_FSYS0, 7, CLK_IGNORE_UNUSED, 0),
1237 GATE(CLK_ACLK_MMC0, "aclk_mmc0", "mout_aclk_fsys_200_user",
1238 ENABLE_ACLK_FSYS0, 6, CLK_IGNORE_UNUSED, 0),
1239 GATE(CLK_ACLK_UFS, "aclk_ufs", "mout_aclk_fsys_200_user",
1240 ENABLE_ACLK_FSYS0, 5, CLK_IGNORE_UNUSED, 0),
1241 GATE(CLK_ACLK_USBHOST20, "aclk_usbhost20", "mout_aclk_fsys_200_user",
1242 ENABLE_ACLK_FSYS0, 3, CLK_IGNORE_UNUSED, 0),
1243 GATE(CLK_ACLK_USBHOST30, "aclk_usbhost30", "mout_aclk_fsys_200_user",
1244 ENABLE_ACLK_FSYS0, 2, CLK_IGNORE_UNUSED, 0),
1245 GATE(CLK_ACLK_USBDRD30, "aclk_usbdrd30", "mout_aclk_fsys_200_user",
1246 ENABLE_ACLK_FSYS0, 1, CLK_IGNORE_UNUSED, 0),
1247 GATE(CLK_ACLK_PDMA0, "aclk_pdma0", "mout_aclk_fsys_200_user",
1248 ENABLE_ACLK_FSYS0, 0, CLK_IGNORE_UNUSED, 0),
1250 /* ENABLE_SCLK_FSYS */
1251 GATE(CLK_SCLK_MMC2, "sclk_mmc2", "mout_sclk_mmc2_user",
1252 ENABLE_SCLK_FSYS, 4, CLK_SET_RATE_PARENT, 0),
1253 GATE(CLK_SCLK_MMC1, "sclk_mmc1", "mout_sclk_mmc1_user",
1254 ENABLE_SCLK_FSYS, 3, CLK_SET_RATE_PARENT, 0),
1255 GATE(CLK_SCLK_MMC0, "sclk_mmc0", "mout_sclk_mmc0_user",
1256 ENABLE_SCLK_FSYS, 2, CLK_SET_RATE_PARENT, 0),
1258 /* ENABLE_IP_FSYS0 */
1259 GATE(CLK_PDMA1, "pdma1", "aclk_pdma1", ENABLE_IP_FSYS0, 15, 0, 0),
1260 GATE(CLK_PDMA0, "pdma0", "aclk_pdma0", ENABLE_IP_FSYS0, 0, 0, 0),
1263 static struct samsung_cmu_info fsys_cmu_info __initdata = {
1264 .mux_clks = fsys_mux_clks,
1265 .nr_mux_clks = ARRAY_SIZE(fsys_mux_clks),
1266 .gate_clks = fsys_gate_clks,
1267 .nr_gate_clks = ARRAY_SIZE(fsys_gate_clks),
1268 .nr_clk_ids = FSYS_NR_CLK,
1269 .clk_regs = fsys_clk_regs,
1270 .nr_clk_regs = ARRAY_SIZE(fsys_clk_regs),
1273 static void __init exynos5433_cmu_fsys_init(struct device_node *np)
1275 samsung_cmu_register_one(np, &fsys_cmu_info);
1278 CLK_OF_DECLARE(exynos5433_cmu_fsys, "samsung,exynos5433-cmu-fsys",
1279 exynos5433_cmu_fsys_init);