2 * Clock tree for CSR SiRFatlasVI
4 * Copyright (c) 2011 - 2014 Cambridge Silicon Radio Limited, a CSR plc group
7 * Licensed under GPLv2 or later.
10 #include <linux/module.h>
11 #include <linux/bitops.h>
13 #include <linux/clk.h>
14 #include <linux/clkdev.h>
15 #include <linux/clk-provider.h>
16 #include <linux/of_address.h>
17 #include <linux/syscore_ops.h>
20 #include "clk-common.c"
22 static struct clk_dmn clk_mmc01 = {
23 .regofs = SIRFSOC_CLKC_MMC01_CFG,
26 .init = &clk_mmc01_init,
30 static struct clk_dmn clk_mmc23 = {
31 .regofs = SIRFSOC_CLKC_MMC23_CFG,
34 .init = &clk_mmc23_init,
38 static struct clk_dmn clk_mmc45 = {
39 .regofs = SIRFSOC_CLKC_MMC45_CFG,
42 .init = &clk_mmc45_init,
46 static struct clk_init_data clk_nand_init = {
49 .parent_names = dmn_clk_parents,
50 .num_parents = ARRAY_SIZE(dmn_clk_parents),
53 static struct clk_dmn clk_nand = {
54 .regofs = SIRFSOC_CLKC_NAND_CFG,
57 .init = &clk_nand_init,
61 enum atlas6_clk_index {
62 /* 0 1 2 3 4 5 6 7 8 9 */
63 rtc, osc, pll1, pll2, pll3, mem, sys, security, dsp, gps,
64 mf, io, cpu, uart0, uart1, uart2, tsc, i2c0, i2c1, spi0,
65 spi1, pwmc, efuse, pulse, dmac0, dmac1, nand, audio, usp0, usp1,
66 usp2, vip, gfx, gfx2d, lcd, vpp, mmc01, mmc23, mmc45, usbpll,
67 usb0, usb1, cphif, maxclk,
70 static __initdata struct clk_hw *atlas6_clk_hw_array[maxclk] = {
116 static struct clk *atlas6_clks[maxclk];
118 static void __init atlas6_clk_init(struct device_node *np)
120 struct device_node *rscnp;
123 rscnp = of_find_compatible_node(NULL, NULL, "sirf,prima2-rsc");
124 sirfsoc_rsc_vbase = of_iomap(rscnp, 0);
125 if (!sirfsoc_rsc_vbase)
126 panic("unable to map rsc registers\n");
129 sirfsoc_clk_vbase = of_iomap(np, 0);
130 if (!sirfsoc_clk_vbase)
131 panic("unable to map clkc registers\n");
133 /* These are always available (RTC and 26MHz OSC)*/
134 atlas6_clks[rtc] = clk_register_fixed_rate(NULL, "rtc", NULL,
136 atlas6_clks[osc] = clk_register_fixed_rate(NULL, "osc", NULL,
137 CLK_IS_ROOT, 26000000);
139 for (i = pll1; i < maxclk; i++) {
140 atlas6_clks[i] = clk_register(NULL, atlas6_clk_hw_array[i]);
141 BUG_ON(!atlas6_clks[i]);
143 clk_register_clkdev(atlas6_clks[cpu], NULL, "cpu");
144 clk_register_clkdev(atlas6_clks[io], NULL, "io");
145 clk_register_clkdev(atlas6_clks[mem], NULL, "mem");
146 clk_register_clkdev(atlas6_clks[mem], NULL, "osc");
148 clk_data.clks = atlas6_clks;
149 clk_data.clk_num = maxclk;
151 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
153 CLK_OF_DECLARE(atlas6_clk, "sirf,atlas6-clkc", atlas6_clk_init);