drivers/clk/sirf/clk-atlas7.c

   1 /*
   2  * Clock tree for CSR SiRFAtlas7
   3  *
   4  * Copyright (c) 2014 Cambridge Silicon Radio Limited, a CSR plc group company.
   5  *
   6  * Licensed under GPLv2 or later.
   7  */
   8
   9 #include <linux/bitops.h>
  10 #include <linux/io.h>
  11 #include <linux/clk-provider.h>
  12 #include <linux/delay.h>
  13 #include <linux/of_address.h>
  14 #include <linux/reset-controller.h>
  15 #include <linux/slab.h>
  16
  17 #define SIRFSOC_CLKC_MEMPLL_AB_FREQ          0x0000
  18 #define SIRFSOC_CLKC_MEMPLL_AB_SSC           0x0004
  19 #define SIRFSOC_CLKC_MEMPLL_AB_CTRL0         0x0008
  20 #define SIRFSOC_CLKC_MEMPLL_AB_CTRL1         0x000c
  21 #define SIRFSOC_CLKC_MEMPLL_AB_STATUS        0x0010
  22 #define SIRFSOC_CLKC_MEMPLL_AB_SSRAM_ADDR    0x0014
  23 #define SIRFSOC_CLKC_MEMPLL_AB_SSRAM_DATA    0x0018
  24
  25 #define SIRFSOC_CLKC_CPUPLL_AB_FREQ          0x001c
  26 #define SIRFSOC_CLKC_CPUPLL_AB_SSC           0x0020
  27 #define SIRFSOC_CLKC_CPUPLL_AB_CTRL0         0x0024
  28 #define SIRFSOC_CLKC_CPUPLL_AB_CTRL1         0x0028
  29 #define SIRFSOC_CLKC_CPUPLL_AB_STATUS        0x002c
  30
  31 #define SIRFSOC_CLKC_SYS0PLL_AB_FREQ         0x0030
  32 #define SIRFSOC_CLKC_SYS0PLL_AB_SSC          0x0034
  33 #define SIRFSOC_CLKC_SYS0PLL_AB_CTRL0        0x0038
  34 #define SIRFSOC_CLKC_SYS0PLL_AB_CTRL1        0x003c
  35 #define SIRFSOC_CLKC_SYS0PLL_AB_STATUS       0x0040
  36
  37 #define SIRFSOC_CLKC_SYS1PLL_AB_FREQ         0x0044
  38 #define SIRFSOC_CLKC_SYS1PLL_AB_SSC          0x0048
  39 #define SIRFSOC_CLKC_SYS1PLL_AB_CTRL0        0x004c
  40 #define SIRFSOC_CLKC_SYS1PLL_AB_CTRL1        0x0050
  41 #define SIRFSOC_CLKC_SYS1PLL_AB_STATUS       0x0054
  42
  43 #define SIRFSOC_CLKC_SYS2PLL_AB_FREQ         0x0058
  44 #define SIRFSOC_CLKC_SYS2PLL_AB_SSC          0x005c
  45 #define SIRFSOC_CLKC_SYS2PLL_AB_CTRL0        0x0060
  46 #define SIRFSOC_CLKC_SYS2PLL_AB_CTRL1        0x0064
  47 #define SIRFSOC_CLKC_SYS2PLL_AB_STATUS       0x0068
  48
  49 #define SIRFSOC_CLKC_SYS3PLL_AB_FREQ         0x006c
  50 #define SIRFSOC_CLKC_SYS3PLL_AB_SSC          0x0070
  51 #define SIRFSOC_CLKC_SYS3PLL_AB_CTRL0        0x0074
  52 #define SIRFSOC_CLKC_SYS3PLL_AB_CTRL1        0x0078
  53 #define SIRFSOC_CLKC_SYS3PLL_AB_STATUS       0x007c
  54
  55 #define SIRFSOC_ABPLL_CTRL0_SSEN     0x00001000
  56 #define SIRFSOC_ABPLL_CTRL0_BYPASS   0x00000010
  57 #define SIRFSOC_ABPLL_CTRL0_RESET    0x00000001
  58
  59 #define SIRFSOC_CLKC_AUDIO_DTO_INC           0x0088
  60 #define SIRFSOC_CLKC_DISP0_DTO_INC           0x008c
  61 #define SIRFSOC_CLKC_DISP1_DTO_INC           0x0090
  62
  63 #define SIRFSOC_CLKC_AUDIO_DTO_SRC           0x0094
  64 #define SIRFSOC_CLKC_AUDIO_DTO_ENA           0x0098
  65 #define SIRFSOC_CLKC_AUDIO_DTO_DROFF         0x009c
  66
  67 #define SIRFSOC_CLKC_DISP0_DTO_SRC           0x00a0
  68 #define SIRFSOC_CLKC_DISP0_DTO_ENA           0x00a4
  69 #define SIRFSOC_CLKC_DISP0_DTO_DROFF         0x00a8
  70
  71 #define SIRFSOC_CLKC_DISP1_DTO_SRC           0x00ac
  72 #define SIRFSOC_CLKC_DISP1_DTO_ENA           0x00b0
  73 #define SIRFSOC_CLKC_DISP1_DTO_DROFF         0x00b4
  74
  75 #define SIRFSOC_CLKC_I2S_CLK_SEL             0x00b8
  76 #define SIRFSOC_CLKC_I2S_SEL_STAT            0x00bc
  77
  78 #define SIRFSOC_CLKC_USBPHY_CLKDIV_CFG       0x00c0
  79 #define SIRFSOC_CLKC_USBPHY_CLKDIV_ENA       0x00c4
  80 #define SIRFSOC_CLKC_USBPHY_CLK_SEL          0x00c8
  81 #define SIRFSOC_CLKC_USBPHY_CLK_SEL_STAT     0x00cc
  82
  83 #define SIRFSOC_CLKC_BTSS_CLKDIV_CFG         0x00d0
  84 #define SIRFSOC_CLKC_BTSS_CLKDIV_ENA         0x00d4
  85 #define SIRFSOC_CLKC_BTSS_CLK_SEL            0x00d8
  86 #define SIRFSOC_CLKC_BTSS_CLK_SEL_STAT       0x00dc
  87
  88 #define SIRFSOC_CLKC_RGMII_CLKDIV_CFG        0x00e0
  89 #define SIRFSOC_CLKC_RGMII_CLKDIV_ENA        0x00e4
  90 #define SIRFSOC_CLKC_RGMII_CLK_SEL           0x00e8
  91 #define SIRFSOC_CLKC_RGMII_CLK_SEL_STAT      0x00ec
  92
  93 #define SIRFSOC_CLKC_CPU_CLKDIV_CFG          0x00f0
  94 #define SIRFSOC_CLKC_CPU_CLKDIV_ENA          0x00f4
  95 #define SIRFSOC_CLKC_CPU_CLK_SEL             0x00f8
  96 #define SIRFSOC_CLKC_CPU_CLK_SEL_STAT        0x00fc
  97
  98 #define SIRFSOC_CLKC_SDPHY01_CLKDIV_CFG      0x0100
  99 #define SIRFSOC_CLKC_SDPHY01_CLKDIV_ENA      0x0104
 100 #define SIRFSOC_CLKC_SDPHY01_CLK_SEL         0x0108
 101 #define SIRFSOC_CLKC_SDPHY01_CLK_SEL_STAT    0x010c
 102
 103 #define SIRFSOC_CLKC_SDPHY23_CLKDIV_CFG      0x0110
 104 #define SIRFSOC_CLKC_SDPHY23_CLKDIV_ENA      0x0114
 105 #define SIRFSOC_CLKC_SDPHY23_CLK_SEL         0x0118
 106 #define SIRFSOC_CLKC_SDPHY23_CLK_SEL_STAT    0x011c
 107
 108 #define SIRFSOC_CLKC_SDPHY45_CLKDIV_CFG      0x0120
 109 #define SIRFSOC_CLKC_SDPHY45_CLKDIV_ENA      0x0124
 110 #define SIRFSOC_CLKC_SDPHY45_CLK_SEL         0x0128
 111 #define SIRFSOC_CLKC_SDPHY45_CLK_SEL_STAT    0x012c
 112
 113 #define SIRFSOC_CLKC_SDPHY67_CLKDIV_CFG      0x0130
 114 #define SIRFSOC_CLKC_SDPHY67_CLKDIV_ENA      0x0134
 115 #define SIRFSOC_CLKC_SDPHY67_CLK_SEL         0x0138
 116 #define SIRFSOC_CLKC_SDPHY67_CLK_SEL_STAT    0x013c
 117
 118 #define SIRFSOC_CLKC_CAN_CLKDIV_CFG          0x0140
 119 #define SIRFSOC_CLKC_CAN_CLKDIV_ENA          0x0144
 120 #define SIRFSOC_CLKC_CAN_CLK_SEL             0x0148
 121 #define SIRFSOC_CLKC_CAN_CLK_SEL_STAT        0x014c
 122
 123 #define SIRFSOC_CLKC_DEINT_CLKDIV_CFG        0x0150
 124 #define SIRFSOC_CLKC_DEINT_CLKDIV_ENA        0x0154
 125 #define SIRFSOC_CLKC_DEINT_CLK_SEL           0x0158
 126 #define SIRFSOC_CLKC_DEINT_CLK_SEL_STAT      0x015c
 127
 128 #define SIRFSOC_CLKC_NAND_CLKDIV_CFG         0x0160
 129 #define SIRFSOC_CLKC_NAND_CLKDIV_ENA         0x0164
 130 #define SIRFSOC_CLKC_NAND_CLK_SEL            0x0168
 131 #define SIRFSOC_CLKC_NAND_CLK_SEL_STAT       0x016c
 132
 133 #define SIRFSOC_CLKC_DISP0_CLKDIV_CFG        0x0170
 134 #define SIRFSOC_CLKC_DISP0_CLKDIV_ENA        0x0174
 135 #define SIRFSOC_CLKC_DISP0_CLK_SEL           0x0178
 136 #define SIRFSOC_CLKC_DISP0_CLK_SEL_STAT      0x017c
 137
 138 #define SIRFSOC_CLKC_DISP1_CLKDIV_CFG        0x0180
 139 #define SIRFSOC_CLKC_DISP1_CLKDIV_ENA        0x0184
 140 #define SIRFSOC_CLKC_DISP1_CLK_SEL           0x0188
 141 #define SIRFSOC_CLKC_DISP1_CLK_SEL_STAT      0x018c
 142
 143 #define SIRFSOC_CLKC_GPU_CLKDIV_CFG          0x0190
 144 #define SIRFSOC_CLKC_GPU_CLKDIV_ENA          0x0194
 145 #define SIRFSOC_CLKC_GPU_CLK_SEL             0x0198
 146 #define SIRFSOC_CLKC_GPU_CLK_SEL_STAT        0x019c
 147
 148 #define SIRFSOC_CLKC_GNSS_CLKDIV_CFG         0x01a0
 149 #define SIRFSOC_CLKC_GNSS_CLKDIV_ENA         0x01a4
 150 #define SIRFSOC_CLKC_GNSS_CLK_SEL            0x01a8
 151 #define SIRFSOC_CLKC_GNSS_CLK_SEL_STAT       0x01ac
 152
 153 #define SIRFSOC_CLKC_SHARED_DIVIDER_CFG0     0x01b0
 154 #define SIRFSOC_CLKC_SHARED_DIVIDER_CFG1     0x01b4
 155 #define SIRFSOC_CLKC_SHARED_DIVIDER_ENA      0x01b8
 156
 157 #define SIRFSOC_CLKC_SYS_CLK_SEL             0x01bc
 158 #define SIRFSOC_CLKC_SYS_CLK_SEL_STAT        0x01c0
 159 #define SIRFSOC_CLKC_IO_CLK_SEL              0x01c4
 160 #define SIRFSOC_CLKC_IO_CLK_SEL_STAT         0x01c8
 161 #define SIRFSOC_CLKC_G2D_CLK_SEL             0x01cc
 162 #define SIRFSOC_CLKC_G2D_CLK_SEL_STAT        0x01d0
 163 #define SIRFSOC_CLKC_JPENC_CLK_SEL           0x01d4
 164 #define SIRFSOC_CLKC_JPENC_CLK_SEL_STAT      0x01d8
 165 #define SIRFSOC_CLKC_VDEC_CLK_SEL            0x01dc
 166 #define SIRFSOC_CLKC_VDEC_CLK_SEL_STAT       0x01e0
 167 #define SIRFSOC_CLKC_GMAC_CLK_SEL            0x01e4
 168 #define SIRFSOC_CLKC_GMAC_CLK_SEL_STAT       0x01e8
 169 #define SIRFSOC_CLKC_USB_CLK_SEL             0x01ec
 170 #define SIRFSOC_CLKC_USB_CLK_SEL_STAT        0x01f0
 171 #define SIRFSOC_CLKC_KAS_CLK_SEL             0x01f4
 172 #define SIRFSOC_CLKC_KAS_CLK_SEL_STAT        0x01f8
 173 #define SIRFSOC_CLKC_SEC_CLK_SEL             0x01fc
 174 #define SIRFSOC_CLKC_SEC_CLK_SEL_STAT        0x0200
 175 #define SIRFSOC_CLKC_SDR_CLK_SEL             0x0204
 176 #define SIRFSOC_CLKC_SDR_CLK_SEL_STAT        0x0208
 177 #define SIRFSOC_CLKC_VIP_CLK_SEL             0x020c
 178 #define SIRFSOC_CLKC_VIP_CLK_SEL_STAT        0x0210
 179 #define SIRFSOC_CLKC_NOCD_CLK_SEL            0x0214
 180 #define SIRFSOC_CLKC_NOCD_CLK_SEL_STAT       0x0218
 181 #define SIRFSOC_CLKC_NOCR_CLK_SEL            0x021c
 182 #define SIRFSOC_CLKC_NOCR_CLK_SEL_STAT       0x0220
 183 #define SIRFSOC_CLKC_TPIU_CLK_SEL            0x0224
 184 #define SIRFSOC_CLKC_TPIU_CLK_SEL_STAT       0x0228
 185
 186 #define SIRFSOC_CLKC_ROOT_CLK_EN0_SET        0x022c
 187 #define SIRFSOC_CLKC_ROOT_CLK_EN0_CLR        0x0230
 188 #define SIRFSOC_CLKC_ROOT_CLK_EN0_STAT       0x0234
 189 #define SIRFSOC_CLKC_ROOT_CLK_EN1_SET        0x0238
 190 #define SIRFSOC_CLKC_ROOT_CLK_EN1_CLR        0x023c
 191 #define SIRFSOC_CLKC_ROOT_CLK_EN1_STAT       0x0240
 192
 193 #define SIRFSOC_CLKC_LEAF_CLK_EN0_SET        0x0244
 194 #define SIRFSOC_CLKC_LEAF_CLK_EN0_CLR        0x0248
 195 #define SIRFSOC_CLKC_LEAF_CLK_EN0_STAT       0x024c
 196
 197 #define SIRFSOC_CLKC_RSTC_A7_SW_RST          0x0308
 198
 199 #define SIRFSOC_CLKC_LEAF_CLK_EN1_SET        0x04a0
 200 #define SIRFSOC_CLKC_LEAF_CLK_EN2_SET        0x04b8
 201 #define SIRFSOC_CLKC_LEAF_CLK_EN3_SET        0x04d0
 202 #define SIRFSOC_CLKC_LEAF_CLK_EN4_SET        0x04e8
 203 #define SIRFSOC_CLKC_LEAF_CLK_EN5_SET        0x0500
 204 #define SIRFSOC_CLKC_LEAF_CLK_EN6_SET        0x0518
 205 #define SIRFSOC_CLKC_LEAF_CLK_EN7_SET        0x0530
 206 #define SIRFSOC_CLKC_LEAF_CLK_EN8_SET        0x0548
 207
 208
 209 static void __iomem *sirfsoc_clk_vbase;
 210 static struct clk_onecell_data clk_data;
 211
 212 static const struct clk_div_table pll_div_table[] = {
 213         { .val = 0, .div = 1 },
 214         { .val = 1, .div = 2 },
 215         { .val = 2, .div = 4 },
 216         { .val = 3, .div = 8 },
 217         { .val = 4, .div = 16 },
 218         { .val = 5, .div = 32 },
 219 };
 220
 221 struct clk_pll {
 222         struct clk_hw hw;
 223         u16 regofs;  /* register offset */
 224 };
 225 #define to_pllclk(_hw) container_of(_hw, struct clk_pll, hw)
 226
 227 struct clk_dto {
 228         struct clk_hw hw;
 229         u16 inc_offset;  /* dto increment offset */
 230         u16 src_offset;  /* dto src offset */
 231 };
 232 #define to_dtoclk(_hw) container_of(_hw, struct clk_dto, hw)
 233
 234 struct clk_unit {
 235         struct clk_hw hw;
 236         u16 regofs;
 237         u16 bit;
 238         spinlock_t *lock;
 239 };
 240 #define to_unitclk(_hw) container_of(_hw, struct clk_unit, hw)
 241
 242 struct atlas7_div_init_data {
 243         const char *div_name;
 244         const char *parent_name;
 245         const char *gate_name;
 246         unsigned long flags;
 247         u8 divider_flags;
 248         u8 gate_flags;
 249         u32 div_offset;
 250         u8 shift;
 251         u8 width;
 252         u32 gate_offset;
 253         u8 gate_bit;
 254         spinlock_t *lock;
 255 };
 256
 257 struct atlas7_mux_init_data {
 258         const char *mux_name;
 259         const char * const *parent_names;
 260         u8 parent_num;
 261         unsigned long flags;
 262         u8 mux_flags;
 263         u32 mux_offset;
 264         u8 shift;
 265         u8 width;
 266 };
 267
 268 struct atlas7_unit_init_data {
 269         u32 index;
 270         const char *unit_name;
 271         const char *parent_name;
 272         unsigned long flags;
 273         u32 regofs;
 274         u8 bit;
 275         spinlock_t *lock;
 276 };
 277
 278 struct atlas7_reset_desc {
 279         const char *name;
 280         u32 clk_ofs;
 281         u8  clk_bit;
 282         u32 rst_ofs;
 283         u8  rst_bit;
 284         spinlock_t *lock;
 285 };
 286
 287 static DEFINE_SPINLOCK(cpupll_ctrl1_lock);
 288 static DEFINE_SPINLOCK(mempll_ctrl1_lock);
 289 static DEFINE_SPINLOCK(sys0pll_ctrl1_lock);
 290 static DEFINE_SPINLOCK(sys1pll_ctrl1_lock);
 291 static DEFINE_SPINLOCK(sys2pll_ctrl1_lock);
 292 static DEFINE_SPINLOCK(sys3pll_ctrl1_lock);
 293 static DEFINE_SPINLOCK(usbphy_div_lock);
 294 static DEFINE_SPINLOCK(btss_div_lock);
 295 static DEFINE_SPINLOCK(rgmii_div_lock);
 296 static DEFINE_SPINLOCK(cpu_div_lock);
 297 static DEFINE_SPINLOCK(sdphy01_div_lock);
 298 static DEFINE_SPINLOCK(sdphy23_div_lock);
 299 static DEFINE_SPINLOCK(sdphy45_div_lock);
 300 static DEFINE_SPINLOCK(sdphy67_div_lock);
 301 static DEFINE_SPINLOCK(can_div_lock);
 302 static DEFINE_SPINLOCK(deint_div_lock);
 303 static DEFINE_SPINLOCK(nand_div_lock);
 304 static DEFINE_SPINLOCK(disp0_div_lock);
 305 static DEFINE_SPINLOCK(disp1_div_lock);
 306 static DEFINE_SPINLOCK(gpu_div_lock);
 307 static DEFINE_SPINLOCK(gnss_div_lock);
 308 /* gate register shared */
 309 static DEFINE_SPINLOCK(share_div_lock);
 310 static DEFINE_SPINLOCK(root0_gate_lock);
 311 static DEFINE_SPINLOCK(root1_gate_lock);
 312 static DEFINE_SPINLOCK(leaf0_gate_lock);
 313 static DEFINE_SPINLOCK(leaf1_gate_lock);
 314 static DEFINE_SPINLOCK(leaf2_gate_lock);
 315 static DEFINE_SPINLOCK(leaf3_gate_lock);
 316 static DEFINE_SPINLOCK(leaf4_gate_lock);
 317 static DEFINE_SPINLOCK(leaf5_gate_lock);
 318 static DEFINE_SPINLOCK(leaf6_gate_lock);
 319 static DEFINE_SPINLOCK(leaf7_gate_lock);
 320 static DEFINE_SPINLOCK(leaf8_gate_lock);
 321
 322 static inline unsigned long clkc_readl(unsigned reg)
 323 {
 324         return readl(sirfsoc_clk_vbase + reg);
 325 }
 326
 327 static inline void clkc_writel(u32 val, unsigned reg)
 328 {
 329         writel(val, sirfsoc_clk_vbase + reg);
 330 }
 331
 332 /*
 333 *  ABPLL
 334 *  integer mode: Fvco = Fin * 2 * NF / NR
 335 *  Spread Spectrum mode: Fvco = Fin * SSN / NR
 336 *  SSN = 2^24 / (256 * ((ssdiv >> ssdepth) << ssdepth) + (ssmod << ssdepth))
 337 */
 338 static unsigned long pll_clk_recalc_rate(struct clk_hw *hw,
 339         unsigned long parent_rate)
 340 {
 341         unsigned long fin = parent_rate;
 342         struct clk_pll *clk = to_pllclk(hw);
 343         u64 rate;
 344         u32 regctrl0 = clkc_readl(clk->regofs + SIRFSOC_CLKC_MEMPLL_AB_CTRL0 -
 345                         SIRFSOC_CLKC_MEMPLL_AB_FREQ);
 346         u32 regfreq = clkc_readl(clk->regofs);
 347         u32 regssc = clkc_readl(clk->regofs + SIRFSOC_CLKC_MEMPLL_AB_SSC -
 348                         SIRFSOC_CLKC_MEMPLL_AB_FREQ);
 349         u32 nr = (regfreq  >> 16 & (BIT(3) - 1)) + 1;
 350         u32 nf = (regfreq & (BIT(9) - 1)) + 1;
 351         u32 ssdiv = regssc >> 8 & (BIT(12) - 1);
 352         u32 ssdepth = regssc >> 20 & (BIT(2) - 1);
 353         u32 ssmod = regssc & (BIT(8) - 1);
 354
 355         if (regctrl0 & SIRFSOC_ABPLL_CTRL0_BYPASS)
 356                 return fin;
 357
 358         if (regctrl0 & SIRFSOC_ABPLL_CTRL0_SSEN) {
 359                 rate = fin;
 360                 rate *= 1 << 24;
 361                 do_div(rate, (256 * ((ssdiv >> ssdepth) << ssdepth)
 362                         + (ssmod << ssdepth)));
 363         } else {
 364                 rate = 2 * fin;
 365                 rate *= nf;
 366                 do_div(rate, nr);
 367         }
 368         return rate;
 369 }
 370
 371 static const struct clk_ops ab_pll_ops = {
 372         .recalc_rate = pll_clk_recalc_rate,
 373 };
 374
 375 static const char * const pll_clk_parents[] = {
 376         "xin",
 377 };
 378
 379 static struct clk_init_data clk_cpupll_init = {
 380         .name = "cpupll_vco",
 381         .ops = &ab_pll_ops,
 382         .parent_names = pll_clk_parents,
 383         .num_parents = ARRAY_SIZE(pll_clk_parents),
 384 };
 385
 386 static struct clk_pll clk_cpupll = {
 387         .regofs = SIRFSOC_CLKC_CPUPLL_AB_FREQ,
 388         .hw = {
 389                 .init = &clk_cpupll_init,
 390         },
 391 };
 392
 393 static struct clk_init_data clk_mempll_init = {
 394         .name = "mempll_vco",
 395         .ops = &ab_pll_ops,
 396         .parent_names = pll_clk_parents,
 397         .num_parents = ARRAY_SIZE(pll_clk_parents),
 398 };
 399
 400 static struct clk_pll clk_mempll = {
 401         .regofs = SIRFSOC_CLKC_MEMPLL_AB_FREQ,
 402         .hw = {
 403                 .init = &clk_mempll_init,
 404         },
 405 };
 406
 407 static struct clk_init_data clk_sys0pll_init = {
 408         .name = "sys0pll_vco",
 409         .ops = &ab_pll_ops,
 410         .parent_names = pll_clk_parents,
 411         .num_parents = ARRAY_SIZE(pll_clk_parents),
 412 };
 413
 414 static struct clk_pll clk_sys0pll = {
 415         .regofs = SIRFSOC_CLKC_SYS0PLL_AB_FREQ,
 416         .hw = {
 417                 .init = &clk_sys0pll_init,
 418         },
 419 };
 420
 421 static struct clk_init_data clk_sys1pll_init = {
 422         .name = "sys1pll_vco",
 423         .ops = &ab_pll_ops,
 424         .parent_names = pll_clk_parents,
 425         .num_parents = ARRAY_SIZE(pll_clk_parents),
 426 };
 427
 428 static struct clk_pll clk_sys1pll = {
 429         .regofs = SIRFSOC_CLKC_SYS1PLL_AB_FREQ,
 430         .hw = {
 431                 .init = &clk_sys1pll_init,
 432         },
 433 };
 434
 435 static struct clk_init_data clk_sys2pll_init = {
 436         .name = "sys2pll_vco",
 437         .ops = &ab_pll_ops,
 438         .parent_names = pll_clk_parents,
 439         .num_parents = ARRAY_SIZE(pll_clk_parents),
 440 };
 441
 442 static struct clk_pll clk_sys2pll = {
 443         .regofs = SIRFSOC_CLKC_SYS2PLL_AB_FREQ,
 444         .hw = {
 445                 .init = &clk_sys2pll_init,
 446         },
 447 };
 448
 449 static struct clk_init_data clk_sys3pll_init = {
 450         .name = "sys3pll_vco",
 451         .ops = &ab_pll_ops,
 452         .parent_names = pll_clk_parents,
 453         .num_parents = ARRAY_SIZE(pll_clk_parents),
 454 };
 455
 456 static struct clk_pll clk_sys3pll = {
 457         .regofs = SIRFSOC_CLKC_SYS3PLL_AB_FREQ,
 458         .hw = {
 459                 .init = &clk_sys3pll_init,
 460         },
 461 };
 462
 463 /*
 464  *  DTO in clkc, default enable double resolution mode
 465  *  double resolution mode:fout = fin * finc / 2^29
 466  *  normal mode:fout = fin * finc / 2^28
 467  */
 468 #define DTO_RESL_DOUBLE (1ULL << 29)
 469 #define DTO_RESL_NORMAL (1ULL << 28)
 470
 471 static int dto_clk_is_enabled(struct clk_hw *hw)
 472 {
 473         struct clk_dto *clk = to_dtoclk(hw);
 474         int reg;
 475
 476         reg = clk->src_offset + SIRFSOC_CLKC_AUDIO_DTO_ENA - SIRFSOC_CLKC_AUDIO_DTO_SRC;
 477
 478         return !!(clkc_readl(reg) & BIT(0));
 479 }
 480
 481 static int dto_clk_enable(struct clk_hw *hw)
 482 {
 483         u32 val, reg;
 484         struct clk_dto *clk = to_dtoclk(hw);
 485
 486         reg = clk->src_offset + SIRFSOC_CLKC_AUDIO_DTO_ENA - SIRFSOC_CLKC_AUDIO_DTO_SRC;
 487
 488         val = clkc_readl(reg) | BIT(0);
 489         clkc_writel(val, reg);
 490         return 0;
 491 }
 492
 493 static void dto_clk_disable(struct clk_hw *hw)
 494 {
 495         u32 val, reg;
 496         struct clk_dto *clk = to_dtoclk(hw);
 497
 498         reg = clk->src_offset + SIRFSOC_CLKC_AUDIO_DTO_ENA - SIRFSOC_CLKC_AUDIO_DTO_SRC;
 499
 500         val = clkc_readl(reg) & ~BIT(0);
 501         clkc_writel(val, reg);
 502 }
 503
 504 static unsigned long dto_clk_recalc_rate(struct clk_hw *hw,
 505         unsigned long parent_rate)
 506 {
 507         u64 rate = parent_rate;
 508         struct clk_dto *clk = to_dtoclk(hw);
 509         u32 finc = clkc_readl(clk->inc_offset);
 510         u32 droff = clkc_readl(clk->src_offset + SIRFSOC_CLKC_AUDIO_DTO_DROFF - SIRFSOC_CLKC_AUDIO_DTO_SRC);
 511
 512         rate *= finc;
 513         if (droff & BIT(0))
 514                 /* Double resolution off */
 515                 do_div(rate, DTO_RESL_NORMAL);
 516         else
 517                 do_div(rate, DTO_RESL_DOUBLE);
 518
 519         return rate;
 520 }
 521
 522 static long dto_clk_round_rate(struct clk_hw *hw, unsigned long rate,
 523         unsigned long *parent_rate)
 524 {
 525         u64 dividend = rate * DTO_RESL_DOUBLE;
 526
 527         do_div(dividend, *parent_rate);
 528         dividend *= *parent_rate;
 529         do_div(dividend, DTO_RESL_DOUBLE);
 530
 531         return dividend;
 532 }
 533
 534 static int dto_clk_set_rate(struct clk_hw *hw, unsigned long rate,
 535         unsigned long parent_rate)
 536 {
 537         u64 dividend = rate * DTO_RESL_DOUBLE;
 538         struct clk_dto *clk = to_dtoclk(hw);
 539
 540         do_div(dividend, parent_rate);
 541         clkc_writel(0, clk->src_offset + SIRFSOC_CLKC_AUDIO_DTO_DROFF - SIRFSOC_CLKC_AUDIO_DTO_SRC);
 542         clkc_writel(dividend, clk->inc_offset);
 543
 544         return 0;
 545 }
 546
 547 static u8 dto_clk_get_parent(struct clk_hw *hw)
 548 {
 549         struct clk_dto *clk = to_dtoclk(hw);
 550
 551         return clkc_readl(clk->src_offset);
 552 }
 553
 554 /*
 555  *   dto need CLK_SET_PARENT_GATE
 556  */
 557 static int dto_clk_set_parent(struct clk_hw *hw, u8 index)
 558 {
 559         struct clk_dto *clk = to_dtoclk(hw);
 560
 561         clkc_writel(index, clk->src_offset);
 562         return 0;
 563 }
 564
 565 static const struct clk_ops dto_ops = {
 566         .is_enabled = dto_clk_is_enabled,
 567         .enable = dto_clk_enable,
 568         .disable = dto_clk_disable,
 569         .recalc_rate = dto_clk_recalc_rate,
 570         .round_rate = dto_clk_round_rate,
 571         .set_rate = dto_clk_set_rate,
 572         .get_parent = dto_clk_get_parent,
 573         .set_parent = dto_clk_set_parent,
 574 };
 575
 576 /* dto parent clock as syspllvco/clk1 */
 577 static const char * const audiodto_clk_parents[] = {
 578         "sys0pll_clk1",
 579         "sys1pll_clk1",
 580         "sys3pll_clk1",
 581 };
 582
 583 static struct clk_init_data clk_audiodto_init = {
 584         .name = "audio_dto",
 585         .ops = &dto_ops,
 586         .parent_names = audiodto_clk_parents,
 587         .num_parents = ARRAY_SIZE(audiodto_clk_parents),
 588 };
 589
 590 static struct clk_dto clk_audio_dto = {
 591         .inc_offset = SIRFSOC_CLKC_AUDIO_DTO_INC,
 592         .src_offset = SIRFSOC_CLKC_AUDIO_DTO_SRC,
 593         .hw = {
 594                 .init = &clk_audiodto_init,
 595         },
 596 };
 597
 598 static const char * const disp0dto_clk_parents[] = {
 599         "sys0pll_clk1",
 600         "sys1pll_clk1",
 601         "sys3pll_clk1",
 602 };
 603
 604 static struct clk_init_data clk_disp0dto_init = {
 605         .name = "disp0_dto",
 606         .ops = &dto_ops,
 607         .parent_names = disp0dto_clk_parents,
 608         .num_parents = ARRAY_SIZE(disp0dto_clk_parents),
 609 };
 610
 611 static struct clk_dto clk_disp0_dto = {
 612         .inc_offset = SIRFSOC_CLKC_DISP0_DTO_INC,
 613         .src_offset = SIRFSOC_CLKC_DISP0_DTO_SRC,
 614         .hw = {
 615                 .init = &clk_disp0dto_init,
 616         },
 617 };
 618
 619 static const char * const disp1dto_clk_parents[] = {
 620         "sys0pll_clk1",
 621         "sys1pll_clk1",
 622         "sys3pll_clk1",
 623 };
 624
 625 static struct clk_init_data clk_disp1dto_init = {
 626         .name = "disp1_dto",
 627         .ops = &dto_ops,
 628         .parent_names = disp1dto_clk_parents,
 629         .num_parents = ARRAY_SIZE(disp1dto_clk_parents),
 630 };
 631
 632 static struct clk_dto clk_disp1_dto = {
 633         .inc_offset = SIRFSOC_CLKC_DISP1_DTO_INC,
 634         .src_offset = SIRFSOC_CLKC_DISP1_DTO_SRC,
 635         .hw = {
 636                 .init = &clk_disp1dto_init,
 637         },
 638 };
 639
 640 static struct atlas7_div_init_data divider_list[] __initdata = {
 641         /* div_name, parent_name, gate_name, clk_flag, divider_flag, gate_flag, div_offset, shift, wdith, gate_offset, bit_enable, lock */
 642         { "sys0pll_qa1", "sys0pll_fixdiv", "sys0pll_a1", 0, 0, 0, SIRFSOC_CLKC_USBPHY_CLKDIV_CFG, 0, 6, SIRFSOC_CLKC_USBPHY_CLKDIV_ENA, 0, &usbphy_div_lock },
 643         { "sys1pll_qa1", "sys1pll_fixdiv", "sys1pll_a1", 0, 0, 0, SIRFSOC_CLKC_USBPHY_CLKDIV_CFG, 8, 6, SIRFSOC_CLKC_USBPHY_CLKDIV_ENA, 4, &usbphy_div_lock },
 644         { "sys2pll_qa1", "sys2pll_fixdiv", "sys2pll_a1", 0, 0, 0, SIRFSOC_CLKC_USBPHY_CLKDIV_CFG, 16, 6, SIRFSOC_CLKC_USBPHY_CLKDIV_ENA, 8, &usbphy_div_lock },
 645         { "sys3pll_qa1", "sys3pll_fixdiv", "sys3pll_a1", 0, 0, 0, SIRFSOC_CLKC_USBPHY_CLKDIV_CFG, 24, 6, SIRFSOC_CLKC_USBPHY_CLKDIV_ENA, 12, &usbphy_div_lock },
 646         { "sys0pll_qa2", "sys0pll_fixdiv", "sys0pll_a2", 0, 0, 0, SIRFSOC_CLKC_BTSS_CLKDIV_CFG, 0, 6, SIRFSOC_CLKC_BTSS_CLKDIV_ENA, 0, &btss_div_lock },
 647         { "sys1pll_qa2", "sys1pll_fixdiv", "sys1pll_a2", 0, 0, 0, SIRFSOC_CLKC_BTSS_CLKDIV_CFG, 8, 6, SIRFSOC_CLKC_BTSS_CLKDIV_ENA, 4, &btss_div_lock },
 648         { "sys2pll_qa2", "sys2pll_fixdiv", "sys2pll_a2", 0, 0, 0, SIRFSOC_CLKC_BTSS_CLKDIV_CFG, 16, 6, SIRFSOC_CLKC_BTSS_CLKDIV_ENA, 8, &btss_div_lock },
 649         { "sys3pll_qa2", "sys3pll_fixdiv", "sys3pll_a2", 0, 0, 0, SIRFSOC_CLKC_BTSS_CLKDIV_CFG, 24, 6, SIRFSOC_CLKC_BTSS_CLKDIV_ENA, 12, &btss_div_lock },
 650         { "sys0pll_qa3", "sys0pll_fixdiv", "sys0pll_a3", 0, 0, 0, SIRFSOC_CLKC_RGMII_CLKDIV_CFG, 0, 6, SIRFSOC_CLKC_RGMII_CLKDIV_ENA, 0, &rgmii_div_lock },
 651         { "sys1pll_qa3", "sys1pll_fixdiv", "sys1pll_a3", 0, 0, 0, SIRFSOC_CLKC_RGMII_CLKDIV_CFG, 8, 6, SIRFSOC_CLKC_RGMII_CLKDIV_ENA, 4, &rgmii_div_lock },
 652         { "sys2pll_qa3", "sys2pll_fixdiv", "sys2pll_a3", 0, 0, 0, SIRFSOC_CLKC_RGMII_CLKDIV_CFG, 16, 6, SIRFSOC_CLKC_RGMII_CLKDIV_ENA, 8, &rgmii_div_lock },
 653         { "sys3pll_qa3", "sys3pll_fixdiv", "sys3pll_a3", 0, 0, 0, SIRFSOC_CLKC_RGMII_CLKDIV_CFG, 24, 6, SIRFSOC_CLKC_RGMII_CLKDIV_ENA, 12, &rgmii_div_lock },
 654         { "sys0pll_qa4", "sys0pll_fixdiv", "sys0pll_a4", 0, 0, 0, SIRFSOC_CLKC_CPU_CLKDIV_CFG, 0, 6, SIRFSOC_CLKC_CPU_CLKDIV_ENA, 0, &cpu_div_lock },
 655         { "sys1pll_qa4", "sys1pll_fixdiv", "sys1pll_a4", 0, 0, CLK_IGNORE_UNUSED, SIRFSOC_CLKC_CPU_CLKDIV_CFG, 8, 6, SIRFSOC_CLKC_CPU_CLKDIV_ENA, 4, &cpu_div_lock },
 656         { "sys0pll_qa5", "sys0pll_fixdiv", "sys0pll_a5", 0, 0, 0, SIRFSOC_CLKC_SDPHY01_CLKDIV_CFG, 0, 6, SIRFSOC_CLKC_SDPHY01_CLKDIV_ENA, 0, &sdphy01_div_lock },
 657         { "sys1pll_qa5", "sys1pll_fixdiv", "sys1pll_a5", 0, 0, 0, SIRFSOC_CLKC_SDPHY01_CLKDIV_CFG, 8, 6, SIRFSOC_CLKC_SDPHY01_CLKDIV_ENA, 4, &sdphy01_div_lock },
 658         { "sys2pll_qa5", "sys2pll_fixdiv", "sys2pll_a5", 0, 0, 0, SIRFSOC_CLKC_SDPHY01_CLKDIV_CFG, 16, 6, SIRFSOC_CLKC_SDPHY01_CLKDIV_ENA, 8, &sdphy01_div_lock },
 659         { "sys3pll_qa5", "sys3pll_fixdiv", "sys3pll_a5", 0, 0, 0, SIRFSOC_CLKC_SDPHY01_CLKDIV_CFG, 24, 6, SIRFSOC_CLKC_SDPHY01_CLKDIV_ENA, 12, &sdphy01_div_lock },
 660         { "sys0pll_qa6", "sys0pll_fixdiv", "sys0pll_a6", 0, 0, 0, SIRFSOC_CLKC_SDPHY23_CLKDIV_CFG, 0, 6, SIRFSOC_CLKC_SDPHY23_CLKDIV_ENA, 0, &sdphy23_div_lock },
 661         { "sys1pll_qa6", "sys1pll_fixdiv", "sys1pll_a6", 0, 0, 0, SIRFSOC_CLKC_SDPHY23_CLKDIV_CFG, 8, 6, SIRFSOC_CLKC_SDPHY23_CLKDIV_ENA, 4, &sdphy23_div_lock },
 662         { "sys2pll_qa6", "sys2pll_fixdiv", "sys2pll_a6", 0, 0, 0, SIRFSOC_CLKC_SDPHY23_CLKDIV_CFG, 16, 6, SIRFSOC_CLKC_SDPHY23_CLKDIV_ENA, 8, &sdphy23_div_lock },
 663         { "sys3pll_qa6", "sys3pll_fixdiv", "sys3pll_a6", 0, 0, 0, SIRFSOC_CLKC_SDPHY23_CLKDIV_CFG, 24, 6, SIRFSOC_CLKC_SDPHY23_CLKDIV_ENA, 12, &sdphy23_div_lock },
 664         { "sys0pll_qa7", "sys0pll_fixdiv", "sys0pll_a7", 0, 0, 0, SIRFSOC_CLKC_SDPHY45_CLKDIV_CFG, 0, 6, SIRFSOC_CLKC_SDPHY45_CLKDIV_ENA, 0, &sdphy45_div_lock },
 665         { "sys1pll_qa7", "sys1pll_fixdiv", "sys1pll_a7", 0, 0, 0, SIRFSOC_CLKC_SDPHY45_CLKDIV_CFG, 8, 6, SIRFSOC_CLKC_SDPHY45_CLKDIV_ENA, 4, &sdphy45_div_lock },
 666         { "sys2pll_qa7", "sys2pll_fixdiv", "sys2pll_a7", 0, 0, 0, SIRFSOC_CLKC_SDPHY45_CLKDIV_CFG, 16, 6, SIRFSOC_CLKC_SDPHY45_CLKDIV_ENA, 8, &sdphy45_div_lock },
 667         { "sys3pll_qa7", "sys3pll_fixdiv", "sys3pll_a7", 0, 0, 0, SIRFSOC_CLKC_SDPHY45_CLKDIV_CFG, 24, 6, SIRFSOC_CLKC_SDPHY45_CLKDIV_ENA, 12, &sdphy45_div_lock },
 668         { "sys0pll_qa8", "sys0pll_fixdiv", "sys0pll_a8", 0, 0, 0, SIRFSOC_CLKC_SDPHY67_CLKDIV_CFG, 0, 6, SIRFSOC_CLKC_SDPHY67_CLKDIV_ENA, 0, &sdphy67_div_lock },
 669         { "sys1pll_qa8", "sys1pll_fixdiv", "sys1pll_a8", 0, 0, 0, SIRFSOC_CLKC_SDPHY67_CLKDIV_CFG, 8, 6, SIRFSOC_CLKC_SDPHY67_CLKDIV_ENA, 4, &sdphy67_div_lock },
 670         { "sys2pll_qa8", "sys2pll_fixdiv", "sys2pll_a8", 0, 0, 0, SIRFSOC_CLKC_SDPHY67_CLKDIV_CFG, 16, 6, SIRFSOC_CLKC_SDPHY67_CLKDIV_ENA, 8, &sdphy67_div_lock },
 671         { "sys3pll_qa8", "sys3pll_fixdiv", "sys3pll_a8", 0, 0, 0, SIRFSOC_CLKC_SDPHY67_CLKDIV_CFG, 24, 6, SIRFSOC_CLKC_SDPHY67_CLKDIV_ENA, 12, &sdphy67_div_lock },
 672         { "sys0pll_qa9", "sys0pll_fixdiv", "sys0pll_a9", 0, 0, 0, SIRFSOC_CLKC_CAN_CLKDIV_CFG, 0, 6, SIRFSOC_CLKC_CAN_CLKDIV_ENA, 0, &can_div_lock },
 673         { "sys1pll_qa9", "sys1pll_fixdiv", "sys1pll_a9", 0, 0, 0, SIRFSOC_CLKC_CAN_CLKDIV_CFG, 8, 6, SIRFSOC_CLKC_CAN_CLKDIV_ENA, 4, &can_div_lock },
 674         { "sys2pll_qa9", "sys2pll_fixdiv", "sys2pll_a9", 0, 0, 0, SIRFSOC_CLKC_CAN_CLKDIV_CFG, 16, 6, SIRFSOC_CLKC_CAN_CLKDIV_ENA, 8, &can_div_lock },
 675         { "sys3pll_qa9", "sys3pll_fixdiv", "sys3pll_a9", 0, 0, 0, SIRFSOC_CLKC_CAN_CLKDIV_CFG, 24, 6, SIRFSOC_CLKC_CAN_CLKDIV_ENA, 12, &can_div_lock },
 676         { "sys0pll_qa10", "sys0pll_fixdiv", "sys0pll_a10", 0, 0, 0, SIRFSOC_CLKC_DEINT_CLKDIV_CFG, 0, 6, SIRFSOC_CLKC_DEINT_CLKDIV_ENA, 0, &deint_div_lock },
 677         { "sys1pll_qa10", "sys1pll_fixdiv", "sys1pll_a10", 0, 0, 0, SIRFSOC_CLKC_DEINT_CLKDIV_CFG, 8, 6, SIRFSOC_CLKC_DEINT_CLKDIV_ENA, 4, &deint_div_lock },
 678         { "sys2pll_qa10", "sys2pll_fixdiv", "sys2pll_a10", 0, 0, 0, SIRFSOC_CLKC_DEINT_CLKDIV_CFG, 16, 6, SIRFSOC_CLKC_DEINT_CLKDIV_ENA, 8, &deint_div_lock },
 679         { "sys3pll_qa10", "sys3pll_fixdiv", "sys3pll_a10", 0, 0, 0, SIRFSOC_CLKC_DEINT_CLKDIV_CFG, 24, 6, SIRFSOC_CLKC_DEINT_CLKDIV_ENA, 12, &deint_div_lock },
 680         { "sys0pll_qa11", "sys0pll_fixdiv", "sys0pll_a11", 0, 0, 0, SIRFSOC_CLKC_NAND_CLKDIV_CFG, 0, 6, SIRFSOC_CLKC_NAND_CLKDIV_ENA, 0, &nand_div_lock },
 681         { "sys1pll_qa11", "sys1pll_fixdiv", "sys1pll_a11", 0, 0, 0, SIRFSOC_CLKC_NAND_CLKDIV_CFG, 8, 6, SIRFSOC_CLKC_NAND_CLKDIV_ENA, 4, &nand_div_lock },
 682         { "sys2pll_qa11", "sys2pll_fixdiv", "sys2pll_a11", 0, 0, 0, SIRFSOC_CLKC_NAND_CLKDIV_CFG, 16, 6, SIRFSOC_CLKC_NAND_CLKDIV_ENA, 8, &nand_div_lock },
 683         { "sys3pll_qa11", "sys3pll_fixdiv", "sys3pll_a11", 0, 0, 0, SIRFSOC_CLKC_NAND_CLKDIV_CFG, 24, 6, SIRFSOC_CLKC_NAND_CLKDIV_ENA, 12, &nand_div_lock },
 684         { "sys0pll_qa12", "sys0pll_fixdiv", "sys0pll_a12", 0, 0, 0, SIRFSOC_CLKC_DISP0_CLKDIV_CFG, 0, 6, SIRFSOC_CLKC_DISP0_CLKDIV_ENA, 0, &disp0_div_lock },
 685         { "sys1pll_qa12", "sys1pll_fixdiv", "sys1pll_a12", 0, 0, 0, SIRFSOC_CLKC_DISP0_CLKDIV_CFG, 8, 6, SIRFSOC_CLKC_DISP0_CLKDIV_ENA, 4, &disp0_div_lock },
 686         { "sys2pll_qa12", "sys2pll_fixdiv", "sys2pll_a12", 0, 0, 0, SIRFSOC_CLKC_DISP0_CLKDIV_CFG, 16, 6, SIRFSOC_CLKC_DISP0_CLKDIV_ENA, 8, &disp0_div_lock },
 687         { "sys3pll_qa12", "sys3pll_fixdiv", "sys3pll_a12", 0, 0, 0, SIRFSOC_CLKC_DISP0_CLKDIV_CFG, 24, 6, SIRFSOC_CLKC_DISP0_CLKDIV_ENA, 12, &disp0_div_lock },
 688         { "sys0pll_qa13", "sys0pll_fixdiv", "sys0pll_a13", 0, 0, 0, SIRFSOC_CLKC_DISP1_CLKDIV_CFG, 0, 6, SIRFSOC_CLKC_DISP1_CLKDIV_ENA, 0, &disp1_div_lock },
 689         { "sys1pll_qa13", "sys1pll_fixdiv", "sys1pll_a13", 0, 0, 0, SIRFSOC_CLKC_DISP1_CLKDIV_CFG, 8, 6, SIRFSOC_CLKC_DISP1_CLKDIV_ENA, 4, &disp1_div_lock },
 690         { "sys2pll_qa13", "sys2pll_fixdiv", "sys2pll_a13", 0, 0, 0, SIRFSOC_CLKC_DISP1_CLKDIV_CFG, 16, 6, SIRFSOC_CLKC_DISP1_CLKDIV_ENA, 8, &disp1_div_lock },
 691         { "sys3pll_qa13", "sys3pll_fixdiv", "sys3pll_a13", 0, 0, 0, SIRFSOC_CLKC_DISP1_CLKDIV_CFG, 24, 6, SIRFSOC_CLKC_DISP1_CLKDIV_ENA, 12, &disp1_div_lock },
 692         { "sys0pll_qa14", "sys0pll_fixdiv", "sys0pll_a14", 0, 0, 0, SIRFSOC_CLKC_GPU_CLKDIV_CFG, 0, 6, SIRFSOC_CLKC_GPU_CLKDIV_ENA, 0, &gpu_div_lock },
 693         { "sys1pll_qa14", "sys1pll_fixdiv", "sys1pll_a14", 0, 0, 0, SIRFSOC_CLKC_GPU_CLKDIV_CFG, 8, 6, SIRFSOC_CLKC_GPU_CLKDIV_ENA, 4, &gpu_div_lock },
 694         { "sys2pll_qa14", "sys2pll_fixdiv", "sys2pll_a14", 0, 0, 0, SIRFSOC_CLKC_GPU_CLKDIV_CFG, 16, 6, SIRFSOC_CLKC_GPU_CLKDIV_ENA, 8, &gpu_div_lock },
 695         { "sys3pll_qa14", "sys3pll_fixdiv", "sys3pll_a14", 0, 0, 0, SIRFSOC_CLKC_GPU_CLKDIV_CFG, 24, 6, SIRFSOC_CLKC_GPU_CLKDIV_ENA, 12, &gpu_div_lock },
 696         { "sys0pll_qa15", "sys0pll_fixdiv", "sys0pll_a15", 0, 0, 0, SIRFSOC_CLKC_GNSS_CLKDIV_CFG, 0, 6, SIRFSOC_CLKC_GNSS_CLKDIV_ENA, 0, &gnss_div_lock },
 697         { "sys1pll_qa15", "sys1pll_fixdiv", "sys1pll_a15", 0, 0, 0, SIRFSOC_CLKC_GNSS_CLKDIV_CFG, 8, 6, SIRFSOC_CLKC_GNSS_CLKDIV_ENA, 4, &gnss_div_lock },
 698         { "sys2pll_qa15", "sys2pll_fixdiv", "sys2pll_a15", 0, 0, 0, SIRFSOC_CLKC_GNSS_CLKDIV_CFG, 16, 6, SIRFSOC_CLKC_GNSS_CLKDIV_ENA, 8, &gnss_div_lock },
 699         { "sys3pll_qa15", "sys3pll_fixdiv", "sys3pll_a15", 0, 0, 0, SIRFSOC_CLKC_GNSS_CLKDIV_CFG, 24, 6, SIRFSOC_CLKC_GNSS_CLKDIV_ENA, 12, &gnss_div_lock },
 700         { "sys1pll_qa18", "sys1pll_fixdiv", "sys1pll_a18", 0, 0, 0, SIRFSOC_CLKC_SHARED_DIVIDER_CFG0, 24, 6, SIRFSOC_CLKC_SHARED_DIVIDER_ENA, 12, &share_div_lock },
 701         { "sys1pll_qa19", "sys1pll_fixdiv", "sys1pll_a19", 0, 0, CLK_IGNORE_UNUSED, SIRFSOC_CLKC_SHARED_DIVIDER_CFG0, 16, 6, SIRFSOC_CLKC_SHARED_DIVIDER_ENA, 8, &share_div_lock },
 702         { "sys1pll_qa20", "sys1pll_fixdiv", "sys1pll_a20", 0, 0, 0, SIRFSOC_CLKC_SHARED_DIVIDER_CFG0, 8, 6, SIRFSOC_CLKC_SHARED_DIVIDER_ENA, 4, &share_div_lock },
 703         { "sys2pll_qa20", "sys2pll_fixdiv", "sys2pll_a20", 0, 0, 0, SIRFSOC_CLKC_SHARED_DIVIDER_CFG0, 0, 6, SIRFSOC_CLKC_SHARED_DIVIDER_ENA, 0, &share_div_lock },
 704         { "sys1pll_qa17", "sys1pll_fixdiv", "sys1pll_a17", 0, 0, CLK_IGNORE_UNUSED, SIRFSOC_CLKC_SHARED_DIVIDER_CFG1, 8, 6, SIRFSOC_CLKC_SHARED_DIVIDER_ENA, 20, &share_div_lock },
 705         { "sys0pll_qa20", "sys0pll_fixdiv", "sys0pll_a20", 0, 0, 0, SIRFSOC_CLKC_SHARED_DIVIDER_CFG1, 0, 6, SIRFSOC_CLKC_SHARED_DIVIDER_ENA, 16, &share_div_lock },
 706 };
 707
 708 static const char * const i2s_clk_parents[] = {
 709         "xin",
 710         "xinw",
 711         "audio_dto",
 712         /* "pwm_i2s01" */
 713 };
 714
 715 static const char * const usbphy_clk_parents[] = {
 716         "xin",
 717         "xinw",
 718         "sys0pll_a1",
 719         "sys1pll_a1",
 720         "sys2pll_a1",
 721         "sys3pll_a1",
 722 };
 723
 724 static const char * const btss_clk_parents[] = {
 725         "xin",
 726         "xinw",
 727         "sys0pll_a2",
 728         "sys1pll_a2",
 729         "sys2pll_a2",
 730         "sys3pll_a2",
 731 };
 732
 733 static const char * const rgmii_clk_parents[] = {
 734         "xin",
 735         "xinw",
 736         "sys0pll_a3",
 737         "sys1pll_a3",
 738         "sys2pll_a3",
 739         "sys3pll_a3",
 740 };
 741
 742 static const char * const cpu_clk_parents[] = {
 743         "xin",
 744         "xinw",
 745         "sys0pll_a4",
 746         "sys1pll_a4",
 747         "cpupll_clk1",
 748 };
 749
 750 static const char * const sdphy01_clk_parents[] = {
 751         "xin",
 752         "xinw",
 753         "sys0pll_a5",
 754         "sys1pll_a5",
 755         "sys2pll_a5",
 756         "sys3pll_a5",
 757 };
 758
 759 static const char * const sdphy23_clk_parents[] = {
 760         "xin",
 761         "xinw",
 762         "sys0pll_a6",
 763         "sys1pll_a6",
 764         "sys2pll_a6",
 765         "sys3pll_a6",
 766 };
 767
 768 static const char * const sdphy45_clk_parents[] = {
 769         "xin",
 770         "xinw",
 771         "sys0pll_a7",
 772         "sys1pll_a7",
 773         "sys2pll_a7",
 774         "sys3pll_a7",
 775 };
 776
 777 static const char * const sdphy67_clk_parents[] = {
 778         "xin",
 779         "xinw",
 780         "sys0pll_a8",
 781         "sys1pll_a8",
 782         "sys2pll_a8",
 783         "sys3pll_a8",
 784 };
 785
 786 static const char * const can_clk_parents[] = {
 787         "xin",
 788         "xinw",
 789         "sys0pll_a9",
 790         "sys1pll_a9",
 791         "sys2pll_a9",
 792         "sys3pll_a9",
 793 };
 794
 795 static const char * const deint_clk_parents[] = {
 796         "xin",
 797         "xinw",
 798         "sys0pll_a10",
 799         "sys1pll_a10",
 800         "sys2pll_a10",
 801         "sys3pll_a10",
 802 };
 803
 804 static const char * const nand_clk_parents[] = {
 805         "xin",
 806         "xinw",
 807         "sys0pll_a11",
 808         "sys1pll_a11",
 809         "sys2pll_a11",
 810         "sys3pll_a11",
 811 };
 812
 813 static const char * const disp0_clk_parents[] = {
 814         "xin",
 815         "xinw",
 816         "sys0pll_a12",
 817         "sys1pll_a12",
 818         "sys2pll_a12",
 819         "sys3pll_a12",
 820         "disp0_dto",
 821 };
 822
 823 static const char * const disp1_clk_parents[] = {
 824         "xin",
 825         "xinw",
 826         "sys0pll_a13",
 827         "sys1pll_a13",
 828         "sys2pll_a13",
 829         "sys3pll_a13",
 830         "disp1_dto",
 831 };
 832
 833 static const char * const gpu_clk_parents[] = {
 834         "xin",
 835         "xinw",
 836         "sys0pll_a14",
 837         "sys1pll_a14",
 838         "sys2pll_a14",
 839         "sys3pll_a14",
 840 };
 841
 842 static const char * const gnss_clk_parents[] = {
 843         "xin",
 844         "xinw",
 845         "sys0pll_a15",
 846         "sys1pll_a15",
 847         "sys2pll_a15",
 848         "sys3pll_a15",
 849 };
 850
 851 static const char * const sys_clk_parents[] = {
 852         "xin",
 853         "xinw",
 854         "sys2pll_a20",
 855         "sys1pll_a20",
 856         "sys1pll_a19",
 857         "sys1pll_a18",
 858         "sys0pll_a20",
 859         "sys1pll_a17",
 860 };
 861
 862 static const char * const io_clk_parents[] = {
 863         "xin",
 864         "xinw",
 865         "sys2pll_a20",
 866         "sys1pll_a20",
 867         "sys1pll_a19",
 868         "sys1pll_a18",
 869         "sys0pll_a20",
 870         "sys1pll_a17",
 871 };
 872
 873 static const char * const g2d_clk_parents[] = {
 874         "xin",
 875         "xinw",
 876         "sys2pll_a20",
 877         "sys1pll_a20",
 878         "sys1pll_a19",
 879         "sys1pll_a18",
 880         "sys0pll_a20",
 881         "sys1pll_a17",
 882 };
 883
 884 static const char * const jpenc_clk_parents[] = {
 885         "xin",
 886         "xinw",
 887         "sys2pll_a20",
 888         "sys1pll_a20",
 889         "sys1pll_a19",
 890         "sys1pll_a18",
 891         "sys0pll_a20",
 892         "sys1pll_a17",
 893 };
 894
 895 static const char * const vdec_clk_parents[] = {
 896         "xin",
 897         "xinw",
 898         "sys2pll_a20",
 899         "sys1pll_a20",
 900         "sys1pll_a19",
 901         "sys1pll_a18",
 902         "sys0pll_a20",
 903         "sys1pll_a17",
 904 };
 905
 906 static const char * const gmac_clk_parents[] = {
 907         "xin",
 908         "xinw",
 909         "sys2pll_a20",
 910         "sys1pll_a20",
 911         "sys1pll_a19",
 912         "sys1pll_a18",
 913         "sys0pll_a20",
 914         "sys1pll_a17",
 915 };
 916
 917 static const char * const usb_clk_parents[] = {
 918         "xin",
 919         "xinw",
 920         "sys2pll_a20",
 921         "sys1pll_a20",
 922         "sys1pll_a19",
 923         "sys1pll_a18",
 924         "sys0pll_a20",
 925         "sys1pll_a17",
 926 };
 927
 928 static const char * const kas_clk_parents[] = {
 929         "xin",
 930         "xinw",
 931         "sys2pll_a20",
 932         "sys1pll_a20",
 933         "sys1pll_a19",
 934         "sys1pll_a18",
 935         "sys0pll_a20",
 936         "sys1pll_a17",
 937 };
 938
 939 static const char * const sec_clk_parents[] = {
 940         "xin",
 941         "xinw",
 942         "sys2pll_a20",
 943         "sys1pll_a20",
 944         "sys1pll_a19",
 945         "sys1pll_a18",
 946         "sys0pll_a20",
 947         "sys1pll_a17",
 948 };
 949
 950 static const char * const sdr_clk_parents[] = {
 951         "xin",
 952         "xinw",
 953         "sys2pll_a20",
 954         "sys1pll_a20",
 955         "sys1pll_a19",
 956         "sys1pll_a18",
 957         "sys0pll_a20",
 958         "sys1pll_a17",
 959 };
 960
 961 static const char * const vip_clk_parents[] = {
 962         "xin",
 963         "xinw",
 964         "sys2pll_a20",
 965         "sys1pll_a20",
 966         "sys1pll_a19",
 967         "sys1pll_a18",
 968         "sys0pll_a20",
 969         "sys1pll_a17",
 970 };
 971
 972 static const char * const nocd_clk_parents[] = {
 973         "xin",
 974         "xinw",
 975         "sys2pll_a20",
 976         "sys1pll_a20",
 977         "sys1pll_a19",
 978         "sys1pll_a18",
 979         "sys0pll_a20",
 980         "sys1pll_a17",
 981 };
 982
 983 static const char * const nocr_clk_parents[] = {
 984         "xin",
 985         "xinw",
 986         "sys2pll_a20",
 987         "sys1pll_a20",
 988         "sys1pll_a19",
 989         "sys1pll_a18",
 990         "sys0pll_a20",
 991         "sys1pll_a17",
 992 };
 993
 994 static const char * const tpiu_clk_parents[] = {
 995         "xin",
 996         "xinw",
 997         "sys2pll_a20",
 998         "sys1pll_a20",
 999         "sys1pll_a19",
1000         "sys1pll_a18",
1001         "sys0pll_a20",
1002         "sys1pll_a17",
1003 };
1004
1005 static struct atlas7_mux_init_data mux_list[] __initdata = {
1006         /* mux_name, parent_names, parent_num, flags, mux_flags, mux_offset, shift, width */
1007         { "i2s_mux", i2s_clk_parents, ARRAY_SIZE(i2s_clk_parents), 0, 0, SIRFSOC_CLKC_I2S_CLK_SEL, 0, 2 },
1008         { "usbphy_mux", usbphy_clk_parents, ARRAY_SIZE(usbphy_clk_parents), 0, 0, SIRFSOC_CLKC_I2S_CLK_SEL, 0, 3 },
1009         { "btss_mux", btss_clk_parents, ARRAY_SIZE(btss_clk_parents), 0, 0, SIRFSOC_CLKC_BTSS_CLK_SEL, 0, 3 },
1010         { "rgmii_mux", rgmii_clk_parents, ARRAY_SIZE(rgmii_clk_parents), 0, 0, SIRFSOC_CLKC_RGMII_CLK_SEL, 0, 3 },
1011         { "cpu_mux", cpu_clk_parents, ARRAY_SIZE(cpu_clk_parents), 0, 0, SIRFSOC_CLKC_CPU_CLK_SEL, 0, 3 },
1012         { "sdphy01_mux", sdphy01_clk_parents, ARRAY_SIZE(sdphy01_clk_parents), 0, 0, SIRFSOC_CLKC_SDPHY01_CLK_SEL, 0, 3 },
1013         { "sdphy23_mux", sdphy23_clk_parents, ARRAY_SIZE(sdphy23_clk_parents), 0, 0, SIRFSOC_CLKC_SDPHY23_CLK_SEL, 0, 3 },
1014         { "sdphy45_mux", sdphy45_clk_parents, ARRAY_SIZE(sdphy45_clk_parents), 0, 0, SIRFSOC_CLKC_SDPHY45_CLK_SEL, 0, 3 },
1015         { "sdphy67_mux", sdphy67_clk_parents, ARRAY_SIZE(sdphy67_clk_parents), 0, 0, SIRFSOC_CLKC_SDPHY67_CLK_SEL, 0, 3 },
1016         { "can_mux", can_clk_parents, ARRAY_SIZE(can_clk_parents), 0, 0, SIRFSOC_CLKC_CAN_CLK_SEL, 0, 3 },
1017         { "deint_mux", deint_clk_parents, ARRAY_SIZE(deint_clk_parents), 0, 0, SIRFSOC_CLKC_DEINT_CLK_SEL, 0, 3 },
1018         { "nand_mux", nand_clk_parents, ARRAY_SIZE(nand_clk_parents), 0, 0, SIRFSOC_CLKC_NAND_CLK_SEL, 0, 3 },
1019         { "disp0_mux", disp0_clk_parents, ARRAY_SIZE(disp0_clk_parents), 0, 0, SIRFSOC_CLKC_DISP0_CLK_SEL, 0, 3 },
1020         { "disp1_mux", disp1_clk_parents, ARRAY_SIZE(disp1_clk_parents), 0, 0, SIRFSOC_CLKC_DISP1_CLK_SEL, 0, 3 },
1021         { "gpu_mux", gpu_clk_parents, ARRAY_SIZE(gpu_clk_parents), 0, 0, SIRFSOC_CLKC_GPU_CLK_SEL, 0, 3 },
1022         { "gnss_mux", gnss_clk_parents, ARRAY_SIZE(gnss_clk_parents), 0, 0, SIRFSOC_CLKC_GNSS_CLK_SEL, 0, 3 },
1023         { "sys_mux", sys_clk_parents, ARRAY_SIZE(sys_clk_parents), 0, 0, SIRFSOC_CLKC_SYS_CLK_SEL, 0, 3 },
1024         { "io_mux", io_clk_parents, ARRAY_SIZE(io_clk_parents), 0, 0, SIRFSOC_CLKC_IO_CLK_SEL, 0, 3 },
1025         { "g2d_mux", g2d_clk_parents, ARRAY_SIZE(g2d_clk_parents), 0, 0, SIRFSOC_CLKC_G2D_CLK_SEL, 0, 3 },
1026         { "jpenc_mux", jpenc_clk_parents, ARRAY_SIZE(jpenc_clk_parents), 0, 0, SIRFSOC_CLKC_JPENC_CLK_SEL, 0, 3 },
1027         { "vdec_mux", vdec_clk_parents, ARRAY_SIZE(vdec_clk_parents), 0, 0, SIRFSOC_CLKC_VDEC_CLK_SEL, 0, 3 },
1028         { "gmac_mux", gmac_clk_parents, ARRAY_SIZE(gmac_clk_parents), 0, 0, SIRFSOC_CLKC_GMAC_CLK_SEL, 0, 3 },
1029         { "usb_mux", usb_clk_parents, ARRAY_SIZE(usb_clk_parents), 0, 0, SIRFSOC_CLKC_USB_CLK_SEL, 0, 3 },
1030         { "kas_mux", kas_clk_parents, ARRAY_SIZE(kas_clk_parents), 0, 0, SIRFSOC_CLKC_KAS_CLK_SEL, 0, 3 },
1031         { "sec_mux", sec_clk_parents, ARRAY_SIZE(sec_clk_parents), 0, 0, SIRFSOC_CLKC_SEC_CLK_SEL, 0, 3 },
1032         { "sdr_mux", sdr_clk_parents, ARRAY_SIZE(sdr_clk_parents), 0, 0, SIRFSOC_CLKC_SDR_CLK_SEL, 0, 3 },
1033         { "vip_mux", vip_clk_parents, ARRAY_SIZE(vip_clk_parents), 0, 0, SIRFSOC_CLKC_VIP_CLK_SEL, 0, 3 },
1034         { "nocd_mux", nocd_clk_parents, ARRAY_SIZE(nocd_clk_parents), 0, 0, SIRFSOC_CLKC_NOCD_CLK_SEL, 0, 3 },
1035         { "nocr_mux", nocr_clk_parents, ARRAY_SIZE(nocr_clk_parents), 0, 0, SIRFSOC_CLKC_NOCR_CLK_SEL, 0, 3 },
1036         { "tpiu_mux", tpiu_clk_parents, ARRAY_SIZE(tpiu_clk_parents), 0, 0, SIRFSOC_CLKC_TPIU_CLK_SEL, 0, 3 },
1037 };
1038
1039         /* new unit should add start from the tail of list */
1040 static struct atlas7_unit_init_data unit_list[] __initdata = {
1041         /* unit_name, parent_name, flags, regofs, bit, lock */
1042         { 0, "audmscm_kas", "kas_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 0, &root0_gate_lock },
1043         { 1, "gnssm_gnss", "gnss_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 1, &root0_gate_lock },
1044         { 2, "gpum_gpu", "gpu_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 2, &root0_gate_lock },
1045         { 3, "mediam_g2d", "g2d_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 3, &root0_gate_lock },
1046         { 4, "mediam_jpenc", "jpenc_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 4, &root0_gate_lock },
1047         { 5, "vdifm_disp0", "disp0_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 5, &root0_gate_lock },
1048         { 6, "vdifm_disp1", "disp1_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 6, &root0_gate_lock },
1049         { 7, "audmscm_i2s", "i2s_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 8, &root0_gate_lock },
1050         { 8, "audmscm_io", "io_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 11, &root0_gate_lock },
1051         { 9, "vdifm_io", "io_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 12, &root0_gate_lock },
1052         { 10, "gnssm_io", "io_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 13, &root0_gate_lock },
1053         { 11, "mediam_io", "io_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 14, &root0_gate_lock },
1054         { 12, "btm_io", "io_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 17, &root0_gate_lock },
1055         { 13, "mediam_sdphy01", "sdphy01_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 18, &root0_gate_lock },
1056         { 14, "vdifm_sdphy23", "sdphy23_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 19, &root0_gate_lock },
1057         { 15, "vdifm_sdphy45", "sdphy45_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 20, &root0_gate_lock },
1058         { 16, "vdifm_sdphy67", "sdphy67_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 21, &root0_gate_lock },
1059         { 17, "audmscm_xin", "xin", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 22, &root0_gate_lock },
1060         { 18, "mediam_nand", "nand_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 27, &root0_gate_lock },
1061         { 19, "gnssm_sec", "sec_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 28, &root0_gate_lock },
1062         { 20, "cpum_cpu", "cpu_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 29, &root0_gate_lock },
1063         { 21, "gnssm_xin", "xin", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 30, &root0_gate_lock },
1064         { 22, "vdifm_vip", "vip_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 31, &root0_gate_lock },
1065         { 23, "btm_btss", "btss_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 0, &root1_gate_lock },
1066         { 24, "mediam_usbphy", "usbphy_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 1, &root1_gate_lock },
1067         { 25, "rtcm_kas", "kas_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 2, &root1_gate_lock },
1068         { 26, "audmscm_nocd", "nocd_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 3, &root1_gate_lock },
1069         { 27, "vdifm_nocd", "nocd_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 4, &root1_gate_lock },
1070         { 28, "gnssm_nocd", "nocd_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 5, &root1_gate_lock },
1071         { 29, "mediam_nocd", "nocd_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 6, &root1_gate_lock },
1072         { 30, "cpum_nocd", "nocd_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 8, &root1_gate_lock },
1073         { 31, "gpum_nocd", "nocd_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 9, &root1_gate_lock },
1074         { 32, "audmscm_nocr", "nocr_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 11, &root1_gate_lock },
1075         { 33, "vdifm_nocr", "nocr_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 12, &root1_gate_lock },
1076         { 34, "gnssm_nocr", "nocr_mux", CLK_IGNORE_UNUSED, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 13, &root1_gate_lock },
1077         { 35, "mediam_nocr", "nocr_mux", CLK_IGNORE_UNUSED, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 14, &root1_gate_lock },
1078         { 36, "ddrm_nocr", "nocr_mux", CLK_IGNORE_UNUSED, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 15, &root1_gate_lock },
1079         { 37, "cpum_tpiu", "tpiu_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 16, &root1_gate_lock },
1080         { 38, "gpum_nocr", "nocr_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 17, &root1_gate_lock },
1081         { 39, "gnssm_rgmii", "rgmii_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 20, &root1_gate_lock },
1082         { 40, "mediam_vdec", "vdec_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 21, &root1_gate_lock },
1083         { 41, "gpum_sdr", "sdr_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 22, &root1_gate_lock },
1084         { 42, "vdifm_deint", "deint_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 23, &root1_gate_lock },
1085         { 43, "gnssm_can", "can_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 26, &root1_gate_lock },
1086         { 44, "mediam_usb", "usb_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 28, &root1_gate_lock },
1087         { 45, "gnssm_gmac", "gmac_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 29, &root1_gate_lock },
1088         { 46, "cvd_io", "audmscm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN1_SET, 0, &leaf1_gate_lock },
1089         { 47, "timer_io", "audmscm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN1_SET, 1, &leaf1_gate_lock },
1090         { 48, "pulse_io", "audmscm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN1_SET, 2, &leaf1_gate_lock },
1091         { 49, "tsc_io", "audmscm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN1_SET, 3, &leaf1_gate_lock },
1092         { 50, "tsc_xin", "audmscm_xin", 0, SIRFSOC_CLKC_LEAF_CLK_EN1_SET, 21, &leaf1_gate_lock },
1093         { 51, "ioctop_io", "audmscm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN1_SET, 4, &leaf1_gate_lock },
1094         { 52, "rsc_io", "audmscm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN1_SET, 5, &leaf1_gate_lock },
1095         { 53, "dvm_io", "audmscm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN1_SET, 6, &leaf1_gate_lock },
1096         { 54, "lvds_xin", "audmscm_xin", 0, SIRFSOC_CLKC_LEAF_CLK_EN1_SET, 7, &leaf1_gate_lock },
1097         { 55, "kas_kas", "audmscm_kas", 0, SIRFSOC_CLKC_LEAF_CLK_EN1_SET, 8, &leaf1_gate_lock },
1098         { 56, "ac97_kas", "audmscm_kas", 0, SIRFSOC_CLKC_LEAF_CLK_EN1_SET, 9, &leaf1_gate_lock },
1099         { 57, "usp0_kas", "audmscm_kas", 0, SIRFSOC_CLKC_LEAF_CLK_EN1_SET, 10, &leaf1_gate_lock },
1100         { 58, "usp1_kas", "audmscm_kas", 0, SIRFSOC_CLKC_LEAF_CLK_EN1_SET, 11, &leaf1_gate_lock },
1101         { 59, "usp2_kas", "audmscm_kas", 0, SIRFSOC_CLKC_LEAF_CLK_EN1_SET, 12, &leaf1_gate_lock },
1102         { 60, "dmac2_kas", "audmscm_kas", 0, SIRFSOC_CLKC_LEAF_CLK_EN1_SET, 13, &leaf1_gate_lock },
1103         { 61, "dmac3_kas", "audmscm_kas", 0, SIRFSOC_CLKC_LEAF_CLK_EN1_SET, 14, &leaf1_gate_lock },
1104         { 62, "audioif_kas", "audmscm_kas", 0, SIRFSOC_CLKC_LEAF_CLK_EN1_SET, 15, &leaf1_gate_lock },
1105         { 63, "i2s1_kas", "audmscm_kas", 0, SIRFSOC_CLKC_LEAF_CLK_EN1_SET, 17, &leaf1_gate_lock },
1106         { 64, "thaudmscm_io", "audmscm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN1_SET, 22, &leaf1_gate_lock },
1107         { 65, "analogtest_xin", "audmscm_xin", 0, SIRFSOC_CLKC_LEAF_CLK_EN1_SET, 23, &leaf1_gate_lock },
1108         { 66, "sys2pci_io", "vdifm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN2_SET, 0, &leaf2_gate_lock },
1109         { 67, "pciarb_io", "vdifm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN2_SET, 1, &leaf2_gate_lock },
1110         { 68, "pcicopy_io", "vdifm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN2_SET, 2, &leaf2_gate_lock },
1111         { 69, "rom_io", "vdifm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN2_SET, 3, &leaf2_gate_lock },
1112         { 70, "sdio23_io", "vdifm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN2_SET, 4, &leaf2_gate_lock },
1113         { 71, "sdio45_io", "vdifm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN2_SET, 5, &leaf2_gate_lock },
1114         { 72, "sdio67_io", "vdifm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN2_SET, 6, &leaf2_gate_lock },
1115         { 73, "vip1_io", "vdifm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN2_SET, 7, &leaf2_gate_lock },
1116         { 74, "vip1_vip", "vdifm_vip", 0, SIRFSOC_CLKC_LEAF_CLK_EN2_SET, 16, &leaf2_gate_lock },
1117         { 75, "sdio23_sdphy23", "vdifm_sdphy23", 0, SIRFSOC_CLKC_LEAF_CLK_EN2_SET, 8, &leaf2_gate_lock },
1118         { 76, "sdio45_sdphy45", "vdifm_sdphy45", 0, SIRFSOC_CLKC_LEAF_CLK_EN2_SET, 9, &leaf2_gate_lock },
1119         { 77, "sdio67_sdphy67", "vdifm_sdphy67", 0, SIRFSOC_CLKC_LEAF_CLK_EN2_SET, 10, &leaf2_gate_lock },
1120         { 78, "vpp0_disp0", "vdifm_disp0", 0, SIRFSOC_CLKC_LEAF_CLK_EN2_SET, 11, &leaf2_gate_lock },
1121         { 79, "lcd0_disp0", "vdifm_disp0", 0, SIRFSOC_CLKC_LEAF_CLK_EN2_SET, 12, &leaf2_gate_lock },
1122         { 80, "vpp1_disp1", "vdifm_disp1", 0, SIRFSOC_CLKC_LEAF_CLK_EN2_SET, 13, &leaf2_gate_lock },
1123         { 81, "lcd1_disp1", "vdifm_disp1", 0, SIRFSOC_CLKC_LEAF_CLK_EN2_SET, 14, &leaf2_gate_lock },
1124         { 82, "dcu_deint", "vdifm_deint", 0, SIRFSOC_CLKC_LEAF_CLK_EN2_SET, 15, &leaf2_gate_lock },
1125         { 83, "vdifm_dapa_r_nocr", "vdifm_nocr", 0, SIRFSOC_CLKC_LEAF_CLK_EN2_SET, 17, &leaf2_gate_lock },
1126         { 84, "gpio1_io", "vdifm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN2_SET, 18, &leaf2_gate_lock },
1127         { 85, "thvdifm_io", "vdifm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN2_SET, 19, &leaf2_gate_lock },
1128         { 86, "gmac_rgmii", "gnssm_rgmii", 0, SIRFSOC_CLKC_LEAF_CLK_EN3_SET, 0, &leaf3_gate_lock },
1129         { 87, "gmac_gmac", "gnssm_gmac", 0, SIRFSOC_CLKC_LEAF_CLK_EN3_SET, 1, &leaf3_gate_lock },
1130         { 88, "uart1_io", "gnssm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN3_SET, 2, &leaf3_gate_lock },
1131         { 89, "dmac0_io", "gnssm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN3_SET, 3, &leaf3_gate_lock },
1132         { 90, "uart0_io", "gnssm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN3_SET, 4, &leaf3_gate_lock },
1133         { 91, "uart2_io", "gnssm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN3_SET, 5, &leaf3_gate_lock },
1134         { 92, "uart3_io", "gnssm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN3_SET, 6, &leaf3_gate_lock },
1135         { 93, "uart4_io", "gnssm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN3_SET, 7, &leaf3_gate_lock },
1136         { 94, "uart5_io", "gnssm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN3_SET, 8, &leaf3_gate_lock },
1137         { 95, "spi1_io", "gnssm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN3_SET, 9, &leaf3_gate_lock },
1138         { 96, "gnss_gnss", "gnssm_gnss", 0, SIRFSOC_CLKC_LEAF_CLK_EN3_SET, 10, &leaf3_gate_lock },
1139         { 97, "canbus1_can", "gnssm_can", 0, SIRFSOC_CLKC_LEAF_CLK_EN3_SET, 12, &leaf3_gate_lock },
1140         { 98, "ccsec_sec", "gnssm_sec", 0, SIRFSOC_CLKC_LEAF_CLK_EN3_SET, 15, &leaf3_gate_lock },
1141         { 99,  "ccpub_sec", "gnssm_sec", 0, SIRFSOC_CLKC_LEAF_CLK_EN3_SET, 16, &leaf3_gate_lock },
1142         { 100, "gnssm_dapa_r_nocr", "gnssm_nocr", 0, SIRFSOC_CLKC_LEAF_CLK_EN3_SET, 13, &leaf3_gate_lock },
1143         { 101, "thgnssm_io", "gnssm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN3_SET, 14, &leaf3_gate_lock },
1144         { 102, "media_vdec", "mediam_vdec", 0, SIRFSOC_CLKC_LEAF_CLK_EN4_SET, 0, &leaf4_gate_lock },
1145         { 103, "media_jpenc", "mediam_jpenc", 0, SIRFSOC_CLKC_LEAF_CLK_EN4_SET, 1, &leaf4_gate_lock },
1146         { 104, "g2d_g2d", "mediam_g2d", 0, SIRFSOC_CLKC_LEAF_CLK_EN4_SET, 2, &leaf4_gate_lock },
1147         { 105, "i2c0_io", "mediam_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN4_SET, 3, &leaf4_gate_lock },
1148         { 106, "i2c1_io", "mediam_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN4_SET, 4, &leaf4_gate_lock },
1149         { 107, "gpio0_io", "mediam_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN4_SET, 5, &leaf4_gate_lock },
1150         { 108, "nand_io", "mediam_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN4_SET, 6, &leaf4_gate_lock },
1151         { 109, "sdio01_io", "mediam_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN4_SET, 7, &leaf4_gate_lock },
1152         { 110, "sys2pci2_io", "mediam_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN4_SET, 8, &leaf4_gate_lock },
1153         { 111, "sdio01_sdphy01", "mediam_sdphy01", 0, SIRFSOC_CLKC_LEAF_CLK_EN4_SET, 9, &leaf4_gate_lock },
1154         { 112, "nand_nand", "mediam_nand", 0, SIRFSOC_CLKC_LEAF_CLK_EN4_SET, 10, &leaf4_gate_lock },
1155         { 113, "usb0_usb", "mediam_usb", 0, SIRFSOC_CLKC_LEAF_CLK_EN4_SET, 11, &leaf4_gate_lock },
1156         { 114, "usb1_usb", "mediam_usb", 0, SIRFSOC_CLKC_LEAF_CLK_EN4_SET, 12, &leaf4_gate_lock },
1157         { 115, "usbphy0_usbphy", "mediam_usbphy", 0, SIRFSOC_CLKC_LEAF_CLK_EN4_SET, 13, &leaf4_gate_lock },
1158         { 116, "usbphy1_usbphy", "mediam_usbphy", 0, SIRFSOC_CLKC_LEAF_CLK_EN4_SET, 14, &leaf4_gate_lock },
1159         { 117, "thmediam_io", "mediam_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN4_SET, 15, &leaf4_gate_lock },
1160         { 118, "memc_mem", "mempll_clk1", CLK_IGNORE_UNUSED, SIRFSOC_CLKC_LEAF_CLK_EN5_SET, 0, &leaf5_gate_lock },
1161         { 119, "dapa_mem", "mempll_clk1", 0, SIRFSOC_CLKC_LEAF_CLK_EN5_SET, 1, &leaf5_gate_lock },
1162         { 120, "nocddrm_nocr", "ddrm_nocr", 0, SIRFSOC_CLKC_LEAF_CLK_EN5_SET, 2, &leaf5_gate_lock },
1163         { 121, "thddrm_nocr", "ddrm_nocr", 0, SIRFSOC_CLKC_LEAF_CLK_EN5_SET, 3, &leaf5_gate_lock },
1164         { 122, "spram1_cpudiv2", "cpum_cpu", 0, SIRFSOC_CLKC_LEAF_CLK_EN6_SET, 0, &leaf6_gate_lock },
1165         { 123, "spram2_cpudiv2", "cpum_cpu", 0, SIRFSOC_CLKC_LEAF_CLK_EN6_SET, 1, &leaf6_gate_lock },
1166         { 124, "coresight_cpudiv2", "cpum_cpu", 0, SIRFSOC_CLKC_LEAF_CLK_EN6_SET, 2, &leaf6_gate_lock },
1167         { 125, "thcpum_cpudiv4", "cpum_cpu", 0, SIRFSOC_CLKC_LEAF_CLK_EN6_SET, 3, &leaf6_gate_lock },
1168         { 126, "graphic_gpu", "gpum_gpu", 0, SIRFSOC_CLKC_LEAF_CLK_EN7_SET, 0, &leaf7_gate_lock },
1169         { 127, "vss_sdr", "gpum_sdr", 0, SIRFSOC_CLKC_LEAF_CLK_EN7_SET, 1, &leaf7_gate_lock },
1170         { 128, "thgpum_nocr", "gpum_nocr", 0, SIRFSOC_CLKC_LEAF_CLK_EN7_SET, 2, &leaf7_gate_lock },
1171         { 129, "a7ca_btss", "btm_btss", 0, SIRFSOC_CLKC_LEAF_CLK_EN8_SET, 1, &leaf8_gate_lock },
1172         { 130, "dmac4_io", "btm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN8_SET, 2, &leaf8_gate_lock },
1173         { 131, "uart6_io", "btm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN8_SET, 3, &leaf8_gate_lock },
1174         { 132, "usp3_io", "btm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN8_SET, 4, &leaf8_gate_lock },
1175         { 133, "a7ca_io", "btm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN8_SET, 5, &leaf8_gate_lock },
1176         { 134, "noc_btm_io", "btm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN8_SET, 6, &leaf8_gate_lock },
1177         { 135, "thbtm_io", "btm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN8_SET, 7, &leaf8_gate_lock },
1178         { 136, "btslow", "xinw_fixdiv_btslow", 0, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 25, &root1_gate_lock },
1179         { 137, "a7ca_btslow", "btslow", 0, SIRFSOC_CLKC_LEAF_CLK_EN8_SET, 0, &leaf8_gate_lock },
1180         { 138, "pwm_io", "io_mux", 0, SIRFSOC_CLKC_LEAF_CLK_EN0_SET, 0, &leaf0_gate_lock },
1181         { 139, "pwm_xin", "xin", 0, SIRFSOC_CLKC_LEAF_CLK_EN0_SET, 1, &leaf0_gate_lock },
1182         { 140, "pwm_xinw", "xinw", 0, SIRFSOC_CLKC_LEAF_CLK_EN0_SET, 2, &leaf0_gate_lock },
1183         { 141, "thcgum_sys", "sys_mux", 0, SIRFSOC_CLKC_LEAF_CLK_EN0_SET, 3, &leaf0_gate_lock },
1184 };
1185
1186 static struct clk *atlas7_clks[ARRAY_SIZE(unit_list) + ARRAY_SIZE(mux_list)];
1187
1188 static int unit_clk_is_enabled(struct clk_hw *hw)
1189 {
1190         struct clk_unit *clk = to_unitclk(hw);
1191         u32 reg;
1192
1193         reg = clk->regofs + SIRFSOC_CLKC_ROOT_CLK_EN0_STAT - SIRFSOC_CLKC_ROOT_CLK_EN0_SET;
1194
1195         return !!(clkc_readl(reg) & BIT(clk->bit));
1196 }
1197
1198 static int unit_clk_enable(struct clk_hw *hw)
1199 {
1200         u32 reg;
1201         struct clk_unit *clk = to_unitclk(hw);
1202         unsigned long flags;
1203
1204         reg = clk->regofs;
1205
1206         spin_lock_irqsave(clk->lock, flags);
1207         clkc_writel(BIT(clk->bit), reg);
1208         spin_unlock_irqrestore(clk->lock, flags);
1209         return 0;
1210 }
1211
1212 static void unit_clk_disable(struct clk_hw *hw)
1213 {
1214         u32  reg;
1215         struct clk_unit *clk = to_unitclk(hw);
1216         unsigned long flags;
1217
1218         reg = clk->regofs + SIRFSOC_CLKC_ROOT_CLK_EN0_CLR - SIRFSOC_CLKC_ROOT_CLK_EN0_SET;
1219
1220         spin_lock_irqsave(clk->lock, flags);
1221         clkc_writel(BIT(clk->bit), reg);
1222         spin_unlock_irqrestore(clk->lock, flags);
1223 }
1224
1225 static const struct clk_ops unit_clk_ops = {
1226         .is_enabled = unit_clk_is_enabled,
1227         .enable = unit_clk_enable,
1228         .disable = unit_clk_disable,
1229 };
1230
1231 static struct clk * __init
1232 atlas7_unit_clk_register(struct device *dev, const char *name,
1233                  const char * const parent_name, unsigned long flags,
1234                  u32 regofs, u8 bit, spinlock_t *lock)
1235 {
1236         struct clk *clk;
1237         struct clk_unit *unit;
1238         struct clk_init_data init;
1239
1240         unit = kzalloc(sizeof(*unit), GFP_KERNEL);
1241         if (!unit)
1242                 return ERR_PTR(-ENOMEM);
1243
1244         init.name = name;
1245         init.parent_names = &parent_name;
1246         init.num_parents = 1;
1247         init.ops = &unit_clk_ops;
1248         init.flags = flags;
1249
1250         unit->hw.init = &init;
1251         unit->regofs = regofs;
1252         unit->bit = bit;
1253         unit->lock = lock;
1254
1255         clk = clk_register(dev, &unit->hw);
1256         if (IS_ERR(clk))
1257                 kfree(unit);
1258
1259         return clk;
1260 }
1261
1262 static struct atlas7_reset_desc atlas7_reset_unit[] = {
1263         { "PWM", 0x0244, 0, 0x0320, 0, &leaf0_gate_lock }, /* 0-5 */
1264         { "THCGUM", 0x0244, 3, 0x0320, 1, &leaf0_gate_lock },
1265         { "CVD", 0x04A0, 0, 0x032C, 0, &leaf1_gate_lock },
1266         { "TIMER", 0x04A0, 1, 0x032C, 1, &leaf1_gate_lock },
1267         { "PULSEC", 0x04A0, 2, 0x032C, 2, &leaf1_gate_lock },
1268         { "TSC", 0x04A0, 3, 0x032C, 3, &leaf1_gate_lock },
1269         { "IOCTOP", 0x04A0, 4, 0x032C, 4, &leaf1_gate_lock }, /* 6-10 */
1270         { "RSC", 0x04A0, 5, 0x032C, 5, &leaf1_gate_lock },
1271         { "DVM", 0x04A0, 6, 0x032C, 6, &leaf1_gate_lock },
1272         { "LVDS", 0x04A0, 7, 0x032C, 7, &leaf1_gate_lock },
1273         { "KAS", 0x04A0, 8, 0x032C, 8, &leaf1_gate_lock },
1274         { "AC97", 0x04A0, 9, 0x032C, 9, &leaf1_gate_lock }, /* 11-15 */
1275         { "USP0", 0x04A0, 10, 0x032C, 10, &leaf1_gate_lock },
1276         { "USP1", 0x04A0, 11, 0x032C, 11, &leaf1_gate_lock },
1277         { "USP2", 0x04A0, 12, 0x032C, 12, &leaf1_gate_lock },
1278         { "DMAC2", 0x04A0, 13, 0x032C, 13, &leaf1_gate_lock },
1279         { "DMAC3", 0x04A0, 14, 0x032C, 14, &leaf1_gate_lock }, /* 16-20 */
1280         { "AUDIO", 0x04A0, 15, 0x032C, 15, &leaf1_gate_lock },
1281         { "I2S1", 0x04A0, 17, 0x032C, 16, &leaf1_gate_lock },
1282         { "PMU_AUDIO", 0x04A0, 22, 0x032C, 17, &leaf1_gate_lock },
1283         { "THAUDMSCM", 0x04A0, 23, 0x032C, 18, &leaf1_gate_lock },
1284         { "SYS2PCI", 0x04B8, 0, 0x0338, 0, &leaf2_gate_lock }, /* 21-25 */
1285         { "PCIARB", 0x04B8, 1, 0x0338, 1, &leaf2_gate_lock },
1286         { "PCICOPY", 0x04B8, 2, 0x0338, 2, &leaf2_gate_lock },
1287         { "ROM", 0x04B8, 3, 0x0338, 3, &leaf2_gate_lock },
1288         { "SDIO23", 0x04B8, 4, 0x0338, 4, &leaf2_gate_lock },
1289         { "SDIO45", 0x04B8, 5, 0x0338, 5, &leaf2_gate_lock }, /* 26-30 */
1290         { "SDIO67", 0x04B8, 6, 0x0338, 6, &leaf2_gate_lock },
1291         { "VIP1", 0x04B8, 7, 0x0338, 7, &leaf2_gate_lock },
1292         { "VPP0", 0x04B8, 11, 0x0338, 8, &leaf2_gate_lock },
1293         { "LCD0", 0x04B8, 12, 0x0338, 9, &leaf2_gate_lock },
1294         { "VPP1", 0x04B8, 13, 0x0338, 10, &leaf2_gate_lock }, /* 31-35 */
1295         { "LCD1", 0x04B8, 14, 0x0338, 11, &leaf2_gate_lock },
1296         { "DCU", 0x04B8, 15, 0x0338, 12, &leaf2_gate_lock },
1297         { "GPIO", 0x04B8, 18, 0x0338, 13, &leaf2_gate_lock },
1298         { "DAPA_VDIFM", 0x04B8, 17, 0x0338, 15, &leaf2_gate_lock },
1299         { "THVDIFM", 0x04B8, 19, 0x0338, 16, &leaf2_gate_lock }, /* 36-40 */
1300         { "RGMII", 0x04D0, 0, 0x0344, 0, &leaf3_gate_lock },
1301         { "GMAC", 0x04D0, 1, 0x0344, 1, &leaf3_gate_lock },
1302         { "UART1", 0x04D0, 2, 0x0344, 2, &leaf3_gate_lock },
1303         { "DMAC0", 0x04D0, 3, 0x0344, 3, &leaf3_gate_lock },
1304         { "UART0", 0x04D0, 4, 0x0344, 4, &leaf3_gate_lock }, /* 41-45 */
1305         { "UART2", 0x04D0, 5, 0x0344, 5, &leaf3_gate_lock },
1306         { "UART3", 0x04D0, 6, 0x0344, 6, &leaf3_gate_lock },
1307         { "UART4", 0x04D0, 7, 0x0344, 7, &leaf3_gate_lock },
1308         { "UART5", 0x04D0, 8, 0x0344, 8, &leaf3_gate_lock },
1309         { "SPI1", 0x04D0, 9, 0x0344, 9, &leaf3_gate_lock }, /* 46-50 */
1310         { "GNSS_SYS_M0", 0x04D0, 10, 0x0344, 10, &leaf3_gate_lock },
1311         { "CANBUS1", 0x04D0, 12, 0x0344, 11, &leaf3_gate_lock },
1312         { "CCSEC", 0x04D0, 15, 0x0344, 12, &leaf3_gate_lock },
1313         { "CCPUB", 0x04D0, 16, 0x0344, 13, &leaf3_gate_lock },
1314         { "DAPA_GNSSM", 0x04D0, 13, 0x0344, 14, &leaf3_gate_lock }, /* 51-55 */
1315         { "THGNSSM", 0x04D0, 14, 0x0344, 15, &leaf3_gate_lock },
1316         { "VDEC", 0x04E8, 0, 0x0350, 0, &leaf4_gate_lock },
1317         { "JPENC", 0x04E8, 1, 0x0350, 1, &leaf4_gate_lock },
1318         { "G2D", 0x04E8, 2, 0x0350, 2, &leaf4_gate_lock },
1319         { "I2C0", 0x04E8, 3, 0x0350, 3, &leaf4_gate_lock }, /* 56-60 */
1320         { "I2C1", 0x04E8, 4, 0x0350, 4, &leaf4_gate_lock },
1321         { "GPIO0", 0x04E8, 5, 0x0350, 5, &leaf4_gate_lock },
1322         { "NAND", 0x04E8, 6, 0x0350, 6, &leaf4_gate_lock },
1323         { "SDIO01", 0x04E8, 7, 0x0350, 7, &leaf4_gate_lock },
1324         { "SYS2PCI2", 0x04E8, 8, 0x0350, 8, &leaf4_gate_lock }, /* 61-65 */
1325         { "USB0", 0x04E8, 11, 0x0350, 9, &leaf4_gate_lock },
1326         { "USB1", 0x04E8, 12, 0x0350, 10, &leaf4_gate_lock },
1327         { "THMEDIAM", 0x04E8, 15, 0x0350, 11, &leaf4_gate_lock },
1328         { "MEMC_DDRPHY", 0x0500, 0, 0x035C, 0, &leaf5_gate_lock },
1329         { "MEMC_UPCTL", 0x0500, 0, 0x035C, 1, &leaf5_gate_lock }, /* 66-70 */
1330         { "DAPA_MEM", 0x0500, 1, 0x035C, 2, &leaf5_gate_lock },
1331         { "MEMC_MEMDIV", 0x0500, 0, 0x035C, 3, &leaf5_gate_lock },
1332         { "THDDRM", 0x0500, 3, 0x035C, 4, &leaf5_gate_lock },
1333         { "CORESIGHT", 0x0518, 3, 0x0368, 13, &leaf6_gate_lock },
1334         { "THCPUM", 0x0518, 4, 0x0368, 17, &leaf6_gate_lock }, /* 71-75 */
1335         { "GRAPHIC", 0x0530, 0, 0x0374, 0, &leaf7_gate_lock },
1336         { "VSS_SDR", 0x0530, 1, 0x0374, 1, &leaf7_gate_lock },
1337         { "THGPUM", 0x0530, 2, 0x0374, 2, &leaf7_gate_lock },
1338         { "DMAC4", 0x0548, 2, 0x0380, 1, &leaf8_gate_lock },
1339         { "UART6", 0x0548, 3, 0x0380, 2, &leaf8_gate_lock }, /* 76- */
1340         { "USP3", 0x0548, 4, 0x0380, 3, &leaf8_gate_lock },
1341         { "THBTM", 0x0548, 5, 0x0380, 5, &leaf8_gate_lock },
1342         { "A7CA", 0x0548, 1, 0x0380, 0, &leaf8_gate_lock },
1343         { "A7CA_APB", 0x0548, 5, 0x0380, 4, &leaf8_gate_lock },
1344 };
1345
1346 static int atlas7_reset_module(struct reset_controller_dev *rcdev,
1347                                         unsigned long reset_idx)
1348 {
1349         struct atlas7_reset_desc *reset = &atlas7_reset_unit[reset_idx];
1350         unsigned long flags;
1351
1352         /*
1353          * HW suggest unit reset sequence:
1354          * assert sw reset (0)
1355          * setting sw clk_en to if the clock was disabled before reset
1356          * delay 16 clocks
1357          * disable clock (sw clk_en = 0)
1358          * de-assert reset (1)
1359          * after this sequence, restore clock or not is decided by SW
1360          */
1361
1362         spin_lock_irqsave(reset->lock, flags);
1363         /* clock enable or not */
1364         if (clkc_readl(reset->clk_ofs + 8) & (1 << reset->clk_bit)) {
1365                 clkc_writel(1 << reset->rst_bit, reset->rst_ofs + 4);
1366                 udelay(2);
1367                 clkc_writel(1 << reset->clk_bit, reset->clk_ofs + 4);
1368                 clkc_writel(1 << reset->rst_bit, reset->rst_ofs);
1369                 /* restore clock enable */
1370                 clkc_writel(1 << reset->clk_bit, reset->clk_ofs);
1371         } else {
1372                 clkc_writel(1 << reset->rst_bit, reset->rst_ofs + 4);
1373                 clkc_writel(1 << reset->clk_bit, reset->clk_ofs);
1374                 udelay(2);
1375                 clkc_writel(1 << reset->clk_bit, reset->clk_ofs + 4);
1376                 clkc_writel(1 << reset->rst_bit, reset->rst_ofs);
1377         }
1378         spin_unlock_irqrestore(reset->lock, flags);
1379
1380         return 0;
1381 }
1382
1383 static struct reset_control_ops atlas7_rst_ops = {
1384         .reset = atlas7_reset_module,
1385 };
1386
1387 static struct reset_controller_dev atlas7_rst_ctlr = {
1388         .ops = &atlas7_rst_ops,
1389         .owner = THIS_MODULE,
1390         .of_reset_n_cells = 1,
1391 };
1392
1393 static void __init atlas7_clk_init(struct device_node *np)
1394 {
1395         struct clk *clk;
1396         struct atlas7_div_init_data *div;
1397         struct atlas7_mux_init_data *mux;
1398         struct atlas7_unit_init_data *unit;
1399         int i;
1400         int ret;
1401
1402         sirfsoc_clk_vbase = of_iomap(np, 0);
1403         if (!sirfsoc_clk_vbase)
1404                 panic("unable to map clkc registers\n");
1405
1406         of_node_put(np);
1407
1408         clk = clk_register(NULL, &clk_cpupll.hw);
1409         BUG_ON(!clk);
1410         clk = clk_register(NULL, &clk_mempll.hw);
1411         BUG_ON(!clk);
1412         clk = clk_register(NULL, &clk_sys0pll.hw);
1413         BUG_ON(!clk);
1414         clk = clk_register(NULL, &clk_sys1pll.hw);
1415         BUG_ON(!clk);
1416         clk = clk_register(NULL, &clk_sys2pll.hw);
1417         BUG_ON(!clk);
1418         clk = clk_register(NULL, &clk_sys3pll.hw);
1419         BUG_ON(!clk);
1420
1421         clk = clk_register_divider_table(NULL, "cpupll_div1", "cpupll_vco", 0,
1422                          sirfsoc_clk_vbase + SIRFSOC_CLKC_CPUPLL_AB_CTRL1, 0, 3, 0,
1423                          pll_div_table, &cpupll_ctrl1_lock);
1424         BUG_ON(!clk);
1425         clk = clk_register_divider_table(NULL, "cpupll_div2", "cpupll_vco", 0,
1426                          sirfsoc_clk_vbase + SIRFSOC_CLKC_CPUPLL_AB_CTRL1, 4, 3, 0,
1427                          pll_div_table, &cpupll_ctrl1_lock);
1428         BUG_ON(!clk);
1429         clk = clk_register_divider_table(NULL, "cpupll_div3", "cpupll_vco", 0,
1430                          sirfsoc_clk_vbase + SIRFSOC_CLKC_CPUPLL_AB_CTRL1, 8, 3, 0,
1431                          pll_div_table, &cpupll_ctrl1_lock);
1432         BUG_ON(!clk);
1433
1434         clk = clk_register_divider_table(NULL, "mempll_div1", "mempll_vco", 0,
1435                          sirfsoc_clk_vbase + SIRFSOC_CLKC_MEMPLL_AB_CTRL1, 0, 3, 0,
1436                          pll_div_table, &mempll_ctrl1_lock);
1437         BUG_ON(!clk);
1438         clk = clk_register_divider_table(NULL, "mempll_div2", "mempll_vco", 0,
1439                          sirfsoc_clk_vbase + SIRFSOC_CLKC_MEMPLL_AB_CTRL1, 4, 3, 0,
1440                          pll_div_table, &mempll_ctrl1_lock);
1441         BUG_ON(!clk);
1442         clk = clk_register_divider_table(NULL, "mempll_div3", "mempll_vco", 0,
1443                          sirfsoc_clk_vbase + SIRFSOC_CLKC_MEMPLL_AB_CTRL1, 8, 3, 0,
1444                          pll_div_table, &mempll_ctrl1_lock);
1445         BUG_ON(!clk);
1446
1447         clk = clk_register_divider_table(NULL, "sys0pll_div1", "sys0pll_vco", 0,
1448                          sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS0PLL_AB_CTRL1, 0, 3, 0,
1449                          pll_div_table, &sys0pll_ctrl1_lock);
1450         BUG_ON(!clk);
1451         clk = clk_register_divider_table(NULL, "sys0pll_div2", "sys0pll_vco", 0,
1452                          sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS0PLL_AB_CTRL1, 4, 3, 0,
1453                          pll_div_table, &sys0pll_ctrl1_lock);
1454         BUG_ON(!clk);
1455         clk = clk_register_divider_table(NULL, "sys0pll_div3", "sys0pll_vco", 0,
1456                          sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS0PLL_AB_CTRL1, 8, 3, 0,
1457                          pll_div_table, &sys0pll_ctrl1_lock);
1458         BUG_ON(!clk);
1459         clk = clk_register_fixed_factor(NULL, "sys0pll_fixdiv", "sys0pll_vco",
1460                                         CLK_SET_RATE_PARENT, 1, 2);
1461
1462         clk = clk_register_divider_table(NULL, "sys1pll_div1", "sys1pll_vco", 0,
1463                          sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS1PLL_AB_CTRL1, 0, 3, 0,
1464                          pll_div_table, &sys1pll_ctrl1_lock);
1465         BUG_ON(!clk);
1466         clk = clk_register_divider_table(NULL, "sys1pll_div2", "sys1pll_vco", 0,
1467                          sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS1PLL_AB_CTRL1, 4, 3, 0,
1468                          pll_div_table, &sys1pll_ctrl1_lock);
1469         BUG_ON(!clk);
1470         clk = clk_register_divider_table(NULL, "sys1pll_div3", "sys1pll_vco", 0,
1471                          sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS1PLL_AB_CTRL1, 8, 3, 0,
1472                          pll_div_table, &sys1pll_ctrl1_lock);
1473         BUG_ON(!clk);
1474         clk = clk_register_fixed_factor(NULL, "sys1pll_fixdiv", "sys1pll_vco",
1475                                         CLK_SET_RATE_PARENT, 1, 2);
1476
1477         clk = clk_register_divider_table(NULL, "sys2pll_div1", "sys2pll_vco", 0,
1478                          sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS2PLL_AB_CTRL1, 0, 3, 0,
1479                          pll_div_table, &sys2pll_ctrl1_lock);
1480         BUG_ON(!clk);
1481         clk = clk_register_divider_table(NULL, "sys2pll_div2", "sys2pll_vco", 0,
1482                          sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS2PLL_AB_CTRL1, 4, 3, 0,
1483                          pll_div_table, &sys2pll_ctrl1_lock);
1484         BUG_ON(!clk);
1485         clk = clk_register_divider_table(NULL, "sys2pll_div3", "sys2pll_vco", 0,
1486                          sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS2PLL_AB_CTRL1, 8, 3, 0,
1487                          pll_div_table, &sys2pll_ctrl1_lock);
1488         BUG_ON(!clk);
1489         clk = clk_register_fixed_factor(NULL, "sys2pll_fixdiv", "sys2pll_vco",
1490                                         CLK_SET_RATE_PARENT, 1, 2);
1491
1492         clk = clk_register_divider_table(NULL, "sys3pll_div1", "sys3pll_vco", 0,
1493                          sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS3PLL_AB_CTRL1, 0, 3, 0,
1494                          pll_div_table, &sys3pll_ctrl1_lock);
1495         BUG_ON(!clk);
1496         clk = clk_register_divider_table(NULL, "sys3pll_div2", "sys3pll_vco", 0,
1497                          sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS3PLL_AB_CTRL1, 4, 3, 0,
1498                          pll_div_table, &sys3pll_ctrl1_lock);
1499         BUG_ON(!clk);
1500         clk = clk_register_divider_table(NULL, "sys3pll_div3", "sys3pll_vco", 0,
1501                          sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS3PLL_AB_CTRL1, 8, 3, 0,
1502                          pll_div_table, &sys3pll_ctrl1_lock);
1503         BUG_ON(!clk);
1504         clk = clk_register_fixed_factor(NULL, "sys3pll_fixdiv", "sys3pll_vco",
1505                                         CLK_SET_RATE_PARENT, 1, 2);
1506
1507         BUG_ON(!clk);
1508         clk = clk_register_fixed_factor(NULL, "xinw_fixdiv_btslow", "xinw",
1509                                         CLK_SET_RATE_PARENT, 1, 4);
1510
1511         BUG_ON(!clk);
1512         clk = clk_register_gate(NULL, "cpupll_clk1", "cpupll_div1",
1513                 CLK_SET_RATE_PARENT, sirfsoc_clk_vbase + SIRFSOC_CLKC_CPUPLL_AB_CTRL1,
1514                                 12, 0, &cpupll_ctrl1_lock);
1515         BUG_ON(!clk);
1516         clk = clk_register_gate(NULL, "cpupll_clk2", "cpupll_div2",
1517                 CLK_SET_RATE_PARENT, sirfsoc_clk_vbase + SIRFSOC_CLKC_CPUPLL_AB_CTRL1,
1518                                 13, 0, &cpupll_ctrl1_lock);
1519         BUG_ON(!clk);
1520         clk = clk_register_gate(NULL, "cpupll_clk3", "cpupll_div3",
1521                 CLK_SET_RATE_PARENT, sirfsoc_clk_vbase + SIRFSOC_CLKC_CPUPLL_AB_CTRL1,
1522                                 14, 0, &cpupll_ctrl1_lock);
1523         BUG_ON(!clk);
1524
1525         clk = clk_register_gate(NULL, "mempll_clk1", "mempll_div1",
1526                 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1527                 sirfsoc_clk_vbase + SIRFSOC_CLKC_MEMPLL_AB_CTRL1,
1528                 12, 0, &mempll_ctrl1_lock);
1529         BUG_ON(!clk);
1530         clk = clk_register_gate(NULL, "mempll_clk2", "mempll_div2",
1531                 CLK_SET_RATE_PARENT, sirfsoc_clk_vbase + SIRFSOC_CLKC_MEMPLL_AB_CTRL1,
1532                                 13, 0, &mempll_ctrl1_lock);
1533         BUG_ON(!clk);
1534         clk = clk_register_gate(NULL, "mempll_clk3", "mempll_div3",
1535                 CLK_SET_RATE_PARENT, sirfsoc_clk_vbase + SIRFSOC_CLKC_MEMPLL_AB_CTRL1,
1536                                 14, 0, &mempll_ctrl1_lock);
1537         BUG_ON(!clk);
1538
1539         clk = clk_register_gate(NULL, "sys0pll_clk1", "sys0pll_div1",
1540                 CLK_SET_RATE_PARENT, sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS0PLL_AB_CTRL1,
1541                                 12, 0, &sys0pll_ctrl1_lock);
1542         BUG_ON(!clk);
1543         clk = clk_register_gate(NULL, "sys0pll_clk2", "sys0pll_div2",
1544                 CLK_SET_RATE_PARENT, sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS0PLL_AB_CTRL1,
1545                                 13, 0, &sys0pll_ctrl1_lock);
1546         BUG_ON(!clk);
1547         clk = clk_register_gate(NULL, "sys0pll_clk3", "sys0pll_div3",
1548                 CLK_SET_RATE_PARENT, sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS0PLL_AB_CTRL1,
1549                                 14, 0, &sys0pll_ctrl1_lock);
1550         BUG_ON(!clk);
1551
1552         clk = clk_register_gate(NULL, "sys1pll_clk1", "sys1pll_div1",
1553                 CLK_SET_RATE_PARENT, sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS1PLL_AB_CTRL1,
1554                                 12, 0, &sys1pll_ctrl1_lock);
1555         BUG_ON(!clk);
1556         clk = clk_register_gate(NULL, "sys1pll_clk2", "sys1pll_div2",
1557                 CLK_SET_RATE_PARENT, sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS1PLL_AB_CTRL1,
1558                                 13, 0, &sys1pll_ctrl1_lock);
1559         BUG_ON(!clk);
1560         clk = clk_register_gate(NULL, "sys1pll_clk3", "sys1pll_div3",
1561                 CLK_SET_RATE_PARENT, sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS1PLL_AB_CTRL1,
1562                                 14, 0, &sys1pll_ctrl1_lock);
1563         BUG_ON(!clk);
1564
1565         clk = clk_register_gate(NULL, "sys2pll_clk1", "sys2pll_div1",
1566                 CLK_SET_RATE_PARENT, sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS2PLL_AB_CTRL1,
1567                                 12, 0, &sys2pll_ctrl1_lock);
1568         BUG_ON(!clk);
1569         clk = clk_register_gate(NULL, "sys2pll_clk2", "sys2pll_div2",
1570                 CLK_SET_RATE_PARENT, sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS2PLL_AB_CTRL1,
1571                                 13, 0, &sys2pll_ctrl1_lock);
1572         BUG_ON(!clk);
1573         clk = clk_register_gate(NULL, "sys2pll_clk3", "sys2pll_div3",
1574                 CLK_SET_RATE_PARENT, sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS2PLL_AB_CTRL1,
1575                                 14, 0, &sys2pll_ctrl1_lock);
1576         BUG_ON(!clk);
1577
1578         clk = clk_register_gate(NULL, "sys3pll_clk1", "sys3pll_div1",
1579                 CLK_SET_RATE_PARENT, sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS3PLL_AB_CTRL1,
1580                                 12, 0, &sys3pll_ctrl1_lock);
1581         BUG_ON(!clk);
1582         clk = clk_register_gate(NULL, "sys3pll_clk2", "sys3pll_div2",
1583                 CLK_SET_RATE_PARENT, sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS3PLL_AB_CTRL1,
1584                                 13, 0, &sys3pll_ctrl1_lock);
1585         BUG_ON(!clk);
1586         clk = clk_register_gate(NULL, "sys3pll_clk3", "sys3pll_div3",
1587                 CLK_SET_RATE_PARENT, sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS3PLL_AB_CTRL1,
1588                                 14, 0, &sys3pll_ctrl1_lock);
1589         BUG_ON(!clk);
1590
1591         clk = clk_register(NULL, &clk_audio_dto.hw);
1592         BUG_ON(!clk);
1593
1594         clk = clk_register(NULL, &clk_disp0_dto.hw);
1595         BUG_ON(!clk);
1596
1597         clk = clk_register(NULL, &clk_disp1_dto.hw);
1598         BUG_ON(!clk);
1599
1600         for (i = 0; i < ARRAY_SIZE(divider_list); i++) {
1601                 div = &divider_list[i];
1602                 clk = clk_register_divider(NULL, div->div_name,
1603                         div->parent_name, div->divider_flags, sirfsoc_clk_vbase + div->div_offset,
1604                         div->shift, div->width, 0, div->lock);
1605                 BUG_ON(!clk);
1606                 clk = clk_register_gate(NULL, div->gate_name, div->div_name,
1607                         div->gate_flags, sirfsoc_clk_vbase + div->gate_offset,
1608                                 div->gate_bit, 0, div->lock);
1609                 BUG_ON(!clk);
1610         }
1611         /* ignore selector status register check */
1612         for (i = 0; i < ARRAY_SIZE(mux_list); i++) {
1613                 mux = &mux_list[i];
1614                 clk = clk_register_mux(NULL, mux->mux_name, mux->parent_names,
1615                                mux->parent_num, mux->flags,
1616                                sirfsoc_clk_vbase + mux->mux_offset,
1617                                mux->shift, mux->width,
1618                                mux->mux_flags, NULL);
1619                 atlas7_clks[ARRAY_SIZE(unit_list) + i] = clk;
1620                 BUG_ON(!clk);
1621         }
1622
1623         for (i = 0; i < ARRAY_SIZE(unit_list); i++) {
1624                 unit = &unit_list[i];
1625                 atlas7_clks[i] = atlas7_unit_clk_register(NULL, unit->unit_name, unit->parent_name,
1626                                 unit->flags, unit->regofs, unit->bit, unit->lock);
1627                 BUG_ON(!atlas7_clks[i]);
1628         }
1629
1630         clk_data.clks = atlas7_clks;
1631         clk_data.clk_num = ARRAY_SIZE(unit_list) + ARRAY_SIZE(mux_list);
1632
1633         ret = of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
1634         BUG_ON(ret);
1635
1636         atlas7_rst_ctlr.of_node = np;
1637         atlas7_rst_ctlr.nr_resets = ARRAY_SIZE(atlas7_reset_unit);
1638         reset_controller_register(&atlas7_rst_ctlr);
1639 }
1640 CLK_OF_DECLARE(atlas7_clk, "sirf,atlas7-car", atlas7_clk_init);