2 * Copyright 2011-2012 Calxeda, Inc.
3 * Copyright (C) 2012-2013 Altera Corporation <www.altera.com>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * Based from clk-highbank.c
18 #include <linux/clk.h>
19 #include <linux/clkdev.h>
20 #include <linux/clk-provider.h>
22 #include <linux/mfd/syscon.h>
24 #include <linux/regmap.h>
28 #define SOCFPGA_L4_MP_CLK "l4_mp_clk"
29 #define SOCFPGA_L4_SP_CLK "l4_sp_clk"
30 #define SOCFPGA_NAND_CLK "nand_clk"
31 #define SOCFPGA_NAND_X_CLK "nand_x_clk"
32 #define SOCFPGA_MMC_CLK "sdmmc_clk"
33 #define SOCFPGA_GPIO_DB_CLK_OFFSET 0xA8
35 #define streq(a, b) (strcmp((a), (b)) == 0)
37 #define to_socfpga_gate_clk(p) container_of(p, struct socfpga_gate_clk, hw.hw)
39 /* SDMMC Group for System Manager defines */
40 #define SYSMGR_SDMMCGRP_CTRL_OFFSET 0x108
41 #define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel) \
42 ((((smplsel) & 0x7) << 3) | (((drvsel) & 0x7) << 0))
44 static u8 socfpga_clk_get_parent(struct clk_hw *hwclk)
49 if (streq(hwclk->init->name, SOCFPGA_L4_MP_CLK)) {
50 l4_src = readl(clk_mgr_base_addr + CLKMGR_L4SRC);
53 if (streq(hwclk->init->name, SOCFPGA_L4_SP_CLK)) {
54 l4_src = readl(clk_mgr_base_addr + CLKMGR_L4SRC);
55 return !!(l4_src & 2);
58 perpll_src = readl(clk_mgr_base_addr + CLKMGR_PERPLL_SRC);
59 if (streq(hwclk->init->name, SOCFPGA_MMC_CLK))
60 return perpll_src &= 0x3;
61 if (streq(hwclk->init->name, SOCFPGA_NAND_CLK) ||
62 streq(hwclk->init->name, SOCFPGA_NAND_X_CLK))
63 return (perpll_src >> 2) & 3;
66 return (perpll_src >> 4) & 3;
70 static int socfpga_clk_set_parent(struct clk_hw *hwclk, u8 parent)
74 if (streq(hwclk->init->name, SOCFPGA_L4_MP_CLK)) {
75 src_reg = readl(clk_mgr_base_addr + CLKMGR_L4SRC);
78 writel(src_reg, clk_mgr_base_addr + CLKMGR_L4SRC);
79 } else if (streq(hwclk->init->name, SOCFPGA_L4_SP_CLK)) {
80 src_reg = readl(clk_mgr_base_addr + CLKMGR_L4SRC);
82 src_reg |= (parent << 1);
83 writel(src_reg, clk_mgr_base_addr + CLKMGR_L4SRC);
85 src_reg = readl(clk_mgr_base_addr + CLKMGR_PERPLL_SRC);
86 if (streq(hwclk->init->name, SOCFPGA_MMC_CLK)) {
89 } else if (streq(hwclk->init->name, SOCFPGA_NAND_CLK) ||
90 streq(hwclk->init->name, SOCFPGA_NAND_X_CLK)) {
92 src_reg |= (parent << 2);
93 } else {/* QSPI clock */
95 src_reg |= (parent << 4);
97 writel(src_reg, clk_mgr_base_addr + CLKMGR_PERPLL_SRC);
103 static unsigned long socfpga_clk_recalc_rate(struct clk_hw *hwclk,
104 unsigned long parent_rate)
106 struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk);
109 if (socfpgaclk->fixed_div)
110 div = socfpgaclk->fixed_div;
111 else if (socfpgaclk->div_reg) {
112 val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift;
113 val &= div_mask(socfpgaclk->width);
114 /* Check for GPIO_DB_CLK by its offset */
115 if ((int) socfpgaclk->div_reg & SOCFPGA_GPIO_DB_CLK_OFFSET)
121 return parent_rate / div;
124 static int socfpga_clk_prepare(struct clk_hw *hwclk)
126 struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk);
127 struct regmap *sys_mgr_base_addr;
132 if (socfpgaclk->clk_phase[0] || socfpgaclk->clk_phase[1]) {
133 sys_mgr_base_addr = syscon_regmap_lookup_by_compatible("altr,sys-mgr");
134 if (IS_ERR(sys_mgr_base_addr)) {
135 pr_err("%s: failed to find altr,sys-mgr regmap!\n", __func__);
139 for (i = 0; i < 2; i++) {
140 switch (socfpgaclk->clk_phase[i]) {
170 hs_timing = SYSMGR_SDMMC_CTRL_SET(clk_phase[0], clk_phase[1]);
171 regmap_write(sys_mgr_base_addr, SYSMGR_SDMMCGRP_CTRL_OFFSET,
177 static struct clk_ops gateclk_ops = {
178 .prepare = socfpga_clk_prepare,
179 .recalc_rate = socfpga_clk_recalc_rate,
180 .get_parent = socfpga_clk_get_parent,
181 .set_parent = socfpga_clk_set_parent,
184 static void __init __socfpga_gate_init(struct device_node *node,
185 const struct clk_ops *ops)
192 struct socfpga_gate_clk *socfpga_clk;
193 const char *clk_name = node->name;
194 const char *parent_name[SOCFPGA_MAX_PARENTS];
195 struct clk_init_data init;
199 socfpga_clk = kzalloc(sizeof(*socfpga_clk), GFP_KERNEL);
200 if (WARN_ON(!socfpga_clk))
203 rc = of_property_read_u32_array(node, "clk-gate", clk_gate, 2);
208 socfpga_clk->hw.reg = clk_mgr_base_addr + clk_gate[0];
209 socfpga_clk->hw.bit_idx = clk_gate[1];
211 gateclk_ops.enable = clk_gate_ops.enable;
212 gateclk_ops.disable = clk_gate_ops.disable;
215 rc = of_property_read_u32(node, "fixed-divider", &fixed_div);
217 socfpga_clk->fixed_div = 0;
219 socfpga_clk->fixed_div = fixed_div;
221 rc = of_property_read_u32_array(node, "div-reg", div_reg, 3);
223 socfpga_clk->div_reg = clk_mgr_base_addr + div_reg[0];
224 socfpga_clk->shift = div_reg[1];
225 socfpga_clk->width = div_reg[2];
227 socfpga_clk->div_reg = 0;
230 rc = of_property_read_u32_array(node, "clk-phase", clk_phase, 2);
232 socfpga_clk->clk_phase[0] = clk_phase[0];
233 socfpga_clk->clk_phase[1] = clk_phase[1];
236 of_property_read_string(node, "clock-output-names", &clk_name);
238 init.name = clk_name;
241 while (i < SOCFPGA_MAX_PARENTS && (parent_name[i] =
242 of_clk_get_parent_name(node, i)) != NULL)
245 init.parent_names = parent_name;
246 init.num_parents = i;
247 socfpga_clk->hw.hw.init = &init;
249 clk = clk_register(NULL, &socfpga_clk->hw.hw);
250 if (WARN_ON(IS_ERR(clk))) {
254 rc = of_clk_add_provider(node, of_clk_src_simple_get, clk);
259 void __init socfpga_gate_init(struct device_node *node)
261 __socfpga_gate_init(node, &gateclk_ops);