4 * Copyright (C) ST-Microelectronics SA 2013
5 * Author: Maxime Coquelin <maxime.coquelin@st.com> for ST-Microelectronics.
6 * License terms: GNU General Public License (GPL), version 2 */
8 #include <linux/clk-provider.h>
9 #include <linux/module.h>
10 #include <linux/slab.h>
12 #include <linux/err.h>
13 #include <linux/string.h>
15 #include <linux/of_address.h>
22 /* Pre-divisor's gate */
23 struct clk_gate pgate;
25 struct clk_divider pdiv;
26 /* Final divisor's gate */
27 struct clk_gate fgate;
29 struct clk_divider fdiv;
32 #define to_flexgen(_hw) container_of(_hw, struct flexgen, hw)
34 static int flexgen_enable(struct clk_hw *hw)
36 struct flexgen *flexgen = to_flexgen(hw);
37 struct clk_hw *pgate_hw = &flexgen->pgate.hw;
38 struct clk_hw *fgate_hw = &flexgen->fgate.hw;
40 __clk_hw_set_clk(pgate_hw, hw);
41 __clk_hw_set_clk(fgate_hw, hw);
43 clk_gate_ops.enable(pgate_hw);
45 clk_gate_ops.enable(fgate_hw);
47 pr_debug("%s: flexgen output enabled\n", __clk_get_name(hw->clk));
51 static void flexgen_disable(struct clk_hw *hw)
53 struct flexgen *flexgen = to_flexgen(hw);
54 struct clk_hw *fgate_hw = &flexgen->fgate.hw;
56 /* disable only the final gate */
57 __clk_hw_set_clk(fgate_hw, hw);
59 clk_gate_ops.disable(fgate_hw);
61 pr_debug("%s: flexgen output disabled\n", __clk_get_name(hw->clk));
64 static int flexgen_is_enabled(struct clk_hw *hw)
66 struct flexgen *flexgen = to_flexgen(hw);
67 struct clk_hw *fgate_hw = &flexgen->fgate.hw;
69 __clk_hw_set_clk(fgate_hw, hw);
71 if (!clk_gate_ops.is_enabled(fgate_hw))
77 static u8 flexgen_get_parent(struct clk_hw *hw)
79 struct flexgen *flexgen = to_flexgen(hw);
80 struct clk_hw *mux_hw = &flexgen->mux.hw;
82 __clk_hw_set_clk(mux_hw, hw);
84 return clk_mux_ops.get_parent(mux_hw);
87 static int flexgen_set_parent(struct clk_hw *hw, u8 index)
89 struct flexgen *flexgen = to_flexgen(hw);
90 struct clk_hw *mux_hw = &flexgen->mux.hw;
92 __clk_hw_set_clk(mux_hw, hw);
94 return clk_mux_ops.set_parent(mux_hw, index);
97 static inline unsigned long
98 clk_best_div(unsigned long parent_rate, unsigned long rate)
100 return parent_rate / rate + ((rate > (2*(parent_rate % rate))) ? 0 : 1);
103 static long flexgen_round_rate(struct clk_hw *hw, unsigned long rate,
104 unsigned long *prate)
108 /* Round div according to exact prate and wished rate */
109 div = clk_best_div(*prate, rate);
111 if (__clk_get_flags(hw->clk) & CLK_SET_RATE_PARENT) {
119 unsigned long flexgen_recalc_rate(struct clk_hw *hw,
120 unsigned long parent_rate)
122 struct flexgen *flexgen = to_flexgen(hw);
123 struct clk_hw *pdiv_hw = &flexgen->pdiv.hw;
124 struct clk_hw *fdiv_hw = &flexgen->fdiv.hw;
125 unsigned long mid_rate;
127 __clk_hw_set_clk(pdiv_hw, hw);
128 __clk_hw_set_clk(fdiv_hw, hw);
130 mid_rate = clk_divider_ops.recalc_rate(pdiv_hw, parent_rate);
132 return clk_divider_ops.recalc_rate(fdiv_hw, mid_rate);
135 static int flexgen_set_rate(struct clk_hw *hw, unsigned long rate,
136 unsigned long parent_rate)
138 struct flexgen *flexgen = to_flexgen(hw);
139 struct clk_hw *pdiv_hw = &flexgen->pdiv.hw;
140 struct clk_hw *fdiv_hw = &flexgen->fdiv.hw;
141 unsigned long div = 0;
144 __clk_hw_set_clk(pdiv_hw, hw);
145 __clk_hw_set_clk(fdiv_hw, hw);
147 div = clk_best_div(parent_rate, rate);
150 * pdiv is mainly targeted for low freq results, while fdiv
151 * should be used for div <= 64. The other way round can
152 * lead to 'duty cycle' issues.
156 clk_divider_ops.set_rate(pdiv_hw, parent_rate, parent_rate);
157 ret = clk_divider_ops.set_rate(fdiv_hw, rate, rate * div);
159 clk_divider_ops.set_rate(fdiv_hw, parent_rate, parent_rate);
160 ret = clk_divider_ops.set_rate(pdiv_hw, rate, rate * div);
166 static const struct clk_ops flexgen_ops = {
167 .enable = flexgen_enable,
168 .disable = flexgen_disable,
169 .is_enabled = flexgen_is_enabled,
170 .get_parent = flexgen_get_parent,
171 .set_parent = flexgen_set_parent,
172 .round_rate = flexgen_round_rate,
173 .recalc_rate = flexgen_recalc_rate,
174 .set_rate = flexgen_set_rate,
177 struct clk *clk_register_flexgen(const char *name,
178 const char **parent_names, u8 num_parents,
179 void __iomem *reg, spinlock_t *lock, u32 idx,
180 unsigned long flexgen_flags) {
181 struct flexgen *fgxbar;
183 struct clk_init_data init;
185 void __iomem *xbar_reg, *fdiv_reg;
187 fgxbar = kzalloc(sizeof(struct flexgen), GFP_KERNEL);
189 return ERR_PTR(-ENOMEM);
192 init.ops = &flexgen_ops;
193 init.flags = CLK_IS_BASIC | flexgen_flags;
194 init.parent_names = parent_names;
195 init.num_parents = num_parents;
197 xbar_reg = reg + 0x18 + (idx & ~0x3);
198 xbar_shift = (idx % 4) * 0x8;
199 fdiv_reg = reg + 0x164 + idx * 4;
201 /* Crossbar element config */
202 fgxbar->mux.lock = lock;
203 fgxbar->mux.mask = BIT(6) - 1;
204 fgxbar->mux.reg = xbar_reg;
205 fgxbar->mux.shift = xbar_shift;
206 fgxbar->mux.table = NULL;
209 /* Pre-divider's gate config (in xbar register)*/
210 fgxbar->pgate.lock = lock;
211 fgxbar->pgate.reg = xbar_reg;
212 fgxbar->pgate.bit_idx = xbar_shift + 6;
214 /* Pre-divider config */
215 fgxbar->pdiv.lock = lock;
216 fgxbar->pdiv.reg = reg + 0x58 + idx * 4;
217 fgxbar->pdiv.width = 10;
219 /* Final divider's gate config */
220 fgxbar->fgate.lock = lock;
221 fgxbar->fgate.reg = fdiv_reg;
222 fgxbar->fgate.bit_idx = 6;
224 /* Final divider config */
225 fgxbar->fdiv.lock = lock;
226 fgxbar->fdiv.reg = fdiv_reg;
227 fgxbar->fdiv.width = 6;
229 fgxbar->hw.init = &init;
231 clk = clk_register(NULL, &fgxbar->hw);
235 pr_debug("%s: parent %s rate %u\n",
237 __clk_get_name(clk_get_parent(clk)),
238 (unsigned int)clk_get_rate(clk));
242 static const char ** __init flexgen_get_parents(struct device_node *np,
245 const char **parents;
248 nparents = of_count_phandle_with_args(np, "clocks", "#clock-cells");
249 if (WARN_ON(nparents <= 0))
252 parents = kcalloc(nparents, sizeof(const char *), GFP_KERNEL);
256 for (i = 0; i < nparents; i++)
257 parents[i] = of_clk_get_parent_name(np, i);
259 *num_parents = nparents;
263 void __init st_of_flexgen_setup(struct device_node *np)
265 struct device_node *pnode;
267 struct clk_onecell_data *clk_data;
268 const char **parents;
270 spinlock_t *rlock = NULL;
271 unsigned long flex_flags = 0;
273 pnode = of_get_parent(np);
277 reg = of_iomap(pnode, 0);
281 parents = flexgen_get_parents(np, &num_parents);
285 clk_data = kzalloc(sizeof(*clk_data), GFP_KERNEL);
289 clk_data->clk_num = of_property_count_strings(np ,
290 "clock-output-names");
291 if (clk_data->clk_num <= 0) {
292 pr_err("%s: Failed to get number of output clocks (%d)",
293 __func__, clk_data->clk_num);
297 clk_data->clks = kcalloc(clk_data->clk_num, sizeof(struct clk *),
302 rlock = kzalloc(sizeof(spinlock_t), GFP_KERNEL);
306 for (i = 0; i < clk_data->clk_num; i++) {
308 const char *clk_name;
310 if (of_property_read_string_index(np, "clock-output-names",
316 * If we read an empty clock name then the output is unused
318 if (*clk_name == '\0')
321 clk = clk_register_flexgen(clk_name, parents, num_parents,
322 reg, rlock, i, flex_flags);
327 clk_data->clks[i] = clk;
331 of_clk_add_provider(np, of_clk_src_onecell_get, clk_data);
337 kfree(clk_data->clks);
342 CLK_OF_DECLARE(flexgen, "st,flexgen", st_of_flexgen_setup);