2 * Copyright (C) 2014 STMicroelectronics (R&D) Limited
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
13 * Stephen Gallimore <stephen.gallimore@st.com>,
14 * Pankaj Dev <pankaj.dev@st.com>.
17 #include <linux/slab.h>
18 #include <linux/of_address.h>
19 #include <linux/clk.h>
20 #include <linux/clk-provider.h>
24 static DEFINE_SPINLOCK(clkgena_c32_odf_lock);
27 * Common PLL configuration register bits for PLL800 and PLL1600 C65
29 #define C65_MDIV_PLL800_MASK (0xff)
30 #define C65_MDIV_PLL1600_MASK (0x7)
31 #define C65_NDIV_MASK (0xff)
32 #define C65_PDIV_MASK (0x7)
35 * PLL configuration register bits for PLL3200 C32
37 #define C32_NDIV_MASK (0xff)
38 #define C32_IDF_MASK (0x7)
39 #define C32_ODF_MASK (0x3f)
40 #define C32_LDF_MASK (0x7f)
42 #define C32_MAX_ODFS (4)
44 struct clkgen_pll_data {
45 struct clkgen_field pdn_status;
46 struct clkgen_field locked_status;
47 struct clkgen_field mdiv;
48 struct clkgen_field ndiv;
49 struct clkgen_field pdiv;
50 struct clkgen_field idf;
51 struct clkgen_field ldf;
52 unsigned int num_odfs;
53 struct clkgen_field odf[C32_MAX_ODFS];
54 struct clkgen_field odf_gate[C32_MAX_ODFS];
55 const struct clk_ops *ops;
58 static const struct clk_ops st_pll1600c65_ops;
59 static const struct clk_ops st_pll800c65_ops;
60 static const struct clk_ops stm_pll3200c32_ops;
61 static const struct clk_ops st_pll1200c32_ops;
63 static const struct clkgen_pll_data st_pll1600c65_ax = {
64 .pdn_status = CLKGEN_FIELD(0x0, 0x1, 19),
65 .locked_status = CLKGEN_FIELD(0x0, 0x1, 31),
66 .mdiv = CLKGEN_FIELD(0x0, C65_MDIV_PLL1600_MASK, 0),
67 .ndiv = CLKGEN_FIELD(0x0, C65_NDIV_MASK, 8),
68 .ops = &st_pll1600c65_ops
71 static const struct clkgen_pll_data st_pll800c65_ax = {
72 .pdn_status = CLKGEN_FIELD(0x0, 0x1, 19),
73 .locked_status = CLKGEN_FIELD(0x0, 0x1, 31),
74 .mdiv = CLKGEN_FIELD(0x0, C65_MDIV_PLL800_MASK, 0),
75 .ndiv = CLKGEN_FIELD(0x0, C65_NDIV_MASK, 8),
76 .pdiv = CLKGEN_FIELD(0x0, C65_PDIV_MASK, 16),
77 .ops = &st_pll800c65_ops
80 static const struct clkgen_pll_data st_pll3200c32_a1x_0 = {
81 .pdn_status = CLKGEN_FIELD(0x0, 0x1, 31),
82 .locked_status = CLKGEN_FIELD(0x4, 0x1, 31),
83 .ndiv = CLKGEN_FIELD(0x0, C32_NDIV_MASK, 0x0),
84 .idf = CLKGEN_FIELD(0x4, C32_IDF_MASK, 0x0),
86 .odf = { CLKGEN_FIELD(0x54, C32_ODF_MASK, 4),
87 CLKGEN_FIELD(0x54, C32_ODF_MASK, 10),
88 CLKGEN_FIELD(0x54, C32_ODF_MASK, 16),
89 CLKGEN_FIELD(0x54, C32_ODF_MASK, 22) },
90 .odf_gate = { CLKGEN_FIELD(0x54, 0x1, 0),
91 CLKGEN_FIELD(0x54, 0x1, 1),
92 CLKGEN_FIELD(0x54, 0x1, 2),
93 CLKGEN_FIELD(0x54, 0x1, 3) },
94 .ops = &stm_pll3200c32_ops,
97 static const struct clkgen_pll_data st_pll3200c32_a1x_1 = {
98 .pdn_status = CLKGEN_FIELD(0xC, 0x1, 31),
99 .locked_status = CLKGEN_FIELD(0x10, 0x1, 31),
100 .ndiv = CLKGEN_FIELD(0xC, C32_NDIV_MASK, 0x0),
101 .idf = CLKGEN_FIELD(0x10, C32_IDF_MASK, 0x0),
103 .odf = { CLKGEN_FIELD(0x58, C32_ODF_MASK, 4),
104 CLKGEN_FIELD(0x58, C32_ODF_MASK, 10),
105 CLKGEN_FIELD(0x58, C32_ODF_MASK, 16),
106 CLKGEN_FIELD(0x58, C32_ODF_MASK, 22) },
107 .odf_gate = { CLKGEN_FIELD(0x58, 0x1, 0),
108 CLKGEN_FIELD(0x58, 0x1, 1),
109 CLKGEN_FIELD(0x58, 0x1, 2),
110 CLKGEN_FIELD(0x58, 0x1, 3) },
111 .ops = &stm_pll3200c32_ops,
115 static const struct clkgen_pll_data st_pll3200c32_a9_415 = {
116 .pdn_status = CLKGEN_FIELD(0x0, 0x1, 0),
117 .locked_status = CLKGEN_FIELD(0x6C, 0x1, 0),
118 .ndiv = CLKGEN_FIELD(0x0, C32_NDIV_MASK, 9),
119 .idf = CLKGEN_FIELD(0x0, C32_IDF_MASK, 22),
121 .odf = { CLKGEN_FIELD(0x0, C32_ODF_MASK, 3) },
122 .odf_gate = { CLKGEN_FIELD(0x0, 0x1, 28) },
123 .ops = &stm_pll3200c32_ops,
126 static const struct clkgen_pll_data st_pll3200c32_ddr_415 = {
127 .pdn_status = CLKGEN_FIELD(0x0, 0x1, 0),
128 .locked_status = CLKGEN_FIELD(0x100, 0x1, 0),
129 .ndiv = CLKGEN_FIELD(0x8, C32_NDIV_MASK, 0),
130 .idf = CLKGEN_FIELD(0x0, C32_IDF_MASK, 25),
132 .odf = { CLKGEN_FIELD(0x8, C32_ODF_MASK, 8),
133 CLKGEN_FIELD(0x8, C32_ODF_MASK, 14) },
134 .odf_gate = { CLKGEN_FIELD(0x4, 0x1, 28),
135 CLKGEN_FIELD(0x4, 0x1, 29) },
136 .ops = &stm_pll3200c32_ops,
139 static const struct clkgen_pll_data st_pll1200c32_gpu_415 = {
140 .pdn_status = CLKGEN_FIELD(0x144, 0x1, 3),
141 .locked_status = CLKGEN_FIELD(0x168, 0x1, 0),
142 .ldf = CLKGEN_FIELD(0x0, C32_LDF_MASK, 3),
143 .idf = CLKGEN_FIELD(0x0, C32_IDF_MASK, 0),
145 .odf = { CLKGEN_FIELD(0x0, C32_ODF_MASK, 10) },
146 .ops = &st_pll1200c32_ops,
150 static const struct clkgen_pll_data st_pll3200c32_a9_416 = {
151 .pdn_status = CLKGEN_FIELD(0x0, 0x1, 0),
152 .locked_status = CLKGEN_FIELD(0x6C, 0x1, 0),
153 .ndiv = CLKGEN_FIELD(0x8, C32_NDIV_MASK, 0),
154 .idf = CLKGEN_FIELD(0x0, C32_IDF_MASK, 25),
156 .odf = { CLKGEN_FIELD(0x8, C32_ODF_MASK, 8) },
157 .odf_gate = { CLKGEN_FIELD(0x4, 0x1, 28) },
158 .ops = &stm_pll3200c32_ops,
161 static const struct clkgen_pll_data st_pll3200c32_ddr_416 = {
162 .pdn_status = CLKGEN_FIELD(0x0, 0x1, 0),
163 .locked_status = CLKGEN_FIELD(0x10C, 0x1, 0),
164 .ndiv = CLKGEN_FIELD(0x8, C32_NDIV_MASK, 0),
165 .idf = CLKGEN_FIELD(0x0, C32_IDF_MASK, 25),
167 .odf = { CLKGEN_FIELD(0x8, C32_ODF_MASK, 8),
168 CLKGEN_FIELD(0x8, C32_ODF_MASK, 14) },
169 .odf_gate = { CLKGEN_FIELD(0x4, 0x1, 28),
170 CLKGEN_FIELD(0x4, 0x1, 29) },
171 .ops = &stm_pll3200c32_ops,
174 static const struct clkgen_pll_data st_pll1200c32_gpu_416 = {
175 .pdn_status = CLKGEN_FIELD(0x8E4, 0x1, 3),
176 .locked_status = CLKGEN_FIELD(0x90C, 0x1, 0),
177 .ldf = CLKGEN_FIELD(0x0, C32_LDF_MASK, 3),
178 .idf = CLKGEN_FIELD(0x0, C32_IDF_MASK, 0),
180 .odf = { CLKGEN_FIELD(0x0, C32_ODF_MASK, 10) },
181 .ops = &st_pll1200c32_ops,
184 static const struct clkgen_pll_data st_pll3200c32_407_a0 = {
186 .pdn_status = CLKGEN_FIELD(0x2a0, 0x1, 8),
187 .locked_status = CLKGEN_FIELD(0x2a0, 0x1, 24),
188 .ndiv = CLKGEN_FIELD(0x2a4, C32_NDIV_MASK, 16),
189 .idf = CLKGEN_FIELD(0x2a4, C32_IDF_MASK, 0x0),
191 .odf = { CLKGEN_FIELD(0x2b4, C32_ODF_MASK, 0) },
192 .odf_gate = { CLKGEN_FIELD(0x2b4, 0x1, 6) },
193 .ops = &stm_pll3200c32_ops,
196 static const struct clkgen_pll_data st_pll3200c32_cx_0 = {
198 .pdn_status = CLKGEN_FIELD(0x2a0, 0x1, 8),
199 .locked_status = CLKGEN_FIELD(0x2a0, 0x1, 24),
200 .ndiv = CLKGEN_FIELD(0x2a4, C32_NDIV_MASK, 16),
201 .idf = CLKGEN_FIELD(0x2a4, C32_IDF_MASK, 0x0),
203 .odf = { CLKGEN_FIELD(0x2b4, C32_ODF_MASK, 0) },
204 .odf_gate = { CLKGEN_FIELD(0x2b4, 0x1, 6) },
205 .ops = &stm_pll3200c32_ops,
208 static const struct clkgen_pll_data st_pll3200c32_cx_1 = {
210 .pdn_status = CLKGEN_FIELD(0x2c8, 0x1, 8),
211 .locked_status = CLKGEN_FIELD(0x2c8, 0x1, 24),
212 .ndiv = CLKGEN_FIELD(0x2cc, C32_NDIV_MASK, 16),
213 .idf = CLKGEN_FIELD(0x2cc, C32_IDF_MASK, 0x0),
215 .odf = { CLKGEN_FIELD(0x2dc, C32_ODF_MASK, 0) },
216 .odf_gate = { CLKGEN_FIELD(0x2dc, 0x1, 6) },
217 .ops = &stm_pll3200c32_ops,
220 static const struct clkgen_pll_data st_pll3200c32_407_a9 = {
222 .pdn_status = CLKGEN_FIELD(0x1a8, 0x1, 0),
223 .locked_status = CLKGEN_FIELD(0x87c, 0x1, 0),
224 .ndiv = CLKGEN_FIELD(0x1b0, C32_NDIV_MASK, 0),
225 .idf = CLKGEN_FIELD(0x1a8, C32_IDF_MASK, 25),
227 .odf = { CLKGEN_FIELD(0x1b0, C32_ODF_MASK, 8) },
228 .odf_gate = { CLKGEN_FIELD(0x1ac, 0x1, 28) },
229 .ops = &stm_pll3200c32_ops,
233 * DOC: Clock Generated by PLL, rate set and enabled by bootloader
235 * Traits of this clock:
236 * prepare - clk_(un)prepare only ensures parent is (un)prepared
237 * enable - clk_enable/disable only ensures parent is enabled
238 * rate - rate is fixed. No clk_set_rate support
239 * parent - fixed parent. No clk_set_parent support
243 * PLL clock that is integrated in the ClockGenA instances on the STiH415
246 * @hw: handle between common and hardware-specific interfaces.
247 * @type: PLL instance type.
248 * @regs_base: base of the PLL configuration register(s).
253 struct clkgen_pll_data *data;
254 void __iomem *regs_base;
257 #define to_clkgen_pll(_hw) container_of(_hw, struct clkgen_pll, hw)
259 static int clkgen_pll_is_locked(struct clk_hw *hw)
261 struct clkgen_pll *pll = to_clkgen_pll(hw);
262 u32 locked = CLKGEN_READ(pll, locked_status);
267 static int clkgen_pll_is_enabled(struct clk_hw *hw)
269 struct clkgen_pll *pll = to_clkgen_pll(hw);
270 u32 poweroff = CLKGEN_READ(pll, pdn_status);
274 static unsigned long recalc_stm_pll800c65(struct clk_hw *hw,
275 unsigned long parent_rate)
277 struct clkgen_pll *pll = to_clkgen_pll(hw);
278 unsigned long mdiv, ndiv, pdiv;
282 if (!clkgen_pll_is_enabled(hw) || !clkgen_pll_is_locked(hw))
285 pdiv = CLKGEN_READ(pll, pdiv);
286 mdiv = CLKGEN_READ(pll, mdiv);
287 ndiv = CLKGEN_READ(pll, ndiv);
290 mdiv++; /* mdiv=0 or 1 => MDIV=1 */
292 res = (uint64_t)2 * (uint64_t)parent_rate * (uint64_t)ndiv;
293 rate = (unsigned long)div64_u64(res, mdiv * (1 << pdiv));
295 pr_debug("%s:%s rate %lu\n", clk_hw_get_name(hw), __func__, rate);
301 static unsigned long recalc_stm_pll1600c65(struct clk_hw *hw,
302 unsigned long parent_rate)
304 struct clkgen_pll *pll = to_clkgen_pll(hw);
305 unsigned long mdiv, ndiv;
308 if (!clkgen_pll_is_enabled(hw) || !clkgen_pll_is_locked(hw))
311 mdiv = CLKGEN_READ(pll, mdiv);
312 ndiv = CLKGEN_READ(pll, ndiv);
317 /* Note: input is divided by 1000 to avoid overflow */
318 rate = ((2 * (parent_rate / 1000) * ndiv) / mdiv) * 1000;
320 pr_debug("%s:%s rate %lu\n", clk_hw_get_name(hw), __func__, rate);
325 static unsigned long recalc_stm_pll3200c32(struct clk_hw *hw,
326 unsigned long parent_rate)
328 struct clkgen_pll *pll = to_clkgen_pll(hw);
329 unsigned long ndiv, idf;
330 unsigned long rate = 0;
332 if (!clkgen_pll_is_enabled(hw) || !clkgen_pll_is_locked(hw))
335 ndiv = CLKGEN_READ(pll, ndiv);
336 idf = CLKGEN_READ(pll, idf);
339 /* Note: input is divided to avoid overflow */
340 rate = ((2 * (parent_rate/1000) * ndiv) / idf) * 1000;
342 pr_debug("%s:%s rate %lu\n", clk_hw_get_name(hw), __func__, rate);
347 static unsigned long recalc_stm_pll1200c32(struct clk_hw *hw,
348 unsigned long parent_rate)
350 struct clkgen_pll *pll = to_clkgen_pll(hw);
351 unsigned long odf, ldf, idf;
354 if (!clkgen_pll_is_enabled(hw) || !clkgen_pll_is_locked(hw))
357 odf = CLKGEN_READ(pll, odf[0]);
358 ldf = CLKGEN_READ(pll, ldf);
359 idf = CLKGEN_READ(pll, idf);
361 if (!idf) /* idf==0 means 1 */
363 if (!odf) /* odf==0 means 1 */
366 /* Note: input is divided by 1000 to avoid overflow */
367 rate = (((parent_rate / 1000) * ldf) / (odf * idf)) * 1000;
369 pr_debug("%s:%s rate %lu\n", clk_hw_get_name(hw), __func__, rate);
374 static const struct clk_ops st_pll1600c65_ops = {
375 .is_enabled = clkgen_pll_is_enabled,
376 .recalc_rate = recalc_stm_pll1600c65,
379 static const struct clk_ops st_pll800c65_ops = {
380 .is_enabled = clkgen_pll_is_enabled,
381 .recalc_rate = recalc_stm_pll800c65,
384 static const struct clk_ops stm_pll3200c32_ops = {
385 .is_enabled = clkgen_pll_is_enabled,
386 .recalc_rate = recalc_stm_pll3200c32,
389 static const struct clk_ops st_pll1200c32_ops = {
390 .is_enabled = clkgen_pll_is_enabled,
391 .recalc_rate = recalc_stm_pll1200c32,
394 static struct clk * __init clkgen_pll_register(const char *parent_name,
395 struct clkgen_pll_data *pll_data,
397 const char *clk_name)
399 struct clkgen_pll *pll;
401 struct clk_init_data init;
403 pll = kzalloc(sizeof(*pll), GFP_KERNEL);
405 return ERR_PTR(-ENOMEM);
407 init.name = clk_name;
408 init.ops = pll_data->ops;
410 init.flags = CLK_IS_BASIC | CLK_GET_RATE_NOCACHE;
411 init.parent_names = &parent_name;
412 init.num_parents = 1;
414 pll->data = pll_data;
415 pll->regs_base = reg;
416 pll->hw.init = &init;
418 clk = clk_register(NULL, &pll->hw);
424 pr_debug("%s: parent %s rate %lu\n",
426 __clk_get_name(clk_get_parent(clk)),
432 static struct clk * __init clkgen_c65_lsdiv_register(const char *parent_name,
433 const char *clk_name)
437 clk = clk_register_fixed_factor(NULL, clk_name, parent_name, 0, 1, 2);
441 pr_debug("%s: parent %s rate %lu\n",
443 __clk_get_name(clk_get_parent(clk)),
448 static void __iomem * __init clkgen_get_register_base(
449 struct device_node *np)
451 struct device_node *pnode;
452 void __iomem *reg = NULL;
454 pnode = of_get_parent(np);
458 reg = of_iomap(pnode, 0);
464 #define CLKGENAx_PLL0_OFFSET 0x0
465 #define CLKGENAx_PLL1_OFFSET 0x4
467 static void __init clkgena_c65_pll_setup(struct device_node *np)
469 const int num_pll_outputs = 3;
470 struct clk_onecell_data *clk_data;
471 const char *parent_name;
473 const char *clk_name;
475 parent_name = of_clk_get_parent_name(np, 0);
479 reg = clkgen_get_register_base(np);
483 clk_data = kzalloc(sizeof(*clk_data), GFP_KERNEL);
487 clk_data->clk_num = num_pll_outputs;
488 clk_data->clks = kzalloc(clk_data->clk_num * sizeof(struct clk *),
494 if (of_property_read_string_index(np, "clock-output-names",
499 * PLL0 HS (high speed) output
501 clk_data->clks[0] = clkgen_pll_register(parent_name,
502 (struct clkgen_pll_data *) &st_pll1600c65_ax,
503 reg + CLKGENAx_PLL0_OFFSET, clk_name);
505 if (IS_ERR(clk_data->clks[0]))
508 if (of_property_read_string_index(np, "clock-output-names",
513 * PLL0 LS (low speed) output, which is a fixed divide by 2 of the
516 clk_data->clks[1] = clkgen_c65_lsdiv_register(__clk_get_name
520 if (IS_ERR(clk_data->clks[1]))
523 if (of_property_read_string_index(np, "clock-output-names",
530 clk_data->clks[2] = clkgen_pll_register(parent_name,
531 (struct clkgen_pll_data *) &st_pll800c65_ax,
532 reg + CLKGENAx_PLL1_OFFSET, clk_name);
534 if (IS_ERR(clk_data->clks[2]))
537 of_clk_add_provider(np, of_clk_src_onecell_get, clk_data);
541 kfree(clk_data->clks);
544 CLK_OF_DECLARE(clkgena_c65_plls,
545 "st,clkgena-plls-c65", clkgena_c65_pll_setup);
547 static struct clk * __init clkgen_odf_register(const char *parent_name,
549 struct clkgen_pll_data *pll_data,
551 spinlock_t *odf_lock,
552 const char *odf_name)
556 struct clk_gate *gate;
557 struct clk_divider *div;
559 flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_GATE;
561 gate = kzalloc(sizeof(*gate), GFP_KERNEL);
563 return ERR_PTR(-ENOMEM);
565 gate->flags = CLK_GATE_SET_TO_DISABLE;
566 gate->reg = reg + pll_data->odf_gate[odf].offset;
567 gate->bit_idx = pll_data->odf_gate[odf].shift;
568 gate->lock = odf_lock;
570 div = kzalloc(sizeof(*div), GFP_KERNEL);
573 return ERR_PTR(-ENOMEM);
576 div->flags = CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO;
577 div->reg = reg + pll_data->odf[odf].offset;
578 div->shift = pll_data->odf[odf].shift;
579 div->width = fls(pll_data->odf[odf].mask);
580 div->lock = odf_lock;
582 clk = clk_register_composite(NULL, odf_name, &parent_name, 1,
584 &div->hw, &clk_divider_ops,
585 &gate->hw, &clk_gate_ops,
590 pr_debug("%s: parent %s rate %lu\n",
592 __clk_get_name(clk_get_parent(clk)),
597 static const struct of_device_id c32_pll_of_match[] = {
599 .compatible = "st,plls-c32-a1x-0",
600 .data = &st_pll3200c32_a1x_0,
603 .compatible = "st,plls-c32-a1x-1",
604 .data = &st_pll3200c32_a1x_1,
607 .compatible = "st,stih415-plls-c32-a9",
608 .data = &st_pll3200c32_a9_415,
611 .compatible = "st,stih415-plls-c32-ddr",
612 .data = &st_pll3200c32_ddr_415,
615 .compatible = "st,stih416-plls-c32-a9",
616 .data = &st_pll3200c32_a9_416,
619 .compatible = "st,stih416-plls-c32-ddr",
620 .data = &st_pll3200c32_ddr_416,
623 .compatible = "st,stih407-plls-c32-a0",
624 .data = &st_pll3200c32_407_a0,
627 .compatible = "st,plls-c32-cx_0",
628 .data = &st_pll3200c32_cx_0,
631 .compatible = "st,plls-c32-cx_1",
632 .data = &st_pll3200c32_cx_1,
635 .compatible = "st,stih407-plls-c32-a9",
636 .data = &st_pll3200c32_407_a9,
641 static void __init clkgen_c32_pll_setup(struct device_node *np)
643 const struct of_device_id *match;
645 const char *parent_name, *pll_name;
646 void __iomem *pll_base;
648 struct clk_onecell_data *clk_data;
649 struct clkgen_pll_data *data;
651 match = of_match_node(c32_pll_of_match, np);
653 pr_err("%s: No matching data\n", __func__);
657 data = (struct clkgen_pll_data *) match->data;
659 parent_name = of_clk_get_parent_name(np, 0);
663 pll_base = clkgen_get_register_base(np);
667 clk = clkgen_pll_register(parent_name, data, pll_base, np->name);
671 pll_name = __clk_get_name(clk);
673 num_odfs = data->num_odfs;
675 clk_data = kzalloc(sizeof(*clk_data), GFP_KERNEL);
679 clk_data->clk_num = num_odfs;
680 clk_data->clks = kzalloc(clk_data->clk_num * sizeof(struct clk *),
686 for (odf = 0; odf < num_odfs; odf++) {
688 const char *clk_name;
690 if (of_property_read_string_index(np, "clock-output-names",
694 clk = clkgen_odf_register(pll_name, pll_base, data,
695 odf, &clkgena_c32_odf_lock, clk_name);
699 clk_data->clks[odf] = clk;
702 of_clk_add_provider(np, of_clk_src_onecell_get, clk_data);
707 kfree(clk_data->clks);
710 CLK_OF_DECLARE(clkgen_c32_pll, "st,clkgen-plls-c32", clkgen_c32_pll_setup);
712 static const struct of_device_id c32_gpu_pll_of_match[] = {
714 .compatible = "st,stih415-gpu-pll-c32",
715 .data = &st_pll1200c32_gpu_415,
718 .compatible = "st,stih416-gpu-pll-c32",
719 .data = &st_pll1200c32_gpu_416,
724 static void __init clkgengpu_c32_pll_setup(struct device_node *np)
726 const struct of_device_id *match;
728 const char *parent_name;
730 const char *clk_name;
731 struct clkgen_pll_data *data;
733 match = of_match_node(c32_gpu_pll_of_match, np);
735 pr_err("%s: No matching data\n", __func__);
739 data = (struct clkgen_pll_data *)match->data;
741 parent_name = of_clk_get_parent_name(np, 0);
745 reg = clkgen_get_register_base(np);
749 if (of_property_read_string_index(np, "clock-output-names",
756 clk = clkgen_pll_register(parent_name, data, reg, clk_name);
759 of_clk_add_provider(np, of_clk_src_simple_get, clk);
763 CLK_OF_DECLARE(clkgengpu_c32_pll,
764 "st,clkgengpu-pll-c32", clkgengpu_c32_pll_setup);