2 * Copyright 2013 Emilio López
4 * Emilio López <emilio@elopez.com.ar>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
17 #include <linux/clk-provider.h>
18 #include <linux/clkdev.h>
19 #include <linux/of_address.h>
21 #include "clk-factors.h"
24 * sun4i_get_mod0_factors() - calculates m, n factors for MOD0-style clocks
25 * MOD0 rate is calculated as follows
26 * rate = (parent_rate >> p) / (m + 1);
29 static void sun4i_a10_get_mod0_factors(u32 *freq, u32 parent_rate,
30 u8 *n, u8 *k, u8 *m, u8 *p)
34 /* These clocks can only divide, so we will never be able to achieve
35 * frequencies higher than the parent frequency */
36 if (*freq > parent_rate)
39 div = DIV_ROUND_UP(parent_rate, *freq);
43 else if (div / 2 < 16)
45 else if (div / 4 < 16)
50 calcm = DIV_ROUND_UP(div, 1 << calcp);
52 *freq = (parent_rate >> calcp) / calcm;
54 /* we were called to round the frequency, we can now return */
62 /* user manual says "n" but it's really "p" */
63 static struct clk_factors_config sun4i_a10_mod0_config = {
70 static const struct factors_data sun4i_a10_mod0_data __initconst = {
73 .muxmask = BIT(1) | BIT(0),
74 .table = &sun4i_a10_mod0_config,
75 .getter = sun4i_a10_get_mod0_factors,
78 static DEFINE_SPINLOCK(sun4i_a10_mod0_lock);
80 static void __init sun4i_a10_mod0_setup(struct device_node *node)
82 sunxi_factors_register(node, &sun4i_a10_mod0_data, &sun4i_a10_mod0_lock);
84 CLK_OF_DECLARE(sun4i_a10_mod0, "allwinner,sun4i-a10-mod0-clk", sun4i_a10_mod0_setup);
86 static DEFINE_SPINLOCK(sun5i_a13_mbus_lock);
88 static void __init sun5i_a13_mbus_setup(struct device_node *node)
90 struct clk *mbus = sunxi_factors_register(node, &sun4i_a10_mod0_data, &sun5i_a13_mbus_lock);
92 /* The MBUS clocks needs to be always enabled */
94 clk_prepare_enable(mbus);
96 CLK_OF_DECLARE(sun5i_a13_mbus, "allwinner,sun5i-a13-mbus-clk", sun5i_a13_mbus_setup);
98 struct mmc_phase_data {
105 struct mmc_phase_data *data;
109 #define to_mmc_phase(_hw) container_of(_hw, struct mmc_phase, hw)
111 static int mmc_get_phase(struct clk_hw *hw)
113 struct clk *mmc, *mmc_parent, *clk = hw->clk;
114 struct mmc_phase *phase = to_mmc_phase(hw);
115 unsigned int mmc_rate, mmc_parent_rate;
120 value = readl(phase->reg);
121 delay = (value >> phase->data->offset) & 0x3;
126 /* Get the main MMC clock */
127 mmc = clk_get_parent(clk);
132 mmc_rate = clk_get_rate(mmc);
136 /* Now, get the MMC parent (most likely some PLL) */
137 mmc_parent = clk_get_parent(mmc);
142 mmc_parent_rate = clk_get_rate(mmc_parent);
143 if (!mmc_parent_rate)
146 /* Get MMC clock divider */
147 mmc_div = mmc_parent_rate / mmc_rate;
149 step = DIV_ROUND_CLOSEST(360, mmc_div);
153 static int mmc_set_phase(struct clk_hw *hw, int degrees)
155 struct clk *mmc, *mmc_parent, *clk = hw->clk;
156 struct mmc_phase *phase = to_mmc_phase(hw);
157 unsigned int mmc_rate, mmc_parent_rate;
162 /* Get the main MMC clock */
163 mmc = clk_get_parent(clk);
168 mmc_rate = clk_get_rate(mmc);
172 /* Now, get the MMC parent (most likely some PLL) */
173 mmc_parent = clk_get_parent(mmc);
178 mmc_parent_rate = clk_get_rate(mmc_parent);
179 if (!mmc_parent_rate)
182 if (degrees != 180) {
185 /* Get MMC clock divider */
186 mmc_div = mmc_parent_rate / mmc_rate;
189 * We can only outphase the clocks by multiple of the
192 * Since the MMC clock in only a divider, and the
193 * formula to get the outphasing in degrees is deg =
194 * 360 * delta / period
196 * If we simplify this formula, we can see that the
197 * only thing that we're concerned about is the number
198 * of period we want to outphase our clock from, and
199 * the divider set by the MMC clock.
201 step = DIV_ROUND_CLOSEST(360, mmc_div);
202 delay = DIV_ROUND_CLOSEST(degrees, step);
207 spin_lock_irqsave(phase->lock, flags);
208 value = readl(phase->reg);
209 value &= ~GENMASK(phase->data->offset + 3, phase->data->offset);
210 value |= delay << phase->data->offset;
211 writel(value, phase->reg);
212 spin_unlock_irqrestore(phase->lock, flags);
217 static const struct clk_ops mmc_clk_ops = {
218 .get_phase = mmc_get_phase,
219 .set_phase = mmc_set_phase,
222 static void __init sun4i_a10_mmc_phase_setup(struct device_node *node,
223 struct mmc_phase_data *data)
225 const char *parent_names[1] = { of_clk_get_parent_name(node, 0) };
226 struct clk_init_data init = {
228 .parent_names = parent_names,
232 struct mmc_phase *phase;
235 phase = kmalloc(sizeof(*phase), GFP_KERNEL);
239 phase->hw.init = &init;
241 phase->reg = of_iomap(node, 0);
246 phase->lock = &sun4i_a10_mod0_lock;
248 if (of_property_read_string(node, "clock-output-names", &init.name))
249 init.name = node->name;
251 clk = clk_register(NULL, &phase->hw);
255 of_clk_add_provider(node, of_clk_src_simple_get, clk);
266 static struct mmc_phase_data mmc_output_clk = {
270 static struct mmc_phase_data mmc_sample_clk = {
274 static void __init sun4i_a10_mmc_output_setup(struct device_node *node)
276 sun4i_a10_mmc_phase_setup(node, &mmc_output_clk);
278 CLK_OF_DECLARE(sun4i_a10_mmc_output, "allwinner,sun4i-a10-mmc-output-clk", sun4i_a10_mmc_output_setup);
280 static void __init sun4i_a10_mmc_sample_setup(struct device_node *node)
282 sun4i_a10_mmc_phase_setup(node, &mmc_sample_clk);
284 CLK_OF_DECLARE(sun4i_a10_mmc_sample, "allwinner,sun4i-a10-mmc-sample-clk", sun4i_a10_mmc_sample_setup);