2 * Copyright 2014 Chen-Yu Tsai
4 * Chen-Yu Tsai <wens@csie.org>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
17 #include <linux/clk-provider.h>
18 #include <linux/clkdev.h>
20 #include <linux/of_address.h>
21 #include <linux/log2.h>
23 #include "clk-factors.h"
27 * sun9i_a80_get_pll4_factors() - calculates n, p, m factors for PLL1
28 * PLL4 rate is calculated as follows
29 * rate = (parent_rate * n >> p) / (m + 1);
30 * parent_rate is always 24Mhz
32 * p and m are named div1 and div2 in Allwinner's SDK
35 static void sun9i_a80_get_pll4_factors(u32 *freq, u32 parent_rate,
36 u8 *n, u8 *k, u8 *m, u8 *p)
40 /* Normalize value to a 6M multiple */
41 div = DIV_ROUND_UP(*freq, 6000000);
43 /* divs above 256 cannot be odd */
45 div = round_up(div, 2);
47 /* divs above 512 must be a multiple of 4 */
49 div = round_up(div, 4);
51 *freq = 6000000 * div;
53 /* we were called to round the frequency, we can now return */
57 /* p will be 1 for divs under 512 */
63 /* m will be 1 if div is odd */
69 /* calculate a suitable n based on m and p */
70 *n = div / (*p + 1) / (*m + 1);
73 static struct clk_factors_config sun9i_a80_pll4_config = {
82 static const struct factors_data sun9i_a80_pll4_data __initconst = {
84 .table = &sun9i_a80_pll4_config,
85 .getter = sun9i_a80_get_pll4_factors,
88 static DEFINE_SPINLOCK(sun9i_a80_pll4_lock);
90 static void __init sun9i_a80_pll4_setup(struct device_node *node)
92 sunxi_factors_register(node, &sun9i_a80_pll4_data, &sun9i_a80_pll4_lock);
94 CLK_OF_DECLARE(sun9i_a80_pll4, "allwinner,sun9i-a80-pll4-clk", sun9i_a80_pll4_setup);
98 * sun9i_a80_get_gt_factors() - calculates m factor for GT
99 * GT rate is calculated as follows
100 * rate = parent_rate / (m + 1);
103 static void sun9i_a80_get_gt_factors(u32 *freq, u32 parent_rate,
104 u8 *n, u8 *k, u8 *m, u8 *p)
108 if (parent_rate < *freq)
111 div = DIV_ROUND_UP(parent_rate, *freq);
113 /* maximum divider is 4 */
117 *freq = parent_rate / div;
119 /* we were called to round the frequency, we can now return */
126 static struct clk_factors_config sun9i_a80_gt_config = {
131 static const struct factors_data sun9i_a80_gt_data __initconst = {
133 .muxmask = BIT(1) | BIT(0),
134 .table = &sun9i_a80_gt_config,
135 .getter = sun9i_a80_get_gt_factors,
138 static DEFINE_SPINLOCK(sun9i_a80_gt_lock);
140 static void __init sun9i_a80_gt_setup(struct device_node *node)
142 struct clk *gt = sunxi_factors_register(node, &sun9i_a80_gt_data,
145 /* The GT bus clock needs to be always enabled */
147 clk_prepare_enable(gt);
149 CLK_OF_DECLARE(sun9i_a80_gt, "allwinner,sun9i-a80-gt-clk", sun9i_a80_gt_setup);
153 * sun9i_a80_get_ahb_factors() - calculates p factor for AHB0/1/2
154 * AHB rate is calculated as follows
155 * rate = parent_rate >> p;
158 static void sun9i_a80_get_ahb_factors(u32 *freq, u32 parent_rate,
159 u8 *n, u8 *k, u8 *m, u8 *p)
163 if (parent_rate < *freq)
166 _p = order_base_2(DIV_ROUND_UP(parent_rate, *freq));
172 *freq = parent_rate >> _p;
174 /* we were called to round the frequency, we can now return */
181 static struct clk_factors_config sun9i_a80_ahb_config = {
186 static const struct factors_data sun9i_a80_ahb_data __initconst = {
188 .muxmask = BIT(1) | BIT(0),
189 .table = &sun9i_a80_ahb_config,
190 .getter = sun9i_a80_get_ahb_factors,
193 static DEFINE_SPINLOCK(sun9i_a80_ahb_lock);
195 static void __init sun9i_a80_ahb_setup(struct device_node *node)
197 sunxi_factors_register(node, &sun9i_a80_ahb_data, &sun9i_a80_ahb_lock);
199 CLK_OF_DECLARE(sun9i_a80_ahb, "allwinner,sun9i-a80-ahb-clk", sun9i_a80_ahb_setup);
202 static const struct factors_data sun9i_a80_apb0_data __initconst = {
205 .table = &sun9i_a80_ahb_config,
206 .getter = sun9i_a80_get_ahb_factors,
209 static DEFINE_SPINLOCK(sun9i_a80_apb0_lock);
211 static void __init sun9i_a80_apb0_setup(struct device_node *node)
213 sunxi_factors_register(node, &sun9i_a80_apb0_data, &sun9i_a80_apb0_lock);
215 CLK_OF_DECLARE(sun9i_a80_apb0, "allwinner,sun9i-a80-apb0-clk", sun9i_a80_apb0_setup);
219 * sun9i_a80_get_apb1_factors() - calculates m, p factors for APB1
220 * APB1 rate is calculated as follows
221 * rate = (parent_rate >> p) / (m + 1);
224 static void sun9i_a80_get_apb1_factors(u32 *freq, u32 parent_rate,
225 u8 *n, u8 *k, u8 *m, u8 *p)
230 if (parent_rate < *freq)
233 div = DIV_ROUND_UP(parent_rate, *freq);
235 /* Highest possible divider is 256 (p = 3, m = 31) */
239 calcp = order_base_2(div);
240 calcm = (parent_rate >> calcp) - 1;
241 *freq = (parent_rate >> calcp) / (calcm + 1);
243 /* we were called to round the frequency, we can now return */
251 static struct clk_factors_config sun9i_a80_apb1_config = {
258 static const struct factors_data sun9i_a80_apb1_data __initconst = {
261 .table = &sun9i_a80_apb1_config,
262 .getter = sun9i_a80_get_apb1_factors,
265 static DEFINE_SPINLOCK(sun9i_a80_apb1_lock);
267 static void __init sun9i_a80_apb1_setup(struct device_node *node)
269 sunxi_factors_register(node, &sun9i_a80_apb1_data, &sun9i_a80_apb1_lock);
271 CLK_OF_DECLARE(sun9i_a80_apb1, "allwinner,sun9i-a80-apb1-clk", sun9i_a80_apb1_setup);