2 * Copyright 2013 Emilio López
4 * Emilio López <emilio@elopez.com.ar>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
17 #include <linux/clk.h>
18 #include <linux/clk-provider.h>
19 #include <linux/clkdev.h>
21 #include <linux/of_address.h>
22 #include <linux/reset-controller.h>
23 #include <linux/slab.h>
24 #include <linux/spinlock.h>
25 #include <linux/log2.h>
27 #include "clk-factors.h"
29 static DEFINE_SPINLOCK(clk_lock);
32 * sun6i_a31_ahb1_clk_setup() - Setup function for a31 ahb1 composite clk
35 #define SUN6I_AHB1_MAX_PARENTS 4
36 #define SUN6I_AHB1_MUX_PARENT_PLL6 3
37 #define SUN6I_AHB1_MUX_SHIFT 12
38 /* un-shifted mask is what mux_clk expects */
39 #define SUN6I_AHB1_MUX_MASK 0x3
40 #define SUN6I_AHB1_MUX_GET_PARENT(reg) ((reg >> SUN6I_AHB1_MUX_SHIFT) & \
43 #define SUN6I_AHB1_DIV_SHIFT 4
44 #define SUN6I_AHB1_DIV_MASK (0x3 << SUN6I_AHB1_DIV_SHIFT)
45 #define SUN6I_AHB1_DIV_GET(reg) ((reg & SUN6I_AHB1_DIV_MASK) >> \
47 #define SUN6I_AHB1_DIV_SET(reg, div) ((reg & ~SUN6I_AHB1_DIV_MASK) | \
48 (div << SUN6I_AHB1_DIV_SHIFT))
49 #define SUN6I_AHB1_PLL6_DIV_SHIFT 6
50 #define SUN6I_AHB1_PLL6_DIV_MASK (0x3 << SUN6I_AHB1_PLL6_DIV_SHIFT)
51 #define SUN6I_AHB1_PLL6_DIV_GET(reg) ((reg & SUN6I_AHB1_PLL6_DIV_MASK) >> \
52 SUN6I_AHB1_PLL6_DIV_SHIFT)
53 #define SUN6I_AHB1_PLL6_DIV_SET(reg, div) ((reg & ~SUN6I_AHB1_PLL6_DIV_MASK) | \
54 (div << SUN6I_AHB1_PLL6_DIV_SHIFT))
56 struct sun6i_ahb1_clk {
61 #define to_sun6i_ahb1_clk(_hw) container_of(_hw, struct sun6i_ahb1_clk, hw)
63 static unsigned long sun6i_ahb1_clk_recalc_rate(struct clk_hw *hw,
64 unsigned long parent_rate)
66 struct sun6i_ahb1_clk *ahb1 = to_sun6i_ahb1_clk(hw);
70 /* Fetch the register value */
71 reg = readl(ahb1->reg);
73 /* apply pre-divider first if parent is pll6 */
74 if (SUN6I_AHB1_MUX_GET_PARENT(reg) == SUN6I_AHB1_MUX_PARENT_PLL6)
75 parent_rate /= SUN6I_AHB1_PLL6_DIV_GET(reg) + 1;
78 rate = parent_rate >> SUN6I_AHB1_DIV_GET(reg);
83 static long sun6i_ahb1_clk_round(unsigned long rate, u8 *divp, u8 *pre_divp,
84 u8 parent, unsigned long parent_rate)
86 u8 div, calcp, calcm = 1;
89 * clock can only divide, so we will never be able to achieve
90 * frequencies higher than the parent frequency
92 if (parent_rate && rate > parent_rate)
95 div = DIV_ROUND_UP(parent_rate, rate);
97 /* calculate pre-divider if parent is pll6 */
98 if (parent == SUN6I_AHB1_MUX_PARENT_PLL6) {
101 else if (div / 2 < 4)
103 else if (div / 4 < 4)
108 calcm = DIV_ROUND_UP(div, 1 << calcp);
110 calcp = __roundup_pow_of_two(div);
111 calcp = calcp > 3 ? 3 : calcp;
114 /* we were asked to pass back divider values */
117 *pre_divp = calcm - 1;
120 return (parent_rate / calcm) >> calcp;
123 static int sun6i_ahb1_clk_determine_rate(struct clk_hw *hw,
124 struct clk_rate_request *req)
126 struct clk *clk = hw->clk, *parent, *best_parent = NULL;
128 unsigned long parent_rate, best = 0, child_rate, best_child_rate = 0;
130 /* find the parent that can help provide the fastest rate <= rate */
131 num_parents = __clk_get_num_parents(clk);
132 for (i = 0; i < num_parents; i++) {
133 parent = clk_get_parent_by_index(clk, i);
136 if (__clk_get_flags(clk) & CLK_SET_RATE_PARENT)
137 parent_rate = __clk_round_rate(parent, req->rate);
139 parent_rate = __clk_get_rate(parent);
141 child_rate = sun6i_ahb1_clk_round(req->rate, NULL, NULL, i,
144 if (child_rate <= req->rate && child_rate > best_child_rate) {
145 best_parent = parent;
147 best_child_rate = child_rate;
154 req->best_parent_hw = __clk_get_hw(best_parent);
155 req->best_parent_rate = best;
156 req->rate = best_child_rate;
161 static int sun6i_ahb1_clk_set_rate(struct clk_hw *hw, unsigned long rate,
162 unsigned long parent_rate)
164 struct sun6i_ahb1_clk *ahb1 = to_sun6i_ahb1_clk(hw);
166 u8 div, pre_div, parent;
169 spin_lock_irqsave(&clk_lock, flags);
171 reg = readl(ahb1->reg);
173 /* need to know which parent is used to apply pre-divider */
174 parent = SUN6I_AHB1_MUX_GET_PARENT(reg);
175 sun6i_ahb1_clk_round(rate, &div, &pre_div, parent, parent_rate);
177 reg = SUN6I_AHB1_DIV_SET(reg, div);
178 reg = SUN6I_AHB1_PLL6_DIV_SET(reg, pre_div);
179 writel(reg, ahb1->reg);
181 spin_unlock_irqrestore(&clk_lock, flags);
186 static const struct clk_ops sun6i_ahb1_clk_ops = {
187 .determine_rate = sun6i_ahb1_clk_determine_rate,
188 .recalc_rate = sun6i_ahb1_clk_recalc_rate,
189 .set_rate = sun6i_ahb1_clk_set_rate,
192 static void __init sun6i_ahb1_clk_setup(struct device_node *node)
195 struct sun6i_ahb1_clk *ahb1;
197 const char *clk_name = node->name;
198 const char *parents[SUN6I_AHB1_MAX_PARENTS];
202 reg = of_io_request_and_map(node, 0, of_node_full_name(node));
206 /* we have a mux, we will have >1 parents */
207 i = of_clk_parent_fill(node, parents, SUN6I_AHB1_MAX_PARENTS);
208 of_property_read_string(node, "clock-output-names", &clk_name);
210 ahb1 = kzalloc(sizeof(struct sun6i_ahb1_clk), GFP_KERNEL);
214 mux = kzalloc(sizeof(struct clk_mux), GFP_KERNEL);
220 /* set up clock properties */
222 mux->shift = SUN6I_AHB1_MUX_SHIFT;
223 mux->mask = SUN6I_AHB1_MUX_MASK;
224 mux->lock = &clk_lock;
227 clk = clk_register_composite(NULL, clk_name, parents, i,
228 &mux->hw, &clk_mux_ops,
229 &ahb1->hw, &sun6i_ahb1_clk_ops,
233 of_clk_add_provider(node, of_clk_src_simple_get, clk);
234 clk_register_clkdev(clk, clk_name, NULL);
237 CLK_OF_DECLARE(sun6i_a31_ahb1, "allwinner,sun6i-a31-ahb1-clk", sun6i_ahb1_clk_setup);
239 /* Maximum number of parents our clocks have */
240 #define SUNXI_MAX_PARENTS 5
243 * sun4i_get_pll1_factors() - calculates n, k, m, p factors for PLL1
244 * PLL1 rate is calculated as follows
245 * rate = (parent_rate * n * (k + 1) >> p) / (m + 1);
246 * parent_rate is always 24Mhz
249 static void sun4i_get_pll1_factors(u32 *freq, u32 parent_rate,
250 u8 *n, u8 *k, u8 *m, u8 *p)
254 /* Normalize value to a 6M multiple */
255 div = *freq / 6000000;
256 *freq = 6000000 * div;
258 /* we were called to round the frequency, we can now return */
262 /* m is always zero for pll1 */
265 /* k is 1 only on these cases */
266 if (*freq >= 768000000 || *freq == 42000000 || *freq == 54000000)
271 /* p will be 3 for divs under 10 */
275 /* p will be 2 for divs between 10 - 20 and odd divs under 32 */
276 else if (div < 20 || (div < 32 && (div & 1)))
279 /* p will be 1 for even divs under 32, divs under 40 and odd pairs
280 * of divs between 40-62 */
281 else if (div < 40 || (div < 64 && (div & 2)))
284 /* any other entries have p = 0 */
288 /* calculate a suitable n based on k and p */
295 * sun6i_a31_get_pll1_factors() - calculates n, k and m factors for PLL1
296 * PLL1 rate is calculated as follows
297 * rate = parent_rate * (n + 1) * (k + 1) / (m + 1);
298 * parent_rate should always be 24MHz
300 static void sun6i_a31_get_pll1_factors(u32 *freq, u32 parent_rate,
301 u8 *n, u8 *k, u8 *m, u8 *p)
304 * We can operate only on MHz, this will make our life easier
307 u32 freq_mhz = *freq / 1000000;
308 u32 parent_freq_mhz = parent_rate / 1000000;
311 * Round down the frequency to the closest multiple of either
314 u32 round_freq_6 = round_down(freq_mhz, 6);
315 u32 round_freq_16 = round_down(freq_mhz, 16);
317 if (round_freq_6 > round_freq_16)
318 freq_mhz = round_freq_6;
320 freq_mhz = round_freq_16;
322 *freq = freq_mhz * 1000000;
325 * If the factors pointer are null, we were just called to
326 * round down the frequency.
332 /* If the frequency is a multiple of 32 MHz, k is always 3 */
333 if (!(freq_mhz % 32))
335 /* If the frequency is a multiple of 9 MHz, k is always 2 */
336 else if (!(freq_mhz % 9))
338 /* If the frequency is a multiple of 8 MHz, k is always 1 */
339 else if (!(freq_mhz % 8))
341 /* Otherwise, we don't use the k factor */
346 * If the frequency is a multiple of 2 but not a multiple of
347 * 3, m is 3. This is the first time we use 6 here, yet we
348 * will use it on several other places.
349 * We use this number because it's the lowest frequency we can
350 * generate (with n = 0, k = 0, m = 3), so every other frequency
351 * somehow relates to this frequency.
353 if ((freq_mhz % 6) == 2 || (freq_mhz % 6) == 4)
356 * If the frequency is a multiple of 6MHz, but the factor is
359 else if ((freq_mhz / 6) & 1)
361 /* Otherwise, we end up with m = 1 */
365 /* Calculate n thanks to the above factors we already got */
366 *n = freq_mhz * (*m + 1) / ((*k + 1) * parent_freq_mhz) - 1;
369 * If n end up being outbound, and that we can still decrease
372 if ((*n + 1) > 31 && (*m + 1) > 1) {
373 *n = (*n + 1) / 2 - 1;
374 *m = (*m + 1) / 2 - 1;
379 * sun8i_a23_get_pll1_factors() - calculates n, k, m, p factors for PLL1
380 * PLL1 rate is calculated as follows
381 * rate = (parent_rate * (n + 1) * (k + 1) >> p) / (m + 1);
382 * parent_rate is always 24Mhz
385 static void sun8i_a23_get_pll1_factors(u32 *freq, u32 parent_rate,
386 u8 *n, u8 *k, u8 *m, u8 *p)
390 /* Normalize value to a 6M multiple */
391 div = *freq / 6000000;
392 *freq = 6000000 * div;
394 /* we were called to round the frequency, we can now return */
398 /* m is always zero for pll1 */
401 /* k is 1 only on these cases */
402 if (*freq >= 768000000 || *freq == 42000000 || *freq == 54000000)
407 /* p will be 2 for divs under 20 and odd divs under 32 */
408 if (div < 20 || (div < 32 && (div & 1)))
411 /* p will be 1 for even divs under 32, divs under 40 and odd pairs
412 * of divs between 40-62 */
413 else if (div < 40 || (div < 64 && (div & 2)))
416 /* any other entries have p = 0 */
420 /* calculate a suitable n based on k and p */
427 * sun4i_get_pll5_factors() - calculates n, k factors for PLL5
428 * PLL5 rate is calculated as follows
429 * rate = parent_rate * n * (k + 1)
430 * parent_rate is always 24Mhz
433 static void sun4i_get_pll5_factors(u32 *freq, u32 parent_rate,
434 u8 *n, u8 *k, u8 *m, u8 *p)
438 /* Normalize value to a parent_rate multiple (24M) */
439 div = *freq / parent_rate;
440 *freq = parent_rate * div;
442 /* we were called to round the frequency, we can now return */
448 else if (div / 2 < 31)
450 else if (div / 3 < 31)
455 *n = DIV_ROUND_UP(div, (*k+1));
459 * sun6i_a31_get_pll6_factors() - calculates n, k factors for A31 PLL6x2
460 * PLL6x2 rate is calculated as follows
461 * rate = parent_rate * (n + 1) * (k + 1)
462 * parent_rate is always 24Mhz
465 static void sun6i_a31_get_pll6_factors(u32 *freq, u32 parent_rate,
466 u8 *n, u8 *k, u8 *m, u8 *p)
470 /* Normalize value to a parent_rate multiple (24M) */
471 div = *freq / parent_rate;
472 *freq = parent_rate * div;
474 /* we were called to round the frequency, we can now return */
482 *n = DIV_ROUND_UP(div, (*k+1)) - 1;
486 * sun5i_a13_get_ahb_factors() - calculates m, p factors for AHB
487 * AHB rate is calculated as follows
488 * rate = parent_rate >> p
491 static void sun5i_a13_get_ahb_factors(u32 *freq, u32 parent_rate,
492 u8 *n, u8 *k, u8 *m, u8 *p)
497 if (parent_rate < *freq)
501 * user manual says valid speed is 8k ~ 276M, but tests show it
502 * can work at speeds up to 300M, just after reparenting to pll6
506 if (*freq > 300000000)
509 div = order_base_2(DIV_ROUND_UP(parent_rate, *freq));
515 *freq = parent_rate >> div;
517 /* we were called to round the frequency, we can now return */
525 * sun4i_get_apb1_factors() - calculates m, p factors for APB1
526 * APB1 rate is calculated as follows
527 * rate = (parent_rate >> p) / (m + 1);
530 static void sun4i_get_apb1_factors(u32 *freq, u32 parent_rate,
531 u8 *n, u8 *k, u8 *m, u8 *p)
535 if (parent_rate < *freq)
538 parent_rate = DIV_ROUND_UP(parent_rate, *freq);
541 if (parent_rate > 32)
544 if (parent_rate <= 4)
546 else if (parent_rate <= 8)
548 else if (parent_rate <= 16)
553 calcm = (parent_rate >> calcp) - 1;
555 *freq = (parent_rate >> calcp) / (calcm + 1);
557 /* we were called to round the frequency, we can now return */
569 * sun7i_a20_get_out_factors() - calculates m, p factors for CLK_OUT_A/B
570 * CLK_OUT rate is calculated as follows
571 * rate = (parent_rate >> p) / (m + 1);
574 static void sun7i_a20_get_out_factors(u32 *freq, u32 parent_rate,
575 u8 *n, u8 *k, u8 *m, u8 *p)
577 u8 div, calcm, calcp;
579 /* These clocks can only divide, so we will never be able to achieve
580 * frequencies higher than the parent frequency */
581 if (*freq > parent_rate)
584 div = DIV_ROUND_UP(parent_rate, *freq);
588 else if (div / 2 < 32)
590 else if (div / 4 < 32)
595 calcm = DIV_ROUND_UP(div, 1 << calcp);
597 *freq = (parent_rate >> calcp) / calcm;
599 /* we were called to round the frequency, we can now return */
608 * sunxi_factors_clk_setup() - Setup function for factor clocks
611 static struct clk_factors_config sun4i_pll1_config = {
622 static struct clk_factors_config sun6i_a31_pll1_config = {
632 static struct clk_factors_config sun8i_a23_pll1_config = {
644 static struct clk_factors_config sun4i_pll5_config = {
651 static struct clk_factors_config sun6i_a31_pll6_config = {
659 static struct clk_factors_config sun5i_a13_ahb_config = {
664 static struct clk_factors_config sun4i_apb1_config = {
671 /* user manual says "n" but it's really "p" */
672 static struct clk_factors_config sun7i_a20_out_config = {
679 static const struct factors_data sun4i_pll1_data __initconst = {
681 .table = &sun4i_pll1_config,
682 .getter = sun4i_get_pll1_factors,
685 static const struct factors_data sun6i_a31_pll1_data __initconst = {
687 .table = &sun6i_a31_pll1_config,
688 .getter = sun6i_a31_get_pll1_factors,
691 static const struct factors_data sun8i_a23_pll1_data __initconst = {
693 .table = &sun8i_a23_pll1_config,
694 .getter = sun8i_a23_get_pll1_factors,
697 static const struct factors_data sun7i_a20_pll4_data __initconst = {
699 .table = &sun4i_pll5_config,
700 .getter = sun4i_get_pll5_factors,
703 static const struct factors_data sun4i_pll5_data __initconst = {
705 .table = &sun4i_pll5_config,
706 .getter = sun4i_get_pll5_factors,
710 static const struct factors_data sun4i_pll6_data __initconst = {
712 .table = &sun4i_pll5_config,
713 .getter = sun4i_get_pll5_factors,
717 static const struct factors_data sun6i_a31_pll6_data __initconst = {
719 .table = &sun6i_a31_pll6_config,
720 .getter = sun6i_a31_get_pll6_factors,
724 static const struct factors_data sun5i_a13_ahb_data __initconst = {
726 .muxmask = BIT(1) | BIT(0),
727 .table = &sun5i_a13_ahb_config,
728 .getter = sun5i_a13_get_ahb_factors,
731 static const struct factors_data sun4i_apb1_data __initconst = {
733 .muxmask = BIT(1) | BIT(0),
734 .table = &sun4i_apb1_config,
735 .getter = sun4i_get_apb1_factors,
738 static const struct factors_data sun7i_a20_out_data __initconst = {
741 .muxmask = BIT(1) | BIT(0),
742 .table = &sun7i_a20_out_config,
743 .getter = sun7i_a20_get_out_factors,
746 static struct clk * __init sunxi_factors_clk_setup(struct device_node *node,
747 const struct factors_data *data)
751 reg = of_iomap(node, 0);
753 pr_err("Could not get registers for factors-clk: %s\n",
758 return sunxi_factors_register(node, data, &clk_lock, reg);
764 * sunxi_mux_clk_setup() - Setup function for muxes
767 #define SUNXI_MUX_GATE_WIDTH 2
773 static const struct mux_data sun4i_cpu_mux_data __initconst = {
777 static const struct mux_data sun6i_a31_ahb1_mux_data __initconst = {
781 static void __init sunxi_mux_clk_setup(struct device_node *node,
782 struct mux_data *data)
785 const char *clk_name = node->name;
786 const char *parents[SUNXI_MAX_PARENTS];
790 reg = of_iomap(node, 0);
792 i = of_clk_parent_fill(node, parents, SUNXI_MAX_PARENTS);
793 of_property_read_string(node, "clock-output-names", &clk_name);
795 clk = clk_register_mux(NULL, clk_name, parents, i,
796 CLK_SET_RATE_PARENT, reg,
797 data->shift, SUNXI_MUX_GATE_WIDTH,
801 of_clk_add_provider(node, of_clk_src_simple_get, clk);
802 clk_register_clkdev(clk, clk_name, NULL);
809 * sunxi_divider_clk_setup() - Setup function for simple divider clocks
816 const struct clk_div_table *table;
819 static const struct div_data sun4i_axi_data __initconst = {
825 static const struct clk_div_table sun8i_a23_axi_table[] __initconst = {
826 { .val = 0, .div = 1 },
827 { .val = 1, .div = 2 },
828 { .val = 2, .div = 3 },
829 { .val = 3, .div = 4 },
830 { .val = 4, .div = 4 },
831 { .val = 5, .div = 4 },
832 { .val = 6, .div = 4 },
833 { .val = 7, .div = 4 },
837 static const struct div_data sun8i_a23_axi_data __initconst = {
839 .table = sun8i_a23_axi_table,
842 static const struct div_data sun4i_ahb_data __initconst = {
848 static const struct clk_div_table sun4i_apb0_table[] __initconst = {
849 { .val = 0, .div = 2 },
850 { .val = 1, .div = 2 },
851 { .val = 2, .div = 4 },
852 { .val = 3, .div = 8 },
856 static const struct div_data sun4i_apb0_data __initconst = {
860 .table = sun4i_apb0_table,
863 static void __init sunxi_divider_clk_setup(struct device_node *node,
864 struct div_data *data)
867 const char *clk_name = node->name;
868 const char *clk_parent;
871 reg = of_iomap(node, 0);
873 clk_parent = of_clk_get_parent_name(node, 0);
875 of_property_read_string(node, "clock-output-names", &clk_name);
877 clk = clk_register_divider_table(NULL, clk_name, clk_parent, 0,
878 reg, data->shift, data->width,
879 data->pow ? CLK_DIVIDER_POWER_OF_TWO : 0,
880 data->table, &clk_lock);
882 of_clk_add_provider(node, of_clk_src_simple_get, clk);
883 clk_register_clkdev(clk, clk_name, NULL);
890 * sunxi_gates_clk_setup() - Setup function for leaf gates on clocks
893 #define SUNXI_GATES_MAX_SIZE 64
896 DECLARE_BITMAP(mask, SUNXI_GATES_MAX_SIZE);
899 static const struct gates_data sun4i_axi_gates_data __initconst = {
903 static const struct gates_data sun4i_ahb_gates_data __initconst = {
904 .mask = {0x7F77FFF, 0x14FB3F},
907 static const struct gates_data sun5i_a10s_ahb_gates_data __initconst = {
908 .mask = {0x147667e7, 0x185915},
911 static const struct gates_data sun5i_a13_ahb_gates_data __initconst = {
912 .mask = {0x107067e7, 0x185111},
915 static const struct gates_data sun6i_a31_ahb1_gates_data __initconst = {
916 .mask = {0xEDFE7F62, 0x794F931},
919 static const struct gates_data sun7i_a20_ahb_gates_data __initconst = {
920 .mask = { 0x12f77fff, 0x16ff3f },
923 static const struct gates_data sun8i_a23_ahb1_gates_data __initconst = {
924 .mask = {0x25386742, 0x2505111},
927 static const struct gates_data sun9i_a80_ahb0_gates_data __initconst = {
931 static const struct gates_data sun9i_a80_ahb1_gates_data __initconst = {
935 static const struct gates_data sun9i_a80_ahb2_gates_data __initconst = {
939 static const struct gates_data sun4i_apb0_gates_data __initconst = {
943 static const struct gates_data sun5i_a10s_apb0_gates_data __initconst = {
947 static const struct gates_data sun5i_a13_apb0_gates_data __initconst = {
951 static const struct gates_data sun7i_a20_apb0_gates_data __initconst = {
955 static const struct gates_data sun9i_a80_apb0_gates_data __initconst = {
959 static const struct gates_data sun4i_apb1_gates_data __initconst = {
963 static const struct gates_data sun5i_a10s_apb1_gates_data __initconst = {
967 static const struct gates_data sun5i_a13_apb1_gates_data __initconst = {
971 static const struct gates_data sun6i_a31_apb1_gates_data __initconst = {
975 static const struct gates_data sun8i_a23_apb1_gates_data __initconst = {
979 static const struct gates_data sun6i_a31_apb2_gates_data __initconst = {
983 static const struct gates_data sun7i_a20_apb1_gates_data __initconst = {
984 .mask = { 0xff80ff },
987 static const struct gates_data sun9i_a80_apb1_gates_data __initconst = {
991 static const struct gates_data sun8i_a23_apb2_gates_data __initconst = {
995 static void __init sunxi_gates_clk_setup(struct device_node *node,
996 struct gates_data *data)
998 struct clk_onecell_data *clk_data;
999 const char *clk_parent;
1000 const char *clk_name;
1006 reg = of_iomap(node, 0);
1008 clk_parent = of_clk_get_parent_name(node, 0);
1010 /* Worst-case size approximation and memory allocation */
1011 qty = find_last_bit(data->mask, SUNXI_GATES_MAX_SIZE);
1012 clk_data = kmalloc(sizeof(struct clk_onecell_data), GFP_KERNEL);
1015 clk_data->clks = kzalloc((qty+1) * sizeof(struct clk *), GFP_KERNEL);
1016 if (!clk_data->clks) {
1021 for_each_set_bit(i, data->mask, SUNXI_GATES_MAX_SIZE) {
1022 of_property_read_string_index(node, "clock-output-names",
1025 clk_data->clks[i] = clk_register_gate(NULL, clk_name,
1027 reg + 4 * (i/32), i % 32,
1029 WARN_ON(IS_ERR(clk_data->clks[i]));
1030 clk_register_clkdev(clk_data->clks[i], clk_name, NULL);
1035 /* Adjust to the real max */
1036 clk_data->clk_num = i;
1038 of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
1044 * sunxi_divs_clk_setup() helper data
1047 #define SUNXI_DIVS_MAX_QTY 4
1048 #define SUNXI_DIVISOR_WIDTH 2
1051 const struct factors_data *factors; /* data for the factor clock */
1052 int ndivs; /* number of outputs */
1054 * List of outputs. Refer to the diagram for sunxi_divs_clk_setup():
1055 * self or base factor clock refers to the output from the pll
1056 * itself. The remaining refer to fixed or configurable divider
1060 u8 self; /* is it the base factor clock? (only one) */
1061 u8 fixed; /* is it a fixed divisor? if not... */
1062 struct clk_div_table *table; /* is it a table based divisor? */
1063 u8 shift; /* otherwise it's a normal divisor with this shift */
1064 u8 pow; /* is it power-of-two based? */
1065 u8 gate; /* is it independently gateable? */
1066 } div[SUNXI_DIVS_MAX_QTY];
1069 static struct clk_div_table pll6_sata_tbl[] = {
1070 { .val = 0, .div = 6, },
1071 { .val = 1, .div = 12, },
1072 { .val = 2, .div = 18, },
1073 { .val = 3, .div = 24, },
1077 static const struct divs_data pll5_divs_data __initconst = {
1078 .factors = &sun4i_pll5_data,
1081 { .shift = 0, .pow = 0, }, /* M, DDR */
1082 { .shift = 16, .pow = 1, }, /* P, other */
1083 /* No output for the base factor clock */
1087 static const struct divs_data pll6_divs_data __initconst = {
1088 .factors = &sun4i_pll6_data,
1091 { .shift = 0, .table = pll6_sata_tbl, .gate = 14 }, /* M, SATA */
1092 { .fixed = 2 }, /* P, other */
1093 { .self = 1 }, /* base factor clock, 2x */
1094 { .fixed = 4 }, /* pll6 / 4, used as ahb input */
1098 static const struct divs_data sun6i_a31_pll6_divs_data __initconst = {
1099 .factors = &sun6i_a31_pll6_data,
1102 { .fixed = 2 }, /* normal output */
1103 { .self = 1 }, /* base factor clock, 2x */
1108 * sunxi_divs_clk_setup() - Setup function for leaf divisors on clocks
1110 * These clocks look something like this
1111 * ________________________
1112 * | ___divisor 1---|----> to consumer
1113 * parent >--| pll___/___divisor 2---|----> to consumer
1114 * | \_______________|____> to consumer
1115 * |________________________|
1118 static void __init sunxi_divs_clk_setup(struct device_node *node,
1119 struct divs_data *data)
1121 struct clk_onecell_data *clk_data;
1123 const char *clk_name;
1124 struct clk **clks, *pclk;
1125 struct clk_hw *gate_hw, *rate_hw;
1126 const struct clk_ops *rate_ops;
1127 struct clk_gate *gate = NULL;
1128 struct clk_fixed_factor *fix_factor;
1129 struct clk_divider *divider;
1131 int ndivs = SUNXI_DIVS_MAX_QTY, i = 0;
1132 int flags, clkflags;
1134 /* if number of children known, use it */
1136 ndivs = data->ndivs;
1138 /* Set up factor clock that we will be dividing */
1139 pclk = sunxi_factors_clk_setup(node, data->factors);
1140 parent = __clk_get_name(pclk);
1142 reg = of_iomap(node, 0);
1144 clk_data = kmalloc(sizeof(struct clk_onecell_data), GFP_KERNEL);
1148 clks = kcalloc(ndivs, sizeof(*clks), GFP_KERNEL);
1152 clk_data->clks = clks;
1154 /* It's not a good idea to have automatic reparenting changing
1156 clkflags = !strcmp("pll5", parent) ? 0 : CLK_SET_RATE_PARENT;
1158 for (i = 0; i < ndivs; i++) {
1159 if (of_property_read_string_index(node, "clock-output-names",
1163 /* If this is the base factor clock, only update clks */
1164 if (data->div[i].self) {
1165 clk_data->clks[i] = pclk;
1173 /* If this leaf clock can be gated, create a gate */
1174 if (data->div[i].gate) {
1175 gate = kzalloc(sizeof(*gate), GFP_KERNEL);
1180 gate->bit_idx = data->div[i].gate;
1181 gate->lock = &clk_lock;
1183 gate_hw = &gate->hw;
1186 /* Leaves can be fixed or configurable divisors */
1187 if (data->div[i].fixed) {
1188 fix_factor = kzalloc(sizeof(*fix_factor), GFP_KERNEL);
1192 fix_factor->mult = 1;
1193 fix_factor->div = data->div[i].fixed;
1195 rate_hw = &fix_factor->hw;
1196 rate_ops = &clk_fixed_factor_ops;
1198 divider = kzalloc(sizeof(*divider), GFP_KERNEL);
1202 flags = data->div[i].pow ? CLK_DIVIDER_POWER_OF_TWO : 0;
1205 divider->shift = data->div[i].shift;
1206 divider->width = SUNXI_DIVISOR_WIDTH;
1207 divider->flags = flags;
1208 divider->lock = &clk_lock;
1209 divider->table = data->div[i].table;
1211 rate_hw = ÷r->hw;
1212 rate_ops = &clk_divider_ops;
1215 /* Wrap the (potential) gate and the divisor on a composite
1216 * clock to unify them */
1217 clks[i] = clk_register_composite(NULL, clk_name, &parent, 1,
1220 gate_hw, &clk_gate_ops,
1223 WARN_ON(IS_ERR(clk_data->clks[i]));
1224 clk_register_clkdev(clks[i], clk_name, NULL);
1227 /* Adjust to the real max */
1228 clk_data->clk_num = i;
1230 of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
1244 /* Matches for factors clocks */
1245 static const struct of_device_id clk_factors_match[] __initconst = {
1246 {.compatible = "allwinner,sun4i-a10-pll1-clk", .data = &sun4i_pll1_data,},
1247 {.compatible = "allwinner,sun6i-a31-pll1-clk", .data = &sun6i_a31_pll1_data,},
1248 {.compatible = "allwinner,sun8i-a23-pll1-clk", .data = &sun8i_a23_pll1_data,},
1249 {.compatible = "allwinner,sun7i-a20-pll4-clk", .data = &sun7i_a20_pll4_data,},
1250 {.compatible = "allwinner,sun5i-a13-ahb-clk", .data = &sun5i_a13_ahb_data,},
1251 {.compatible = "allwinner,sun4i-a10-apb1-clk", .data = &sun4i_apb1_data,},
1252 {.compatible = "allwinner,sun7i-a20-out-clk", .data = &sun7i_a20_out_data,},
1256 /* Matches for divider clocks */
1257 static const struct of_device_id clk_div_match[] __initconst = {
1258 {.compatible = "allwinner,sun4i-a10-axi-clk", .data = &sun4i_axi_data,},
1259 {.compatible = "allwinner,sun8i-a23-axi-clk", .data = &sun8i_a23_axi_data,},
1260 {.compatible = "allwinner,sun4i-a10-ahb-clk", .data = &sun4i_ahb_data,},
1261 {.compatible = "allwinner,sun4i-a10-apb0-clk", .data = &sun4i_apb0_data,},
1265 /* Matches for divided outputs */
1266 static const struct of_device_id clk_divs_match[] __initconst = {
1267 {.compatible = "allwinner,sun4i-a10-pll5-clk", .data = &pll5_divs_data,},
1268 {.compatible = "allwinner,sun4i-a10-pll6-clk", .data = &pll6_divs_data,},
1269 {.compatible = "allwinner,sun6i-a31-pll6-clk", .data = &sun6i_a31_pll6_divs_data,},
1273 /* Matches for mux clocks */
1274 static const struct of_device_id clk_mux_match[] __initconst = {
1275 {.compatible = "allwinner,sun4i-a10-cpu-clk", .data = &sun4i_cpu_mux_data,},
1276 {.compatible = "allwinner,sun6i-a31-ahb1-mux-clk", .data = &sun6i_a31_ahb1_mux_data,},
1280 /* Matches for gate clocks */
1281 static const struct of_device_id clk_gates_match[] __initconst = {
1282 {.compatible = "allwinner,sun4i-a10-axi-gates-clk", .data = &sun4i_axi_gates_data,},
1283 {.compatible = "allwinner,sun4i-a10-ahb-gates-clk", .data = &sun4i_ahb_gates_data,},
1284 {.compatible = "allwinner,sun5i-a10s-ahb-gates-clk", .data = &sun5i_a10s_ahb_gates_data,},
1285 {.compatible = "allwinner,sun5i-a13-ahb-gates-clk", .data = &sun5i_a13_ahb_gates_data,},
1286 {.compatible = "allwinner,sun6i-a31-ahb1-gates-clk", .data = &sun6i_a31_ahb1_gates_data,},
1287 {.compatible = "allwinner,sun7i-a20-ahb-gates-clk", .data = &sun7i_a20_ahb_gates_data,},
1288 {.compatible = "allwinner,sun8i-a23-ahb1-gates-clk", .data = &sun8i_a23_ahb1_gates_data,},
1289 {.compatible = "allwinner,sun9i-a80-ahb0-gates-clk", .data = &sun9i_a80_ahb0_gates_data,},
1290 {.compatible = "allwinner,sun9i-a80-ahb1-gates-clk", .data = &sun9i_a80_ahb1_gates_data,},
1291 {.compatible = "allwinner,sun9i-a80-ahb2-gates-clk", .data = &sun9i_a80_ahb2_gates_data,},
1292 {.compatible = "allwinner,sun4i-a10-apb0-gates-clk", .data = &sun4i_apb0_gates_data,},
1293 {.compatible = "allwinner,sun5i-a10s-apb0-gates-clk", .data = &sun5i_a10s_apb0_gates_data,},
1294 {.compatible = "allwinner,sun5i-a13-apb0-gates-clk", .data = &sun5i_a13_apb0_gates_data,},
1295 {.compatible = "allwinner,sun7i-a20-apb0-gates-clk", .data = &sun7i_a20_apb0_gates_data,},
1296 {.compatible = "allwinner,sun9i-a80-apb0-gates-clk", .data = &sun9i_a80_apb0_gates_data,},
1297 {.compatible = "allwinner,sun4i-a10-apb1-gates-clk", .data = &sun4i_apb1_gates_data,},
1298 {.compatible = "allwinner,sun5i-a10s-apb1-gates-clk", .data = &sun5i_a10s_apb1_gates_data,},
1299 {.compatible = "allwinner,sun5i-a13-apb1-gates-clk", .data = &sun5i_a13_apb1_gates_data,},
1300 {.compatible = "allwinner,sun6i-a31-apb1-gates-clk", .data = &sun6i_a31_apb1_gates_data,},
1301 {.compatible = "allwinner,sun7i-a20-apb1-gates-clk", .data = &sun7i_a20_apb1_gates_data,},
1302 {.compatible = "allwinner,sun8i-a23-apb1-gates-clk", .data = &sun8i_a23_apb1_gates_data,},
1303 {.compatible = "allwinner,sun9i-a80-apb1-gates-clk", .data = &sun9i_a80_apb1_gates_data,},
1304 {.compatible = "allwinner,sun6i-a31-apb2-gates-clk", .data = &sun6i_a31_apb2_gates_data,},
1305 {.compatible = "allwinner,sun8i-a23-apb2-gates-clk", .data = &sun8i_a23_apb2_gates_data,},
1309 static void __init of_sunxi_table_clock_setup(const struct of_device_id *clk_match,
1312 struct device_node *np;
1313 const struct div_data *data;
1314 const struct of_device_id *match;
1315 void (*setup_function)(struct device_node *, const void *) = function;
1317 for_each_matching_node_and_match(np, clk_match, &match) {
1319 setup_function(np, data);
1323 static void __init sunxi_init_clocks(const char *clocks[], int nclocks)
1327 /* Register divided output clocks */
1328 of_sunxi_table_clock_setup(clk_divs_match, sunxi_divs_clk_setup);
1330 /* Register factor clocks */
1331 of_sunxi_table_clock_setup(clk_factors_match, sunxi_factors_clk_setup);
1333 /* Register divider clocks */
1334 of_sunxi_table_clock_setup(clk_div_match, sunxi_divider_clk_setup);
1336 /* Register mux clocks */
1337 of_sunxi_table_clock_setup(clk_mux_match, sunxi_mux_clk_setup);
1339 /* Register gate clocks */
1340 of_sunxi_table_clock_setup(clk_gates_match, sunxi_gates_clk_setup);
1342 /* Protect the clocks that needs to stay on */
1343 for (i = 0; i < nclocks; i++) {
1344 struct clk *clk = clk_get(NULL, clocks[i]);
1347 clk_prepare_enable(clk);
1351 static const char *sun4i_a10_critical_clocks[] __initdata = {
1356 static void __init sun4i_a10_init_clocks(struct device_node *node)
1358 sunxi_init_clocks(sun4i_a10_critical_clocks,
1359 ARRAY_SIZE(sun4i_a10_critical_clocks));
1361 CLK_OF_DECLARE(sun4i_a10_clk_init, "allwinner,sun4i-a10", sun4i_a10_init_clocks);
1363 static const char *sun5i_critical_clocks[] __initdata = {
1369 static void __init sun5i_init_clocks(struct device_node *node)
1371 sunxi_init_clocks(sun5i_critical_clocks,
1372 ARRAY_SIZE(sun5i_critical_clocks));
1374 CLK_OF_DECLARE(sun5i_a10s_clk_init, "allwinner,sun5i-a10s", sun5i_init_clocks);
1375 CLK_OF_DECLARE(sun5i_a13_clk_init, "allwinner,sun5i-a13", sun5i_init_clocks);
1376 CLK_OF_DECLARE(sun7i_a20_clk_init, "allwinner,sun7i-a20", sun5i_init_clocks);
1378 static const char *sun6i_critical_clocks[] __initdata = {
1382 static void __init sun6i_init_clocks(struct device_node *node)
1384 sunxi_init_clocks(sun6i_critical_clocks,
1385 ARRAY_SIZE(sun6i_critical_clocks));
1387 CLK_OF_DECLARE(sun6i_a31_clk_init, "allwinner,sun6i-a31", sun6i_init_clocks);
1388 CLK_OF_DECLARE(sun6i_a31s_clk_init, "allwinner,sun6i-a31s", sun6i_init_clocks);
1389 CLK_OF_DECLARE(sun8i_a23_clk_init, "allwinner,sun8i-a23", sun6i_init_clocks);
1391 static void __init sun9i_init_clocks(struct device_node *node)
1393 sunxi_init_clocks(NULL, 0);
1395 CLK_OF_DECLARE(sun9i_a80_clk_init, "allwinner,sun9i-a80", sun9i_init_clocks);