2 * Copyright 2013 Emilio López
4 * Emilio López <emilio@elopez.com.ar>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
17 #include <linux/clk-provider.h>
18 #include <linux/clkdev.h>
20 #include <linux/of_address.h>
21 #include <linux/reset-controller.h>
23 #include "clk-factors.h"
25 static DEFINE_SPINLOCK(clk_lock);
27 /* Maximum number of parents our clocks have */
28 #define SUNXI_MAX_PARENTS 5
31 * sun4i_get_pll1_factors() - calculates n, k, m, p factors for PLL1
32 * PLL1 rate is calculated as follows
33 * rate = (parent_rate * n * (k + 1) >> p) / (m + 1);
34 * parent_rate is always 24Mhz
37 static void sun4i_get_pll1_factors(u32 *freq, u32 parent_rate,
38 u8 *n, u8 *k, u8 *m, u8 *p)
42 /* Normalize value to a 6M multiple */
43 div = *freq / 6000000;
44 *freq = 6000000 * div;
46 /* we were called to round the frequency, we can now return */
50 /* m is always zero for pll1 */
53 /* k is 1 only on these cases */
54 if (*freq >= 768000000 || *freq == 42000000 || *freq == 54000000)
59 /* p will be 3 for divs under 10 */
63 /* p will be 2 for divs between 10 - 20 and odd divs under 32 */
64 else if (div < 20 || (div < 32 && (div & 1)))
67 /* p will be 1 for even divs under 32, divs under 40 and odd pairs
68 * of divs between 40-62 */
69 else if (div < 40 || (div < 64 && (div & 2)))
72 /* any other entries have p = 0 */
76 /* calculate a suitable n based on k and p */
83 * sun6i_a31_get_pll1_factors() - calculates n, k and m factors for PLL1
84 * PLL1 rate is calculated as follows
85 * rate = parent_rate * (n + 1) * (k + 1) / (m + 1);
86 * parent_rate should always be 24MHz
88 static void sun6i_a31_get_pll1_factors(u32 *freq, u32 parent_rate,
89 u8 *n, u8 *k, u8 *m, u8 *p)
92 * We can operate only on MHz, this will make our life easier
95 u32 freq_mhz = *freq / 1000000;
96 u32 parent_freq_mhz = parent_rate / 1000000;
99 * Round down the frequency to the closest multiple of either
102 u32 round_freq_6 = round_down(freq_mhz, 6);
103 u32 round_freq_16 = round_down(freq_mhz, 16);
105 if (round_freq_6 > round_freq_16)
106 freq_mhz = round_freq_6;
108 freq_mhz = round_freq_16;
110 *freq = freq_mhz * 1000000;
113 * If the factors pointer are null, we were just called to
114 * round down the frequency.
120 /* If the frequency is a multiple of 32 MHz, k is always 3 */
121 if (!(freq_mhz % 32))
123 /* If the frequency is a multiple of 9 MHz, k is always 2 */
124 else if (!(freq_mhz % 9))
126 /* If the frequency is a multiple of 8 MHz, k is always 1 */
127 else if (!(freq_mhz % 8))
129 /* Otherwise, we don't use the k factor */
134 * If the frequency is a multiple of 2 but not a multiple of
135 * 3, m is 3. This is the first time we use 6 here, yet we
136 * will use it on several other places.
137 * We use this number because it's the lowest frequency we can
138 * generate (with n = 0, k = 0, m = 3), so every other frequency
139 * somehow relates to this frequency.
141 if ((freq_mhz % 6) == 2 || (freq_mhz % 6) == 4)
144 * If the frequency is a multiple of 6MHz, but the factor is
147 else if ((freq_mhz / 6) & 1)
149 /* Otherwise, we end up with m = 1 */
153 /* Calculate n thanks to the above factors we already got */
154 *n = freq_mhz * (*m + 1) / ((*k + 1) * parent_freq_mhz) - 1;
157 * If n end up being outbound, and that we can still decrease
160 if ((*n + 1) > 31 && (*m + 1) > 1) {
161 *n = (*n + 1) / 2 - 1;
162 *m = (*m + 1) / 2 - 1;
167 * sun4i_get_pll5_factors() - calculates n, k factors for PLL5
168 * PLL5 rate is calculated as follows
169 * rate = parent_rate * n * (k + 1)
170 * parent_rate is always 24Mhz
173 static void sun4i_get_pll5_factors(u32 *freq, u32 parent_rate,
174 u8 *n, u8 *k, u8 *m, u8 *p)
178 /* Normalize value to a parent_rate multiple (24M) */
179 div = *freq / parent_rate;
180 *freq = parent_rate * div;
182 /* we were called to round the frequency, we can now return */
188 else if (div / 2 < 31)
190 else if (div / 3 < 31)
195 *n = DIV_ROUND_UP(div, (*k+1));
199 * sun6i_a31_get_pll6_factors() - calculates n, k factors for A31 PLL6
200 * PLL6 rate is calculated as follows
201 * rate = parent_rate * n * (k + 1) / 2
202 * parent_rate is always 24Mhz
205 static void sun6i_a31_get_pll6_factors(u32 *freq, u32 parent_rate,
206 u8 *n, u8 *k, u8 *m, u8 *p)
211 * We always have 24MHz / 2, so we can just say that our
212 * parent clock is 12MHz.
214 parent_rate = parent_rate / 2;
216 /* Normalize value to a parent_rate multiple (24M / 2) */
217 div = *freq / parent_rate;
218 *freq = parent_rate * div;
220 /* we were called to round the frequency, we can now return */
228 *n = DIV_ROUND_UP(div, (*k+1));
232 * sun4i_get_apb1_factors() - calculates m, p factors for APB1
233 * APB1 rate is calculated as follows
234 * rate = (parent_rate >> p) / (m + 1);
237 static void sun4i_get_apb1_factors(u32 *freq, u32 parent_rate,
238 u8 *n, u8 *k, u8 *m, u8 *p)
242 if (parent_rate < *freq)
245 parent_rate = DIV_ROUND_UP(parent_rate, *freq);
248 if (parent_rate > 32)
251 if (parent_rate <= 4)
253 else if (parent_rate <= 8)
255 else if (parent_rate <= 16)
260 calcm = (parent_rate >> calcp) - 1;
262 *freq = (parent_rate >> calcp) / (calcm + 1);
264 /* we were called to round the frequency, we can now return */
275 * sun4i_get_mod0_factors() - calculates m, n factors for MOD0-style clocks
276 * MOD0 rate is calculated as follows
277 * rate = (parent_rate >> p) / (m + 1);
280 static void sun4i_get_mod0_factors(u32 *freq, u32 parent_rate,
281 u8 *n, u8 *k, u8 *m, u8 *p)
283 u8 div, calcm, calcp;
285 /* These clocks can only divide, so we will never be able to achieve
286 * frequencies higher than the parent frequency */
287 if (*freq > parent_rate)
290 div = DIV_ROUND_UP(parent_rate, *freq);
294 else if (div / 2 < 16)
296 else if (div / 4 < 16)
301 calcm = DIV_ROUND_UP(div, 1 << calcp);
303 *freq = (parent_rate >> calcp) / calcm;
305 /* we were called to round the frequency, we can now return */
316 * sun7i_a20_get_out_factors() - calculates m, p factors for CLK_OUT_A/B
317 * CLK_OUT rate is calculated as follows
318 * rate = (parent_rate >> p) / (m + 1);
321 static void sun7i_a20_get_out_factors(u32 *freq, u32 parent_rate,
322 u8 *n, u8 *k, u8 *m, u8 *p)
324 u8 div, calcm, calcp;
326 /* These clocks can only divide, so we will never be able to achieve
327 * frequencies higher than the parent frequency */
328 if (*freq > parent_rate)
331 div = DIV_ROUND_UP(parent_rate, *freq);
335 else if (div / 2 < 32)
337 else if (div / 4 < 32)
342 calcm = DIV_ROUND_UP(div, 1 << calcp);
344 *freq = (parent_rate >> calcp) / calcm;
346 /* we were called to round the frequency, we can now return */
355 * clk_sunxi_mmc_phase_control() - configures MMC clock phase control
358 void clk_sunxi_mmc_phase_control(struct clk *clk, u8 sample, u8 output)
360 #define to_clk_composite(_hw) container_of(_hw, struct clk_composite, hw)
361 #define to_clk_factors(_hw) container_of(_hw, struct clk_factors, hw)
363 struct clk_hw *hw = __clk_get_hw(clk);
364 struct clk_composite *composite = to_clk_composite(hw);
365 struct clk_hw *rate_hw = composite->rate_hw;
366 struct clk_factors *factors = to_clk_factors(rate_hw);
367 unsigned long flags = 0;
371 spin_lock_irqsave(factors->lock, flags);
373 reg = readl(factors->reg);
375 /* set sample clock phase control */
377 reg |= ((sample & 0x7) << 20);
379 /* set output clock phase control */
381 reg |= ((output & 0x7) << 8);
383 writel(reg, factors->reg);
386 spin_unlock_irqrestore(factors->lock, flags);
388 EXPORT_SYMBOL(clk_sunxi_mmc_phase_control);
392 * sunxi_factors_clk_setup() - Setup function for factor clocks
395 #define SUNXI_FACTORS_MUX_MASK 0x3
397 struct factors_data {
400 struct clk_factors_config *table;
401 void (*getter) (u32 *rate, u32 parent_rate, u8 *n, u8 *k, u8 *m, u8 *p);
405 static struct clk_factors_config sun4i_pll1_config = {
416 static struct clk_factors_config sun6i_a31_pll1_config = {
425 static struct clk_factors_config sun4i_pll5_config = {
432 static struct clk_factors_config sun6i_a31_pll6_config = {
439 static struct clk_factors_config sun4i_apb1_config = {
446 /* user manual says "n" but it's really "p" */
447 static struct clk_factors_config sun4i_mod0_config = {
454 /* user manual says "n" but it's really "p" */
455 static struct clk_factors_config sun7i_a20_out_config = {
462 static const struct factors_data sun4i_pll1_data __initconst = {
464 .table = &sun4i_pll1_config,
465 .getter = sun4i_get_pll1_factors,
468 static const struct factors_data sun6i_a31_pll1_data __initconst = {
470 .table = &sun6i_a31_pll1_config,
471 .getter = sun6i_a31_get_pll1_factors,
474 static const struct factors_data sun7i_a20_pll4_data __initconst = {
476 .table = &sun4i_pll5_config,
477 .getter = sun4i_get_pll5_factors,
480 static const struct factors_data sun4i_pll5_data __initconst = {
482 .table = &sun4i_pll5_config,
483 .getter = sun4i_get_pll5_factors,
487 static const struct factors_data sun4i_pll6_data __initconst = {
489 .table = &sun4i_pll5_config,
490 .getter = sun4i_get_pll5_factors,
494 static const struct factors_data sun6i_a31_pll6_data __initconst = {
496 .table = &sun6i_a31_pll6_config,
497 .getter = sun6i_a31_get_pll6_factors,
500 static const struct factors_data sun4i_apb1_data __initconst = {
501 .table = &sun4i_apb1_config,
502 .getter = sun4i_get_apb1_factors,
505 static const struct factors_data sun4i_mod0_data __initconst = {
508 .table = &sun4i_mod0_config,
509 .getter = sun4i_get_mod0_factors,
512 static const struct factors_data sun7i_a20_out_data __initconst = {
515 .table = &sun7i_a20_out_config,
516 .getter = sun7i_a20_get_out_factors,
519 static struct clk * __init sunxi_factors_clk_setup(struct device_node *node,
520 const struct factors_data *data)
523 struct clk_factors *factors;
524 struct clk_gate *gate = NULL;
525 struct clk_mux *mux = NULL;
526 struct clk_hw *gate_hw = NULL;
527 struct clk_hw *mux_hw = NULL;
528 const char *clk_name = node->name;
529 const char *parents[SUNXI_MAX_PARENTS];
533 reg = of_iomap(node, 0);
535 /* if we have a mux, we will have >1 parents */
536 while (i < SUNXI_MAX_PARENTS &&
537 (parents[i] = of_clk_get_parent_name(node, i)) != NULL)
541 * some factor clocks, such as pll5 and pll6, may have multiple
542 * outputs, and have their name designated in factors_data
545 clk_name = data->name;
547 of_property_read_string(node, "clock-output-names", &clk_name);
549 factors = kzalloc(sizeof(struct clk_factors), GFP_KERNEL);
553 /* Add a gate if this factor clock can be gated */
555 gate = kzalloc(sizeof(struct clk_gate), GFP_KERNEL);
561 /* set up gate properties */
563 gate->bit_idx = data->enable;
564 gate->lock = &clk_lock;
568 /* Add a mux if this factor clock can be muxed */
570 mux = kzalloc(sizeof(struct clk_mux), GFP_KERNEL);
577 /* set up gate properties */
579 mux->shift = data->mux;
580 mux->mask = SUNXI_FACTORS_MUX_MASK;
581 mux->lock = &clk_lock;
585 /* set up factors properties */
587 factors->config = data->table;
588 factors->get_factors = data->getter;
589 factors->lock = &clk_lock;
591 clk = clk_register_composite(NULL, clk_name,
593 mux_hw, &clk_mux_ops,
594 &factors->hw, &clk_factors_ops,
595 gate_hw, &clk_gate_ops, 0);
598 of_clk_add_provider(node, of_clk_src_simple_get, clk);
599 clk_register_clkdev(clk, clk_name, NULL);
608 * sunxi_mux_clk_setup() - Setup function for muxes
611 #define SUNXI_MUX_GATE_WIDTH 2
617 static const struct mux_data sun4i_cpu_mux_data __initconst = {
621 static const struct mux_data sun6i_a31_ahb1_mux_data __initconst = {
625 static const struct mux_data sun4i_apb1_mux_data __initconst = {
629 static void __init sunxi_mux_clk_setup(struct device_node *node,
630 struct mux_data *data)
633 const char *clk_name = node->name;
634 const char *parents[SUNXI_MAX_PARENTS];
638 reg = of_iomap(node, 0);
640 while (i < SUNXI_MAX_PARENTS &&
641 (parents[i] = of_clk_get_parent_name(node, i)) != NULL)
644 of_property_read_string(node, "clock-output-names", &clk_name);
646 clk = clk_register_mux(NULL, clk_name, parents, i,
647 CLK_SET_RATE_NO_REPARENT, reg,
648 data->shift, SUNXI_MUX_GATE_WIDTH,
652 of_clk_add_provider(node, of_clk_src_simple_get, clk);
653 clk_register_clkdev(clk, clk_name, NULL);
660 * sunxi_divider_clk_setup() - Setup function for simple divider clocks
669 static const struct div_data sun4i_axi_data __initconst = {
675 static const struct div_data sun4i_ahb_data __initconst = {
681 static const struct div_data sun4i_apb0_data __initconst = {
687 static const struct div_data sun6i_a31_apb2_div_data __initconst = {
693 static void __init sunxi_divider_clk_setup(struct device_node *node,
694 struct div_data *data)
697 const char *clk_name = node->name;
698 const char *clk_parent;
701 reg = of_iomap(node, 0);
703 clk_parent = of_clk_get_parent_name(node, 0);
705 of_property_read_string(node, "clock-output-names", &clk_name);
707 clk = clk_register_divider(NULL, clk_name, clk_parent, 0,
708 reg, data->shift, data->width,
709 data->pow ? CLK_DIVIDER_POWER_OF_TWO : 0,
712 of_clk_add_provider(node, of_clk_src_simple_get, clk);
713 clk_register_clkdev(clk, clk_name, NULL);
720 * sunxi_gates_reset... - reset bits in leaf gate clk registers handling
723 struct gates_reset_data {
726 struct reset_controller_dev rcdev;
729 static int sunxi_gates_reset_assert(struct reset_controller_dev *rcdev,
732 struct gates_reset_data *data = container_of(rcdev,
733 struct gates_reset_data,
738 spin_lock_irqsave(data->lock, flags);
740 reg = readl(data->reg);
741 writel(reg & ~BIT(id), data->reg);
743 spin_unlock_irqrestore(data->lock, flags);
748 static int sunxi_gates_reset_deassert(struct reset_controller_dev *rcdev,
751 struct gates_reset_data *data = container_of(rcdev,
752 struct gates_reset_data,
757 spin_lock_irqsave(data->lock, flags);
759 reg = readl(data->reg);
760 writel(reg | BIT(id), data->reg);
762 spin_unlock_irqrestore(data->lock, flags);
767 static struct reset_control_ops sunxi_gates_reset_ops = {
768 .assert = sunxi_gates_reset_assert,
769 .deassert = sunxi_gates_reset_deassert,
773 * sunxi_gates_clk_setup() - Setup function for leaf gates on clocks
776 #define SUNXI_GATES_MAX_SIZE 64
779 DECLARE_BITMAP(mask, SUNXI_GATES_MAX_SIZE);
783 static const struct gates_data sun4i_axi_gates_data __initconst = {
787 static const struct gates_data sun4i_ahb_gates_data __initconst = {
788 .mask = {0x7F77FFF, 0x14FB3F},
791 static const struct gates_data sun5i_a10s_ahb_gates_data __initconst = {
792 .mask = {0x147667e7, 0x185915},
795 static const struct gates_data sun5i_a13_ahb_gates_data __initconst = {
796 .mask = {0x107067e7, 0x185111},
799 static const struct gates_data sun6i_a31_ahb1_gates_data __initconst = {
800 .mask = {0xEDFE7F62, 0x794F931},
803 static const struct gates_data sun7i_a20_ahb_gates_data __initconst = {
804 .mask = { 0x12f77fff, 0x16ff3f },
807 static const struct gates_data sun4i_apb0_gates_data __initconst = {
811 static const struct gates_data sun5i_a10s_apb0_gates_data __initconst = {
815 static const struct gates_data sun5i_a13_apb0_gates_data __initconst = {
819 static const struct gates_data sun7i_a20_apb0_gates_data __initconst = {
823 static const struct gates_data sun4i_apb1_gates_data __initconst = {
827 static const struct gates_data sun5i_a10s_apb1_gates_data __initconst = {
831 static const struct gates_data sun5i_a13_apb1_gates_data __initconst = {
835 static const struct gates_data sun6i_a31_apb1_gates_data __initconst = {
839 static const struct gates_data sun6i_a31_apb2_gates_data __initconst = {
843 static const struct gates_data sun7i_a20_apb1_gates_data __initconst = {
844 .mask = { 0xff80ff },
847 static const struct gates_data sun4i_a10_usb_gates_data __initconst = {
852 static const struct gates_data sun5i_a13_usb_gates_data __initconst = {
857 static const struct gates_data sun6i_a31_usb_gates_data __initconst = {
858 .mask = { BIT(18) | BIT(17) | BIT(16) | BIT(10) | BIT(9) | BIT(8) },
859 .reset_mask = BIT(2) | BIT(1) | BIT(0),
862 static void __init sunxi_gates_clk_setup(struct device_node *node,
863 struct gates_data *data)
865 struct clk_onecell_data *clk_data;
866 struct gates_reset_data *reset_data;
867 const char *clk_parent;
868 const char *clk_name;
875 reg = of_iomap(node, 0);
877 clk_parent = of_clk_get_parent_name(node, 0);
879 /* Worst-case size approximation and memory allocation */
880 qty = find_last_bit(data->mask, SUNXI_GATES_MAX_SIZE);
881 clk_data = kmalloc(sizeof(struct clk_onecell_data), GFP_KERNEL);
884 clk_data->clks = kzalloc((qty+1) * sizeof(struct clk *), GFP_KERNEL);
885 if (!clk_data->clks) {
890 for_each_set_bit(i, data->mask, SUNXI_GATES_MAX_SIZE) {
891 of_property_read_string_index(node, "clock-output-names",
894 /* No driver claims this clock, but it should remain gated */
895 ignore = !strcmp("ahb_sdram", clk_name) ? CLK_IGNORE_UNUSED : 0;
897 clk_data->clks[i] = clk_register_gate(NULL, clk_name,
899 reg + 4 * (i/32), i % 32,
901 WARN_ON(IS_ERR(clk_data->clks[i]));
906 /* Adjust to the real max */
907 clk_data->clk_num = i;
909 of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
911 /* Register a reset controler for gates with reset bits */
912 if (data->reset_mask == 0)
915 reset_data = kzalloc(sizeof(*reset_data), GFP_KERNEL);
919 reset_data->reg = reg;
920 reset_data->lock = &clk_lock;
921 reset_data->rcdev.nr_resets = __fls(data->reset_mask) + 1;
922 reset_data->rcdev.ops = &sunxi_gates_reset_ops;
923 reset_data->rcdev.of_node = node;
924 reset_controller_register(&reset_data->rcdev);
930 * sunxi_divs_clk_setup() helper data
933 #define SUNXI_DIVS_MAX_QTY 2
934 #define SUNXI_DIVISOR_WIDTH 2
937 const struct factors_data *factors; /* data for the factor clock */
939 u8 fixed; /* is it a fixed divisor? if not... */
940 struct clk_div_table *table; /* is it a table based divisor? */
941 u8 shift; /* otherwise it's a normal divisor with this shift */
942 u8 pow; /* is it power-of-two based? */
943 u8 gate; /* is it independently gateable? */
944 } div[SUNXI_DIVS_MAX_QTY];
947 static struct clk_div_table pll6_sata_tbl[] = {
948 { .val = 0, .div = 6, },
949 { .val = 1, .div = 12, },
950 { .val = 2, .div = 18, },
951 { .val = 3, .div = 24, },
955 static const struct divs_data pll5_divs_data __initconst = {
956 .factors = &sun4i_pll5_data,
958 { .shift = 0, .pow = 0, }, /* M, DDR */
959 { .shift = 16, .pow = 1, }, /* P, other */
963 static const struct divs_data pll6_divs_data __initconst = {
964 .factors = &sun4i_pll6_data,
966 { .shift = 0, .table = pll6_sata_tbl, .gate = 14 }, /* M, SATA */
967 { .fixed = 2 }, /* P, other */
972 * sunxi_divs_clk_setup() - Setup function for leaf divisors on clocks
974 * These clocks look something like this
975 * ________________________
976 * | ___divisor 1---|----> to consumer
977 * parent >--| pll___/___divisor 2---|----> to consumer
978 * | \_______________|____> to consumer
979 * |________________________|
982 static void __init sunxi_divs_clk_setup(struct device_node *node,
983 struct divs_data *data)
985 struct clk_onecell_data *clk_data;
987 const char *clk_name;
988 struct clk **clks, *pclk;
989 struct clk_hw *gate_hw, *rate_hw;
990 const struct clk_ops *rate_ops;
991 struct clk_gate *gate = NULL;
992 struct clk_fixed_factor *fix_factor;
993 struct clk_divider *divider;
998 /* Set up factor clock that we will be dividing */
999 pclk = sunxi_factors_clk_setup(node, data->factors);
1000 parent = __clk_get_name(pclk);
1002 reg = of_iomap(node, 0);
1004 clk_data = kmalloc(sizeof(struct clk_onecell_data), GFP_KERNEL);
1008 clks = kzalloc((SUNXI_DIVS_MAX_QTY+1) * sizeof(*clks), GFP_KERNEL);
1012 clk_data->clks = clks;
1014 /* It's not a good idea to have automatic reparenting changing
1016 clkflags = !strcmp("pll5", parent) ? 0 : CLK_SET_RATE_PARENT;
1018 for (i = 0; i < SUNXI_DIVS_MAX_QTY; i++) {
1019 if (of_property_read_string_index(node, "clock-output-names",
1027 /* If this leaf clock can be gated, create a gate */
1028 if (data->div[i].gate) {
1029 gate = kzalloc(sizeof(*gate), GFP_KERNEL);
1034 gate->bit_idx = data->div[i].gate;
1035 gate->lock = &clk_lock;
1037 gate_hw = &gate->hw;
1040 /* Leaves can be fixed or configurable divisors */
1041 if (data->div[i].fixed) {
1042 fix_factor = kzalloc(sizeof(*fix_factor), GFP_KERNEL);
1046 fix_factor->mult = 1;
1047 fix_factor->div = data->div[i].fixed;
1049 rate_hw = &fix_factor->hw;
1050 rate_ops = &clk_fixed_factor_ops;
1052 divider = kzalloc(sizeof(*divider), GFP_KERNEL);
1056 flags = data->div[i].pow ? CLK_DIVIDER_POWER_OF_TWO : 0;
1059 divider->shift = data->div[i].shift;
1060 divider->width = SUNXI_DIVISOR_WIDTH;
1061 divider->flags = flags;
1062 divider->lock = &clk_lock;
1063 divider->table = data->div[i].table;
1065 rate_hw = ÷r->hw;
1066 rate_ops = &clk_divider_ops;
1069 /* Wrap the (potential) gate and the divisor on a composite
1070 * clock to unify them */
1071 clks[i] = clk_register_composite(NULL, clk_name, &parent, 1,
1074 gate_hw, &clk_gate_ops,
1077 WARN_ON(IS_ERR(clk_data->clks[i]));
1078 clk_register_clkdev(clks[i], clk_name, NULL);
1081 /* The last clock available on the getter is the parent */
1084 /* Adjust to the real max */
1085 clk_data->clk_num = i;
1087 of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
1101 /* Matches for factors clocks */
1102 static const struct of_device_id clk_factors_match[] __initconst = {
1103 {.compatible = "allwinner,sun4i-a10-pll1-clk", .data = &sun4i_pll1_data,},
1104 {.compatible = "allwinner,sun6i-a31-pll1-clk", .data = &sun6i_a31_pll1_data,},
1105 {.compatible = "allwinner,sun7i-a20-pll4-clk", .data = &sun7i_a20_pll4_data,},
1106 {.compatible = "allwinner,sun6i-a31-pll6-clk", .data = &sun6i_a31_pll6_data,},
1107 {.compatible = "allwinner,sun4i-a10-apb1-clk", .data = &sun4i_apb1_data,},
1108 {.compatible = "allwinner,sun4i-a10-mod0-clk", .data = &sun4i_mod0_data,},
1109 {.compatible = "allwinner,sun7i-a20-out-clk", .data = &sun7i_a20_out_data,},
1113 /* Matches for divider clocks */
1114 static const struct of_device_id clk_div_match[] __initconst = {
1115 {.compatible = "allwinner,sun4i-a10-axi-clk", .data = &sun4i_axi_data,},
1116 {.compatible = "allwinner,sun4i-a10-ahb-clk", .data = &sun4i_ahb_data,},
1117 {.compatible = "allwinner,sun4i-a10-apb0-clk", .data = &sun4i_apb0_data,},
1118 {.compatible = "allwinner,sun6i-a31-apb2-div-clk", .data = &sun6i_a31_apb2_div_data,},
1122 /* Matches for divided outputs */
1123 static const struct of_device_id clk_divs_match[] __initconst = {
1124 {.compatible = "allwinner,sun4i-a10-pll5-clk", .data = &pll5_divs_data,},
1125 {.compatible = "allwinner,sun4i-a10-pll6-clk", .data = &pll6_divs_data,},
1129 /* Matches for mux clocks */
1130 static const struct of_device_id clk_mux_match[] __initconst = {
1131 {.compatible = "allwinner,sun4i-a10-cpu-clk", .data = &sun4i_cpu_mux_data,},
1132 {.compatible = "allwinner,sun4i-a10-apb1-mux-clk", .data = &sun4i_apb1_mux_data,},
1133 {.compatible = "allwinner,sun6i-a31-ahb1-mux-clk", .data = &sun6i_a31_ahb1_mux_data,},
1137 /* Matches for gate clocks */
1138 static const struct of_device_id clk_gates_match[] __initconst = {
1139 {.compatible = "allwinner,sun4i-a10-axi-gates-clk", .data = &sun4i_axi_gates_data,},
1140 {.compatible = "allwinner,sun4i-a10-ahb-gates-clk", .data = &sun4i_ahb_gates_data,},
1141 {.compatible = "allwinner,sun5i-a10s-ahb-gates-clk", .data = &sun5i_a10s_ahb_gates_data,},
1142 {.compatible = "allwinner,sun5i-a13-ahb-gates-clk", .data = &sun5i_a13_ahb_gates_data,},
1143 {.compatible = "allwinner,sun6i-a31-ahb1-gates-clk", .data = &sun6i_a31_ahb1_gates_data,},
1144 {.compatible = "allwinner,sun7i-a20-ahb-gates-clk", .data = &sun7i_a20_ahb_gates_data,},
1145 {.compatible = "allwinner,sun4i-a10-apb0-gates-clk", .data = &sun4i_apb0_gates_data,},
1146 {.compatible = "allwinner,sun5i-a10s-apb0-gates-clk", .data = &sun5i_a10s_apb0_gates_data,},
1147 {.compatible = "allwinner,sun5i-a13-apb0-gates-clk", .data = &sun5i_a13_apb0_gates_data,},
1148 {.compatible = "allwinner,sun7i-a20-apb0-gates-clk", .data = &sun7i_a20_apb0_gates_data,},
1149 {.compatible = "allwinner,sun4i-a10-apb1-gates-clk", .data = &sun4i_apb1_gates_data,},
1150 {.compatible = "allwinner,sun5i-a10s-apb1-gates-clk", .data = &sun5i_a10s_apb1_gates_data,},
1151 {.compatible = "allwinner,sun5i-a13-apb1-gates-clk", .data = &sun5i_a13_apb1_gates_data,},
1152 {.compatible = "allwinner,sun6i-a31-apb1-gates-clk", .data = &sun6i_a31_apb1_gates_data,},
1153 {.compatible = "allwinner,sun7i-a20-apb1-gates-clk", .data = &sun7i_a20_apb1_gates_data,},
1154 {.compatible = "allwinner,sun6i-a31-apb2-gates-clk", .data = &sun6i_a31_apb2_gates_data,},
1155 {.compatible = "allwinner,sun4i-a10-usb-clk", .data = &sun4i_a10_usb_gates_data,},
1156 {.compatible = "allwinner,sun5i-a13-usb-clk", .data = &sun5i_a13_usb_gates_data,},
1157 {.compatible = "allwinner,sun6i-a31-usb-clk", .data = &sun6i_a31_usb_gates_data,},
1161 static void __init of_sunxi_table_clock_setup(const struct of_device_id *clk_match,
1164 struct device_node *np;
1165 const struct div_data *data;
1166 const struct of_device_id *match;
1167 void (*setup_function)(struct device_node *, const void *) = function;
1169 for_each_matching_node_and_match(np, clk_match, &match) {
1171 setup_function(np, data);
1175 static void __init sunxi_init_clocks(const char *clocks[], int nclocks)
1179 /* Register factor clocks */
1180 of_sunxi_table_clock_setup(clk_factors_match, sunxi_factors_clk_setup);
1182 /* Register divider clocks */
1183 of_sunxi_table_clock_setup(clk_div_match, sunxi_divider_clk_setup);
1185 /* Register divided output clocks */
1186 of_sunxi_table_clock_setup(clk_divs_match, sunxi_divs_clk_setup);
1188 /* Register mux clocks */
1189 of_sunxi_table_clock_setup(clk_mux_match, sunxi_mux_clk_setup);
1191 /* Register gate clocks */
1192 of_sunxi_table_clock_setup(clk_gates_match, sunxi_gates_clk_setup);
1194 /* Protect the clocks that needs to stay on */
1195 for (i = 0; i < nclocks; i++) {
1196 struct clk *clk = clk_get(NULL, clocks[i]);
1199 clk_prepare_enable(clk);
1203 static const char *sun4i_a10_critical_clocks[] __initdata = {
1207 static void __init sun4i_a10_init_clocks(struct device_node *node)
1209 sunxi_init_clocks(sun4i_a10_critical_clocks,
1210 ARRAY_SIZE(sun4i_a10_critical_clocks));
1212 CLK_OF_DECLARE(sun4i_a10_clk_init, "allwinner,sun4i-a10", sun4i_a10_init_clocks);
1214 static const char *sun5i_critical_clocks[] __initdata = {
1219 static void __init sun5i_init_clocks(struct device_node *node)
1221 sunxi_init_clocks(sun5i_critical_clocks,
1222 ARRAY_SIZE(sun5i_critical_clocks));
1224 CLK_OF_DECLARE(sun5i_a10s_clk_init, "allwinner,sun5i-a10s", sun5i_init_clocks);
1225 CLK_OF_DECLARE(sun5i_a13_clk_init, "allwinner,sun5i-a13", sun5i_init_clocks);
1226 CLK_OF_DECLARE(sun7i_a20_clk_init, "allwinner,sun7i-a20", sun5i_init_clocks);
1228 static const char *sun6i_critical_clocks[] __initdata = {
1233 static void __init sun6i_init_clocks(struct device_node *node)
1235 sunxi_init_clocks(sun6i_critical_clocks,
1236 ARRAY_SIZE(sun6i_critical_clocks));
1238 CLK_OF_DECLARE(sun6i_a31_clk_init, "allwinner,sun6i-a31", sun6i_init_clocks);