2 * Copyright 2013 Emilio López
4 * Emilio López <emilio@elopez.com.ar>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
17 #include <linux/clk-provider.h>
18 #include <linux/clkdev.h>
20 #include <linux/of_address.h>
21 #include <linux/reset-controller.h>
22 #include <linux/spinlock.h>
24 #include "clk-factors.h"
26 static DEFINE_SPINLOCK(clk_lock);
28 /* Maximum number of parents our clocks have */
29 #define SUNXI_MAX_PARENTS 5
32 * sun4i_get_pll1_factors() - calculates n, k, m, p factors for PLL1
33 * PLL1 rate is calculated as follows
34 * rate = (parent_rate * n * (k + 1) >> p) / (m + 1);
35 * parent_rate is always 24Mhz
38 static void sun4i_get_pll1_factors(u32 *freq, u32 parent_rate,
39 u8 *n, u8 *k, u8 *m, u8 *p)
43 /* Normalize value to a 6M multiple */
44 div = *freq / 6000000;
45 *freq = 6000000 * div;
47 /* we were called to round the frequency, we can now return */
51 /* m is always zero for pll1 */
54 /* k is 1 only on these cases */
55 if (*freq >= 768000000 || *freq == 42000000 || *freq == 54000000)
60 /* p will be 3 for divs under 10 */
64 /* p will be 2 for divs between 10 - 20 and odd divs under 32 */
65 else if (div < 20 || (div < 32 && (div & 1)))
68 /* p will be 1 for even divs under 32, divs under 40 and odd pairs
69 * of divs between 40-62 */
70 else if (div < 40 || (div < 64 && (div & 2)))
73 /* any other entries have p = 0 */
77 /* calculate a suitable n based on k and p */
84 * sun6i_a31_get_pll1_factors() - calculates n, k and m factors for PLL1
85 * PLL1 rate is calculated as follows
86 * rate = parent_rate * (n + 1) * (k + 1) / (m + 1);
87 * parent_rate should always be 24MHz
89 static void sun6i_a31_get_pll1_factors(u32 *freq, u32 parent_rate,
90 u8 *n, u8 *k, u8 *m, u8 *p)
93 * We can operate only on MHz, this will make our life easier
96 u32 freq_mhz = *freq / 1000000;
97 u32 parent_freq_mhz = parent_rate / 1000000;
100 * Round down the frequency to the closest multiple of either
103 u32 round_freq_6 = round_down(freq_mhz, 6);
104 u32 round_freq_16 = round_down(freq_mhz, 16);
106 if (round_freq_6 > round_freq_16)
107 freq_mhz = round_freq_6;
109 freq_mhz = round_freq_16;
111 *freq = freq_mhz * 1000000;
114 * If the factors pointer are null, we were just called to
115 * round down the frequency.
121 /* If the frequency is a multiple of 32 MHz, k is always 3 */
122 if (!(freq_mhz % 32))
124 /* If the frequency is a multiple of 9 MHz, k is always 2 */
125 else if (!(freq_mhz % 9))
127 /* If the frequency is a multiple of 8 MHz, k is always 1 */
128 else if (!(freq_mhz % 8))
130 /* Otherwise, we don't use the k factor */
135 * If the frequency is a multiple of 2 but not a multiple of
136 * 3, m is 3. This is the first time we use 6 here, yet we
137 * will use it on several other places.
138 * We use this number because it's the lowest frequency we can
139 * generate (with n = 0, k = 0, m = 3), so every other frequency
140 * somehow relates to this frequency.
142 if ((freq_mhz % 6) == 2 || (freq_mhz % 6) == 4)
145 * If the frequency is a multiple of 6MHz, but the factor is
148 else if ((freq_mhz / 6) & 1)
150 /* Otherwise, we end up with m = 1 */
154 /* Calculate n thanks to the above factors we already got */
155 *n = freq_mhz * (*m + 1) / ((*k + 1) * parent_freq_mhz) - 1;
158 * If n end up being outbound, and that we can still decrease
161 if ((*n + 1) > 31 && (*m + 1) > 1) {
162 *n = (*n + 1) / 2 - 1;
163 *m = (*m + 1) / 2 - 1;
168 * sun8i_a23_get_pll1_factors() - calculates n, k, m, p factors for PLL1
169 * PLL1 rate is calculated as follows
170 * rate = (parent_rate * (n + 1) * (k + 1) >> p) / (m + 1);
171 * parent_rate is always 24Mhz
174 static void sun8i_a23_get_pll1_factors(u32 *freq, u32 parent_rate,
175 u8 *n, u8 *k, u8 *m, u8 *p)
179 /* Normalize value to a 6M multiple */
180 div = *freq / 6000000;
181 *freq = 6000000 * div;
183 /* we were called to round the frequency, we can now return */
187 /* m is always zero for pll1 */
190 /* k is 1 only on these cases */
191 if (*freq >= 768000000 || *freq == 42000000 || *freq == 54000000)
196 /* p will be 2 for divs under 20 and odd divs under 32 */
197 if (div < 20 || (div < 32 && (div & 1)))
200 /* p will be 1 for even divs under 32, divs under 40 and odd pairs
201 * of divs between 40-62 */
202 else if (div < 40 || (div < 64 && (div & 2)))
205 /* any other entries have p = 0 */
209 /* calculate a suitable n based on k and p */
216 * sun4i_get_pll5_factors() - calculates n, k factors for PLL5
217 * PLL5 rate is calculated as follows
218 * rate = parent_rate * n * (k + 1)
219 * parent_rate is always 24Mhz
222 static void sun4i_get_pll5_factors(u32 *freq, u32 parent_rate,
223 u8 *n, u8 *k, u8 *m, u8 *p)
227 /* Normalize value to a parent_rate multiple (24M) */
228 div = *freq / parent_rate;
229 *freq = parent_rate * div;
231 /* we were called to round the frequency, we can now return */
237 else if (div / 2 < 31)
239 else if (div / 3 < 31)
244 *n = DIV_ROUND_UP(div, (*k+1));
248 * sun6i_a31_get_pll6_factors() - calculates n, k factors for A31 PLL6x2
249 * PLL6x2 rate is calculated as follows
250 * rate = parent_rate * (n + 1) * (k + 1)
251 * parent_rate is always 24Mhz
254 static void sun6i_a31_get_pll6_factors(u32 *freq, u32 parent_rate,
255 u8 *n, u8 *k, u8 *m, u8 *p)
259 /* Normalize value to a parent_rate multiple (24M) */
260 div = *freq / parent_rate;
261 *freq = parent_rate * div;
263 /* we were called to round the frequency, we can now return */
271 *n = DIV_ROUND_UP(div, (*k+1)) - 1;
275 * sun4i_get_apb1_factors() - calculates m, p factors for APB1
276 * APB1 rate is calculated as follows
277 * rate = (parent_rate >> p) / (m + 1);
280 static void sun4i_get_apb1_factors(u32 *freq, u32 parent_rate,
281 u8 *n, u8 *k, u8 *m, u8 *p)
285 if (parent_rate < *freq)
288 parent_rate = DIV_ROUND_UP(parent_rate, *freq);
291 if (parent_rate > 32)
294 if (parent_rate <= 4)
296 else if (parent_rate <= 8)
298 else if (parent_rate <= 16)
303 calcm = (parent_rate >> calcp) - 1;
305 *freq = (parent_rate >> calcp) / (calcm + 1);
307 /* we were called to round the frequency, we can now return */
319 * sun7i_a20_get_out_factors() - calculates m, p factors for CLK_OUT_A/B
320 * CLK_OUT rate is calculated as follows
321 * rate = (parent_rate >> p) / (m + 1);
324 static void sun7i_a20_get_out_factors(u32 *freq, u32 parent_rate,
325 u8 *n, u8 *k, u8 *m, u8 *p)
327 u8 div, calcm, calcp;
329 /* These clocks can only divide, so we will never be able to achieve
330 * frequencies higher than the parent frequency */
331 if (*freq > parent_rate)
334 div = DIV_ROUND_UP(parent_rate, *freq);
338 else if (div / 2 < 32)
340 else if (div / 4 < 32)
345 calcm = DIV_ROUND_UP(div, 1 << calcp);
347 *freq = (parent_rate >> calcp) / calcm;
349 /* we were called to round the frequency, we can now return */
358 * clk_sunxi_mmc_phase_control() - configures MMC clock phase control
361 void clk_sunxi_mmc_phase_control(struct clk *clk, u8 sample, u8 output)
363 #define to_clk_composite(_hw) container_of(_hw, struct clk_composite, hw)
364 #define to_clk_factors(_hw) container_of(_hw, struct clk_factors, hw)
366 struct clk_hw *hw = __clk_get_hw(clk);
367 struct clk_composite *composite = to_clk_composite(hw);
368 struct clk_hw *rate_hw = composite->rate_hw;
369 struct clk_factors *factors = to_clk_factors(rate_hw);
370 unsigned long flags = 0;
374 spin_lock_irqsave(factors->lock, flags);
376 reg = readl(factors->reg);
378 /* set sample clock phase control */
380 reg |= ((sample & 0x7) << 20);
382 /* set output clock phase control */
384 reg |= ((output & 0x7) << 8);
386 writel(reg, factors->reg);
389 spin_unlock_irqrestore(factors->lock, flags);
391 EXPORT_SYMBOL(clk_sunxi_mmc_phase_control);
395 * sunxi_factors_clk_setup() - Setup function for factor clocks
398 static struct clk_factors_config sun4i_pll1_config = {
409 static struct clk_factors_config sun6i_a31_pll1_config = {
418 static struct clk_factors_config sun8i_a23_pll1_config = {
430 static struct clk_factors_config sun4i_pll5_config = {
437 static struct clk_factors_config sun6i_a31_pll6_config = {
445 static struct clk_factors_config sun4i_apb1_config = {
452 /* user manual says "n" but it's really "p" */
453 static struct clk_factors_config sun7i_a20_out_config = {
460 static const struct factors_data sun4i_pll1_data __initconst = {
462 .table = &sun4i_pll1_config,
463 .getter = sun4i_get_pll1_factors,
466 static const struct factors_data sun6i_a31_pll1_data __initconst = {
468 .table = &sun6i_a31_pll1_config,
469 .getter = sun6i_a31_get_pll1_factors,
472 static const struct factors_data sun8i_a23_pll1_data __initconst = {
474 .table = &sun8i_a23_pll1_config,
475 .getter = sun8i_a23_get_pll1_factors,
478 static const struct factors_data sun7i_a20_pll4_data __initconst = {
480 .table = &sun4i_pll5_config,
481 .getter = sun4i_get_pll5_factors,
484 static const struct factors_data sun4i_pll5_data __initconst = {
486 .table = &sun4i_pll5_config,
487 .getter = sun4i_get_pll5_factors,
491 static const struct factors_data sun4i_pll6_data __initconst = {
493 .table = &sun4i_pll5_config,
494 .getter = sun4i_get_pll5_factors,
498 static const struct factors_data sun6i_a31_pll6_data __initconst = {
500 .table = &sun6i_a31_pll6_config,
501 .getter = sun6i_a31_get_pll6_factors,
505 static const struct factors_data sun4i_apb1_data __initconst = {
507 .muxmask = BIT(1) | BIT(0),
508 .table = &sun4i_apb1_config,
509 .getter = sun4i_get_apb1_factors,
512 static const struct factors_data sun7i_a20_out_data __initconst = {
515 .muxmask = BIT(1) | BIT(0),
516 .table = &sun7i_a20_out_config,
517 .getter = sun7i_a20_get_out_factors,
520 static struct clk * __init sunxi_factors_clk_setup(struct device_node *node,
521 const struct factors_data *data)
523 return sunxi_factors_register(node, data, &clk_lock);
529 * sunxi_mux_clk_setup() - Setup function for muxes
532 #define SUNXI_MUX_GATE_WIDTH 2
538 static const struct mux_data sun4i_cpu_mux_data __initconst = {
542 static const struct mux_data sun6i_a31_ahb1_mux_data __initconst = {
546 static void __init sunxi_mux_clk_setup(struct device_node *node,
547 struct mux_data *data)
550 const char *clk_name = node->name;
551 const char *parents[SUNXI_MAX_PARENTS];
555 reg = of_iomap(node, 0);
557 while (i < SUNXI_MAX_PARENTS &&
558 (parents[i] = of_clk_get_parent_name(node, i)) != NULL)
561 of_property_read_string(node, "clock-output-names", &clk_name);
563 clk = clk_register_mux(NULL, clk_name, parents, i,
564 CLK_SET_RATE_NO_REPARENT, reg,
565 data->shift, SUNXI_MUX_GATE_WIDTH,
569 of_clk_add_provider(node, of_clk_src_simple_get, clk);
570 clk_register_clkdev(clk, clk_name, NULL);
577 * sunxi_divider_clk_setup() - Setup function for simple divider clocks
584 const struct clk_div_table *table;
587 static const struct div_data sun4i_axi_data __initconst = {
593 static const struct clk_div_table sun8i_a23_axi_table[] __initconst = {
594 { .val = 0, .div = 1 },
595 { .val = 1, .div = 2 },
596 { .val = 2, .div = 3 },
597 { .val = 3, .div = 4 },
598 { .val = 4, .div = 4 },
599 { .val = 5, .div = 4 },
600 { .val = 6, .div = 4 },
601 { .val = 7, .div = 4 },
605 static const struct div_data sun8i_a23_axi_data __initconst = {
607 .table = sun8i_a23_axi_table,
610 static const struct div_data sun4i_ahb_data __initconst = {
616 static const struct clk_div_table sun4i_apb0_table[] __initconst = {
617 { .val = 0, .div = 2 },
618 { .val = 1, .div = 2 },
619 { .val = 2, .div = 4 },
620 { .val = 3, .div = 8 },
624 static const struct div_data sun4i_apb0_data __initconst = {
628 .table = sun4i_apb0_table,
631 static void __init sunxi_divider_clk_setup(struct device_node *node,
632 struct div_data *data)
635 const char *clk_name = node->name;
636 const char *clk_parent;
639 reg = of_iomap(node, 0);
641 clk_parent = of_clk_get_parent_name(node, 0);
643 of_property_read_string(node, "clock-output-names", &clk_name);
645 clk = clk_register_divider_table(NULL, clk_name, clk_parent, 0,
646 reg, data->shift, data->width,
647 data->pow ? CLK_DIVIDER_POWER_OF_TWO : 0,
648 data->table, &clk_lock);
650 of_clk_add_provider(node, of_clk_src_simple_get, clk);
651 clk_register_clkdev(clk, clk_name, NULL);
658 * sunxi_gates_reset... - reset bits in leaf gate clk registers handling
661 struct gates_reset_data {
664 struct reset_controller_dev rcdev;
667 static int sunxi_gates_reset_assert(struct reset_controller_dev *rcdev,
670 struct gates_reset_data *data = container_of(rcdev,
671 struct gates_reset_data,
676 spin_lock_irqsave(data->lock, flags);
678 reg = readl(data->reg);
679 writel(reg & ~BIT(id), data->reg);
681 spin_unlock_irqrestore(data->lock, flags);
686 static int sunxi_gates_reset_deassert(struct reset_controller_dev *rcdev,
689 struct gates_reset_data *data = container_of(rcdev,
690 struct gates_reset_data,
695 spin_lock_irqsave(data->lock, flags);
697 reg = readl(data->reg);
698 writel(reg | BIT(id), data->reg);
700 spin_unlock_irqrestore(data->lock, flags);
705 static struct reset_control_ops sunxi_gates_reset_ops = {
706 .assert = sunxi_gates_reset_assert,
707 .deassert = sunxi_gates_reset_deassert,
711 * sunxi_gates_clk_setup() - Setup function for leaf gates on clocks
714 #define SUNXI_GATES_MAX_SIZE 64
717 DECLARE_BITMAP(mask, SUNXI_GATES_MAX_SIZE);
721 static const struct gates_data sun4i_axi_gates_data __initconst = {
725 static const struct gates_data sun4i_ahb_gates_data __initconst = {
726 .mask = {0x7F77FFF, 0x14FB3F},
729 static const struct gates_data sun5i_a10s_ahb_gates_data __initconst = {
730 .mask = {0x147667e7, 0x185915},
733 static const struct gates_data sun5i_a13_ahb_gates_data __initconst = {
734 .mask = {0x107067e7, 0x185111},
737 static const struct gates_data sun6i_a31_ahb1_gates_data __initconst = {
738 .mask = {0xEDFE7F62, 0x794F931},
741 static const struct gates_data sun7i_a20_ahb_gates_data __initconst = {
742 .mask = { 0x12f77fff, 0x16ff3f },
745 static const struct gates_data sun8i_a23_ahb1_gates_data __initconst = {
746 .mask = {0x25386742, 0x2505111},
749 static const struct gates_data sun9i_a80_ahb0_gates_data __initconst = {
753 static const struct gates_data sun9i_a80_ahb1_gates_data __initconst = {
757 static const struct gates_data sun9i_a80_ahb2_gates_data __initconst = {
761 static const struct gates_data sun4i_apb0_gates_data __initconst = {
765 static const struct gates_data sun5i_a10s_apb0_gates_data __initconst = {
769 static const struct gates_data sun5i_a13_apb0_gates_data __initconst = {
773 static const struct gates_data sun7i_a20_apb0_gates_data __initconst = {
777 static const struct gates_data sun9i_a80_apb0_gates_data __initconst = {
781 static const struct gates_data sun4i_apb1_gates_data __initconst = {
785 static const struct gates_data sun5i_a10s_apb1_gates_data __initconst = {
789 static const struct gates_data sun5i_a13_apb1_gates_data __initconst = {
793 static const struct gates_data sun6i_a31_apb1_gates_data __initconst = {
797 static const struct gates_data sun8i_a23_apb1_gates_data __initconst = {
801 static const struct gates_data sun6i_a31_apb2_gates_data __initconst = {
805 static const struct gates_data sun7i_a20_apb1_gates_data __initconst = {
806 .mask = { 0xff80ff },
809 static const struct gates_data sun9i_a80_apb1_gates_data __initconst = {
813 static const struct gates_data sun8i_a23_apb2_gates_data __initconst = {
817 static const struct gates_data sun4i_a10_usb_gates_data __initconst = {
822 static const struct gates_data sun5i_a13_usb_gates_data __initconst = {
827 static const struct gates_data sun6i_a31_usb_gates_data __initconst = {
828 .mask = { BIT(18) | BIT(17) | BIT(16) | BIT(10) | BIT(9) | BIT(8) },
829 .reset_mask = BIT(2) | BIT(1) | BIT(0),
832 static void __init sunxi_gates_clk_setup(struct device_node *node,
833 struct gates_data *data)
835 struct clk_onecell_data *clk_data;
836 struct gates_reset_data *reset_data;
837 const char *clk_parent;
838 const char *clk_name;
844 reg = of_iomap(node, 0);
846 clk_parent = of_clk_get_parent_name(node, 0);
848 /* Worst-case size approximation and memory allocation */
849 qty = find_last_bit(data->mask, SUNXI_GATES_MAX_SIZE);
850 clk_data = kmalloc(sizeof(struct clk_onecell_data), GFP_KERNEL);
853 clk_data->clks = kzalloc((qty+1) * sizeof(struct clk *), GFP_KERNEL);
854 if (!clk_data->clks) {
859 for_each_set_bit(i, data->mask, SUNXI_GATES_MAX_SIZE) {
860 of_property_read_string_index(node, "clock-output-names",
863 clk_data->clks[i] = clk_register_gate(NULL, clk_name,
865 reg + 4 * (i/32), i % 32,
867 WARN_ON(IS_ERR(clk_data->clks[i]));
868 clk_register_clkdev(clk_data->clks[i], clk_name, NULL);
873 /* Adjust to the real max */
874 clk_data->clk_num = i;
876 of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
878 /* Register a reset controler for gates with reset bits */
879 if (data->reset_mask == 0)
882 reset_data = kzalloc(sizeof(*reset_data), GFP_KERNEL);
886 reset_data->reg = reg;
887 reset_data->lock = &clk_lock;
888 reset_data->rcdev.nr_resets = __fls(data->reset_mask) + 1;
889 reset_data->rcdev.ops = &sunxi_gates_reset_ops;
890 reset_data->rcdev.of_node = node;
891 reset_controller_register(&reset_data->rcdev);
897 * sunxi_divs_clk_setup() helper data
900 #define SUNXI_DIVS_MAX_QTY 2
901 #define SUNXI_DIVISOR_WIDTH 2
904 const struct factors_data *factors; /* data for the factor clock */
905 int ndivs; /* number of children */
907 u8 fixed; /* is it a fixed divisor? if not... */
908 struct clk_div_table *table; /* is it a table based divisor? */
909 u8 shift; /* otherwise it's a normal divisor with this shift */
910 u8 pow; /* is it power-of-two based? */
911 u8 gate; /* is it independently gateable? */
912 } div[SUNXI_DIVS_MAX_QTY];
915 static struct clk_div_table pll6_sata_tbl[] = {
916 { .val = 0, .div = 6, },
917 { .val = 1, .div = 12, },
918 { .val = 2, .div = 18, },
919 { .val = 3, .div = 24, },
923 static const struct divs_data pll5_divs_data __initconst = {
924 .factors = &sun4i_pll5_data,
927 { .shift = 0, .pow = 0, }, /* M, DDR */
928 { .shift = 16, .pow = 1, }, /* P, other */
932 static const struct divs_data pll6_divs_data __initconst = {
933 .factors = &sun4i_pll6_data,
936 { .shift = 0, .table = pll6_sata_tbl, .gate = 14 }, /* M, SATA */
937 { .fixed = 2 }, /* P, other */
941 static const struct divs_data sun6i_a31_pll6_divs_data __initconst = {
942 .factors = &sun6i_a31_pll6_data,
945 { .fixed = 2 }, /* normal output */
950 * sunxi_divs_clk_setup() - Setup function for leaf divisors on clocks
952 * These clocks look something like this
953 * ________________________
954 * | ___divisor 1---|----> to consumer
955 * parent >--| pll___/___divisor 2---|----> to consumer
956 * | \_______________|____> to consumer
957 * |________________________|
960 static void __init sunxi_divs_clk_setup(struct device_node *node,
961 struct divs_data *data)
963 struct clk_onecell_data *clk_data;
965 const char *clk_name;
966 struct clk **clks, *pclk;
967 struct clk_hw *gate_hw, *rate_hw;
968 const struct clk_ops *rate_ops;
969 struct clk_gate *gate = NULL;
970 struct clk_fixed_factor *fix_factor;
971 struct clk_divider *divider;
973 int ndivs = SUNXI_DIVS_MAX_QTY, i = 0;
976 /* Set up factor clock that we will be dividing */
977 pclk = sunxi_factors_clk_setup(node, data->factors);
978 parent = __clk_get_name(pclk);
980 reg = of_iomap(node, 0);
982 clk_data = kmalloc(sizeof(struct clk_onecell_data), GFP_KERNEL);
986 clks = kzalloc((SUNXI_DIVS_MAX_QTY+1) * sizeof(*clks), GFP_KERNEL);
990 clk_data->clks = clks;
992 /* It's not a good idea to have automatic reparenting changing
994 clkflags = !strcmp("pll5", parent) ? 0 : CLK_SET_RATE_PARENT;
996 /* if number of children known, use it */
1000 for (i = 0; i < ndivs; i++) {
1001 if (of_property_read_string_index(node, "clock-output-names",
1009 /* If this leaf clock can be gated, create a gate */
1010 if (data->div[i].gate) {
1011 gate = kzalloc(sizeof(*gate), GFP_KERNEL);
1016 gate->bit_idx = data->div[i].gate;
1017 gate->lock = &clk_lock;
1019 gate_hw = &gate->hw;
1022 /* Leaves can be fixed or configurable divisors */
1023 if (data->div[i].fixed) {
1024 fix_factor = kzalloc(sizeof(*fix_factor), GFP_KERNEL);
1028 fix_factor->mult = 1;
1029 fix_factor->div = data->div[i].fixed;
1031 rate_hw = &fix_factor->hw;
1032 rate_ops = &clk_fixed_factor_ops;
1034 divider = kzalloc(sizeof(*divider), GFP_KERNEL);
1038 flags = data->div[i].pow ? CLK_DIVIDER_POWER_OF_TWO : 0;
1041 divider->shift = data->div[i].shift;
1042 divider->width = SUNXI_DIVISOR_WIDTH;
1043 divider->flags = flags;
1044 divider->lock = &clk_lock;
1045 divider->table = data->div[i].table;
1047 rate_hw = ÷r->hw;
1048 rate_ops = &clk_divider_ops;
1051 /* Wrap the (potential) gate and the divisor on a composite
1052 * clock to unify them */
1053 clks[i] = clk_register_composite(NULL, clk_name, &parent, 1,
1056 gate_hw, &clk_gate_ops,
1059 WARN_ON(IS_ERR(clk_data->clks[i]));
1060 clk_register_clkdev(clks[i], clk_name, NULL);
1063 /* The last clock available on the getter is the parent */
1066 /* Adjust to the real max */
1067 clk_data->clk_num = i;
1069 of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
1083 /* Matches for factors clocks */
1084 static const struct of_device_id clk_factors_match[] __initconst = {
1085 {.compatible = "allwinner,sun4i-a10-pll1-clk", .data = &sun4i_pll1_data,},
1086 {.compatible = "allwinner,sun6i-a31-pll1-clk", .data = &sun6i_a31_pll1_data,},
1087 {.compatible = "allwinner,sun8i-a23-pll1-clk", .data = &sun8i_a23_pll1_data,},
1088 {.compatible = "allwinner,sun7i-a20-pll4-clk", .data = &sun7i_a20_pll4_data,},
1089 {.compatible = "allwinner,sun4i-a10-apb1-clk", .data = &sun4i_apb1_data,},
1090 {.compatible = "allwinner,sun7i-a20-out-clk", .data = &sun7i_a20_out_data,},
1094 /* Matches for divider clocks */
1095 static const struct of_device_id clk_div_match[] __initconst = {
1096 {.compatible = "allwinner,sun4i-a10-axi-clk", .data = &sun4i_axi_data,},
1097 {.compatible = "allwinner,sun8i-a23-axi-clk", .data = &sun8i_a23_axi_data,},
1098 {.compatible = "allwinner,sun4i-a10-ahb-clk", .data = &sun4i_ahb_data,},
1099 {.compatible = "allwinner,sun4i-a10-apb0-clk", .data = &sun4i_apb0_data,},
1103 /* Matches for divided outputs */
1104 static const struct of_device_id clk_divs_match[] __initconst = {
1105 {.compatible = "allwinner,sun4i-a10-pll5-clk", .data = &pll5_divs_data,},
1106 {.compatible = "allwinner,sun4i-a10-pll6-clk", .data = &pll6_divs_data,},
1107 {.compatible = "allwinner,sun6i-a31-pll6-clk", .data = &sun6i_a31_pll6_divs_data,},
1111 /* Matches for mux clocks */
1112 static const struct of_device_id clk_mux_match[] __initconst = {
1113 {.compatible = "allwinner,sun4i-a10-cpu-clk", .data = &sun4i_cpu_mux_data,},
1114 {.compatible = "allwinner,sun6i-a31-ahb1-mux-clk", .data = &sun6i_a31_ahb1_mux_data,},
1118 /* Matches for gate clocks */
1119 static const struct of_device_id clk_gates_match[] __initconst = {
1120 {.compatible = "allwinner,sun4i-a10-axi-gates-clk", .data = &sun4i_axi_gates_data,},
1121 {.compatible = "allwinner,sun4i-a10-ahb-gates-clk", .data = &sun4i_ahb_gates_data,},
1122 {.compatible = "allwinner,sun5i-a10s-ahb-gates-clk", .data = &sun5i_a10s_ahb_gates_data,},
1123 {.compatible = "allwinner,sun5i-a13-ahb-gates-clk", .data = &sun5i_a13_ahb_gates_data,},
1124 {.compatible = "allwinner,sun6i-a31-ahb1-gates-clk", .data = &sun6i_a31_ahb1_gates_data,},
1125 {.compatible = "allwinner,sun7i-a20-ahb-gates-clk", .data = &sun7i_a20_ahb_gates_data,},
1126 {.compatible = "allwinner,sun8i-a23-ahb1-gates-clk", .data = &sun8i_a23_ahb1_gates_data,},
1127 {.compatible = "allwinner,sun9i-a80-ahb0-gates-clk", .data = &sun9i_a80_ahb0_gates_data,},
1128 {.compatible = "allwinner,sun9i-a80-ahb1-gates-clk", .data = &sun9i_a80_ahb1_gates_data,},
1129 {.compatible = "allwinner,sun9i-a80-ahb2-gates-clk", .data = &sun9i_a80_ahb2_gates_data,},
1130 {.compatible = "allwinner,sun4i-a10-apb0-gates-clk", .data = &sun4i_apb0_gates_data,},
1131 {.compatible = "allwinner,sun5i-a10s-apb0-gates-clk", .data = &sun5i_a10s_apb0_gates_data,},
1132 {.compatible = "allwinner,sun5i-a13-apb0-gates-clk", .data = &sun5i_a13_apb0_gates_data,},
1133 {.compatible = "allwinner,sun7i-a20-apb0-gates-clk", .data = &sun7i_a20_apb0_gates_data,},
1134 {.compatible = "allwinner,sun9i-a80-apb0-gates-clk", .data = &sun9i_a80_apb0_gates_data,},
1135 {.compatible = "allwinner,sun4i-a10-apb1-gates-clk", .data = &sun4i_apb1_gates_data,},
1136 {.compatible = "allwinner,sun5i-a10s-apb1-gates-clk", .data = &sun5i_a10s_apb1_gates_data,},
1137 {.compatible = "allwinner,sun5i-a13-apb1-gates-clk", .data = &sun5i_a13_apb1_gates_data,},
1138 {.compatible = "allwinner,sun6i-a31-apb1-gates-clk", .data = &sun6i_a31_apb1_gates_data,},
1139 {.compatible = "allwinner,sun7i-a20-apb1-gates-clk", .data = &sun7i_a20_apb1_gates_data,},
1140 {.compatible = "allwinner,sun8i-a23-apb1-gates-clk", .data = &sun8i_a23_apb1_gates_data,},
1141 {.compatible = "allwinner,sun9i-a80-apb1-gates-clk", .data = &sun9i_a80_apb1_gates_data,},
1142 {.compatible = "allwinner,sun6i-a31-apb2-gates-clk", .data = &sun6i_a31_apb2_gates_data,},
1143 {.compatible = "allwinner,sun8i-a23-apb2-gates-clk", .data = &sun8i_a23_apb2_gates_data,},
1144 {.compatible = "allwinner,sun4i-a10-usb-clk", .data = &sun4i_a10_usb_gates_data,},
1145 {.compatible = "allwinner,sun5i-a13-usb-clk", .data = &sun5i_a13_usb_gates_data,},
1146 {.compatible = "allwinner,sun6i-a31-usb-clk", .data = &sun6i_a31_usb_gates_data,},
1150 static void __init of_sunxi_table_clock_setup(const struct of_device_id *clk_match,
1153 struct device_node *np;
1154 const struct div_data *data;
1155 const struct of_device_id *match;
1156 void (*setup_function)(struct device_node *, const void *) = function;
1158 for_each_matching_node_and_match(np, clk_match, &match) {
1160 setup_function(np, data);
1164 static void __init sunxi_init_clocks(const char *clocks[], int nclocks)
1168 /* Register factor clocks */
1169 of_sunxi_table_clock_setup(clk_factors_match, sunxi_factors_clk_setup);
1171 /* Register divider clocks */
1172 of_sunxi_table_clock_setup(clk_div_match, sunxi_divider_clk_setup);
1174 /* Register divided output clocks */
1175 of_sunxi_table_clock_setup(clk_divs_match, sunxi_divs_clk_setup);
1177 /* Register mux clocks */
1178 of_sunxi_table_clock_setup(clk_mux_match, sunxi_mux_clk_setup);
1180 /* Register gate clocks */
1181 of_sunxi_table_clock_setup(clk_gates_match, sunxi_gates_clk_setup);
1183 /* Protect the clocks that needs to stay on */
1184 for (i = 0; i < nclocks; i++) {
1185 struct clk *clk = clk_get(NULL, clocks[i]);
1188 clk_prepare_enable(clk);
1192 static const char *sun4i_a10_critical_clocks[] __initdata = {
1197 static void __init sun4i_a10_init_clocks(struct device_node *node)
1199 sunxi_init_clocks(sun4i_a10_critical_clocks,
1200 ARRAY_SIZE(sun4i_a10_critical_clocks));
1202 CLK_OF_DECLARE(sun4i_a10_clk_init, "allwinner,sun4i-a10", sun4i_a10_init_clocks);
1204 static const char *sun5i_critical_clocks[] __initdata = {
1209 static void __init sun5i_init_clocks(struct device_node *node)
1211 sunxi_init_clocks(sun5i_critical_clocks,
1212 ARRAY_SIZE(sun5i_critical_clocks));
1214 CLK_OF_DECLARE(sun5i_a10s_clk_init, "allwinner,sun5i-a10s", sun5i_init_clocks);
1215 CLK_OF_DECLARE(sun5i_a13_clk_init, "allwinner,sun5i-a13", sun5i_init_clocks);
1216 CLK_OF_DECLARE(sun7i_a20_clk_init, "allwinner,sun7i-a20", sun5i_init_clocks);
1218 static const char *sun6i_critical_clocks[] __initdata = {
1223 static void __init sun6i_init_clocks(struct device_node *node)
1225 sunxi_init_clocks(sun6i_critical_clocks,
1226 ARRAY_SIZE(sun6i_critical_clocks));
1228 CLK_OF_DECLARE(sun6i_a31_clk_init, "allwinner,sun6i-a31", sun6i_init_clocks);
1229 CLK_OF_DECLARE(sun6i_a31s_clk_init, "allwinner,sun6i-a31s", sun6i_init_clocks);
1230 CLK_OF_DECLARE(sun8i_a23_clk_init, "allwinner,sun8i-a23", sun6i_init_clocks);
1232 static void __init sun9i_init_clocks(struct device_node *node)
1234 sunxi_init_clocks(NULL, 0);
1236 CLK_OF_DECLARE(sun9i_a80_clk_init, "allwinner,sun9i-a80", sun9i_init_clocks);