2 * Copyright 2013 Emilio López
4 * Emilio López <emilio@elopez.com.ar>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
17 #include <linux/clk-provider.h>
18 #include <linux/clkdev.h>
20 #include <linux/of_address.h>
21 #include <linux/reset-controller.h>
22 #include <linux/spinlock.h>
23 #include <linux/log2.h>
25 #include "clk-factors.h"
27 static DEFINE_SPINLOCK(clk_lock);
30 * sun6i_a31_ahb1_clk_setup() - Setup function for a31 ahb1 composite clk
33 #define SUN6I_AHB1_MAX_PARENTS 4
34 #define SUN6I_AHB1_MUX_PARENT_PLL6 3
35 #define SUN6I_AHB1_MUX_SHIFT 12
36 /* un-shifted mask is what mux_clk expects */
37 #define SUN6I_AHB1_MUX_MASK 0x3
38 #define SUN6I_AHB1_MUX_GET_PARENT(reg) ((reg >> SUN6I_AHB1_MUX_SHIFT) & \
41 #define SUN6I_AHB1_DIV_SHIFT 4
42 #define SUN6I_AHB1_DIV_MASK (0x3 << SUN6I_AHB1_DIV_SHIFT)
43 #define SUN6I_AHB1_DIV_GET(reg) ((reg & SUN6I_AHB1_DIV_MASK) >> \
45 #define SUN6I_AHB1_DIV_SET(reg, div) ((reg & ~SUN6I_AHB1_DIV_MASK) | \
46 (div << SUN6I_AHB1_DIV_SHIFT))
47 #define SUN6I_AHB1_PLL6_DIV_SHIFT 6
48 #define SUN6I_AHB1_PLL6_DIV_MASK (0x3 << SUN6I_AHB1_PLL6_DIV_SHIFT)
49 #define SUN6I_AHB1_PLL6_DIV_GET(reg) ((reg & SUN6I_AHB1_PLL6_DIV_MASK) >> \
50 SUN6I_AHB1_PLL6_DIV_SHIFT)
51 #define SUN6I_AHB1_PLL6_DIV_SET(reg, div) ((reg & ~SUN6I_AHB1_PLL6_DIV_MASK) | \
52 (div << SUN6I_AHB1_PLL6_DIV_SHIFT))
54 struct sun6i_ahb1_clk {
59 #define to_sun6i_ahb1_clk(_hw) container_of(_hw, struct sun6i_ahb1_clk, hw)
61 static unsigned long sun6i_ahb1_clk_recalc_rate(struct clk_hw *hw,
62 unsigned long parent_rate)
64 struct sun6i_ahb1_clk *ahb1 = to_sun6i_ahb1_clk(hw);
68 /* Fetch the register value */
69 reg = readl(ahb1->reg);
71 /* apply pre-divider first if parent is pll6 */
72 if (SUN6I_AHB1_MUX_GET_PARENT(reg) == SUN6I_AHB1_MUX_PARENT_PLL6)
73 parent_rate /= SUN6I_AHB1_PLL6_DIV_GET(reg) + 1;
76 rate = parent_rate >> SUN6I_AHB1_DIV_GET(reg);
81 static long sun6i_ahb1_clk_round(unsigned long rate, u8 *divp, u8 *pre_divp,
82 u8 parent, unsigned long parent_rate)
84 u8 div, calcp, calcm = 1;
87 * clock can only divide, so we will never be able to achieve
88 * frequencies higher than the parent frequency
90 if (parent_rate && rate > parent_rate)
93 div = DIV_ROUND_UP(parent_rate, rate);
95 /* calculate pre-divider if parent is pll6 */
96 if (parent == SUN6I_AHB1_MUX_PARENT_PLL6) {
101 else if (div / 4 < 4)
106 calcm = DIV_ROUND_UP(div, 1 << calcp);
108 calcp = __roundup_pow_of_two(div);
109 calcp = calcp > 3 ? 3 : calcp;
112 /* we were asked to pass back divider values */
115 *pre_divp = calcm - 1;
118 return (parent_rate / calcm) >> calcp;
121 static long sun6i_ahb1_clk_determine_rate(struct clk_hw *hw, unsigned long rate,
122 unsigned long min_rate,
123 unsigned long max_rate,
124 unsigned long *best_parent_rate,
125 struct clk_hw **best_parent_clk)
127 struct clk *clk = hw->clk, *parent, *best_parent = NULL;
129 unsigned long parent_rate, best = 0, child_rate, best_child_rate = 0;
131 /* find the parent that can help provide the fastest rate <= rate */
132 num_parents = __clk_get_num_parents(clk);
133 for (i = 0; i < num_parents; i++) {
134 parent = clk_get_parent_by_index(clk, i);
137 if (__clk_get_flags(clk) & CLK_SET_RATE_PARENT)
138 parent_rate = __clk_round_rate(parent, rate);
140 parent_rate = __clk_get_rate(parent);
142 child_rate = sun6i_ahb1_clk_round(rate, NULL, NULL, i,
145 if (child_rate <= rate && child_rate > best_child_rate) {
146 best_parent = parent;
148 best_child_rate = child_rate;
153 *best_parent_clk = __clk_get_hw(best_parent);
154 *best_parent_rate = best;
156 return best_child_rate;
159 static int sun6i_ahb1_clk_set_rate(struct clk_hw *hw, unsigned long rate,
160 unsigned long parent_rate)
162 struct sun6i_ahb1_clk *ahb1 = to_sun6i_ahb1_clk(hw);
164 u8 div, pre_div, parent;
167 spin_lock_irqsave(&clk_lock, flags);
169 reg = readl(ahb1->reg);
171 /* need to know which parent is used to apply pre-divider */
172 parent = SUN6I_AHB1_MUX_GET_PARENT(reg);
173 sun6i_ahb1_clk_round(rate, &div, &pre_div, parent, parent_rate);
175 reg = SUN6I_AHB1_DIV_SET(reg, div);
176 reg = SUN6I_AHB1_PLL6_DIV_SET(reg, pre_div);
177 writel(reg, ahb1->reg);
179 spin_unlock_irqrestore(&clk_lock, flags);
184 static const struct clk_ops sun6i_ahb1_clk_ops = {
185 .determine_rate = sun6i_ahb1_clk_determine_rate,
186 .recalc_rate = sun6i_ahb1_clk_recalc_rate,
187 .set_rate = sun6i_ahb1_clk_set_rate,
190 static void __init sun6i_ahb1_clk_setup(struct device_node *node)
193 struct sun6i_ahb1_clk *ahb1;
195 const char *clk_name = node->name;
196 const char *parents[SUN6I_AHB1_MAX_PARENTS];
200 reg = of_io_request_and_map(node, 0, of_node_full_name(node));
202 /* we have a mux, we will have >1 parents */
203 while (i < SUN6I_AHB1_MAX_PARENTS &&
204 (parents[i] = of_clk_get_parent_name(node, i)) != NULL)
207 of_property_read_string(node, "clock-output-names", &clk_name);
209 ahb1 = kzalloc(sizeof(struct sun6i_ahb1_clk), GFP_KERNEL);
213 mux = kzalloc(sizeof(struct clk_mux), GFP_KERNEL);
219 /* set up clock properties */
221 mux->shift = SUN6I_AHB1_MUX_SHIFT;
222 mux->mask = SUN6I_AHB1_MUX_MASK;
223 mux->lock = &clk_lock;
226 clk = clk_register_composite(NULL, clk_name, parents, i,
227 &mux->hw, &clk_mux_ops,
228 &ahb1->hw, &sun6i_ahb1_clk_ops,
232 of_clk_add_provider(node, of_clk_src_simple_get, clk);
233 clk_register_clkdev(clk, clk_name, NULL);
236 CLK_OF_DECLARE(sun6i_a31_ahb1, "allwinner,sun6i-a31-ahb1-clk", sun6i_ahb1_clk_setup);
238 /* Maximum number of parents our clocks have */
239 #define SUNXI_MAX_PARENTS 5
242 * sun4i_get_pll1_factors() - calculates n, k, m, p factors for PLL1
243 * PLL1 rate is calculated as follows
244 * rate = (parent_rate * n * (k + 1) >> p) / (m + 1);
245 * parent_rate is always 24Mhz
248 static void sun4i_get_pll1_factors(u32 *freq, u32 parent_rate,
249 u8 *n, u8 *k, u8 *m, u8 *p)
253 /* Normalize value to a 6M multiple */
254 div = *freq / 6000000;
255 *freq = 6000000 * div;
257 /* we were called to round the frequency, we can now return */
261 /* m is always zero for pll1 */
264 /* k is 1 only on these cases */
265 if (*freq >= 768000000 || *freq == 42000000 || *freq == 54000000)
270 /* p will be 3 for divs under 10 */
274 /* p will be 2 for divs between 10 - 20 and odd divs under 32 */
275 else if (div < 20 || (div < 32 && (div & 1)))
278 /* p will be 1 for even divs under 32, divs under 40 and odd pairs
279 * of divs between 40-62 */
280 else if (div < 40 || (div < 64 && (div & 2)))
283 /* any other entries have p = 0 */
287 /* calculate a suitable n based on k and p */
294 * sun6i_a31_get_pll1_factors() - calculates n, k and m factors for PLL1
295 * PLL1 rate is calculated as follows
296 * rate = parent_rate * (n + 1) * (k + 1) / (m + 1);
297 * parent_rate should always be 24MHz
299 static void sun6i_a31_get_pll1_factors(u32 *freq, u32 parent_rate,
300 u8 *n, u8 *k, u8 *m, u8 *p)
303 * We can operate only on MHz, this will make our life easier
306 u32 freq_mhz = *freq / 1000000;
307 u32 parent_freq_mhz = parent_rate / 1000000;
310 * Round down the frequency to the closest multiple of either
313 u32 round_freq_6 = round_down(freq_mhz, 6);
314 u32 round_freq_16 = round_down(freq_mhz, 16);
316 if (round_freq_6 > round_freq_16)
317 freq_mhz = round_freq_6;
319 freq_mhz = round_freq_16;
321 *freq = freq_mhz * 1000000;
324 * If the factors pointer are null, we were just called to
325 * round down the frequency.
331 /* If the frequency is a multiple of 32 MHz, k is always 3 */
332 if (!(freq_mhz % 32))
334 /* If the frequency is a multiple of 9 MHz, k is always 2 */
335 else if (!(freq_mhz % 9))
337 /* If the frequency is a multiple of 8 MHz, k is always 1 */
338 else if (!(freq_mhz % 8))
340 /* Otherwise, we don't use the k factor */
345 * If the frequency is a multiple of 2 but not a multiple of
346 * 3, m is 3. This is the first time we use 6 here, yet we
347 * will use it on several other places.
348 * We use this number because it's the lowest frequency we can
349 * generate (with n = 0, k = 0, m = 3), so every other frequency
350 * somehow relates to this frequency.
352 if ((freq_mhz % 6) == 2 || (freq_mhz % 6) == 4)
355 * If the frequency is a multiple of 6MHz, but the factor is
358 else if ((freq_mhz / 6) & 1)
360 /* Otherwise, we end up with m = 1 */
364 /* Calculate n thanks to the above factors we already got */
365 *n = freq_mhz * (*m + 1) / ((*k + 1) * parent_freq_mhz) - 1;
368 * If n end up being outbound, and that we can still decrease
371 if ((*n + 1) > 31 && (*m + 1) > 1) {
372 *n = (*n + 1) / 2 - 1;
373 *m = (*m + 1) / 2 - 1;
378 * sun8i_a23_get_pll1_factors() - calculates n, k, m, p factors for PLL1
379 * PLL1 rate is calculated as follows
380 * rate = (parent_rate * (n + 1) * (k + 1) >> p) / (m + 1);
381 * parent_rate is always 24Mhz
384 static void sun8i_a23_get_pll1_factors(u32 *freq, u32 parent_rate,
385 u8 *n, u8 *k, u8 *m, u8 *p)
389 /* Normalize value to a 6M multiple */
390 div = *freq / 6000000;
391 *freq = 6000000 * div;
393 /* we were called to round the frequency, we can now return */
397 /* m is always zero for pll1 */
400 /* k is 1 only on these cases */
401 if (*freq >= 768000000 || *freq == 42000000 || *freq == 54000000)
406 /* p will be 2 for divs under 20 and odd divs under 32 */
407 if (div < 20 || (div < 32 && (div & 1)))
410 /* p will be 1 for even divs under 32, divs under 40 and odd pairs
411 * of divs between 40-62 */
412 else if (div < 40 || (div < 64 && (div & 2)))
415 /* any other entries have p = 0 */
419 /* calculate a suitable n based on k and p */
426 * sun4i_get_pll5_factors() - calculates n, k factors for PLL5
427 * PLL5 rate is calculated as follows
428 * rate = parent_rate * n * (k + 1)
429 * parent_rate is always 24Mhz
432 static void sun4i_get_pll5_factors(u32 *freq, u32 parent_rate,
433 u8 *n, u8 *k, u8 *m, u8 *p)
437 /* Normalize value to a parent_rate multiple (24M) */
438 div = *freq / parent_rate;
439 *freq = parent_rate * div;
441 /* we were called to round the frequency, we can now return */
447 else if (div / 2 < 31)
449 else if (div / 3 < 31)
454 *n = DIV_ROUND_UP(div, (*k+1));
458 * sun6i_a31_get_pll6_factors() - calculates n, k factors for A31 PLL6x2
459 * PLL6x2 rate is calculated as follows
460 * rate = parent_rate * (n + 1) * (k + 1)
461 * parent_rate is always 24Mhz
464 static void sun6i_a31_get_pll6_factors(u32 *freq, u32 parent_rate,
465 u8 *n, u8 *k, u8 *m, u8 *p)
469 /* Normalize value to a parent_rate multiple (24M) */
470 div = *freq / parent_rate;
471 *freq = parent_rate * div;
473 /* we were called to round the frequency, we can now return */
481 *n = DIV_ROUND_UP(div, (*k+1)) - 1;
485 * sun4i_get_apb1_factors() - calculates m, p factors for APB1
486 * APB1 rate is calculated as follows
487 * rate = (parent_rate >> p) / (m + 1);
490 static void sun4i_get_apb1_factors(u32 *freq, u32 parent_rate,
491 u8 *n, u8 *k, u8 *m, u8 *p)
495 if (parent_rate < *freq)
498 parent_rate = DIV_ROUND_UP(parent_rate, *freq);
501 if (parent_rate > 32)
504 if (parent_rate <= 4)
506 else if (parent_rate <= 8)
508 else if (parent_rate <= 16)
513 calcm = (parent_rate >> calcp) - 1;
515 *freq = (parent_rate >> calcp) / (calcm + 1);
517 /* we were called to round the frequency, we can now return */
529 * sun7i_a20_get_out_factors() - calculates m, p factors for CLK_OUT_A/B
530 * CLK_OUT rate is calculated as follows
531 * rate = (parent_rate >> p) / (m + 1);
534 static void sun7i_a20_get_out_factors(u32 *freq, u32 parent_rate,
535 u8 *n, u8 *k, u8 *m, u8 *p)
537 u8 div, calcm, calcp;
539 /* These clocks can only divide, so we will never be able to achieve
540 * frequencies higher than the parent frequency */
541 if (*freq > parent_rate)
544 div = DIV_ROUND_UP(parent_rate, *freq);
548 else if (div / 2 < 32)
550 else if (div / 4 < 32)
555 calcm = DIV_ROUND_UP(div, 1 << calcp);
557 *freq = (parent_rate >> calcp) / calcm;
559 /* we were called to round the frequency, we can now return */
568 * sunxi_factors_clk_setup() - Setup function for factor clocks
571 static struct clk_factors_config sun4i_pll1_config = {
582 static struct clk_factors_config sun6i_a31_pll1_config = {
592 static struct clk_factors_config sun8i_a23_pll1_config = {
604 static struct clk_factors_config sun4i_pll5_config = {
611 static struct clk_factors_config sun6i_a31_pll6_config = {
619 static struct clk_factors_config sun4i_apb1_config = {
626 /* user manual says "n" but it's really "p" */
627 static struct clk_factors_config sun7i_a20_out_config = {
634 static const struct factors_data sun4i_pll1_data __initconst = {
636 .table = &sun4i_pll1_config,
637 .getter = sun4i_get_pll1_factors,
640 static const struct factors_data sun6i_a31_pll1_data __initconst = {
642 .table = &sun6i_a31_pll1_config,
643 .getter = sun6i_a31_get_pll1_factors,
646 static const struct factors_data sun8i_a23_pll1_data __initconst = {
648 .table = &sun8i_a23_pll1_config,
649 .getter = sun8i_a23_get_pll1_factors,
652 static const struct factors_data sun7i_a20_pll4_data __initconst = {
654 .table = &sun4i_pll5_config,
655 .getter = sun4i_get_pll5_factors,
658 static const struct factors_data sun4i_pll5_data __initconst = {
660 .table = &sun4i_pll5_config,
661 .getter = sun4i_get_pll5_factors,
665 static const struct factors_data sun4i_pll6_data __initconst = {
667 .table = &sun4i_pll5_config,
668 .getter = sun4i_get_pll5_factors,
672 static const struct factors_data sun6i_a31_pll6_data __initconst = {
674 .table = &sun6i_a31_pll6_config,
675 .getter = sun6i_a31_get_pll6_factors,
679 static const struct factors_data sun4i_apb1_data __initconst = {
681 .muxmask = BIT(1) | BIT(0),
682 .table = &sun4i_apb1_config,
683 .getter = sun4i_get_apb1_factors,
686 static const struct factors_data sun7i_a20_out_data __initconst = {
689 .muxmask = BIT(1) | BIT(0),
690 .table = &sun7i_a20_out_config,
691 .getter = sun7i_a20_get_out_factors,
694 static struct clk * __init sunxi_factors_clk_setup(struct device_node *node,
695 const struct factors_data *data)
699 reg = of_iomap(node, 0);
701 pr_err("Could not get registers for factors-clk: %s\n",
706 return sunxi_factors_register(node, data, &clk_lock, reg);
712 * sunxi_mux_clk_setup() - Setup function for muxes
715 #define SUNXI_MUX_GATE_WIDTH 2
721 static const struct mux_data sun4i_cpu_mux_data __initconst = {
725 static const struct mux_data sun6i_a31_ahb1_mux_data __initconst = {
729 static void __init sunxi_mux_clk_setup(struct device_node *node,
730 struct mux_data *data)
733 const char *clk_name = node->name;
734 const char *parents[SUNXI_MAX_PARENTS];
738 reg = of_iomap(node, 0);
740 while (i < SUNXI_MAX_PARENTS &&
741 (parents[i] = of_clk_get_parent_name(node, i)) != NULL)
744 of_property_read_string(node, "clock-output-names", &clk_name);
746 clk = clk_register_mux(NULL, clk_name, parents, i,
747 CLK_SET_RATE_PARENT, reg,
748 data->shift, SUNXI_MUX_GATE_WIDTH,
752 of_clk_add_provider(node, of_clk_src_simple_get, clk);
753 clk_register_clkdev(clk, clk_name, NULL);
760 * sunxi_divider_clk_setup() - Setup function for simple divider clocks
767 const struct clk_div_table *table;
770 static const struct div_data sun4i_axi_data __initconst = {
776 static const struct clk_div_table sun8i_a23_axi_table[] __initconst = {
777 { .val = 0, .div = 1 },
778 { .val = 1, .div = 2 },
779 { .val = 2, .div = 3 },
780 { .val = 3, .div = 4 },
781 { .val = 4, .div = 4 },
782 { .val = 5, .div = 4 },
783 { .val = 6, .div = 4 },
784 { .val = 7, .div = 4 },
788 static const struct div_data sun8i_a23_axi_data __initconst = {
790 .table = sun8i_a23_axi_table,
793 static const struct div_data sun4i_ahb_data __initconst = {
799 static const struct clk_div_table sun4i_apb0_table[] __initconst = {
800 { .val = 0, .div = 2 },
801 { .val = 1, .div = 2 },
802 { .val = 2, .div = 4 },
803 { .val = 3, .div = 8 },
807 static const struct div_data sun4i_apb0_data __initconst = {
811 .table = sun4i_apb0_table,
814 static void __init sunxi_divider_clk_setup(struct device_node *node,
815 struct div_data *data)
818 const char *clk_name = node->name;
819 const char *clk_parent;
822 reg = of_iomap(node, 0);
824 clk_parent = of_clk_get_parent_name(node, 0);
826 of_property_read_string(node, "clock-output-names", &clk_name);
828 clk = clk_register_divider_table(NULL, clk_name, clk_parent, 0,
829 reg, data->shift, data->width,
830 data->pow ? CLK_DIVIDER_POWER_OF_TWO : 0,
831 data->table, &clk_lock);
833 of_clk_add_provider(node, of_clk_src_simple_get, clk);
834 clk_register_clkdev(clk, clk_name, NULL);
841 * sunxi_gates_reset... - reset bits in leaf gate clk registers handling
844 struct gates_reset_data {
847 struct reset_controller_dev rcdev;
850 static int sunxi_gates_reset_assert(struct reset_controller_dev *rcdev,
853 struct gates_reset_data *data = container_of(rcdev,
854 struct gates_reset_data,
859 spin_lock_irqsave(data->lock, flags);
861 reg = readl(data->reg);
862 writel(reg & ~BIT(id), data->reg);
864 spin_unlock_irqrestore(data->lock, flags);
869 static int sunxi_gates_reset_deassert(struct reset_controller_dev *rcdev,
872 struct gates_reset_data *data = container_of(rcdev,
873 struct gates_reset_data,
878 spin_lock_irqsave(data->lock, flags);
880 reg = readl(data->reg);
881 writel(reg | BIT(id), data->reg);
883 spin_unlock_irqrestore(data->lock, flags);
888 static struct reset_control_ops sunxi_gates_reset_ops = {
889 .assert = sunxi_gates_reset_assert,
890 .deassert = sunxi_gates_reset_deassert,
894 * sunxi_gates_clk_setup() - Setup function for leaf gates on clocks
897 #define SUNXI_GATES_MAX_SIZE 64
900 DECLARE_BITMAP(mask, SUNXI_GATES_MAX_SIZE);
904 static const struct gates_data sun4i_axi_gates_data __initconst = {
908 static const struct gates_data sun4i_ahb_gates_data __initconst = {
909 .mask = {0x7F77FFF, 0x14FB3F},
912 static const struct gates_data sun5i_a10s_ahb_gates_data __initconst = {
913 .mask = {0x147667e7, 0x185915},
916 static const struct gates_data sun5i_a13_ahb_gates_data __initconst = {
917 .mask = {0x107067e7, 0x185111},
920 static const struct gates_data sun6i_a31_ahb1_gates_data __initconst = {
921 .mask = {0xEDFE7F62, 0x794F931},
924 static const struct gates_data sun7i_a20_ahb_gates_data __initconst = {
925 .mask = { 0x12f77fff, 0x16ff3f },
928 static const struct gates_data sun8i_a23_ahb1_gates_data __initconst = {
929 .mask = {0x25386742, 0x2505111},
932 static const struct gates_data sun9i_a80_ahb0_gates_data __initconst = {
936 static const struct gates_data sun9i_a80_ahb1_gates_data __initconst = {
940 static const struct gates_data sun9i_a80_ahb2_gates_data __initconst = {
944 static const struct gates_data sun4i_apb0_gates_data __initconst = {
948 static const struct gates_data sun5i_a10s_apb0_gates_data __initconst = {
952 static const struct gates_data sun5i_a13_apb0_gates_data __initconst = {
956 static const struct gates_data sun7i_a20_apb0_gates_data __initconst = {
960 static const struct gates_data sun9i_a80_apb0_gates_data __initconst = {
964 static const struct gates_data sun4i_apb1_gates_data __initconst = {
968 static const struct gates_data sun5i_a10s_apb1_gates_data __initconst = {
972 static const struct gates_data sun5i_a13_apb1_gates_data __initconst = {
976 static const struct gates_data sun6i_a31_apb1_gates_data __initconst = {
980 static const struct gates_data sun8i_a23_apb1_gates_data __initconst = {
984 static const struct gates_data sun6i_a31_apb2_gates_data __initconst = {
988 static const struct gates_data sun7i_a20_apb1_gates_data __initconst = {
989 .mask = { 0xff80ff },
992 static const struct gates_data sun9i_a80_apb1_gates_data __initconst = {
996 static const struct gates_data sun8i_a23_apb2_gates_data __initconst = {
1000 static const struct gates_data sun4i_a10_usb_gates_data __initconst = {
1005 static const struct gates_data sun5i_a13_usb_gates_data __initconst = {
1010 static const struct gates_data sun6i_a31_usb_gates_data __initconst = {
1011 .mask = { BIT(18) | BIT(17) | BIT(16) | BIT(10) | BIT(9) | BIT(8) },
1012 .reset_mask = BIT(2) | BIT(1) | BIT(0),
1015 static void __init sunxi_gates_clk_setup(struct device_node *node,
1016 struct gates_data *data)
1018 struct clk_onecell_data *clk_data;
1019 struct gates_reset_data *reset_data;
1020 const char *clk_parent;
1021 const char *clk_name;
1027 reg = of_iomap(node, 0);
1029 clk_parent = of_clk_get_parent_name(node, 0);
1031 /* Worst-case size approximation and memory allocation */
1032 qty = find_last_bit(data->mask, SUNXI_GATES_MAX_SIZE);
1033 clk_data = kmalloc(sizeof(struct clk_onecell_data), GFP_KERNEL);
1036 clk_data->clks = kzalloc((qty+1) * sizeof(struct clk *), GFP_KERNEL);
1037 if (!clk_data->clks) {
1042 for_each_set_bit(i, data->mask, SUNXI_GATES_MAX_SIZE) {
1043 of_property_read_string_index(node, "clock-output-names",
1046 clk_data->clks[i] = clk_register_gate(NULL, clk_name,
1048 reg + 4 * (i/32), i % 32,
1050 WARN_ON(IS_ERR(clk_data->clks[i]));
1051 clk_register_clkdev(clk_data->clks[i], clk_name, NULL);
1056 /* Adjust to the real max */
1057 clk_data->clk_num = i;
1059 of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
1061 /* Register a reset controler for gates with reset bits */
1062 if (data->reset_mask == 0)
1065 reset_data = kzalloc(sizeof(*reset_data), GFP_KERNEL);
1069 reset_data->reg = reg;
1070 reset_data->lock = &clk_lock;
1071 reset_data->rcdev.nr_resets = __fls(data->reset_mask) + 1;
1072 reset_data->rcdev.ops = &sunxi_gates_reset_ops;
1073 reset_data->rcdev.of_node = node;
1074 reset_controller_register(&reset_data->rcdev);
1080 * sunxi_divs_clk_setup() helper data
1083 #define SUNXI_DIVS_MAX_QTY 2
1084 #define SUNXI_DIVISOR_WIDTH 2
1087 const struct factors_data *factors; /* data for the factor clock */
1088 int ndivs; /* number of children */
1090 u8 fixed; /* is it a fixed divisor? if not... */
1091 struct clk_div_table *table; /* is it a table based divisor? */
1092 u8 shift; /* otherwise it's a normal divisor with this shift */
1093 u8 pow; /* is it power-of-two based? */
1094 u8 gate; /* is it independently gateable? */
1095 } div[SUNXI_DIVS_MAX_QTY];
1098 static struct clk_div_table pll6_sata_tbl[] = {
1099 { .val = 0, .div = 6, },
1100 { .val = 1, .div = 12, },
1101 { .val = 2, .div = 18, },
1102 { .val = 3, .div = 24, },
1106 static const struct divs_data pll5_divs_data __initconst = {
1107 .factors = &sun4i_pll5_data,
1110 { .shift = 0, .pow = 0, }, /* M, DDR */
1111 { .shift = 16, .pow = 1, }, /* P, other */
1115 static const struct divs_data pll6_divs_data __initconst = {
1116 .factors = &sun4i_pll6_data,
1119 { .shift = 0, .table = pll6_sata_tbl, .gate = 14 }, /* M, SATA */
1120 { .fixed = 2 }, /* P, other */
1124 static const struct divs_data sun6i_a31_pll6_divs_data __initconst = {
1125 .factors = &sun6i_a31_pll6_data,
1128 { .fixed = 2 }, /* normal output */
1133 * sunxi_divs_clk_setup() - Setup function for leaf divisors on clocks
1135 * These clocks look something like this
1136 * ________________________
1137 * | ___divisor 1---|----> to consumer
1138 * parent >--| pll___/___divisor 2---|----> to consumer
1139 * | \_______________|____> to consumer
1140 * |________________________|
1143 static void __init sunxi_divs_clk_setup(struct device_node *node,
1144 struct divs_data *data)
1146 struct clk_onecell_data *clk_data;
1148 const char *clk_name;
1149 struct clk **clks, *pclk;
1150 struct clk_hw *gate_hw, *rate_hw;
1151 const struct clk_ops *rate_ops;
1152 struct clk_gate *gate = NULL;
1153 struct clk_fixed_factor *fix_factor;
1154 struct clk_divider *divider;
1156 int ndivs = SUNXI_DIVS_MAX_QTY, i = 0;
1157 int flags, clkflags;
1159 /* Set up factor clock that we will be dividing */
1160 pclk = sunxi_factors_clk_setup(node, data->factors);
1161 parent = __clk_get_name(pclk);
1163 reg = of_iomap(node, 0);
1165 clk_data = kmalloc(sizeof(struct clk_onecell_data), GFP_KERNEL);
1169 clks = kzalloc((SUNXI_DIVS_MAX_QTY+1) * sizeof(*clks), GFP_KERNEL);
1173 clk_data->clks = clks;
1175 /* It's not a good idea to have automatic reparenting changing
1177 clkflags = !strcmp("pll5", parent) ? 0 : CLK_SET_RATE_PARENT;
1179 /* if number of children known, use it */
1181 ndivs = data->ndivs;
1183 for (i = 0; i < ndivs; i++) {
1184 if (of_property_read_string_index(node, "clock-output-names",
1192 /* If this leaf clock can be gated, create a gate */
1193 if (data->div[i].gate) {
1194 gate = kzalloc(sizeof(*gate), GFP_KERNEL);
1199 gate->bit_idx = data->div[i].gate;
1200 gate->lock = &clk_lock;
1202 gate_hw = &gate->hw;
1205 /* Leaves can be fixed or configurable divisors */
1206 if (data->div[i].fixed) {
1207 fix_factor = kzalloc(sizeof(*fix_factor), GFP_KERNEL);
1211 fix_factor->mult = 1;
1212 fix_factor->div = data->div[i].fixed;
1214 rate_hw = &fix_factor->hw;
1215 rate_ops = &clk_fixed_factor_ops;
1217 divider = kzalloc(sizeof(*divider), GFP_KERNEL);
1221 flags = data->div[i].pow ? CLK_DIVIDER_POWER_OF_TWO : 0;
1224 divider->shift = data->div[i].shift;
1225 divider->width = SUNXI_DIVISOR_WIDTH;
1226 divider->flags = flags;
1227 divider->lock = &clk_lock;
1228 divider->table = data->div[i].table;
1230 rate_hw = ÷r->hw;
1231 rate_ops = &clk_divider_ops;
1234 /* Wrap the (potential) gate and the divisor on a composite
1235 * clock to unify them */
1236 clks[i] = clk_register_composite(NULL, clk_name, &parent, 1,
1239 gate_hw, &clk_gate_ops,
1242 WARN_ON(IS_ERR(clk_data->clks[i]));
1243 clk_register_clkdev(clks[i], clk_name, NULL);
1246 /* The last clock available on the getter is the parent */
1249 /* Adjust to the real max */
1250 clk_data->clk_num = i;
1252 of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
1266 /* Matches for factors clocks */
1267 static const struct of_device_id clk_factors_match[] __initconst = {
1268 {.compatible = "allwinner,sun4i-a10-pll1-clk", .data = &sun4i_pll1_data,},
1269 {.compatible = "allwinner,sun6i-a31-pll1-clk", .data = &sun6i_a31_pll1_data,},
1270 {.compatible = "allwinner,sun8i-a23-pll1-clk", .data = &sun8i_a23_pll1_data,},
1271 {.compatible = "allwinner,sun7i-a20-pll4-clk", .data = &sun7i_a20_pll4_data,},
1272 {.compatible = "allwinner,sun4i-a10-apb1-clk", .data = &sun4i_apb1_data,},
1273 {.compatible = "allwinner,sun7i-a20-out-clk", .data = &sun7i_a20_out_data,},
1277 /* Matches for divider clocks */
1278 static const struct of_device_id clk_div_match[] __initconst = {
1279 {.compatible = "allwinner,sun4i-a10-axi-clk", .data = &sun4i_axi_data,},
1280 {.compatible = "allwinner,sun8i-a23-axi-clk", .data = &sun8i_a23_axi_data,},
1281 {.compatible = "allwinner,sun4i-a10-ahb-clk", .data = &sun4i_ahb_data,},
1282 {.compatible = "allwinner,sun4i-a10-apb0-clk", .data = &sun4i_apb0_data,},
1286 /* Matches for divided outputs */
1287 static const struct of_device_id clk_divs_match[] __initconst = {
1288 {.compatible = "allwinner,sun4i-a10-pll5-clk", .data = &pll5_divs_data,},
1289 {.compatible = "allwinner,sun4i-a10-pll6-clk", .data = &pll6_divs_data,},
1290 {.compatible = "allwinner,sun6i-a31-pll6-clk", .data = &sun6i_a31_pll6_divs_data,},
1294 /* Matches for mux clocks */
1295 static const struct of_device_id clk_mux_match[] __initconst = {
1296 {.compatible = "allwinner,sun4i-a10-cpu-clk", .data = &sun4i_cpu_mux_data,},
1297 {.compatible = "allwinner,sun6i-a31-ahb1-mux-clk", .data = &sun6i_a31_ahb1_mux_data,},
1301 /* Matches for gate clocks */
1302 static const struct of_device_id clk_gates_match[] __initconst = {
1303 {.compatible = "allwinner,sun4i-a10-axi-gates-clk", .data = &sun4i_axi_gates_data,},
1304 {.compatible = "allwinner,sun4i-a10-ahb-gates-clk", .data = &sun4i_ahb_gates_data,},
1305 {.compatible = "allwinner,sun5i-a10s-ahb-gates-clk", .data = &sun5i_a10s_ahb_gates_data,},
1306 {.compatible = "allwinner,sun5i-a13-ahb-gates-clk", .data = &sun5i_a13_ahb_gates_data,},
1307 {.compatible = "allwinner,sun6i-a31-ahb1-gates-clk", .data = &sun6i_a31_ahb1_gates_data,},
1308 {.compatible = "allwinner,sun7i-a20-ahb-gates-clk", .data = &sun7i_a20_ahb_gates_data,},
1309 {.compatible = "allwinner,sun8i-a23-ahb1-gates-clk", .data = &sun8i_a23_ahb1_gates_data,},
1310 {.compatible = "allwinner,sun9i-a80-ahb0-gates-clk", .data = &sun9i_a80_ahb0_gates_data,},
1311 {.compatible = "allwinner,sun9i-a80-ahb1-gates-clk", .data = &sun9i_a80_ahb1_gates_data,},
1312 {.compatible = "allwinner,sun9i-a80-ahb2-gates-clk", .data = &sun9i_a80_ahb2_gates_data,},
1313 {.compatible = "allwinner,sun4i-a10-apb0-gates-clk", .data = &sun4i_apb0_gates_data,},
1314 {.compatible = "allwinner,sun5i-a10s-apb0-gates-clk", .data = &sun5i_a10s_apb0_gates_data,},
1315 {.compatible = "allwinner,sun5i-a13-apb0-gates-clk", .data = &sun5i_a13_apb0_gates_data,},
1316 {.compatible = "allwinner,sun7i-a20-apb0-gates-clk", .data = &sun7i_a20_apb0_gates_data,},
1317 {.compatible = "allwinner,sun9i-a80-apb0-gates-clk", .data = &sun9i_a80_apb0_gates_data,},
1318 {.compatible = "allwinner,sun4i-a10-apb1-gates-clk", .data = &sun4i_apb1_gates_data,},
1319 {.compatible = "allwinner,sun5i-a10s-apb1-gates-clk", .data = &sun5i_a10s_apb1_gates_data,},
1320 {.compatible = "allwinner,sun5i-a13-apb1-gates-clk", .data = &sun5i_a13_apb1_gates_data,},
1321 {.compatible = "allwinner,sun6i-a31-apb1-gates-clk", .data = &sun6i_a31_apb1_gates_data,},
1322 {.compatible = "allwinner,sun7i-a20-apb1-gates-clk", .data = &sun7i_a20_apb1_gates_data,},
1323 {.compatible = "allwinner,sun8i-a23-apb1-gates-clk", .data = &sun8i_a23_apb1_gates_data,},
1324 {.compatible = "allwinner,sun9i-a80-apb1-gates-clk", .data = &sun9i_a80_apb1_gates_data,},
1325 {.compatible = "allwinner,sun6i-a31-apb2-gates-clk", .data = &sun6i_a31_apb2_gates_data,},
1326 {.compatible = "allwinner,sun8i-a23-apb2-gates-clk", .data = &sun8i_a23_apb2_gates_data,},
1327 {.compatible = "allwinner,sun4i-a10-usb-clk", .data = &sun4i_a10_usb_gates_data,},
1328 {.compatible = "allwinner,sun5i-a13-usb-clk", .data = &sun5i_a13_usb_gates_data,},
1329 {.compatible = "allwinner,sun6i-a31-usb-clk", .data = &sun6i_a31_usb_gates_data,},
1333 static void __init of_sunxi_table_clock_setup(const struct of_device_id *clk_match,
1336 struct device_node *np;
1337 const struct div_data *data;
1338 const struct of_device_id *match;
1339 void (*setup_function)(struct device_node *, const void *) = function;
1341 for_each_matching_node_and_match(np, clk_match, &match) {
1343 setup_function(np, data);
1347 static void __init sunxi_init_clocks(const char *clocks[], int nclocks)
1351 /* Register factor clocks */
1352 of_sunxi_table_clock_setup(clk_factors_match, sunxi_factors_clk_setup);
1354 /* Register divider clocks */
1355 of_sunxi_table_clock_setup(clk_div_match, sunxi_divider_clk_setup);
1357 /* Register divided output clocks */
1358 of_sunxi_table_clock_setup(clk_divs_match, sunxi_divs_clk_setup);
1360 /* Register mux clocks */
1361 of_sunxi_table_clock_setup(clk_mux_match, sunxi_mux_clk_setup);
1363 /* Register gate clocks */
1364 of_sunxi_table_clock_setup(clk_gates_match, sunxi_gates_clk_setup);
1366 /* Protect the clocks that needs to stay on */
1367 for (i = 0; i < nclocks; i++) {
1368 struct clk *clk = clk_get(NULL, clocks[i]);
1371 clk_prepare_enable(clk);
1375 static const char *sun4i_a10_critical_clocks[] __initdata = {
1380 static void __init sun4i_a10_init_clocks(struct device_node *node)
1382 sunxi_init_clocks(sun4i_a10_critical_clocks,
1383 ARRAY_SIZE(sun4i_a10_critical_clocks));
1385 CLK_OF_DECLARE(sun4i_a10_clk_init, "allwinner,sun4i-a10", sun4i_a10_init_clocks);
1387 static const char *sun5i_critical_clocks[] __initdata = {
1392 static void __init sun5i_init_clocks(struct device_node *node)
1394 sunxi_init_clocks(sun5i_critical_clocks,
1395 ARRAY_SIZE(sun5i_critical_clocks));
1397 CLK_OF_DECLARE(sun5i_a10s_clk_init, "allwinner,sun5i-a10s", sun5i_init_clocks);
1398 CLK_OF_DECLARE(sun5i_a13_clk_init, "allwinner,sun5i-a13", sun5i_init_clocks);
1399 CLK_OF_DECLARE(sun7i_a20_clk_init, "allwinner,sun7i-a20", sun5i_init_clocks);
1401 static const char *sun6i_critical_clocks[] __initdata = {
1405 static void __init sun6i_init_clocks(struct device_node *node)
1407 sunxi_init_clocks(sun6i_critical_clocks,
1408 ARRAY_SIZE(sun6i_critical_clocks));
1410 CLK_OF_DECLARE(sun6i_a31_clk_init, "allwinner,sun6i-a31", sun6i_init_clocks);
1411 CLK_OF_DECLARE(sun6i_a31s_clk_init, "allwinner,sun6i-a31s", sun6i_init_clocks);
1412 CLK_OF_DECLARE(sun8i_a23_clk_init, "allwinner,sun8i-a23", sun6i_init_clocks);
1414 static void __init sun9i_init_clocks(struct device_node *node)
1416 sunxi_init_clocks(NULL, 0);
1418 CLK_OF_DECLARE(sun9i_a80_clk_init, "allwinner,sun9i-a80", sun9i_init_clocks);