2 * Copyright 2013 Emilio López
4 * Emilio López <emilio@elopez.com.ar>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
17 #include <linux/clk-provider.h>
18 #include <linux/clkdev.h>
20 #include <linux/of_address.h>
21 #include <linux/reset-controller.h>
23 #include "clk-factors.h"
25 static DEFINE_SPINLOCK(clk_lock);
27 /* Maximum number of parents our clocks have */
28 #define SUNXI_MAX_PARENTS 5
31 * sun4i_osc_clk_setup() - Setup function for gatable oscillator
34 #define SUNXI_OSC24M_GATE 0
36 static void __init sun4i_osc_clk_setup(struct device_node *node)
39 struct clk_fixed_rate *fixed;
40 struct clk_gate *gate;
41 const char *clk_name = node->name;
44 if (of_property_read_u32(node, "clock-frequency", &rate))
47 /* allocate fixed-rate and gate clock structs */
48 fixed = kzalloc(sizeof(struct clk_fixed_rate), GFP_KERNEL);
51 gate = kzalloc(sizeof(struct clk_gate), GFP_KERNEL);
55 of_property_read_string(node, "clock-output-names", &clk_name);
57 /* set up gate and fixed rate properties */
58 gate->reg = of_iomap(node, 0);
59 gate->bit_idx = SUNXI_OSC24M_GATE;
60 gate->lock = &clk_lock;
61 fixed->fixed_rate = rate;
63 clk = clk_register_composite(NULL, clk_name,
66 &fixed->hw, &clk_fixed_rate_ops,
67 &gate->hw, &clk_gate_ops,
73 of_clk_add_provider(node, of_clk_src_simple_get, clk);
74 clk_register_clkdev(clk, clk_name, NULL);
83 CLK_OF_DECLARE(sun4i_osc, "allwinner,sun4i-a10-osc-clk", sun4i_osc_clk_setup);
88 * sun4i_get_pll1_factors() - calculates n, k, m, p factors for PLL1
89 * PLL1 rate is calculated as follows
90 * rate = (parent_rate * n * (k + 1) >> p) / (m + 1);
91 * parent_rate is always 24Mhz
94 static void sun4i_get_pll1_factors(u32 *freq, u32 parent_rate,
95 u8 *n, u8 *k, u8 *m, u8 *p)
99 /* Normalize value to a 6M multiple */
100 div = *freq / 6000000;
101 *freq = 6000000 * div;
103 /* we were called to round the frequency, we can now return */
107 /* m is always zero for pll1 */
110 /* k is 1 only on these cases */
111 if (*freq >= 768000000 || *freq == 42000000 || *freq == 54000000)
116 /* p will be 3 for divs under 10 */
120 /* p will be 2 for divs between 10 - 20 and odd divs under 32 */
121 else if (div < 20 || (div < 32 && (div & 1)))
124 /* p will be 1 for even divs under 32, divs under 40 and odd pairs
125 * of divs between 40-62 */
126 else if (div < 40 || (div < 64 && (div & 2)))
129 /* any other entries have p = 0 */
133 /* calculate a suitable n based on k and p */
140 * sun6i_a31_get_pll1_factors() - calculates n, k and m factors for PLL1
141 * PLL1 rate is calculated as follows
142 * rate = parent_rate * (n + 1) * (k + 1) / (m + 1);
143 * parent_rate should always be 24MHz
145 static void sun6i_a31_get_pll1_factors(u32 *freq, u32 parent_rate,
146 u8 *n, u8 *k, u8 *m, u8 *p)
149 * We can operate only on MHz, this will make our life easier
152 u32 freq_mhz = *freq / 1000000;
153 u32 parent_freq_mhz = parent_rate / 1000000;
156 * Round down the frequency to the closest multiple of either
159 u32 round_freq_6 = round_down(freq_mhz, 6);
160 u32 round_freq_16 = round_down(freq_mhz, 16);
162 if (round_freq_6 > round_freq_16)
163 freq_mhz = round_freq_6;
165 freq_mhz = round_freq_16;
167 *freq = freq_mhz * 1000000;
170 * If the factors pointer are null, we were just called to
171 * round down the frequency.
177 /* If the frequency is a multiple of 32 MHz, k is always 3 */
178 if (!(freq_mhz % 32))
180 /* If the frequency is a multiple of 9 MHz, k is always 2 */
181 else if (!(freq_mhz % 9))
183 /* If the frequency is a multiple of 8 MHz, k is always 1 */
184 else if (!(freq_mhz % 8))
186 /* Otherwise, we don't use the k factor */
191 * If the frequency is a multiple of 2 but not a multiple of
192 * 3, m is 3. This is the first time we use 6 here, yet we
193 * will use it on several other places.
194 * We use this number because it's the lowest frequency we can
195 * generate (with n = 0, k = 0, m = 3), so every other frequency
196 * somehow relates to this frequency.
198 if ((freq_mhz % 6) == 2 || (freq_mhz % 6) == 4)
201 * If the frequency is a multiple of 6MHz, but the factor is
204 else if ((freq_mhz / 6) & 1)
206 /* Otherwise, we end up with m = 1 */
210 /* Calculate n thanks to the above factors we already got */
211 *n = freq_mhz * (*m + 1) / ((*k + 1) * parent_freq_mhz) - 1;
214 * If n end up being outbound, and that we can still decrease
217 if ((*n + 1) > 31 && (*m + 1) > 1) {
218 *n = (*n + 1) / 2 - 1;
219 *m = (*m + 1) / 2 - 1;
224 * sun4i_get_pll5_factors() - calculates n, k factors for PLL5
225 * PLL5 rate is calculated as follows
226 * rate = parent_rate * n * (k + 1)
227 * parent_rate is always 24Mhz
230 static void sun4i_get_pll5_factors(u32 *freq, u32 parent_rate,
231 u8 *n, u8 *k, u8 *m, u8 *p)
235 /* Normalize value to a parent_rate multiple (24M) */
236 div = *freq / parent_rate;
237 *freq = parent_rate * div;
239 /* we were called to round the frequency, we can now return */
245 else if (div / 2 < 31)
247 else if (div / 3 < 31)
252 *n = DIV_ROUND_UP(div, (*k+1));
256 * sun6i_a31_get_pll6_factors() - calculates n, k factors for A31 PLL6
257 * PLL6 rate is calculated as follows
258 * rate = parent_rate * n * (k + 1) / 2
259 * parent_rate is always 24Mhz
262 static void sun6i_a31_get_pll6_factors(u32 *freq, u32 parent_rate,
263 u8 *n, u8 *k, u8 *m, u8 *p)
268 * We always have 24MHz / 2, so we can just say that our
269 * parent clock is 12MHz.
271 parent_rate = parent_rate / 2;
273 /* Normalize value to a parent_rate multiple (24M / 2) */
274 div = *freq / parent_rate;
275 *freq = parent_rate * div;
277 /* we were called to round the frequency, we can now return */
285 *n = DIV_ROUND_UP(div, (*k+1));
289 * sun4i_get_apb1_factors() - calculates m, p factors for APB1
290 * APB1 rate is calculated as follows
291 * rate = (parent_rate >> p) / (m + 1);
294 static void sun4i_get_apb1_factors(u32 *freq, u32 parent_rate,
295 u8 *n, u8 *k, u8 *m, u8 *p)
299 if (parent_rate < *freq)
302 parent_rate = DIV_ROUND_UP(parent_rate, *freq);
305 if (parent_rate > 32)
308 if (parent_rate <= 4)
310 else if (parent_rate <= 8)
312 else if (parent_rate <= 16)
317 calcm = (parent_rate >> calcp) - 1;
319 *freq = (parent_rate >> calcp) / (calcm + 1);
321 /* we were called to round the frequency, we can now return */
332 * sun4i_get_mod0_factors() - calculates m, n factors for MOD0-style clocks
333 * MOD0 rate is calculated as follows
334 * rate = (parent_rate >> p) / (m + 1);
337 static void sun4i_get_mod0_factors(u32 *freq, u32 parent_rate,
338 u8 *n, u8 *k, u8 *m, u8 *p)
340 u8 div, calcm, calcp;
342 /* These clocks can only divide, so we will never be able to achieve
343 * frequencies higher than the parent frequency */
344 if (*freq > parent_rate)
347 div = DIV_ROUND_UP(parent_rate, *freq);
351 else if (div / 2 < 16)
353 else if (div / 4 < 16)
358 calcm = DIV_ROUND_UP(div, 1 << calcp);
360 *freq = (parent_rate >> calcp) / calcm;
362 /* we were called to round the frequency, we can now return */
373 * sun7i_a20_get_out_factors() - calculates m, p factors for CLK_OUT_A/B
374 * CLK_OUT rate is calculated as follows
375 * rate = (parent_rate >> p) / (m + 1);
378 static void sun7i_a20_get_out_factors(u32 *freq, u32 parent_rate,
379 u8 *n, u8 *k, u8 *m, u8 *p)
381 u8 div, calcm, calcp;
383 /* These clocks can only divide, so we will never be able to achieve
384 * frequencies higher than the parent frequency */
385 if (*freq > parent_rate)
388 div = DIV_ROUND_UP(parent_rate, *freq);
392 else if (div / 2 < 32)
394 else if (div / 4 < 32)
399 calcm = DIV_ROUND_UP(div, 1 << calcp);
401 *freq = (parent_rate >> calcp) / calcm;
403 /* we were called to round the frequency, we can now return */
414 * sun7i_a20_gmac_clk_setup - Setup function for A20/A31 GMAC clock module
416 * This clock looks something like this
417 * ________________________
418 * MII TX clock from PHY >-----|___________ _________|----> to GMAC core
419 * GMAC Int. RGMII TX clk >----|___________\__/__gate---|----> to PHY
420 * Ext. 125MHz RGMII TX clk >--|__divider__/ |
421 * |________________________|
423 * The external 125 MHz reference is optional, i.e. GMAC can use its
424 * internal TX clock just fine. The A31 GMAC clock module does not have
425 * the divider controls for the external reference.
427 * To keep it simple, let the GMAC use either the MII TX clock for MII mode,
428 * and its internal TX clock for GMII and RGMII modes. The GMAC driver should
429 * select the appropriate source and gate/ungate the output to the PHY.
431 * Only the GMAC should use this clock. Altering the clock so that it doesn't
432 * match the GMAC's operation parameters will result in the GMAC not being
433 * able to send traffic out. The GMAC driver should set the clock rate and
434 * enable/disable this clock to configure the required state. The clock
435 * driver then responds by auto-reparenting the clock.
438 #define SUN7I_A20_GMAC_GPIT 2
439 #define SUN7I_A20_GMAC_MASK 0x3
440 #define SUN7I_A20_GMAC_PARENTS 2
442 static void __init sun7i_a20_gmac_clk_setup(struct device_node *node)
446 struct clk_gate *gate;
447 const char *clk_name = node->name;
448 const char *parents[SUN7I_A20_GMAC_PARENTS];
451 if (of_property_read_string(node, "clock-output-names", &clk_name))
454 /* allocate mux and gate clock structs */
455 mux = kzalloc(sizeof(struct clk_mux), GFP_KERNEL);
459 gate = kzalloc(sizeof(struct clk_gate), GFP_KERNEL);
463 /* gmac clock requires exactly 2 parents */
464 parents[0] = of_clk_get_parent_name(node, 0);
465 parents[1] = of_clk_get_parent_name(node, 1);
466 if (!parents[0] || !parents[1])
469 reg = of_iomap(node, 0);
473 /* set up gate and fixed rate properties */
475 gate->bit_idx = SUN7I_A20_GMAC_GPIT;
476 gate->lock = &clk_lock;
478 mux->mask = SUN7I_A20_GMAC_MASK;
479 mux->flags = CLK_MUX_INDEX_BIT;
480 mux->lock = &clk_lock;
482 clk = clk_register_composite(NULL, clk_name,
483 parents, SUN7I_A20_GMAC_PARENTS,
484 &mux->hw, &clk_mux_ops,
486 &gate->hw, &clk_gate_ops,
492 of_clk_add_provider(node, of_clk_src_simple_get, clk);
493 clk_register_clkdev(clk, clk_name, NULL);
504 CLK_OF_DECLARE(sun7i_a20_gmac, "allwinner,sun7i-a20-gmac-clk",
505 sun7i_a20_gmac_clk_setup);
510 * sunxi_factors_clk_setup() - Setup function for factor clocks
513 #define SUNXI_FACTORS_MUX_MASK 0x3
515 struct factors_data {
518 struct clk_factors_config *table;
519 void (*getter) (u32 *rate, u32 parent_rate, u8 *n, u8 *k, u8 *m, u8 *p);
523 static struct clk_factors_config sun4i_pll1_config = {
534 static struct clk_factors_config sun6i_a31_pll1_config = {
543 static struct clk_factors_config sun4i_pll5_config = {
550 static struct clk_factors_config sun6i_a31_pll6_config = {
557 static struct clk_factors_config sun4i_apb1_config = {
564 /* user manual says "n" but it's really "p" */
565 static struct clk_factors_config sun4i_mod0_config = {
572 /* user manual says "n" but it's really "p" */
573 static struct clk_factors_config sun7i_a20_out_config = {
580 static const struct factors_data sun4i_pll1_data __initconst = {
582 .table = &sun4i_pll1_config,
583 .getter = sun4i_get_pll1_factors,
586 static const struct factors_data sun6i_a31_pll1_data __initconst = {
588 .table = &sun6i_a31_pll1_config,
589 .getter = sun6i_a31_get_pll1_factors,
592 static const struct factors_data sun7i_a20_pll4_data __initconst = {
594 .table = &sun4i_pll5_config,
595 .getter = sun4i_get_pll5_factors,
598 static const struct factors_data sun4i_pll5_data __initconst = {
600 .table = &sun4i_pll5_config,
601 .getter = sun4i_get_pll5_factors,
605 static const struct factors_data sun4i_pll6_data __initconst = {
607 .table = &sun4i_pll5_config,
608 .getter = sun4i_get_pll5_factors,
612 static const struct factors_data sun6i_a31_pll6_data __initconst = {
614 .table = &sun6i_a31_pll6_config,
615 .getter = sun6i_a31_get_pll6_factors,
618 static const struct factors_data sun4i_apb1_data __initconst = {
619 .table = &sun4i_apb1_config,
620 .getter = sun4i_get_apb1_factors,
623 static const struct factors_data sun4i_mod0_data __initconst = {
626 .table = &sun4i_mod0_config,
627 .getter = sun4i_get_mod0_factors,
630 static const struct factors_data sun7i_a20_out_data __initconst = {
633 .table = &sun7i_a20_out_config,
634 .getter = sun7i_a20_get_out_factors,
637 static struct clk * __init sunxi_factors_clk_setup(struct device_node *node,
638 const struct factors_data *data)
641 struct clk_factors *factors;
642 struct clk_gate *gate = NULL;
643 struct clk_mux *mux = NULL;
644 struct clk_hw *gate_hw = NULL;
645 struct clk_hw *mux_hw = NULL;
646 const char *clk_name = node->name;
647 const char *parents[SUNXI_MAX_PARENTS];
651 reg = of_iomap(node, 0);
653 /* if we have a mux, we will have >1 parents */
654 while (i < SUNXI_MAX_PARENTS &&
655 (parents[i] = of_clk_get_parent_name(node, i)) != NULL)
659 * some factor clocks, such as pll5 and pll6, may have multiple
660 * outputs, and have their name designated in factors_data
663 clk_name = data->name;
665 of_property_read_string(node, "clock-output-names", &clk_name);
667 factors = kzalloc(sizeof(struct clk_factors), GFP_KERNEL);
671 /* Add a gate if this factor clock can be gated */
673 gate = kzalloc(sizeof(struct clk_gate), GFP_KERNEL);
679 /* set up gate properties */
681 gate->bit_idx = data->enable;
682 gate->lock = &clk_lock;
686 /* Add a mux if this factor clock can be muxed */
688 mux = kzalloc(sizeof(struct clk_mux), GFP_KERNEL);
695 /* set up gate properties */
697 mux->shift = data->mux;
698 mux->mask = SUNXI_FACTORS_MUX_MASK;
699 mux->lock = &clk_lock;
703 /* set up factors properties */
705 factors->config = data->table;
706 factors->get_factors = data->getter;
707 factors->lock = &clk_lock;
709 clk = clk_register_composite(NULL, clk_name,
711 mux_hw, &clk_mux_ops,
712 &factors->hw, &clk_factors_ops,
713 gate_hw, &clk_gate_ops, 0);
716 of_clk_add_provider(node, of_clk_src_simple_get, clk);
717 clk_register_clkdev(clk, clk_name, NULL);
726 * sunxi_mux_clk_setup() - Setup function for muxes
729 #define SUNXI_MUX_GATE_WIDTH 2
735 static const struct mux_data sun4i_cpu_mux_data __initconst = {
739 static const struct mux_data sun6i_a31_ahb1_mux_data __initconst = {
743 static const struct mux_data sun4i_apb1_mux_data __initconst = {
747 static void __init sunxi_mux_clk_setup(struct device_node *node,
748 struct mux_data *data)
751 const char *clk_name = node->name;
752 const char *parents[SUNXI_MAX_PARENTS];
756 reg = of_iomap(node, 0);
758 while (i < SUNXI_MAX_PARENTS &&
759 (parents[i] = of_clk_get_parent_name(node, i)) != NULL)
762 of_property_read_string(node, "clock-output-names", &clk_name);
764 clk = clk_register_mux(NULL, clk_name, parents, i,
765 CLK_SET_RATE_NO_REPARENT, reg,
766 data->shift, SUNXI_MUX_GATE_WIDTH,
770 of_clk_add_provider(node, of_clk_src_simple_get, clk);
771 clk_register_clkdev(clk, clk_name, NULL);
778 * sunxi_divider_clk_setup() - Setup function for simple divider clocks
787 static const struct div_data sun4i_axi_data __initconst = {
793 static const struct div_data sun4i_ahb_data __initconst = {
799 static const struct div_data sun4i_apb0_data __initconst = {
805 static const struct div_data sun6i_a31_apb2_div_data __initconst = {
811 static void __init sunxi_divider_clk_setup(struct device_node *node,
812 struct div_data *data)
815 const char *clk_name = node->name;
816 const char *clk_parent;
819 reg = of_iomap(node, 0);
821 clk_parent = of_clk_get_parent_name(node, 0);
823 of_property_read_string(node, "clock-output-names", &clk_name);
825 clk = clk_register_divider(NULL, clk_name, clk_parent, 0,
826 reg, data->shift, data->width,
827 data->pow ? CLK_DIVIDER_POWER_OF_TWO : 0,
830 of_clk_add_provider(node, of_clk_src_simple_get, clk);
831 clk_register_clkdev(clk, clk_name, NULL);
838 * sunxi_gates_reset... - reset bits in leaf gate clk registers handling
841 struct gates_reset_data {
844 struct reset_controller_dev rcdev;
847 static int sunxi_gates_reset_assert(struct reset_controller_dev *rcdev,
850 struct gates_reset_data *data = container_of(rcdev,
851 struct gates_reset_data,
856 spin_lock_irqsave(data->lock, flags);
858 reg = readl(data->reg);
859 writel(reg & ~BIT(id), data->reg);
861 spin_unlock_irqrestore(data->lock, flags);
866 static int sunxi_gates_reset_deassert(struct reset_controller_dev *rcdev,
869 struct gates_reset_data *data = container_of(rcdev,
870 struct gates_reset_data,
875 spin_lock_irqsave(data->lock, flags);
877 reg = readl(data->reg);
878 writel(reg | BIT(id), data->reg);
880 spin_unlock_irqrestore(data->lock, flags);
885 static struct reset_control_ops sunxi_gates_reset_ops = {
886 .assert = sunxi_gates_reset_assert,
887 .deassert = sunxi_gates_reset_deassert,
891 * sunxi_gates_clk_setup() - Setup function for leaf gates on clocks
894 #define SUNXI_GATES_MAX_SIZE 64
897 DECLARE_BITMAP(mask, SUNXI_GATES_MAX_SIZE);
901 static const struct gates_data sun4i_axi_gates_data __initconst = {
905 static const struct gates_data sun4i_ahb_gates_data __initconst = {
906 .mask = {0x7F77FFF, 0x14FB3F},
909 static const struct gates_data sun5i_a10s_ahb_gates_data __initconst = {
910 .mask = {0x147667e7, 0x185915},
913 static const struct gates_data sun5i_a13_ahb_gates_data __initconst = {
914 .mask = {0x107067e7, 0x185111},
917 static const struct gates_data sun6i_a31_ahb1_gates_data __initconst = {
918 .mask = {0xEDFE7F62, 0x794F931},
921 static const struct gates_data sun7i_a20_ahb_gates_data __initconst = {
922 .mask = { 0x12f77fff, 0x16ff3f },
925 static const struct gates_data sun4i_apb0_gates_data __initconst = {
929 static const struct gates_data sun5i_a10s_apb0_gates_data __initconst = {
933 static const struct gates_data sun5i_a13_apb0_gates_data __initconst = {
937 static const struct gates_data sun7i_a20_apb0_gates_data __initconst = {
941 static const struct gates_data sun4i_apb1_gates_data __initconst = {
945 static const struct gates_data sun5i_a10s_apb1_gates_data __initconst = {
949 static const struct gates_data sun5i_a13_apb1_gates_data __initconst = {
953 static const struct gates_data sun6i_a31_apb1_gates_data __initconst = {
957 static const struct gates_data sun6i_a31_apb2_gates_data __initconst = {
961 static const struct gates_data sun7i_a20_apb1_gates_data __initconst = {
962 .mask = { 0xff80ff },
965 static const struct gates_data sun4i_a10_usb_gates_data __initconst = {
970 static const struct gates_data sun5i_a13_usb_gates_data __initconst = {
975 static void __init sunxi_gates_clk_setup(struct device_node *node,
976 struct gates_data *data)
978 struct clk_onecell_data *clk_data;
979 struct gates_reset_data *reset_data;
980 const char *clk_parent;
981 const char *clk_name;
988 reg = of_iomap(node, 0);
990 clk_parent = of_clk_get_parent_name(node, 0);
992 /* Worst-case size approximation and memory allocation */
993 qty = find_last_bit(data->mask, SUNXI_GATES_MAX_SIZE);
994 clk_data = kmalloc(sizeof(struct clk_onecell_data), GFP_KERNEL);
997 clk_data->clks = kzalloc((qty+1) * sizeof(struct clk *), GFP_KERNEL);
998 if (!clk_data->clks) {
1003 for_each_set_bit(i, data->mask, SUNXI_GATES_MAX_SIZE) {
1004 of_property_read_string_index(node, "clock-output-names",
1007 /* No driver claims this clock, but it should remain gated */
1008 ignore = !strcmp("ahb_sdram", clk_name) ? CLK_IGNORE_UNUSED : 0;
1010 clk_data->clks[i] = clk_register_gate(NULL, clk_name,
1012 reg + 4 * (i/32), i % 32,
1014 WARN_ON(IS_ERR(clk_data->clks[i]));
1019 /* Adjust to the real max */
1020 clk_data->clk_num = i;
1022 of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
1024 /* Register a reset controler for gates with reset bits */
1025 if (data->reset_mask == 0)
1028 reset_data = kzalloc(sizeof(*reset_data), GFP_KERNEL);
1032 reset_data->reg = reg;
1033 reset_data->lock = &clk_lock;
1034 reset_data->rcdev.nr_resets = __fls(data->reset_mask) + 1;
1035 reset_data->rcdev.ops = &sunxi_gates_reset_ops;
1036 reset_data->rcdev.of_node = node;
1037 reset_controller_register(&reset_data->rcdev);
1043 * sunxi_divs_clk_setup() helper data
1046 #define SUNXI_DIVS_MAX_QTY 2
1047 #define SUNXI_DIVISOR_WIDTH 2
1050 const struct factors_data *factors; /* data for the factor clock */
1052 u8 fixed; /* is it a fixed divisor? if not... */
1053 struct clk_div_table *table; /* is it a table based divisor? */
1054 u8 shift; /* otherwise it's a normal divisor with this shift */
1055 u8 pow; /* is it power-of-two based? */
1056 u8 gate; /* is it independently gateable? */
1057 } div[SUNXI_DIVS_MAX_QTY];
1060 static struct clk_div_table pll6_sata_tbl[] = {
1061 { .val = 0, .div = 6, },
1062 { .val = 1, .div = 12, },
1063 { .val = 2, .div = 18, },
1064 { .val = 3, .div = 24, },
1068 static const struct divs_data pll5_divs_data __initconst = {
1069 .factors = &sun4i_pll5_data,
1071 { .shift = 0, .pow = 0, }, /* M, DDR */
1072 { .shift = 16, .pow = 1, }, /* P, other */
1076 static const struct divs_data pll6_divs_data __initconst = {
1077 .factors = &sun4i_pll6_data,
1079 { .shift = 0, .table = pll6_sata_tbl, .gate = 14 }, /* M, SATA */
1080 { .fixed = 2 }, /* P, other */
1085 * sunxi_divs_clk_setup() - Setup function for leaf divisors on clocks
1087 * These clocks look something like this
1088 * ________________________
1089 * | ___divisor 1---|----> to consumer
1090 * parent >--| pll___/___divisor 2---|----> to consumer
1091 * | \_______________|____> to consumer
1092 * |________________________|
1095 static void __init sunxi_divs_clk_setup(struct device_node *node,
1096 struct divs_data *data)
1098 struct clk_onecell_data *clk_data;
1100 const char *clk_name;
1101 struct clk **clks, *pclk;
1102 struct clk_hw *gate_hw, *rate_hw;
1103 const struct clk_ops *rate_ops;
1104 struct clk_gate *gate = NULL;
1105 struct clk_fixed_factor *fix_factor;
1106 struct clk_divider *divider;
1109 int flags, clkflags;
1111 /* Set up factor clock that we will be dividing */
1112 pclk = sunxi_factors_clk_setup(node, data->factors);
1113 parent = __clk_get_name(pclk);
1115 reg = of_iomap(node, 0);
1117 clk_data = kmalloc(sizeof(struct clk_onecell_data), GFP_KERNEL);
1121 clks = kzalloc((SUNXI_DIVS_MAX_QTY+1) * sizeof(*clks), GFP_KERNEL);
1125 clk_data->clks = clks;
1127 /* It's not a good idea to have automatic reparenting changing
1129 clkflags = !strcmp("pll5", parent) ? 0 : CLK_SET_RATE_PARENT;
1131 for (i = 0; i < SUNXI_DIVS_MAX_QTY; i++) {
1132 if (of_property_read_string_index(node, "clock-output-names",
1140 /* If this leaf clock can be gated, create a gate */
1141 if (data->div[i].gate) {
1142 gate = kzalloc(sizeof(*gate), GFP_KERNEL);
1147 gate->bit_idx = data->div[i].gate;
1148 gate->lock = &clk_lock;
1150 gate_hw = &gate->hw;
1153 /* Leaves can be fixed or configurable divisors */
1154 if (data->div[i].fixed) {
1155 fix_factor = kzalloc(sizeof(*fix_factor), GFP_KERNEL);
1159 fix_factor->mult = 1;
1160 fix_factor->div = data->div[i].fixed;
1162 rate_hw = &fix_factor->hw;
1163 rate_ops = &clk_fixed_factor_ops;
1165 divider = kzalloc(sizeof(*divider), GFP_KERNEL);
1169 flags = data->div[i].pow ? CLK_DIVIDER_POWER_OF_TWO : 0;
1172 divider->shift = data->div[i].shift;
1173 divider->width = SUNXI_DIVISOR_WIDTH;
1174 divider->flags = flags;
1175 divider->lock = &clk_lock;
1176 divider->table = data->div[i].table;
1178 rate_hw = ÷r->hw;
1179 rate_ops = &clk_divider_ops;
1182 /* Wrap the (potential) gate and the divisor on a composite
1183 * clock to unify them */
1184 clks[i] = clk_register_composite(NULL, clk_name, &parent, 1,
1187 gate_hw, &clk_gate_ops,
1190 WARN_ON(IS_ERR(clk_data->clks[i]));
1191 clk_register_clkdev(clks[i], clk_name, NULL);
1194 /* The last clock available on the getter is the parent */
1197 /* Adjust to the real max */
1198 clk_data->clk_num = i;
1200 of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
1214 /* Matches for factors clocks */
1215 static const struct of_device_id clk_factors_match[] __initconst = {
1216 {.compatible = "allwinner,sun4i-a10-pll1-clk", .data = &sun4i_pll1_data,},
1217 {.compatible = "allwinner,sun6i-a31-pll1-clk", .data = &sun6i_a31_pll1_data,},
1218 {.compatible = "allwinner,sun7i-a20-pll4-clk", .data = &sun7i_a20_pll4_data,},
1219 {.compatible = "allwinner,sun6i-a31-pll6-clk", .data = &sun6i_a31_pll6_data,},
1220 {.compatible = "allwinner,sun4i-a10-apb1-clk", .data = &sun4i_apb1_data,},
1221 {.compatible = "allwinner,sun4i-a10-mod0-clk", .data = &sun4i_mod0_data,},
1222 {.compatible = "allwinner,sun7i-a20-out-clk", .data = &sun7i_a20_out_data,},
1226 /* Matches for divider clocks */
1227 static const struct of_device_id clk_div_match[] __initconst = {
1228 {.compatible = "allwinner,sun4i-a10-axi-clk", .data = &sun4i_axi_data,},
1229 {.compatible = "allwinner,sun4i-a10-ahb-clk", .data = &sun4i_ahb_data,},
1230 {.compatible = "allwinner,sun4i-a10-apb0-clk", .data = &sun4i_apb0_data,},
1231 {.compatible = "allwinner,sun6i-a31-apb2-div-clk", .data = &sun6i_a31_apb2_div_data,},
1235 /* Matches for divided outputs */
1236 static const struct of_device_id clk_divs_match[] __initconst = {
1237 {.compatible = "allwinner,sun4i-a10-pll5-clk", .data = &pll5_divs_data,},
1238 {.compatible = "allwinner,sun4i-a10-pll6-clk", .data = &pll6_divs_data,},
1242 /* Matches for mux clocks */
1243 static const struct of_device_id clk_mux_match[] __initconst = {
1244 {.compatible = "allwinner,sun4i-a10-cpu-clk", .data = &sun4i_cpu_mux_data,},
1245 {.compatible = "allwinner,sun4i-a10-apb1-mux-clk", .data = &sun4i_apb1_mux_data,},
1246 {.compatible = "allwinner,sun6i-a31-ahb1-mux-clk", .data = &sun6i_a31_ahb1_mux_data,},
1250 /* Matches for gate clocks */
1251 static const struct of_device_id clk_gates_match[] __initconst = {
1252 {.compatible = "allwinner,sun4i-a10-axi-gates-clk", .data = &sun4i_axi_gates_data,},
1253 {.compatible = "allwinner,sun4i-a10-ahb-gates-clk", .data = &sun4i_ahb_gates_data,},
1254 {.compatible = "allwinner,sun5i-a10s-ahb-gates-clk", .data = &sun5i_a10s_ahb_gates_data,},
1255 {.compatible = "allwinner,sun5i-a13-ahb-gates-clk", .data = &sun5i_a13_ahb_gates_data,},
1256 {.compatible = "allwinner,sun6i-a31-ahb1-gates-clk", .data = &sun6i_a31_ahb1_gates_data,},
1257 {.compatible = "allwinner,sun7i-a20-ahb-gates-clk", .data = &sun7i_a20_ahb_gates_data,},
1258 {.compatible = "allwinner,sun4i-a10-apb0-gates-clk", .data = &sun4i_apb0_gates_data,},
1259 {.compatible = "allwinner,sun5i-a10s-apb0-gates-clk", .data = &sun5i_a10s_apb0_gates_data,},
1260 {.compatible = "allwinner,sun5i-a13-apb0-gates-clk", .data = &sun5i_a13_apb0_gates_data,},
1261 {.compatible = "allwinner,sun7i-a20-apb0-gates-clk", .data = &sun7i_a20_apb0_gates_data,},
1262 {.compatible = "allwinner,sun4i-a10-apb1-gates-clk", .data = &sun4i_apb1_gates_data,},
1263 {.compatible = "allwinner,sun5i-a10s-apb1-gates-clk", .data = &sun5i_a10s_apb1_gates_data,},
1264 {.compatible = "allwinner,sun5i-a13-apb1-gates-clk", .data = &sun5i_a13_apb1_gates_data,},
1265 {.compatible = "allwinner,sun6i-a31-apb1-gates-clk", .data = &sun6i_a31_apb1_gates_data,},
1266 {.compatible = "allwinner,sun7i-a20-apb1-gates-clk", .data = &sun7i_a20_apb1_gates_data,},
1267 {.compatible = "allwinner,sun6i-a31-apb2-gates-clk", .data = &sun6i_a31_apb2_gates_data,},
1268 {.compatible = "allwinner,sun4i-a10-usb-clk", .data = &sun4i_a10_usb_gates_data,},
1269 {.compatible = "allwinner,sun5i-a13-usb-clk", .data = &sun5i_a13_usb_gates_data,},
1273 static void __init of_sunxi_table_clock_setup(const struct of_device_id *clk_match,
1276 struct device_node *np;
1277 const struct div_data *data;
1278 const struct of_device_id *match;
1279 void (*setup_function)(struct device_node *, const void *) = function;
1281 for_each_matching_node_and_match(np, clk_match, &match) {
1283 setup_function(np, data);
1288 * System clock protection
1290 * By enabling these critical clocks, we prevent their accidental gating
1293 static void __init sunxi_clock_protect(void)
1297 /* memory bus clock - sun5i+ */
1298 clk = clk_get(NULL, "mbus");
1300 clk_prepare_enable(clk);
1304 /* DDR clock - sun4i+ */
1305 clk = clk_get(NULL, "pll5_ddr");
1307 clk_prepare_enable(clk);
1312 static void __init sunxi_init_clocks(void)
1314 /* Register factor clocks */
1315 of_sunxi_table_clock_setup(clk_factors_match, sunxi_factors_clk_setup);
1317 /* Register divider clocks */
1318 of_sunxi_table_clock_setup(clk_div_match, sunxi_divider_clk_setup);
1320 /* Register divided output clocks */
1321 of_sunxi_table_clock_setup(clk_divs_match, sunxi_divs_clk_setup);
1323 /* Register mux clocks */
1324 of_sunxi_table_clock_setup(clk_mux_match, sunxi_mux_clk_setup);
1326 /* Register gate clocks */
1327 of_sunxi_table_clock_setup(clk_gates_match, sunxi_gates_clk_setup);
1329 /* Enable core system clocks */
1330 sunxi_clock_protect();
1332 CLK_OF_DECLARE(sun4i_a10_clk_init, "allwinner,sun4i-a10", sunxi_init_clocks);
1333 CLK_OF_DECLARE(sun5i_a10s_clk_init, "allwinner,sun5i-a10s", sunxi_init_clocks);
1334 CLK_OF_DECLARE(sun5i_a13_clk_init, "allwinner,sun5i-a13", sunxi_init_clocks);
1335 CLK_OF_DECLARE(sun6i_a31_clk_init, "allwinner,sun6i-a31", sunxi_init_clocks);
1336 CLK_OF_DECLARE(sun7i_a20_clk_init, "allwinner,sun7i-a20", sunxi_init_clocks);