drivers/clk/tegra/clk-pll.c

   1 /*
   2  * Copyright (c) 2012, 2013, NVIDIA CORPORATION.  All rights reserved.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms and conditions of the GNU General Public License,
   6  * version 2, as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope it will be useful, but WITHOUT
   9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  11  * more details.
  12  *
  13  * You should have received a copy of the GNU General Public License
  14  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  15  */
  16
  17 #include <linux/slab.h>
  18 #include <linux/io.h>
  19 #include <linux/delay.h>
  20 #include <linux/err.h>
  21 #include <linux/clk-provider.h>
  22 #include <linux/clk.h>
  23
  24 #include "clk.h"
  25
  26 #define PLL_BASE_BYPASS BIT(31)
  27 #define PLL_BASE_ENABLE BIT(30)
  28 #define PLL_BASE_REF_ENABLE BIT(29)
  29 #define PLL_BASE_OVERRIDE BIT(28)
  30
  31 #define PLL_BASE_DIVP_SHIFT 20
  32 #define PLL_BASE_DIVP_WIDTH 3
  33 #define PLL_BASE_DIVN_SHIFT 8
  34 #define PLL_BASE_DIVN_WIDTH 10
  35 #define PLL_BASE_DIVM_SHIFT 0
  36 #define PLL_BASE_DIVM_WIDTH 5
  37 #define PLLU_POST_DIVP_MASK 0x1
  38
  39 #define PLL_MISC_DCCON_SHIFT 20
  40 #define PLL_MISC_CPCON_SHIFT 8
  41 #define PLL_MISC_CPCON_WIDTH 4
  42 #define PLL_MISC_CPCON_MASK ((1 << PLL_MISC_CPCON_WIDTH) - 1)
  43 #define PLL_MISC_LFCON_SHIFT 4
  44 #define PLL_MISC_LFCON_WIDTH 4
  45 #define PLL_MISC_LFCON_MASK ((1 << PLL_MISC_LFCON_WIDTH) - 1)
  46 #define PLL_MISC_VCOCON_SHIFT 0
  47 #define PLL_MISC_VCOCON_WIDTH 4
  48 #define PLL_MISC_VCOCON_MASK ((1 << PLL_MISC_VCOCON_WIDTH) - 1)
  49
  50 #define OUT_OF_TABLE_CPCON 8
  51
  52 #define PMC_PLLP_WB0_OVERRIDE 0xf8
  53 #define PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE BIT(12)
  54 #define PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE BIT(11)
  55
  56 #define PLL_POST_LOCK_DELAY 50
  57
  58 #define PLLDU_LFCON_SET_DIVN 600
  59
  60 #define PLLE_BASE_DIVCML_SHIFT 24
  61 #define PLLE_BASE_DIVCML_MASK 0xf
  62 #define PLLE_BASE_DIVP_SHIFT 16
  63 #define PLLE_BASE_DIVP_WIDTH 6
  64 #define PLLE_BASE_DIVN_SHIFT 8
  65 #define PLLE_BASE_DIVN_WIDTH 8
  66 #define PLLE_BASE_DIVM_SHIFT 0
  67 #define PLLE_BASE_DIVM_WIDTH 8
  68
  69 #define PLLE_MISC_SETUP_BASE_SHIFT 16
  70 #define PLLE_MISC_SETUP_BASE_MASK (0xffff << PLLE_MISC_SETUP_BASE_SHIFT)
  71 #define PLLE_MISC_LOCK_ENABLE BIT(9)
  72 #define PLLE_MISC_READY BIT(15)
  73 #define PLLE_MISC_SETUP_EX_SHIFT 2
  74 #define PLLE_MISC_SETUP_EX_MASK (3 << PLLE_MISC_SETUP_EX_SHIFT)
  75 #define PLLE_MISC_SETUP_MASK (PLLE_MISC_SETUP_BASE_MASK |       \
  76                               PLLE_MISC_SETUP_EX_MASK)
  77 #define PLLE_MISC_SETUP_VALUE (7 << PLLE_MISC_SETUP_BASE_SHIFT)
  78
  79 #define PLLE_SS_CTRL 0x68
  80 #define PLLE_SS_CNTL_BYPASS_SS BIT(10)
  81 #define PLLE_SS_CNTL_INTERP_RESET BIT(11)
  82 #define PLLE_SS_CNTL_SSC_BYP BIT(12)
  83 #define PLLE_SS_CNTL_CENTER BIT(14)
  84 #define PLLE_SS_CNTL_INVERT BIT(15)
  85 #define PLLE_SS_DISABLE (PLLE_SS_CNTL_BYPASS_SS | PLLE_SS_CNTL_INTERP_RESET |\
  86                                 PLLE_SS_CNTL_SSC_BYP)
  87 #define PLLE_SS_MAX_MASK 0x1ff
  88 #define PLLE_SS_MAX_VAL 0x25
  89 #define PLLE_SS_INC_MASK (0xff << 16)
  90 #define PLLE_SS_INC_VAL (0x1 << 16)
  91 #define PLLE_SS_INCINTRV_MASK (0x3f << 24)
  92 #define PLLE_SS_INCINTRV_VAL (0x20 << 24)
  93 #define PLLE_SS_COEFFICIENTS_MASK \
  94         (PLLE_SS_MAX_MASK | PLLE_SS_INC_MASK | PLLE_SS_INCINTRV_MASK)
  95 #define PLLE_SS_COEFFICIENTS_VAL \
  96         (PLLE_SS_MAX_VAL | PLLE_SS_INC_VAL | PLLE_SS_INCINTRV_VAL)
  97
  98 #define PLLE_AUX_PLLP_SEL       BIT(2)
  99 #define PLLE_AUX_USE_LOCKDET    BIT(3)
 100 #define PLLE_AUX_ENABLE_SWCTL   BIT(4)
 101 #define PLLE_AUX_SS_SWCTL       BIT(6)
 102 #define PLLE_AUX_SEQ_ENABLE     BIT(24)
 103 #define PLLE_AUX_SEQ_START_STATE BIT(25)
 104 #define PLLE_AUX_PLLRE_SEL      BIT(28)
 105
 106 #define XUSBIO_PLL_CFG0         0x51c
 107 #define XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL      BIT(0)
 108 #define XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL        BIT(2)
 109 #define XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET      BIT(6)
 110 #define XUSBIO_PLL_CFG0_SEQ_ENABLE              BIT(24)
 111 #define XUSBIO_PLL_CFG0_SEQ_START_STATE         BIT(25)
 112
 113 #define SATA_PLL_CFG0           0x490
 114 #define SATA_PLL_CFG0_PADPLL_RESET_SWCTL        BIT(0)
 115 #define SATA_PLL_CFG0_PADPLL_USE_LOCKDET        BIT(2)
 116 #define SATA_PLL_CFG0_SEQ_ENABLE                BIT(24)
 117 #define SATA_PLL_CFG0_SEQ_START_STATE           BIT(25)
 118
 119 #define PLLE_MISC_PLLE_PTS      BIT(8)
 120 #define PLLE_MISC_IDDQ_SW_VALUE BIT(13)
 121 #define PLLE_MISC_IDDQ_SW_CTRL  BIT(14)
 122 #define PLLE_MISC_VREG_BG_CTRL_SHIFT    4
 123 #define PLLE_MISC_VREG_BG_CTRL_MASK     (3 << PLLE_MISC_VREG_BG_CTRL_SHIFT)
 124 #define PLLE_MISC_VREG_CTRL_SHIFT       2
 125 #define PLLE_MISC_VREG_CTRL_MASK        (2 << PLLE_MISC_VREG_CTRL_SHIFT)
 126
 127 #define PLLCX_MISC_STROBE       BIT(31)
 128 #define PLLCX_MISC_RESET        BIT(30)
 129 #define PLLCX_MISC_SDM_DIV_SHIFT 28
 130 #define PLLCX_MISC_SDM_DIV_MASK (0x3 << PLLCX_MISC_SDM_DIV_SHIFT)
 131 #define PLLCX_MISC_FILT_DIV_SHIFT 26
 132 #define PLLCX_MISC_FILT_DIV_MASK (0x3 << PLLCX_MISC_FILT_DIV_SHIFT)
 133 #define PLLCX_MISC_ALPHA_SHIFT 18
 134 #define PLLCX_MISC_DIV_LOW_RANGE \
 135                 ((0x1 << PLLCX_MISC_SDM_DIV_SHIFT) | \
 136                 (0x1 << PLLCX_MISC_FILT_DIV_SHIFT))
 137 #define PLLCX_MISC_DIV_HIGH_RANGE \
 138                 ((0x2 << PLLCX_MISC_SDM_DIV_SHIFT) | \
 139                 (0x2 << PLLCX_MISC_FILT_DIV_SHIFT))
 140 #define PLLCX_MISC_COEF_LOW_RANGE \
 141                 ((0x14 << PLLCX_MISC_KA_SHIFT) | (0x38 << PLLCX_MISC_KB_SHIFT))
 142 #define PLLCX_MISC_KA_SHIFT 2
 143 #define PLLCX_MISC_KB_SHIFT 9
 144 #define PLLCX_MISC_DEFAULT (PLLCX_MISC_COEF_LOW_RANGE | \
 145                             (0x19 << PLLCX_MISC_ALPHA_SHIFT) | \
 146                             PLLCX_MISC_DIV_LOW_RANGE | \
 147                             PLLCX_MISC_RESET)
 148 #define PLLCX_MISC1_DEFAULT 0x000d2308
 149 #define PLLCX_MISC2_DEFAULT 0x30211200
 150 #define PLLCX_MISC3_DEFAULT 0x200
 151
 152 #define PMC_SATA_PWRGT 0x1ac
 153 #define PMC_SATA_PWRGT_PLLE_IDDQ_VALUE BIT(5)
 154 #define PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL BIT(4)
 155
 156 #define PLLSS_MISC_KCP          0
 157 #define PLLSS_MISC_KVCO         0
 158 #define PLLSS_MISC_SETUP        0
 159 #define PLLSS_EN_SDM            0
 160 #define PLLSS_EN_SSC            0
 161 #define PLLSS_EN_DITHER2        0
 162 #define PLLSS_EN_DITHER         1
 163 #define PLLSS_SDM_RESET         0
 164 #define PLLSS_CLAMP             0
 165 #define PLLSS_SDM_SSC_MAX       0
 166 #define PLLSS_SDM_SSC_MIN       0
 167 #define PLLSS_SDM_SSC_STEP      0
 168 #define PLLSS_SDM_DIN           0
 169 #define PLLSS_MISC_DEFAULT ((PLLSS_MISC_KCP << 25) | \
 170                             (PLLSS_MISC_KVCO << 24) | \
 171                             PLLSS_MISC_SETUP)
 172 #define PLLSS_CFG_DEFAULT ((PLLSS_EN_SDM << 31) | \
 173                            (PLLSS_EN_SSC << 30) | \
 174                            (PLLSS_EN_DITHER2 << 29) | \
 175                            (PLLSS_EN_DITHER << 28) | \
 176                            (PLLSS_SDM_RESET) << 27 | \
 177                            (PLLSS_CLAMP << 22))
 178 #define PLLSS_CTRL1_DEFAULT \
 179                         ((PLLSS_SDM_SSC_MAX << 16) | PLLSS_SDM_SSC_MIN)
 180 #define PLLSS_CTRL2_DEFAULT \
 181                         ((PLLSS_SDM_SSC_STEP << 16) | PLLSS_SDM_DIN)
 182 #define PLLSS_LOCK_OVERRIDE     BIT(24)
 183 #define PLLSS_REF_SRC_SEL_SHIFT 25
 184 #define PLLSS_REF_SRC_SEL_MASK  (3 << PLLSS_REF_SRC_SEL_SHIFT)
 185
 186 #define pll_readl(offset, p) readl_relaxed(p->clk_base + offset)
 187 #define pll_readl_base(p) pll_readl(p->params->base_reg, p)
 188 #define pll_readl_misc(p) pll_readl(p->params->misc_reg, p)
 189 #define pll_override_readl(offset, p) readl_relaxed(p->pmc + offset)
 190
 191 #define pll_writel(val, offset, p) writel_relaxed(val, p->clk_base + offset)
 192 #define pll_writel_base(val, p) pll_writel(val, p->params->base_reg, p)
 193 #define pll_writel_misc(val, p) pll_writel(val, p->params->misc_reg, p)
 194 #define pll_override_writel(val, offset, p) writel(val, p->pmc + offset)
 195
 196 #define mask(w) ((1 << (w)) - 1)
 197 #define divm_mask(p) mask(p->params->div_nmp->divm_width)
 198 #define divn_mask(p) mask(p->params->div_nmp->divn_width)
 199 #define divp_mask(p) (p->params->flags & TEGRA_PLLU ? PLLU_POST_DIVP_MASK :\
 200                       mask(p->params->div_nmp->divp_width))
 201
 202 #define divm_shift(p) (p)->params->div_nmp->divm_shift
 203 #define divn_shift(p) (p)->params->div_nmp->divn_shift
 204 #define divp_shift(p) (p)->params->div_nmp->divp_shift
 205
 206 #define divm_mask_shifted(p) (divm_mask(p) << divm_shift(p))
 207 #define divn_mask_shifted(p) (divn_mask(p) << divn_shift(p))
 208 #define divp_mask_shifted(p) (divp_mask(p) << divp_shift(p))
 209
 210 #define divm_max(p) (divm_mask(p))
 211 #define divn_max(p) (divn_mask(p))
 212 #define divp_max(p) (1 << (divp_mask(p)))
 213
 214 static struct div_nmp default_nmp = {
 215         .divn_shift = PLL_BASE_DIVN_SHIFT,
 216         .divn_width = PLL_BASE_DIVN_WIDTH,
 217         .divm_shift = PLL_BASE_DIVM_SHIFT,
 218         .divm_width = PLL_BASE_DIVM_WIDTH,
 219         .divp_shift = PLL_BASE_DIVP_SHIFT,
 220         .divp_width = PLL_BASE_DIVP_WIDTH,
 221 };
 222
 223 static void clk_pll_enable_lock(struct tegra_clk_pll *pll)
 224 {
 225         u32 val;
 226
 227         if (!(pll->params->flags & TEGRA_PLL_USE_LOCK))
 228                 return;
 229
 230         if (!(pll->params->flags & TEGRA_PLL_HAS_LOCK_ENABLE))
 231                 return;
 232
 233         val = pll_readl_misc(pll);
 234         val |= BIT(pll->params->lock_enable_bit_idx);
 235         pll_writel_misc(val, pll);
 236 }
 237
 238 static int clk_pll_wait_for_lock(struct tegra_clk_pll *pll)
 239 {
 240         int i;
 241         u32 val, lock_mask;
 242         void __iomem *lock_addr;
 243
 244         if (!(pll->params->flags & TEGRA_PLL_USE_LOCK)) {
 245                 udelay(pll->params->lock_delay);
 246                 return 0;
 247         }
 248
 249         lock_addr = pll->clk_base;
 250         if (pll->params->flags & TEGRA_PLL_LOCK_MISC)
 251                 lock_addr += pll->params->misc_reg;
 252         else
 253                 lock_addr += pll->params->base_reg;
 254
 255         lock_mask = pll->params->lock_mask;
 256
 257         for (i = 0; i < pll->params->lock_delay; i++) {
 258                 val = readl_relaxed(lock_addr);
 259                 if ((val & lock_mask) == lock_mask) {
 260                         udelay(PLL_POST_LOCK_DELAY);
 261                         return 0;
 262                 }
 263                 udelay(2); /* timeout = 2 * lock time */
 264         }
 265
 266         pr_err("%s: Timed out waiting for pll %s lock\n", __func__,
 267                __clk_get_name(pll->hw.clk));
 268
 269         return -1;
 270 }
 271
 272 static int clk_pll_is_enabled(struct clk_hw *hw)
 273 {
 274         struct tegra_clk_pll *pll = to_clk_pll(hw);
 275         u32 val;
 276
 277         if (pll->params->flags & TEGRA_PLLM) {
 278                 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE);
 279                 if (val & PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE)
 280                         return val & PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE ? 1 : 0;
 281         }
 282
 283         val = pll_readl_base(pll);
 284
 285         return val & PLL_BASE_ENABLE ? 1 : 0;
 286 }
 287
 288 static void _clk_pll_enable(struct clk_hw *hw)
 289 {
 290         struct tegra_clk_pll *pll = to_clk_pll(hw);
 291         u32 val;
 292
 293         clk_pll_enable_lock(pll);
 294
 295         val = pll_readl_base(pll);
 296         if (pll->params->flags & TEGRA_PLL_BYPASS)
 297                 val &= ~PLL_BASE_BYPASS;
 298         val |= PLL_BASE_ENABLE;
 299         pll_writel_base(val, pll);
 300
 301         if (pll->params->flags & TEGRA_PLLM) {
 302                 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE);
 303                 val |= PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE;
 304                 writel_relaxed(val, pll->pmc + PMC_PLLP_WB0_OVERRIDE);
 305         }
 306 }
 307
 308 static void _clk_pll_disable(struct clk_hw *hw)
 309 {
 310         struct tegra_clk_pll *pll = to_clk_pll(hw);
 311         u32 val;
 312
 313         val = pll_readl_base(pll);
 314         if (pll->params->flags & TEGRA_PLL_BYPASS)
 315                 val &= ~PLL_BASE_BYPASS;
 316         val &= ~PLL_BASE_ENABLE;
 317         pll_writel_base(val, pll);
 318
 319         if (pll->params->flags & TEGRA_PLLM) {
 320                 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE);
 321                 val &= ~PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE;
 322                 writel_relaxed(val, pll->pmc + PMC_PLLP_WB0_OVERRIDE);
 323         }
 324 }
 325
 326 static int clk_pll_enable(struct clk_hw *hw)
 327 {
 328         struct tegra_clk_pll *pll = to_clk_pll(hw);
 329         unsigned long flags = 0;
 330         int ret;
 331
 332         if (pll->lock)
 333                 spin_lock_irqsave(pll->lock, flags);
 334
 335         _clk_pll_enable(hw);
 336
 337         ret = clk_pll_wait_for_lock(pll);
 338
 339         if (pll->lock)
 340                 spin_unlock_irqrestore(pll->lock, flags);
 341
 342         return ret;
 343 }
 344
 345 static void clk_pll_disable(struct clk_hw *hw)
 346 {
 347         struct tegra_clk_pll *pll = to_clk_pll(hw);
 348         unsigned long flags = 0;
 349
 350         if (pll->lock)
 351                 spin_lock_irqsave(pll->lock, flags);
 352
 353         _clk_pll_disable(hw);
 354
 355         if (pll->lock)
 356                 spin_unlock_irqrestore(pll->lock, flags);
 357 }
 358
 359 static int _p_div_to_hw(struct clk_hw *hw, u8 p_div)
 360 {
 361         struct tegra_clk_pll *pll = to_clk_pll(hw);
 362         struct pdiv_map *p_tohw = pll->params->pdiv_tohw;
 363
 364         if (p_tohw) {
 365                 while (p_tohw->pdiv) {
 366                         if (p_div <= p_tohw->pdiv)
 367                                 return p_tohw->hw_val;
 368                         p_tohw++;
 369                 }
 370                 return -EINVAL;
 371         }
 372         return -EINVAL;
 373 }
 374
 375 static int _hw_to_p_div(struct clk_hw *hw, u8 p_div_hw)
 376 {
 377         struct tegra_clk_pll *pll = to_clk_pll(hw);
 378         struct pdiv_map *p_tohw = pll->params->pdiv_tohw;
 379
 380         if (p_tohw) {
 381                 while (p_tohw->pdiv) {
 382                         if (p_div_hw == p_tohw->hw_val)
 383                                 return p_tohw->pdiv;
 384                         p_tohw++;
 385                 }
 386                 return -EINVAL;
 387         }
 388
 389         return 1 << p_div_hw;
 390 }
 391
 392 static int _get_table_rate(struct clk_hw *hw,
 393                            struct tegra_clk_pll_freq_table *cfg,
 394                            unsigned long rate, unsigned long parent_rate)
 395 {
 396         struct tegra_clk_pll *pll = to_clk_pll(hw);
 397         struct tegra_clk_pll_freq_table *sel;
 398
 399         for (sel = pll->params->freq_table; sel->input_rate != 0; sel++)
 400                 if (sel->input_rate == parent_rate &&
 401                     sel->output_rate == rate)
 402                         break;
 403
 404         if (sel->input_rate == 0)
 405                 return -EINVAL;
 406
 407         cfg->input_rate = sel->input_rate;
 408         cfg->output_rate = sel->output_rate;
 409         cfg->m = sel->m;
 410         cfg->n = sel->n;
 411         cfg->p = sel->p;
 412         cfg->cpcon = sel->cpcon;
 413
 414         return 0;
 415 }
 416
 417 static int _calc_rate(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg,
 418                       unsigned long rate, unsigned long parent_rate)
 419 {
 420         struct tegra_clk_pll *pll = to_clk_pll(hw);
 421         unsigned long cfreq;
 422         u32 p_div = 0;
 423         int ret;
 424
 425         switch (parent_rate) {
 426         case 12000000:
 427         case 26000000:
 428                 cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2000000;
 429                 break;
 430         case 13000000:
 431                 cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2600000;
 432                 break;
 433         case 16800000:
 434         case 19200000:
 435                 cfreq = (rate <= 1200000 * 1000) ? 1200000 : 2400000;
 436                 break;
 437         case 9600000:
 438         case 28800000:
 439                 /*
 440                  * PLL_P_OUT1 rate is not listed in PLLA table
 441                  */
 442                 cfreq = parent_rate/(parent_rate/1000000);
 443                 break;
 444         default:
 445                 pr_err("%s Unexpected reference rate %lu\n",
 446                        __func__, parent_rate);
 447                 BUG();
 448         }
 449
 450         /* Raise VCO to guarantee 0.5% accuracy */
 451         for (cfg->output_rate = rate; cfg->output_rate < 200 * cfreq;
 452              cfg->output_rate <<= 1)
 453                 p_div++;
 454
 455         cfg->m = parent_rate / cfreq;
 456         cfg->n = cfg->output_rate / cfreq;
 457         cfg->cpcon = OUT_OF_TABLE_CPCON;
 458
 459         if (cfg->m > divm_max(pll) || cfg->n > divn_max(pll) ||
 460             (1 << p_div) > divp_max(pll)
 461             || cfg->output_rate > pll->params->vco_max) {
 462                 return -EINVAL;
 463         }
 464
 465         cfg->output_rate >>= p_div;
 466
 467         if (pll->params->pdiv_tohw) {
 468                 ret = _p_div_to_hw(hw, 1 << p_div);
 469                 if (ret < 0)
 470                         return ret;
 471                 else
 472                         cfg->p = ret;
 473         } else
 474                 cfg->p = p_div;
 475
 476         return 0;
 477 }
 478
 479 static void _update_pll_mnp(struct tegra_clk_pll *pll,
 480                             struct tegra_clk_pll_freq_table *cfg)
 481 {
 482         u32 val;
 483         struct tegra_clk_pll_params *params = pll->params;
 484         struct div_nmp *div_nmp = params->div_nmp;
 485
 486         if ((params->flags & TEGRA_PLLM) &&
 487                 (pll_override_readl(PMC_PLLP_WB0_OVERRIDE, pll) &
 488                         PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE)) {
 489                 val = pll_override_readl(params->pmc_divp_reg, pll);
 490                 val &= ~(divp_mask(pll) << div_nmp->override_divp_shift);
 491                 val |= cfg->p << div_nmp->override_divp_shift;
 492                 pll_override_writel(val, params->pmc_divp_reg, pll);
 493
 494                 val = pll_override_readl(params->pmc_divnm_reg, pll);
 495                 val &= ~(divm_mask(pll) << div_nmp->override_divm_shift) |
 496                         ~(divn_mask(pll) << div_nmp->override_divn_shift);
 497                 val |= (cfg->m << div_nmp->override_divm_shift) |
 498                         (cfg->n << div_nmp->override_divn_shift);
 499                 pll_override_writel(val, params->pmc_divnm_reg, pll);
 500         } else {
 501                 val = pll_readl_base(pll);
 502
 503                 val &= ~(divm_mask_shifted(pll) | divn_mask_shifted(pll) |
 504                          divp_mask_shifted(pll));
 505
 506                 val |= (cfg->m << divm_shift(pll)) |
 507                        (cfg->n << divn_shift(pll)) |
 508                        (cfg->p << divp_shift(pll));
 509
 510                 pll_writel_base(val, pll);
 511         }
 512 }
 513
 514 static void _get_pll_mnp(struct tegra_clk_pll *pll,
 515                          struct tegra_clk_pll_freq_table *cfg)
 516 {
 517         u32 val;
 518         struct tegra_clk_pll_params *params = pll->params;
 519         struct div_nmp *div_nmp = params->div_nmp;
 520
 521         if ((params->flags & TEGRA_PLLM) &&
 522                 (pll_override_readl(PMC_PLLP_WB0_OVERRIDE, pll) &
 523                         PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE)) {
 524                 val = pll_override_readl(params->pmc_divp_reg, pll);
 525                 cfg->p = (val >> div_nmp->override_divp_shift) & divp_mask(pll);
 526
 527                 val = pll_override_readl(params->pmc_divnm_reg, pll);
 528                 cfg->m = (val >> div_nmp->override_divm_shift) & divm_mask(pll);
 529                 cfg->n = (val >> div_nmp->override_divn_shift) & divn_mask(pll);
 530         }  else {
 531                 val = pll_readl_base(pll);
 532
 533                 cfg->m = (val >> div_nmp->divm_shift) & divm_mask(pll);
 534                 cfg->n = (val >> div_nmp->divn_shift) & divn_mask(pll);
 535                 cfg->p = (val >> div_nmp->divp_shift) & divp_mask(pll);
 536         }
 537 }
 538
 539 static void _update_pll_cpcon(struct tegra_clk_pll *pll,
 540                               struct tegra_clk_pll_freq_table *cfg,
 541                               unsigned long rate)
 542 {
 543         u32 val;
 544
 545         val = pll_readl_misc(pll);
 546
 547         val &= ~(PLL_MISC_CPCON_MASK << PLL_MISC_CPCON_SHIFT);
 548         val |= cfg->cpcon << PLL_MISC_CPCON_SHIFT;
 549
 550         if (pll->params->flags & TEGRA_PLL_SET_LFCON) {
 551                 val &= ~(PLL_MISC_LFCON_MASK << PLL_MISC_LFCON_SHIFT);
 552                 if (cfg->n >= PLLDU_LFCON_SET_DIVN)
 553                         val |= 1 << PLL_MISC_LFCON_SHIFT;
 554         } else if (pll->params->flags & TEGRA_PLL_SET_DCCON) {
 555                 val &= ~(1 << PLL_MISC_DCCON_SHIFT);
 556                 if (rate >= (pll->params->vco_max >> 1))
 557                         val |= 1 << PLL_MISC_DCCON_SHIFT;
 558         }
 559
 560         pll_writel_misc(val, pll);
 561 }
 562
 563 static int _program_pll(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg,
 564                         unsigned long rate)
 565 {
 566         struct tegra_clk_pll *pll = to_clk_pll(hw);
 567         int state, ret = 0;
 568
 569         state = clk_pll_is_enabled(hw);
 570
 571         if (state)
 572                 _clk_pll_disable(hw);
 573
 574         _update_pll_mnp(pll, cfg);
 575
 576         if (pll->params->flags & TEGRA_PLL_HAS_CPCON)
 577                 _update_pll_cpcon(pll, cfg, rate);
 578
 579         if (state) {
 580                 _clk_pll_enable(hw);
 581                 ret = clk_pll_wait_for_lock(pll);
 582         }
 583
 584         return ret;
 585 }
 586
 587 static int clk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
 588                         unsigned long parent_rate)
 589 {
 590         struct tegra_clk_pll *pll = to_clk_pll(hw);
 591         struct tegra_clk_pll_freq_table cfg, old_cfg;
 592         unsigned long flags = 0;
 593         int ret = 0;
 594
 595         if (pll->params->flags & TEGRA_PLL_FIXED) {
 596                 if (rate != pll->params->fixed_rate) {
 597                         pr_err("%s: Can not change %s fixed rate %lu to %lu\n",
 598                                 __func__, __clk_get_name(hw->clk),
 599                                 pll->params->fixed_rate, rate);
 600                         return -EINVAL;
 601                 }
 602                 return 0;
 603         }
 604
 605         if (_get_table_rate(hw, &cfg, rate, parent_rate) &&
 606             _calc_rate(hw, &cfg, rate, parent_rate)) {
 607                 pr_err("%s: Failed to set %s rate %lu\n", __func__,
 608                        __clk_get_name(hw->clk), rate);
 609                 WARN_ON(1);
 610                 return -EINVAL;
 611         }
 612         if (pll->lock)
 613                 spin_lock_irqsave(pll->lock, flags);
 614
 615         _get_pll_mnp(pll, &old_cfg);
 616
 617         if (old_cfg.m != cfg.m || old_cfg.n != cfg.n || old_cfg.p != cfg.p)
 618                 ret = _program_pll(hw, &cfg, rate);
 619
 620         if (pll->lock)
 621                 spin_unlock_irqrestore(pll->lock, flags);
 622
 623         return ret;
 624 }
 625
 626 static long clk_pll_round_rate(struct clk_hw *hw, unsigned long rate,
 627                         unsigned long *prate)
 628 {
 629         struct tegra_clk_pll *pll = to_clk_pll(hw);
 630         struct tegra_clk_pll_freq_table cfg;
 631
 632         if (pll->params->flags & TEGRA_PLL_FIXED)
 633                 return pll->params->fixed_rate;
 634
 635         /* PLLM is used for memory; we do not change rate */
 636         if (pll->params->flags & TEGRA_PLLM)
 637                 return __clk_get_rate(hw->clk);
 638
 639         if (_get_table_rate(hw, &cfg, rate, *prate) &&
 640             _calc_rate(hw, &cfg, rate, *prate))
 641                 return -EINVAL;
 642
 643         return cfg.output_rate;
 644 }
 645
 646 static unsigned long clk_pll_recalc_rate(struct clk_hw *hw,
 647                                          unsigned long parent_rate)
 648 {
 649         struct tegra_clk_pll *pll = to_clk_pll(hw);
 650         struct tegra_clk_pll_freq_table cfg;
 651         u32 val;
 652         u64 rate = parent_rate;
 653         int pdiv;
 654
 655         val = pll_readl_base(pll);
 656
 657         if ((pll->params->flags & TEGRA_PLL_BYPASS) && (val & PLL_BASE_BYPASS))
 658                 return parent_rate;
 659
 660         if ((pll->params->flags & TEGRA_PLL_FIXED) &&
 661                         !(val & PLL_BASE_OVERRIDE)) {
 662                 struct tegra_clk_pll_freq_table sel;
 663                 if (_get_table_rate(hw, &sel, pll->params->fixed_rate,
 664                                         parent_rate)) {
 665                         pr_err("Clock %s has unknown fixed frequency\n",
 666                                __clk_get_name(hw->clk));
 667                         BUG();
 668                 }
 669                 return pll->params->fixed_rate;
 670         }
 671
 672         _get_pll_mnp(pll, &cfg);
 673
 674         pdiv = _hw_to_p_div(hw, cfg.p);
 675         if (pdiv < 0) {
 676                 WARN_ON(1);
 677                 pdiv = 1;
 678         }
 679
 680         cfg.m *= pdiv;
 681
 682         rate *= cfg.n;
 683         do_div(rate, cfg.m);
 684
 685         return rate;
 686 }
 687
 688 static int clk_plle_training(struct tegra_clk_pll *pll)
 689 {
 690         u32 val;
 691         unsigned long timeout;
 692
 693         if (!pll->pmc)
 694                 return -ENOSYS;
 695
 696         /*
 697          * PLLE is already disabled, and setup cleared;
 698          * create falling edge on PLLE IDDQ input.
 699          */
 700         val = readl(pll->pmc + PMC_SATA_PWRGT);
 701         val |= PMC_SATA_PWRGT_PLLE_IDDQ_VALUE;
 702         writel(val, pll->pmc + PMC_SATA_PWRGT);
 703
 704         val = readl(pll->pmc + PMC_SATA_PWRGT);
 705         val |= PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL;
 706         writel(val, pll->pmc + PMC_SATA_PWRGT);
 707
 708         val = readl(pll->pmc + PMC_SATA_PWRGT);
 709         val &= ~PMC_SATA_PWRGT_PLLE_IDDQ_VALUE;
 710         writel(val, pll->pmc + PMC_SATA_PWRGT);
 711
 712         val = pll_readl_misc(pll);
 713
 714         timeout = jiffies + msecs_to_jiffies(100);
 715         while (1) {
 716                 val = pll_readl_misc(pll);
 717                 if (val & PLLE_MISC_READY)
 718                         break;
 719                 if (time_after(jiffies, timeout)) {
 720                         pr_err("%s: timeout waiting for PLLE\n", __func__);
 721                         return -EBUSY;
 722                 }
 723                 udelay(300);
 724         }
 725
 726         return 0;
 727 }
 728
 729 static int clk_plle_enable(struct clk_hw *hw)
 730 {
 731         struct tegra_clk_pll *pll = to_clk_pll(hw);
 732         unsigned long input_rate = clk_get_rate(clk_get_parent(hw->clk));
 733         struct tegra_clk_pll_freq_table sel;
 734         u32 val;
 735         int err;
 736
 737         if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate))
 738                 return -EINVAL;
 739
 740         clk_pll_disable(hw);
 741
 742         val = pll_readl_misc(pll);
 743         val &= ~(PLLE_MISC_LOCK_ENABLE | PLLE_MISC_SETUP_MASK);
 744         pll_writel_misc(val, pll);
 745
 746         val = pll_readl_misc(pll);
 747         if (!(val & PLLE_MISC_READY)) {
 748                 err = clk_plle_training(pll);
 749                 if (err)
 750                         return err;
 751         }
 752
 753         if (pll->params->flags & TEGRA_PLLE_CONFIGURE) {
 754                 /* configure dividers */
 755                 val = pll_readl_base(pll);
 756                 val &= ~(divp_mask_shifted(pll) | divn_mask_shifted(pll) |
 757                          divm_mask_shifted(pll));
 758                 val &= ~(PLLE_BASE_DIVCML_MASK << PLLE_BASE_DIVCML_SHIFT);
 759                 val |= sel.m << divm_shift(pll);
 760                 val |= sel.n << divn_shift(pll);
 761                 val |= sel.p << divp_shift(pll);
 762                 val |= sel.cpcon << PLLE_BASE_DIVCML_SHIFT;
 763                 pll_writel_base(val, pll);
 764         }
 765
 766         val = pll_readl_misc(pll);
 767         val |= PLLE_MISC_SETUP_VALUE;
 768         val |= PLLE_MISC_LOCK_ENABLE;
 769         pll_writel_misc(val, pll);
 770
 771         val = readl(pll->clk_base + PLLE_SS_CTRL);
 772         val &= ~PLLE_SS_COEFFICIENTS_MASK;
 773         val |= PLLE_SS_DISABLE;
 774         writel(val, pll->clk_base + PLLE_SS_CTRL);
 775
 776         val = pll_readl_base(pll);
 777         val |= (PLL_BASE_BYPASS | PLL_BASE_ENABLE);
 778         pll_writel_base(val, pll);
 779
 780         clk_pll_wait_for_lock(pll);
 781
 782         return 0;
 783 }
 784
 785 static unsigned long clk_plle_recalc_rate(struct clk_hw *hw,
 786                                          unsigned long parent_rate)
 787 {
 788         struct tegra_clk_pll *pll = to_clk_pll(hw);
 789         u32 val = pll_readl_base(pll);
 790         u32 divn = 0, divm = 0, divp = 0;
 791         u64 rate = parent_rate;
 792
 793         divp = (val >> pll->params->div_nmp->divp_shift) & (divp_mask(pll));
 794         divn = (val >> pll->params->div_nmp->divn_shift) & (divn_mask(pll));
 795         divm = (val >> pll->params->div_nmp->divm_shift) & (divm_mask(pll));
 796         divm *= divp;
 797
 798         rate *= divn;
 799         do_div(rate, divm);
 800         return rate;
 801 }
 802
 803 const struct clk_ops tegra_clk_pll_ops = {
 804         .is_enabled = clk_pll_is_enabled,
 805         .enable = clk_pll_enable,
 806         .disable = clk_pll_disable,
 807         .recalc_rate = clk_pll_recalc_rate,
 808         .round_rate = clk_pll_round_rate,
 809         .set_rate = clk_pll_set_rate,
 810 };
 811
 812 const struct clk_ops tegra_clk_plle_ops = {
 813         .recalc_rate = clk_plle_recalc_rate,
 814         .is_enabled = clk_pll_is_enabled,
 815         .disable = clk_pll_disable,
 816         .enable = clk_plle_enable,
 817 };
 818
 819 #if defined(CONFIG_ARCH_TEGRA_114_SOC) || defined(CONFIG_ARCH_TEGRA_124_SOC)
 820
 821 static int _pll_fixed_mdiv(struct tegra_clk_pll_params *pll_params,
 822                            unsigned long parent_rate)
 823 {
 824         if (parent_rate > pll_params->cf_max)
 825                 return 2;
 826         else
 827                 return 1;
 828 }
 829
 830 static unsigned long _clip_vco_min(unsigned long vco_min,
 831                                    unsigned long parent_rate)
 832 {
 833         return DIV_ROUND_UP(vco_min, parent_rate) * parent_rate;
 834 }
 835
 836 static int _setup_dynamic_ramp(struct tegra_clk_pll_params *pll_params,
 837                                void __iomem *clk_base,
 838                                unsigned long parent_rate)
 839 {
 840         u32 val;
 841         u32 step_a, step_b;
 842
 843         switch (parent_rate) {
 844         case 12000000:
 845         case 13000000:
 846         case 26000000:
 847                 step_a = 0x2B;
 848                 step_b = 0x0B;
 849                 break;
 850         case 16800000:
 851                 step_a = 0x1A;
 852                 step_b = 0x09;
 853                 break;
 854         case 19200000:
 855                 step_a = 0x12;
 856                 step_b = 0x08;
 857                 break;
 858         default:
 859                 pr_err("%s: Unexpected reference rate %lu\n",
 860                         __func__, parent_rate);
 861                 WARN_ON(1);
 862                 return -EINVAL;
 863         }
 864
 865         val = step_a << pll_params->stepa_shift;
 866         val |= step_b << pll_params->stepb_shift;
 867         writel_relaxed(val, clk_base + pll_params->dyn_ramp_reg);
 868
 869         return 0;
 870 }
 871
 872 static int clk_pll_iddq_enable(struct clk_hw *hw)
 873 {
 874         struct tegra_clk_pll *pll = to_clk_pll(hw);
 875         unsigned long flags = 0;
 876
 877         u32 val;
 878         int ret;
 879
 880         if (pll->lock)
 881                 spin_lock_irqsave(pll->lock, flags);
 882
 883         val = pll_readl(pll->params->iddq_reg, pll);
 884         val &= ~BIT(pll->params->iddq_bit_idx);
 885         pll_writel(val, pll->params->iddq_reg, pll);
 886         udelay(2);
 887
 888         _clk_pll_enable(hw);
 889
 890         ret = clk_pll_wait_for_lock(pll);
 891
 892         if (pll->lock)
 893                 spin_unlock_irqrestore(pll->lock, flags);
 894
 895         return 0;
 896 }
 897
 898 static void clk_pll_iddq_disable(struct clk_hw *hw)
 899 {
 900         struct tegra_clk_pll *pll = to_clk_pll(hw);
 901         unsigned long flags = 0;
 902         u32 val;
 903
 904         if (pll->lock)
 905                 spin_lock_irqsave(pll->lock, flags);
 906
 907         _clk_pll_disable(hw);
 908
 909         val = pll_readl(pll->params->iddq_reg, pll);
 910         val |= BIT(pll->params->iddq_bit_idx);
 911         pll_writel(val, pll->params->iddq_reg, pll);
 912         udelay(2);
 913
 914         if (pll->lock)
 915                 spin_unlock_irqrestore(pll->lock, flags);
 916 }
 917
 918 static int _calc_dynamic_ramp_rate(struct clk_hw *hw,
 919                                 struct tegra_clk_pll_freq_table *cfg,
 920                                 unsigned long rate, unsigned long parent_rate)
 921 {
 922         struct tegra_clk_pll *pll = to_clk_pll(hw);
 923         unsigned int p;
 924         int p_div;
 925
 926         if (!rate)
 927                 return -EINVAL;
 928
 929         p = DIV_ROUND_UP(pll->params->vco_min, rate);
 930         cfg->m = _pll_fixed_mdiv(pll->params, parent_rate);
 931         cfg->output_rate = rate * p;
 932         cfg->n = cfg->output_rate * cfg->m / parent_rate;
 933
 934         p_div = _p_div_to_hw(hw, p);
 935         if (p_div < 0)
 936                 return p_div;
 937         else
 938                 cfg->p = p_div;
 939
 940         if (cfg->n > divn_max(pll) || cfg->output_rate > pll->params->vco_max)
 941                 return -EINVAL;
 942
 943         return 0;
 944 }
 945
 946 static int _pll_ramp_calc_pll(struct clk_hw *hw,
 947                               struct tegra_clk_pll_freq_table *cfg,
 948                               unsigned long rate, unsigned long parent_rate)
 949 {
 950         struct tegra_clk_pll *pll = to_clk_pll(hw);
 951         int err = 0, p_div;
 952
 953         err = _get_table_rate(hw, cfg, rate, parent_rate);
 954         if (err < 0)
 955                 err = _calc_dynamic_ramp_rate(hw, cfg, rate, parent_rate);
 956         else {
 957                 if (cfg->m != _pll_fixed_mdiv(pll->params, parent_rate)) {
 958                         WARN_ON(1);
 959                         err = -EINVAL;
 960                         goto out;
 961                 }
 962                 p_div = _p_div_to_hw(hw, cfg->p);
 963                 if (p_div < 0)
 964                         return p_div;
 965                 else
 966                         cfg->p = p_div;
 967         }
 968
 969         if (cfg->p >  pll->params->max_p)
 970                 err = -EINVAL;
 971
 972 out:
 973         return err;
 974 }
 975
 976 static int clk_pllxc_set_rate(struct clk_hw *hw, unsigned long rate,
 977                                 unsigned long parent_rate)
 978 {
 979         struct tegra_clk_pll *pll = to_clk_pll(hw);
 980         struct tegra_clk_pll_freq_table cfg, old_cfg;
 981         unsigned long flags = 0;
 982         int ret = 0;
 983
 984         ret = _pll_ramp_calc_pll(hw, &cfg, rate, parent_rate);
 985         if (ret < 0)
 986                 return ret;
 987
 988         if (pll->lock)
 989                 spin_lock_irqsave(pll->lock, flags);
 990
 991         _get_pll_mnp(pll, &old_cfg);
 992
 993         if (old_cfg.m != cfg.m || old_cfg.n != cfg.n || old_cfg.p != cfg.p)
 994                 ret = _program_pll(hw, &cfg, rate);
 995
 996         if (pll->lock)
 997                 spin_unlock_irqrestore(pll->lock, flags);
 998
 999         return ret;
1000 }
1001
1002 static long clk_pll_ramp_round_rate(struct clk_hw *hw, unsigned long rate,
1003                                 unsigned long *prate)
1004 {
1005         struct tegra_clk_pll_freq_table cfg;
1006         int ret = 0, p_div;
1007         u64 output_rate = *prate;
1008
1009         ret = _pll_ramp_calc_pll(hw, &cfg, rate, *prate);
1010         if (ret < 0)
1011                 return ret;
1012
1013         p_div = _hw_to_p_div(hw, cfg.p);
1014         if (p_div < 0)
1015                 return p_div;
1016
1017         output_rate *= cfg.n;
1018         do_div(output_rate, cfg.m * p_div);
1019
1020         return output_rate;
1021 }
1022
1023 static int clk_pllm_set_rate(struct clk_hw *hw, unsigned long rate,
1024                                 unsigned long parent_rate)
1025 {
1026         struct tegra_clk_pll_freq_table cfg;
1027         struct tegra_clk_pll *pll = to_clk_pll(hw);
1028         unsigned long flags = 0;
1029         int state, ret = 0;
1030
1031         if (pll->lock)
1032                 spin_lock_irqsave(pll->lock, flags);
1033
1034         state = clk_pll_is_enabled(hw);
1035         if (state) {
1036                 if (rate != clk_get_rate(hw->clk)) {
1037                         pr_err("%s: Cannot change active PLLM\n", __func__);
1038                         ret = -EINVAL;
1039                         goto out;
1040                 }
1041                 goto out;
1042         }
1043
1044         ret = _pll_ramp_calc_pll(hw, &cfg, rate, parent_rate);
1045         if (ret < 0)
1046                 goto out;
1047
1048         _update_pll_mnp(pll, &cfg);
1049
1050 out:
1051         if (pll->lock)
1052                 spin_unlock_irqrestore(pll->lock, flags);
1053
1054         return ret;
1055 }
1056
1057 static void _pllcx_strobe(struct tegra_clk_pll *pll)
1058 {
1059         u32 val;
1060
1061         val = pll_readl_misc(pll);
1062         val |= PLLCX_MISC_STROBE;
1063         pll_writel_misc(val, pll);
1064         udelay(2);
1065
1066         val &= ~PLLCX_MISC_STROBE;
1067         pll_writel_misc(val, pll);
1068 }
1069
1070 static int clk_pllc_enable(struct clk_hw *hw)
1071 {
1072         struct tegra_clk_pll *pll = to_clk_pll(hw);
1073         u32 val;
1074         int ret = 0;
1075         unsigned long flags = 0;
1076
1077         if (pll->lock)
1078                 spin_lock_irqsave(pll->lock, flags);
1079
1080         _clk_pll_enable(hw);
1081         udelay(2);
1082
1083         val = pll_readl_misc(pll);
1084         val &= ~PLLCX_MISC_RESET;
1085         pll_writel_misc(val, pll);
1086         udelay(2);
1087
1088         _pllcx_strobe(pll);
1089
1090         ret = clk_pll_wait_for_lock(pll);
1091
1092         if (pll->lock)
1093                 spin_unlock_irqrestore(pll->lock, flags);
1094
1095         return ret;
1096 }
1097
1098 static void _clk_pllc_disable(struct clk_hw *hw)
1099 {
1100         struct tegra_clk_pll *pll = to_clk_pll(hw);
1101         u32 val;
1102
1103         _clk_pll_disable(hw);
1104
1105         val = pll_readl_misc(pll);
1106         val |= PLLCX_MISC_RESET;
1107         pll_writel_misc(val, pll);
1108         udelay(2);
1109 }
1110
1111 static void clk_pllc_disable(struct clk_hw *hw)
1112 {
1113         struct tegra_clk_pll *pll = to_clk_pll(hw);
1114         unsigned long flags = 0;
1115
1116         if (pll->lock)
1117                 spin_lock_irqsave(pll->lock, flags);
1118
1119         _clk_pllc_disable(hw);
1120
1121         if (pll->lock)
1122                 spin_unlock_irqrestore(pll->lock, flags);
1123 }
1124
1125 static int _pllcx_update_dynamic_coef(struct tegra_clk_pll *pll,
1126                                         unsigned long input_rate, u32 n)
1127 {
1128         u32 val, n_threshold;
1129
1130         switch (input_rate) {
1131         case 12000000:
1132                 n_threshold = 70;
1133                 break;
1134         case 13000000:
1135         case 26000000:
1136                 n_threshold = 71;
1137                 break;
1138         case 16800000:
1139                 n_threshold = 55;
1140                 break;
1141         case 19200000:
1142                 n_threshold = 48;
1143                 break;
1144         default:
1145                 pr_err("%s: Unexpected reference rate %lu\n",
1146                         __func__, input_rate);
1147                 return -EINVAL;
1148         }
1149
1150         val = pll_readl_misc(pll);
1151         val &= ~(PLLCX_MISC_SDM_DIV_MASK | PLLCX_MISC_FILT_DIV_MASK);
1152         val |= n <= n_threshold ?
1153                 PLLCX_MISC_DIV_LOW_RANGE : PLLCX_MISC_DIV_HIGH_RANGE;
1154         pll_writel_misc(val, pll);
1155
1156         return 0;
1157 }
1158
1159 static int clk_pllc_set_rate(struct clk_hw *hw, unsigned long rate,
1160                                 unsigned long parent_rate)
1161 {
1162         struct tegra_clk_pll_freq_table cfg, old_cfg;
1163         struct tegra_clk_pll *pll = to_clk_pll(hw);
1164         unsigned long flags = 0;
1165         int state, ret = 0;
1166
1167         if (pll->lock)
1168                 spin_lock_irqsave(pll->lock, flags);
1169
1170         ret = _pll_ramp_calc_pll(hw, &cfg, rate, parent_rate);
1171         if (ret < 0)
1172                 goto out;
1173
1174         _get_pll_mnp(pll, &old_cfg);
1175
1176         if (cfg.m != old_cfg.m) {
1177                 WARN_ON(1);
1178                 goto out;
1179         }
1180
1181         if (old_cfg.n == cfg.n && old_cfg.p == cfg.p)
1182                 goto out;
1183
1184         state = clk_pll_is_enabled(hw);
1185         if (state)
1186                 _clk_pllc_disable(hw);
1187
1188         ret = _pllcx_update_dynamic_coef(pll, parent_rate, cfg.n);
1189         if (ret < 0)
1190                 goto out;
1191
1192         _update_pll_mnp(pll, &cfg);
1193
1194         if (state)
1195                 ret = clk_pllc_enable(hw);
1196
1197 out:
1198         if (pll->lock)
1199                 spin_unlock_irqrestore(pll->lock, flags);
1200
1201         return ret;
1202 }
1203
1204 static long _pllre_calc_rate(struct tegra_clk_pll *pll,
1205                              struct tegra_clk_pll_freq_table *cfg,
1206                              unsigned long rate, unsigned long parent_rate)
1207 {
1208         u16 m, n;
1209         u64 output_rate = parent_rate;
1210
1211         m = _pll_fixed_mdiv(pll->params, parent_rate);
1212         n = rate * m / parent_rate;
1213
1214         output_rate *= n;
1215         do_div(output_rate, m);
1216
1217         if (cfg) {
1218                 cfg->m = m;
1219                 cfg->n = n;
1220         }
1221
1222         return output_rate;
1223 }
1224 static int clk_pllre_set_rate(struct clk_hw *hw, unsigned long rate,
1225                                 unsigned long parent_rate)
1226 {
1227         struct tegra_clk_pll_freq_table cfg, old_cfg;
1228         struct tegra_clk_pll *pll = to_clk_pll(hw);
1229         unsigned long flags = 0;
1230         int state, ret = 0;
1231
1232         if (pll->lock)
1233                 spin_lock_irqsave(pll->lock, flags);
1234
1235         _pllre_calc_rate(pll, &cfg, rate, parent_rate);
1236         _get_pll_mnp(pll, &old_cfg);
1237         cfg.p = old_cfg.p;
1238
1239         if (cfg.m != old_cfg.m || cfg.n != old_cfg.n) {
1240                 state = clk_pll_is_enabled(hw);
1241                 if (state)
1242                         _clk_pll_disable(hw);
1243
1244                 _update_pll_mnp(pll, &cfg);
1245
1246                 if (state) {
1247                         _clk_pll_enable(hw);
1248                         ret = clk_pll_wait_for_lock(pll);
1249                 }
1250         }
1251
1252         if (pll->lock)
1253                 spin_unlock_irqrestore(pll->lock, flags);
1254
1255         return ret;
1256 }
1257
1258 static unsigned long clk_pllre_recalc_rate(struct clk_hw *hw,
1259                                          unsigned long parent_rate)
1260 {
1261         struct tegra_clk_pll_freq_table cfg;
1262         struct tegra_clk_pll *pll = to_clk_pll(hw);
1263         u64 rate = parent_rate;
1264
1265         _get_pll_mnp(pll, &cfg);
1266
1267         rate *= cfg.n;
1268         do_div(rate, cfg.m);
1269
1270         return rate;
1271 }
1272
1273 static long clk_pllre_round_rate(struct clk_hw *hw, unsigned long rate,
1274                                  unsigned long *prate)
1275 {
1276         struct tegra_clk_pll *pll = to_clk_pll(hw);
1277
1278         return _pllre_calc_rate(pll, NULL, rate, *prate);
1279 }
1280
1281 static int clk_plle_tegra114_enable(struct clk_hw *hw)
1282 {
1283         struct tegra_clk_pll *pll = to_clk_pll(hw);
1284         struct tegra_clk_pll_freq_table sel;
1285         u32 val;
1286         int ret;
1287         unsigned long flags = 0;
1288         unsigned long input_rate = clk_get_rate(clk_get_parent(hw->clk));
1289
1290         if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate))
1291                 return -EINVAL;
1292
1293         if (pll->lock)
1294                 spin_lock_irqsave(pll->lock, flags);
1295
1296         val = pll_readl_base(pll);
1297         val &= ~BIT(29); /* Disable lock override */
1298         pll_writel_base(val, pll);
1299
1300         val = pll_readl(pll->params->aux_reg, pll);
1301         val |= PLLE_AUX_ENABLE_SWCTL;
1302         val &= ~PLLE_AUX_SEQ_ENABLE;
1303         pll_writel(val, pll->params->aux_reg, pll);
1304         udelay(1);
1305
1306         val = pll_readl_misc(pll);
1307         val |= PLLE_MISC_LOCK_ENABLE;
1308         val |= PLLE_MISC_IDDQ_SW_CTRL;
1309         val &= ~PLLE_MISC_IDDQ_SW_VALUE;
1310         val |= PLLE_MISC_PLLE_PTS;
1311         val |= PLLE_MISC_VREG_BG_CTRL_MASK | PLLE_MISC_VREG_CTRL_MASK;
1312         pll_writel_misc(val, pll);
1313         udelay(5);
1314
1315         val = pll_readl(PLLE_SS_CTRL, pll);
1316         val |= PLLE_SS_DISABLE;
1317         pll_writel(val, PLLE_SS_CTRL, pll);
1318
1319         val = pll_readl_base(pll);
1320         val &= ~(divp_mask_shifted(pll) | divn_mask_shifted(pll) |
1321                  divm_mask_shifted(pll));
1322         val &= ~(PLLE_BASE_DIVCML_MASK << PLLE_BASE_DIVCML_SHIFT);
1323         val |= sel.m << divm_shift(pll);
1324         val |= sel.n << divn_shift(pll);
1325         val |= sel.cpcon << PLLE_BASE_DIVCML_SHIFT;
1326         pll_writel_base(val, pll);
1327         udelay(1);
1328
1329         _clk_pll_enable(hw);
1330         ret = clk_pll_wait_for_lock(pll);
1331
1332         if (ret < 0)
1333                 goto out;
1334
1335         val = pll_readl(PLLE_SS_CTRL, pll);
1336         val &= ~(PLLE_SS_CNTL_CENTER | PLLE_SS_CNTL_INVERT);
1337         val &= ~PLLE_SS_COEFFICIENTS_MASK;
1338         val |= PLLE_SS_COEFFICIENTS_VAL;
1339         pll_writel(val, PLLE_SS_CTRL, pll);
1340         val &= ~(PLLE_SS_CNTL_SSC_BYP | PLLE_SS_CNTL_BYPASS_SS);
1341         pll_writel(val, PLLE_SS_CTRL, pll);
1342         udelay(1);
1343         val &= ~PLLE_SS_CNTL_INTERP_RESET;
1344         pll_writel(val, PLLE_SS_CTRL, pll);
1345         udelay(1);
1346
1347         /* Enable hw control of xusb brick pll */
1348         val = pll_readl_misc(pll);
1349         val &= ~PLLE_MISC_IDDQ_SW_CTRL;
1350         pll_writel_misc(val, pll);
1351
1352         val = pll_readl(pll->params->aux_reg, pll);
1353         val |= (PLLE_AUX_USE_LOCKDET | PLLE_AUX_SEQ_START_STATE);
1354         val &= ~(PLLE_AUX_ENABLE_SWCTL | PLLE_AUX_SS_SWCTL);
1355         pll_writel(val, pll->params->aux_reg, pll);
1356         udelay(1);
1357         val |= PLLE_AUX_SEQ_ENABLE;
1358         pll_writel(val, pll->params->aux_reg, pll);
1359
1360         val = pll_readl(XUSBIO_PLL_CFG0, pll);
1361         val |= (XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET |
1362                 XUSBIO_PLL_CFG0_SEQ_START_STATE);
1363         val &= ~(XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL |
1364                  XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL);
1365         pll_writel(val, XUSBIO_PLL_CFG0, pll);
1366         udelay(1);
1367         val |= XUSBIO_PLL_CFG0_SEQ_ENABLE;
1368         pll_writel(val, XUSBIO_PLL_CFG0, pll);
1369
1370         /* Enable hw control of SATA pll */
1371         val = pll_readl(SATA_PLL_CFG0, pll);
1372         val &= ~SATA_PLL_CFG0_PADPLL_RESET_SWCTL;
1373         val |= SATA_PLL_CFG0_PADPLL_USE_LOCKDET;
1374         val |= SATA_PLL_CFG0_SEQ_START_STATE;
1375         pll_writel(val, SATA_PLL_CFG0, pll);
1376
1377         udelay(1);
1378
1379         val = pll_readl(SATA_PLL_CFG0, pll);
1380         val |= SATA_PLL_CFG0_SEQ_ENABLE;
1381         pll_writel(val, SATA_PLL_CFG0, pll);
1382
1383 out:
1384         if (pll->lock)
1385                 spin_unlock_irqrestore(pll->lock, flags);
1386
1387         return ret;
1388 }
1389
1390 static void clk_plle_tegra114_disable(struct clk_hw *hw)
1391 {
1392         struct tegra_clk_pll *pll = to_clk_pll(hw);
1393         unsigned long flags = 0;
1394         u32 val;
1395
1396         if (pll->lock)
1397                 spin_lock_irqsave(pll->lock, flags);
1398
1399         _clk_pll_disable(hw);
1400
1401         val = pll_readl_misc(pll);
1402         val |= PLLE_MISC_IDDQ_SW_CTRL | PLLE_MISC_IDDQ_SW_VALUE;
1403         pll_writel_misc(val, pll);
1404         udelay(1);
1405
1406         if (pll->lock)
1407                 spin_unlock_irqrestore(pll->lock, flags);
1408 }
1409 #endif
1410
1411 static struct tegra_clk_pll *_tegra_init_pll(void __iomem *clk_base,
1412                 void __iomem *pmc, struct tegra_clk_pll_params *pll_params,
1413                 spinlock_t *lock)
1414 {
1415         struct tegra_clk_pll *pll;
1416
1417         pll = kzalloc(sizeof(*pll), GFP_KERNEL);
1418         if (!pll)
1419                 return ERR_PTR(-ENOMEM);
1420
1421         pll->clk_base = clk_base;
1422         pll->pmc = pmc;
1423
1424         pll->params = pll_params;
1425         pll->lock = lock;
1426
1427         if (!pll_params->div_nmp)
1428                 pll_params->div_nmp = &default_nmp;
1429
1430         return pll;
1431 }
1432
1433 static struct clk *_tegra_clk_register_pll(struct tegra_clk_pll *pll,
1434                 const char *name, const char *parent_name, unsigned long flags,
1435                 const struct clk_ops *ops)
1436 {
1437         struct clk_init_data init;
1438
1439         init.name = name;
1440         init.ops = ops;
1441         init.flags = flags;
1442         init.parent_names = (parent_name ? &parent_name : NULL);
1443         init.num_parents = (parent_name ? 1 : 0);
1444
1445         /* Data in .init is copied by clk_register(), so stack variable OK */
1446         pll->hw.init = &init;
1447
1448         return clk_register(NULL, &pll->hw);
1449 }
1450
1451 struct clk *tegra_clk_register_pll(const char *name, const char *parent_name,
1452                 void __iomem *clk_base, void __iomem *pmc,
1453                 unsigned long flags, struct tegra_clk_pll_params *pll_params,
1454                 spinlock_t *lock)
1455 {
1456         struct tegra_clk_pll *pll;
1457         struct clk *clk;
1458
1459         pll_params->flags |= TEGRA_PLL_BYPASS;
1460         pll_params->flags |= TEGRA_PLL_HAS_LOCK_ENABLE;
1461         pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
1462         if (IS_ERR(pll))
1463                 return ERR_CAST(pll);
1464
1465         clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1466                                       &tegra_clk_pll_ops);
1467         if (IS_ERR(clk))
1468                 kfree(pll);
1469
1470         return clk;
1471 }
1472
1473 static struct div_nmp pll_e_nmp = {
1474         .divn_shift = PLLE_BASE_DIVN_SHIFT,
1475         .divn_width = PLLE_BASE_DIVN_WIDTH,
1476         .divm_shift = PLLE_BASE_DIVM_SHIFT,
1477         .divm_width = PLLE_BASE_DIVM_WIDTH,
1478         .divp_shift = PLLE_BASE_DIVP_SHIFT,
1479         .divp_width = PLLE_BASE_DIVP_WIDTH,
1480 };
1481
1482 struct clk *tegra_clk_register_plle(const char *name, const char *parent_name,
1483                 void __iomem *clk_base, void __iomem *pmc,
1484                 unsigned long flags, struct tegra_clk_pll_params *pll_params,
1485                 spinlock_t *lock)
1486 {
1487         struct tegra_clk_pll *pll;
1488         struct clk *clk;
1489
1490         pll_params->flags |= TEGRA_PLL_LOCK_MISC | TEGRA_PLL_BYPASS;
1491         pll_params->flags |= TEGRA_PLL_HAS_LOCK_ENABLE;
1492
1493         if (!pll_params->div_nmp)
1494                 pll_params->div_nmp = &pll_e_nmp;
1495
1496         pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
1497         if (IS_ERR(pll))
1498                 return ERR_CAST(pll);
1499
1500         clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1501                                       &tegra_clk_plle_ops);
1502         if (IS_ERR(clk))
1503                 kfree(pll);
1504
1505         return clk;
1506 }
1507
1508 #if defined(CONFIG_ARCH_TEGRA_114_SOC) || defined(CONFIG_ARCH_TEGRA_124_SOC)
1509 static const struct clk_ops tegra_clk_pllxc_ops = {
1510         .is_enabled = clk_pll_is_enabled,
1511         .enable = clk_pll_iddq_enable,
1512         .disable = clk_pll_iddq_disable,
1513         .recalc_rate = clk_pll_recalc_rate,
1514         .round_rate = clk_pll_ramp_round_rate,
1515         .set_rate = clk_pllxc_set_rate,
1516 };
1517
1518 static const struct clk_ops tegra_clk_pllm_ops = {
1519         .is_enabled = clk_pll_is_enabled,
1520         .enable = clk_pll_iddq_enable,
1521         .disable = clk_pll_iddq_disable,
1522         .recalc_rate = clk_pll_recalc_rate,
1523         .round_rate = clk_pll_ramp_round_rate,
1524         .set_rate = clk_pllm_set_rate,
1525 };
1526
1527 static const struct clk_ops tegra_clk_pllc_ops = {
1528         .is_enabled = clk_pll_is_enabled,
1529         .enable = clk_pllc_enable,
1530         .disable = clk_pllc_disable,
1531         .recalc_rate = clk_pll_recalc_rate,
1532         .round_rate = clk_pll_ramp_round_rate,
1533         .set_rate = clk_pllc_set_rate,
1534 };
1535
1536 static const struct clk_ops tegra_clk_pllre_ops = {
1537         .is_enabled = clk_pll_is_enabled,
1538         .enable = clk_pll_iddq_enable,
1539         .disable = clk_pll_iddq_disable,
1540         .recalc_rate = clk_pllre_recalc_rate,
1541         .round_rate = clk_pllre_round_rate,
1542         .set_rate = clk_pllre_set_rate,
1543 };
1544
1545 static const struct clk_ops tegra_clk_plle_tegra114_ops = {
1546         .is_enabled =  clk_pll_is_enabled,
1547         .enable = clk_plle_tegra114_enable,
1548         .disable = clk_plle_tegra114_disable,
1549         .recalc_rate = clk_pll_recalc_rate,
1550 };
1551
1552
1553 struct clk *tegra_clk_register_pllxc(const char *name, const char *parent_name,
1554                           void __iomem *clk_base, void __iomem *pmc,
1555                           unsigned long flags,
1556                           struct tegra_clk_pll_params *pll_params,
1557                           spinlock_t *lock)
1558 {
1559         struct tegra_clk_pll *pll;
1560         struct clk *clk, *parent;
1561         unsigned long parent_rate;
1562         int err;
1563         u32 val, val_iddq;
1564
1565         parent = __clk_lookup(parent_name);
1566         if (!parent) {
1567                 WARN(1, "parent clk %s of %s must be registered first\n",
1568                         name, parent_name);
1569                 return ERR_PTR(-EINVAL);
1570         }
1571
1572         if (!pll_params->pdiv_tohw)
1573                 return ERR_PTR(-EINVAL);
1574
1575         parent_rate = __clk_get_rate(parent);
1576
1577         pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
1578
1579         err = _setup_dynamic_ramp(pll_params, clk_base, parent_rate);
1580         if (err)
1581                 return ERR_PTR(err);
1582
1583         val = readl_relaxed(clk_base + pll_params->base_reg);
1584         val_iddq = readl_relaxed(clk_base + pll_params->iddq_reg);
1585
1586         if (val & PLL_BASE_ENABLE)
1587                 WARN_ON(val_iddq & BIT(pll_params->iddq_bit_idx));
1588         else {
1589                 val_iddq |= BIT(pll_params->iddq_bit_idx);
1590                 writel_relaxed(val_iddq, clk_base + pll_params->iddq_reg);
1591         }
1592
1593         pll_params->flags |= TEGRA_PLL_HAS_LOCK_ENABLE;
1594         pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
1595         if (IS_ERR(pll))
1596                 return ERR_CAST(pll);
1597
1598         clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1599                                       &tegra_clk_pllxc_ops);
1600         if (IS_ERR(clk))
1601                 kfree(pll);
1602
1603         return clk;
1604 }
1605
1606 struct clk *tegra_clk_register_pllre(const char *name, const char *parent_name,
1607                           void __iomem *clk_base, void __iomem *pmc,
1608                           unsigned long flags,
1609                           struct tegra_clk_pll_params *pll_params,
1610                           spinlock_t *lock, unsigned long parent_rate)
1611 {
1612         u32 val;
1613         struct tegra_clk_pll *pll;
1614         struct clk *clk;
1615
1616         pll_params->flags |= TEGRA_PLL_HAS_LOCK_ENABLE | TEGRA_PLL_LOCK_MISC;
1617
1618         pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
1619
1620         pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
1621         if (IS_ERR(pll))
1622                 return ERR_CAST(pll);
1623
1624         /* program minimum rate by default */
1625
1626         val = pll_readl_base(pll);
1627         if (val & PLL_BASE_ENABLE)
1628                 WARN_ON(val & pll_params->iddq_bit_idx);
1629         else {
1630                 int m;
1631
1632                 m = _pll_fixed_mdiv(pll_params, parent_rate);
1633                 val = m << divm_shift(pll);
1634                 val |= (pll_params->vco_min / parent_rate) << divn_shift(pll);
1635                 pll_writel_base(val, pll);
1636         }
1637
1638         /* disable lock override */
1639
1640         val = pll_readl_misc(pll);
1641         val &= ~BIT(29);
1642         pll_writel_misc(val, pll);
1643
1644         clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1645                                       &tegra_clk_pllre_ops);
1646         if (IS_ERR(clk))
1647                 kfree(pll);
1648
1649         return clk;
1650 }
1651
1652 struct clk *tegra_clk_register_pllm(const char *name, const char *parent_name,
1653                           void __iomem *clk_base, void __iomem *pmc,
1654                           unsigned long flags,
1655                           struct tegra_clk_pll_params *pll_params,
1656                           spinlock_t *lock)
1657 {
1658         struct tegra_clk_pll *pll;
1659         struct clk *clk, *parent;
1660         unsigned long parent_rate;
1661
1662         if (!pll_params->pdiv_tohw)
1663                 return ERR_PTR(-EINVAL);
1664
1665         parent = __clk_lookup(parent_name);
1666         if (!parent) {
1667                 WARN(1, "parent clk %s of %s must be registered first\n",
1668                         name, parent_name);
1669                 return ERR_PTR(-EINVAL);
1670         }
1671
1672         parent_rate = __clk_get_rate(parent);
1673
1674         pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
1675
1676         pll_params->flags |= TEGRA_PLL_BYPASS;
1677         pll_params->flags |= TEGRA_PLL_HAS_LOCK_ENABLE;
1678         pll_params->flags |= TEGRA_PLLM;
1679         pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
1680         if (IS_ERR(pll))
1681                 return ERR_CAST(pll);
1682
1683         clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1684                                       &tegra_clk_pllm_ops);
1685         if (IS_ERR(clk))
1686                 kfree(pll);
1687
1688         return clk;
1689 }
1690
1691 struct clk *tegra_clk_register_pllc(const char *name, const char *parent_name,
1692                           void __iomem *clk_base, void __iomem *pmc,
1693                           unsigned long flags,
1694                           struct tegra_clk_pll_params *pll_params,
1695                           spinlock_t *lock)
1696 {
1697         struct clk *parent, *clk;
1698         struct pdiv_map *p_tohw = pll_params->pdiv_tohw;
1699         struct tegra_clk_pll *pll;
1700         struct tegra_clk_pll_freq_table cfg;
1701         unsigned long parent_rate;
1702
1703         if (!p_tohw)
1704                 return ERR_PTR(-EINVAL);
1705
1706         parent = __clk_lookup(parent_name);
1707         if (!parent) {
1708                 WARN(1, "parent clk %s of %s must be registered first\n",
1709                         name, parent_name);
1710                 return ERR_PTR(-EINVAL);
1711         }
1712
1713         parent_rate = __clk_get_rate(parent);
1714
1715         pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
1716
1717         pll_params->flags |= TEGRA_PLL_BYPASS;
1718         pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
1719         if (IS_ERR(pll))
1720                 return ERR_CAST(pll);
1721
1722         /*
1723          * Most of PLLC register fields are shadowed, and can not be read
1724          * directly from PLL h/w. Hence, actual PLLC boot state is unknown.
1725          * Initialize PLL to default state: disabled, reset; shadow registers
1726          * loaded with default parameters; dividers are preset for half of
1727          * minimum VCO rate (the latter assured that shadowed divider settings
1728          * are within supported range).
1729          */
1730
1731         cfg.m = _pll_fixed_mdiv(pll_params, parent_rate);
1732         cfg.n = cfg.m * pll_params->vco_min / parent_rate;
1733
1734         while (p_tohw->pdiv) {
1735                 if (p_tohw->pdiv == 2) {
1736                         cfg.p = p_tohw->hw_val;
1737                         break;
1738                 }
1739                 p_tohw++;
1740         }
1741
1742         if (!p_tohw->pdiv) {
1743                 WARN_ON(1);
1744                 return ERR_PTR(-EINVAL);
1745         }
1746
1747         pll_writel_base(0, pll);
1748         _update_pll_mnp(pll, &cfg);
1749
1750         pll_writel_misc(PLLCX_MISC_DEFAULT, pll);
1751         pll_writel(PLLCX_MISC1_DEFAULT, pll_params->ext_misc_reg[0], pll);
1752         pll_writel(PLLCX_MISC2_DEFAULT, pll_params->ext_misc_reg[1], pll);
1753         pll_writel(PLLCX_MISC3_DEFAULT, pll_params->ext_misc_reg[2], pll);
1754
1755         _pllcx_update_dynamic_coef(pll, parent_rate, cfg.n);
1756
1757         clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1758                                       &tegra_clk_pllc_ops);
1759         if (IS_ERR(clk))
1760                 kfree(pll);
1761
1762         return clk;
1763 }
1764
1765 struct clk *tegra_clk_register_plle_tegra114(const char *name,
1766                                 const char *parent_name,
1767                                 void __iomem *clk_base, unsigned long flags,
1768                                 struct tegra_clk_pll_params *pll_params,
1769                                 spinlock_t *lock)
1770 {
1771         struct tegra_clk_pll *pll;
1772         struct clk *clk;
1773         u32 val, val_aux;
1774
1775         pll_params->flags |= TEGRA_PLL_HAS_LOCK_ENABLE;
1776         pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
1777         if (IS_ERR(pll))
1778                 return ERR_CAST(pll);
1779
1780         /* ensure parent is set to pll_re_vco */
1781
1782         val = pll_readl_base(pll);
1783         val_aux = pll_readl(pll_params->aux_reg, pll);
1784
1785         if (val & PLL_BASE_ENABLE) {
1786                 if ((val_aux & PLLE_AUX_PLLRE_SEL) ||
1787                         (val_aux & PLLE_AUX_PLLP_SEL))
1788                         WARN(1, "pll_e enabled with unsupported parent %s\n",
1789                           (val_aux & PLLE_AUX_PLLP_SEL) ? "pllp_out0" :
1790                                         "pll_re_vco");
1791         } else {
1792                 val_aux &= ~(PLLE_AUX_PLLRE_SEL | PLLE_AUX_PLLP_SEL);
1793                 pll_writel(val_aux, pll_params->aux_reg, pll);
1794         }
1795
1796         clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1797                                       &tegra_clk_plle_tegra114_ops);
1798         if (IS_ERR(clk))
1799                 kfree(pll);
1800
1801         return clk;
1802 }
1803 #endif
1804
1805 #ifdef CONFIG_ARCH_TEGRA_124_SOC
1806 static const struct clk_ops tegra_clk_pllss_ops = {
1807         .is_enabled = clk_pll_is_enabled,
1808         .enable = clk_pll_iddq_enable,
1809         .disable = clk_pll_iddq_disable,
1810         .recalc_rate = clk_pll_recalc_rate,
1811         .round_rate = clk_pll_ramp_round_rate,
1812         .set_rate = clk_pllxc_set_rate,
1813 };
1814
1815 struct clk *tegra_clk_register_pllss(const char *name, const char *parent_name,
1816                                 void __iomem *clk_base, unsigned long flags,
1817                                 struct tegra_clk_pll_params *pll_params,
1818                                 spinlock_t *lock)
1819 {
1820         struct tegra_clk_pll *pll;
1821         struct clk *clk, *parent;
1822         struct tegra_clk_pll_freq_table cfg;
1823         unsigned long parent_rate;
1824         u32 val;
1825         int i;
1826
1827         if (!pll_params->div_nmp)
1828                 return ERR_PTR(-EINVAL);
1829
1830         parent = __clk_lookup(parent_name);
1831         if (!parent) {
1832                 WARN(1, "parent clk %s of %s must be registered first\n",
1833                         name, parent_name);
1834                 return ERR_PTR(-EINVAL);
1835         }
1836
1837         pll_params->flags = TEGRA_PLL_HAS_LOCK_ENABLE | TEGRA_PLL_USE_LOCK;
1838         pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
1839         if (IS_ERR(pll))
1840                 return ERR_CAST(pll);
1841
1842         val = pll_readl_base(pll);
1843         val &= ~PLLSS_REF_SRC_SEL_MASK;
1844         pll_writel_base(val, pll);
1845
1846         parent_rate = __clk_get_rate(parent);
1847
1848         pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
1849
1850         /* initialize PLL to minimum rate */
1851
1852         cfg.m = _pll_fixed_mdiv(pll_params, parent_rate);
1853         cfg.n = cfg.m * pll_params->vco_min / parent_rate;
1854
1855         for (i = 0; pll_params->pdiv_tohw[i].pdiv; i++)
1856                 ;
1857         if (!i) {
1858                 kfree(pll);
1859                 return ERR_PTR(-EINVAL);
1860         }
1861
1862         cfg.p = pll_params->pdiv_tohw[i-1].hw_val;
1863
1864         _update_pll_mnp(pll, &cfg);
1865
1866         pll_writel_misc(PLLSS_MISC_DEFAULT, pll);
1867         pll_writel(PLLSS_CFG_DEFAULT, pll_params->ext_misc_reg[0], pll);
1868         pll_writel(PLLSS_CTRL1_DEFAULT, pll_params->ext_misc_reg[1], pll);
1869         pll_writel(PLLSS_CTRL1_DEFAULT, pll_params->ext_misc_reg[2], pll);
1870
1871         val = pll_readl_base(pll);
1872         if (val & PLL_BASE_ENABLE) {
1873                 if (val & BIT(pll_params->iddq_bit_idx)) {
1874                         WARN(1, "%s is on but IDDQ set\n", name);
1875                         kfree(pll);
1876                         return ERR_PTR(-EINVAL);
1877                 }
1878         } else
1879                 val |= BIT(pll_params->iddq_bit_idx);
1880
1881         val &= ~PLLSS_LOCK_OVERRIDE;
1882         pll_writel_base(val, pll);
1883
1884         clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1885                                         &tegra_clk_pllss_ops);
1886
1887         if (IS_ERR(clk))
1888                 kfree(pll);
1889
1890         return clk;
1891 }
1892 #endif