2 * Copyright (c) 2012, 2013, NVIDIA CORPORATION. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
17 #include <linux/slab.h>
19 #include <linux/delay.h>
20 #include <linux/err.h>
21 #include <linux/clk-provider.h>
22 #include <linux/clk.h>
26 #define PLL_BASE_BYPASS BIT(31)
27 #define PLL_BASE_ENABLE BIT(30)
28 #define PLL_BASE_REF_ENABLE BIT(29)
29 #define PLL_BASE_OVERRIDE BIT(28)
31 #define PLL_BASE_DIVP_SHIFT 20
32 #define PLL_BASE_DIVP_WIDTH 3
33 #define PLL_BASE_DIVN_SHIFT 8
34 #define PLL_BASE_DIVN_WIDTH 10
35 #define PLL_BASE_DIVM_SHIFT 0
36 #define PLL_BASE_DIVM_WIDTH 5
37 #define PLLU_POST_DIVP_MASK 0x1
39 #define PLL_MISC_DCCON_SHIFT 20
40 #define PLL_MISC_CPCON_SHIFT 8
41 #define PLL_MISC_CPCON_WIDTH 4
42 #define PLL_MISC_CPCON_MASK ((1 << PLL_MISC_CPCON_WIDTH) - 1)
43 #define PLL_MISC_LFCON_SHIFT 4
44 #define PLL_MISC_LFCON_WIDTH 4
45 #define PLL_MISC_LFCON_MASK ((1 << PLL_MISC_LFCON_WIDTH) - 1)
46 #define PLL_MISC_VCOCON_SHIFT 0
47 #define PLL_MISC_VCOCON_WIDTH 4
48 #define PLL_MISC_VCOCON_MASK ((1 << PLL_MISC_VCOCON_WIDTH) - 1)
50 #define OUT_OF_TABLE_CPCON 8
52 #define PMC_PLLP_WB0_OVERRIDE 0xf8
53 #define PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE BIT(12)
54 #define PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE BIT(11)
56 #define PLL_POST_LOCK_DELAY 50
58 #define PLLDU_LFCON_SET_DIVN 600
60 #define PLLE_BASE_DIVCML_SHIFT 24
61 #define PLLE_BASE_DIVCML_WIDTH 4
62 #define PLLE_BASE_DIVP_SHIFT 16
63 #define PLLE_BASE_DIVP_WIDTH 7
64 #define PLLE_BASE_DIVN_SHIFT 8
65 #define PLLE_BASE_DIVN_WIDTH 8
66 #define PLLE_BASE_DIVM_SHIFT 0
67 #define PLLE_BASE_DIVM_WIDTH 8
69 #define PLLE_MISC_SETUP_BASE_SHIFT 16
70 #define PLLE_MISC_SETUP_BASE_MASK (0xffff << PLLE_MISC_SETUP_BASE_SHIFT)
71 #define PLLE_MISC_LOCK_ENABLE BIT(9)
72 #define PLLE_MISC_READY BIT(15)
73 #define PLLE_MISC_SETUP_EX_SHIFT 2
74 #define PLLE_MISC_SETUP_EX_MASK (3 << PLLE_MISC_SETUP_EX_SHIFT)
75 #define PLLE_MISC_SETUP_MASK (PLLE_MISC_SETUP_BASE_MASK | \
76 PLLE_MISC_SETUP_EX_MASK)
77 #define PLLE_MISC_SETUP_VALUE (7 << PLLE_MISC_SETUP_BASE_SHIFT)
79 #define PLLE_SS_CTRL 0x68
80 #define PLLE_SS_DISABLE (7 << 10)
82 #define PLLE_AUX_PLLP_SEL BIT(2)
83 #define PLLE_AUX_ENABLE_SWCTL BIT(4)
84 #define PLLE_AUX_SEQ_ENABLE BIT(24)
85 #define PLLE_AUX_PLLRE_SEL BIT(28)
87 #define PLLE_MISC_PLLE_PTS BIT(8)
88 #define PLLE_MISC_IDDQ_SW_VALUE BIT(13)
89 #define PLLE_MISC_IDDQ_SW_CTRL BIT(14)
90 #define PLLE_MISC_VREG_BG_CTRL_SHIFT 4
91 #define PLLE_MISC_VREG_BG_CTRL_MASK (3 << PLLE_MISC_VREG_BG_CTRL_SHIFT)
92 #define PLLE_MISC_VREG_CTRL_SHIFT 2
93 #define PLLE_MISC_VREG_CTRL_MASK (2 << PLLE_MISC_VREG_CTRL_SHIFT)
95 #define PLLCX_MISC_STROBE BIT(31)
96 #define PLLCX_MISC_RESET BIT(30)
97 #define PLLCX_MISC_SDM_DIV_SHIFT 28
98 #define PLLCX_MISC_SDM_DIV_MASK (0x3 << PLLCX_MISC_SDM_DIV_SHIFT)
99 #define PLLCX_MISC_FILT_DIV_SHIFT 26
100 #define PLLCX_MISC_FILT_DIV_MASK (0x3 << PLLCX_MISC_FILT_DIV_SHIFT)
101 #define PLLCX_MISC_ALPHA_SHIFT 18
102 #define PLLCX_MISC_DIV_LOW_RANGE \
103 ((0x1 << PLLCX_MISC_SDM_DIV_SHIFT) | \
104 (0x1 << PLLCX_MISC_FILT_DIV_SHIFT))
105 #define PLLCX_MISC_DIV_HIGH_RANGE \
106 ((0x2 << PLLCX_MISC_SDM_DIV_SHIFT) | \
107 (0x2 << PLLCX_MISC_FILT_DIV_SHIFT))
108 #define PLLCX_MISC_COEF_LOW_RANGE \
109 ((0x14 << PLLCX_MISC_KA_SHIFT) | (0x38 << PLLCX_MISC_KB_SHIFT))
110 #define PLLCX_MISC_KA_SHIFT 2
111 #define PLLCX_MISC_KB_SHIFT 9
112 #define PLLCX_MISC_DEFAULT (PLLCX_MISC_COEF_LOW_RANGE | \
113 (0x19 << PLLCX_MISC_ALPHA_SHIFT) | \
114 PLLCX_MISC_DIV_LOW_RANGE | \
116 #define PLLCX_MISC1_DEFAULT 0x000d2308
117 #define PLLCX_MISC2_DEFAULT 0x30211200
118 #define PLLCX_MISC3_DEFAULT 0x200
120 #define PMC_PLLM_WB0_OVERRIDE 0x1dc
121 #define PMC_PLLM_WB0_OVERRIDE_2 0x2b0
122 #define PMC_PLLM_WB0_OVERRIDE_2_DIVP_MASK BIT(27)
124 #define PMC_SATA_PWRGT 0x1ac
125 #define PMC_SATA_PWRGT_PLLE_IDDQ_VALUE BIT(5)
126 #define PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL BIT(4)
128 #define pll_readl(offset, p) readl_relaxed(p->clk_base + offset)
129 #define pll_readl_base(p) pll_readl(p->params->base_reg, p)
130 #define pll_readl_misc(p) pll_readl(p->params->misc_reg, p)
132 #define pll_writel(val, offset, p) writel_relaxed(val, p->clk_base + offset)
133 #define pll_writel_base(val, p) pll_writel(val, p->params->base_reg, p)
134 #define pll_writel_misc(val, p) pll_writel(val, p->params->misc_reg, p)
136 #define mask(w) ((1 << (w)) - 1)
137 #define divm_mask(p) mask(p->divm_width)
138 #define divn_mask(p) mask(p->divn_width)
139 #define divp_mask(p) (p->flags & TEGRA_PLLU ? PLLU_POST_DIVP_MASK : \
142 #define divm_max(p) (divm_mask(p))
143 #define divn_max(p) (divn_mask(p))
144 #define divp_max(p) (1 << (divp_mask(p)))
147 #ifdef CONFIG_ARCH_TEGRA_114_SOC
148 /* PLLXC has 4-bit PDIV, but entry 15 is not allowed in h/w */
149 #define PLLXC_PDIV_MAX 14
151 /* non-monotonic mapping below is not a typo */
152 static u8 pllxc_p[PLLXC_PDIV_MAX + 1] = {
153 /* PDIV: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 */
154 /* p: */ 1, 2, 3, 4, 5, 6, 8, 10, 12, 16, 12, 16, 20, 24, 32
157 #define PLLCX_PDIV_MAX 7
158 static u8 pllcx_p[PLLCX_PDIV_MAX + 1] = {
159 /* PDIV: 0, 1, 2, 3, 4, 5, 6, 7 */
160 /* p: */ 1, 2, 3, 4, 6, 8, 12, 16
164 static void clk_pll_enable_lock(struct tegra_clk_pll *pll)
168 if (!(pll->flags & TEGRA_PLL_USE_LOCK))
171 if (!(pll->flags & TEGRA_PLL_HAS_LOCK_ENABLE))
174 val = pll_readl_misc(pll);
175 val |= BIT(pll->params->lock_enable_bit_idx);
176 pll_writel_misc(val, pll);
179 static int clk_pll_wait_for_lock(struct tegra_clk_pll *pll)
183 void __iomem *lock_addr;
185 if (!(pll->flags & TEGRA_PLL_USE_LOCK)) {
186 udelay(pll->params->lock_delay);
190 lock_addr = pll->clk_base;
191 if (pll->flags & TEGRA_PLL_LOCK_MISC)
192 lock_addr += pll->params->misc_reg;
194 lock_addr += pll->params->base_reg;
196 lock_mask = pll->params->lock_mask;
198 for (i = 0; i < pll->params->lock_delay; i++) {
199 val = readl_relaxed(lock_addr);
200 if ((val & lock_mask) == lock_mask) {
201 udelay(PLL_POST_LOCK_DELAY);
204 udelay(2); /* timeout = 2 * lock time */
207 pr_err("%s: Timed out waiting for pll %s lock\n", __func__,
208 __clk_get_name(pll->hw.clk));
213 static int clk_pll_is_enabled(struct clk_hw *hw)
215 struct tegra_clk_pll *pll = to_clk_pll(hw);
218 if (pll->flags & TEGRA_PLLM) {
219 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE);
220 if (val & PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE)
221 return val & PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE ? 1 : 0;
224 val = pll_readl_base(pll);
226 return val & PLL_BASE_ENABLE ? 1 : 0;
229 static void _clk_pll_enable(struct clk_hw *hw)
231 struct tegra_clk_pll *pll = to_clk_pll(hw);
234 clk_pll_enable_lock(pll);
236 val = pll_readl_base(pll);
237 if (pll->flags & TEGRA_PLL_BYPASS)
238 val &= ~PLL_BASE_BYPASS;
239 val |= PLL_BASE_ENABLE;
240 pll_writel_base(val, pll);
242 if (pll->flags & TEGRA_PLLM) {
243 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE);
244 val |= PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE;
245 writel_relaxed(val, pll->pmc + PMC_PLLP_WB0_OVERRIDE);
249 static void _clk_pll_disable(struct clk_hw *hw)
251 struct tegra_clk_pll *pll = to_clk_pll(hw);
254 val = pll_readl_base(pll);
255 if (pll->flags & TEGRA_PLL_BYPASS)
256 val &= ~PLL_BASE_BYPASS;
257 val &= ~PLL_BASE_ENABLE;
258 pll_writel_base(val, pll);
260 if (pll->flags & TEGRA_PLLM) {
261 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE);
262 val &= ~PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE;
263 writel_relaxed(val, pll->pmc + PMC_PLLP_WB0_OVERRIDE);
267 static int clk_pll_enable(struct clk_hw *hw)
269 struct tegra_clk_pll *pll = to_clk_pll(hw);
270 unsigned long flags = 0;
274 spin_lock_irqsave(pll->lock, flags);
278 ret = clk_pll_wait_for_lock(pll);
281 spin_unlock_irqrestore(pll->lock, flags);
286 static void clk_pll_disable(struct clk_hw *hw)
288 struct tegra_clk_pll *pll = to_clk_pll(hw);
289 unsigned long flags = 0;
292 spin_lock_irqsave(pll->lock, flags);
294 _clk_pll_disable(hw);
297 spin_unlock_irqrestore(pll->lock, flags);
300 static int _get_table_rate(struct clk_hw *hw,
301 struct tegra_clk_pll_freq_table *cfg,
302 unsigned long rate, unsigned long parent_rate)
304 struct tegra_clk_pll *pll = to_clk_pll(hw);
305 struct tegra_clk_pll_freq_table *sel;
307 for (sel = pll->freq_table; sel->input_rate != 0; sel++)
308 if (sel->input_rate == parent_rate &&
309 sel->output_rate == rate)
312 if (sel->input_rate == 0)
315 cfg->input_rate = sel->input_rate;
316 cfg->output_rate = sel->output_rate;
320 cfg->cpcon = sel->cpcon;
325 static int _calc_rate(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg,
326 unsigned long rate, unsigned long parent_rate)
328 struct tegra_clk_pll *pll = to_clk_pll(hw);
329 struct pdiv_map *p_tohw = pll->params->pdiv_tohw;
333 switch (parent_rate) {
336 cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2000000;
339 cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2600000;
343 cfreq = (rate <= 1200000 * 1000) ? 1200000 : 2400000;
348 * PLL_P_OUT1 rate is not listed in PLLA table
350 cfreq = parent_rate/(parent_rate/1000000);
353 pr_err("%s Unexpected reference rate %lu\n",
354 __func__, parent_rate);
358 /* Raise VCO to guarantee 0.5% accuracy */
359 for (cfg->output_rate = rate; cfg->output_rate < 200 * cfreq;
360 cfg->output_rate <<= 1)
363 cfg->m = parent_rate / cfreq;
364 cfg->n = cfg->output_rate / cfreq;
365 cfg->cpcon = OUT_OF_TABLE_CPCON;
367 if (cfg->m > divm_max(pll) || cfg->n > divn_max(pll) ||
368 (1 << p_div) > divp_max(pll)
369 || cfg->output_rate > pll->params->vco_max) {
370 pr_err("%s: Failed to set %s rate %lu\n",
371 __func__, __clk_get_name(hw->clk), rate);
377 while (p_tohw->pdiv) {
378 if (p_div <= p_tohw->pdiv) {
379 cfg->p = p_tohw->hw_val;
392 static void _update_pll_mnp(struct tegra_clk_pll *pll,
393 struct tegra_clk_pll_freq_table *cfg)
397 val = pll_readl_base(pll);
399 val &= ~((divm_mask(pll) << pll->divm_shift) |
400 (divn_mask(pll) << pll->divn_shift) |
401 (divp_mask(pll) << pll->divp_shift));
402 val |= ((cfg->m << pll->divm_shift) |
403 (cfg->n << pll->divn_shift) |
404 (cfg->p << pll->divp_shift));
406 pll_writel_base(val, pll);
409 static void _get_pll_mnp(struct tegra_clk_pll *pll,
410 struct tegra_clk_pll_freq_table *cfg)
414 val = pll_readl_base(pll);
416 cfg->m = (val >> pll->divm_shift) & (divm_mask(pll));
417 cfg->n = (val >> pll->divn_shift) & (divn_mask(pll));
418 cfg->p = (val >> pll->divp_shift) & (divp_mask(pll));
421 static void _update_pll_cpcon(struct tegra_clk_pll *pll,
422 struct tegra_clk_pll_freq_table *cfg,
427 val = pll_readl_misc(pll);
429 val &= ~(PLL_MISC_CPCON_MASK << PLL_MISC_CPCON_SHIFT);
430 val |= cfg->cpcon << PLL_MISC_CPCON_SHIFT;
432 if (pll->flags & TEGRA_PLL_SET_LFCON) {
433 val &= ~(PLL_MISC_LFCON_MASK << PLL_MISC_LFCON_SHIFT);
434 if (cfg->n >= PLLDU_LFCON_SET_DIVN)
435 val |= 1 << PLL_MISC_LFCON_SHIFT;
436 } else if (pll->flags & TEGRA_PLL_SET_DCCON) {
437 val &= ~(1 << PLL_MISC_DCCON_SHIFT);
438 if (rate >= (pll->params->vco_max >> 1))
439 val |= 1 << PLL_MISC_DCCON_SHIFT;
442 pll_writel_misc(val, pll);
445 static int _program_pll(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg,
448 struct tegra_clk_pll *pll = to_clk_pll(hw);
451 state = clk_pll_is_enabled(hw);
454 _clk_pll_disable(hw);
456 _update_pll_mnp(pll, cfg);
458 if (pll->flags & TEGRA_PLL_HAS_CPCON)
459 _update_pll_cpcon(pll, cfg, rate);
463 ret = clk_pll_wait_for_lock(pll);
469 static int clk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
470 unsigned long parent_rate)
472 struct tegra_clk_pll *pll = to_clk_pll(hw);
473 struct tegra_clk_pll_freq_table cfg, old_cfg;
474 unsigned long flags = 0;
477 if (pll->flags & TEGRA_PLL_FIXED) {
478 if (rate != pll->fixed_rate) {
479 pr_err("%s: Can not change %s fixed rate %lu to %lu\n",
480 __func__, __clk_get_name(hw->clk),
481 pll->fixed_rate, rate);
487 if (_get_table_rate(hw, &cfg, rate, parent_rate) &&
488 _calc_rate(hw, &cfg, rate, parent_rate))
492 spin_lock_irqsave(pll->lock, flags);
494 _get_pll_mnp(pll, &old_cfg);
496 if (old_cfg.m != cfg.m || old_cfg.n != cfg.n || old_cfg.p != cfg.p)
497 ret = _program_pll(hw, &cfg, rate);
500 spin_unlock_irqrestore(pll->lock, flags);
505 static long clk_pll_round_rate(struct clk_hw *hw, unsigned long rate,
506 unsigned long *prate)
508 struct tegra_clk_pll *pll = to_clk_pll(hw);
509 struct tegra_clk_pll_freq_table cfg;
510 u64 output_rate = *prate;
512 if (pll->flags & TEGRA_PLL_FIXED)
513 return pll->fixed_rate;
515 /* PLLM is used for memory; we do not change rate */
516 if (pll->flags & TEGRA_PLLM)
517 return __clk_get_rate(hw->clk);
519 if (_get_table_rate(hw, &cfg, rate, *prate) &&
520 _calc_rate(hw, &cfg, rate, *prate))
523 output_rate *= cfg.n;
524 do_div(output_rate, cfg.m * (1 << cfg.p));
529 static unsigned long clk_pll_recalc_rate(struct clk_hw *hw,
530 unsigned long parent_rate)
532 struct tegra_clk_pll *pll = to_clk_pll(hw);
533 struct tegra_clk_pll_freq_table cfg;
534 struct pdiv_map *p_tohw = pll->params->pdiv_tohw;
536 u64 rate = parent_rate;
539 val = pll_readl_base(pll);
541 if ((pll->flags & TEGRA_PLL_BYPASS) && (val & PLL_BASE_BYPASS))
544 if ((pll->flags & TEGRA_PLL_FIXED) && !(val & PLL_BASE_OVERRIDE)) {
545 struct tegra_clk_pll_freq_table sel;
546 if (_get_table_rate(hw, &sel, pll->fixed_rate, parent_rate)) {
547 pr_err("Clock %s has unknown fixed frequency\n",
548 __clk_get_name(hw->clk));
551 return pll->fixed_rate;
554 _get_pll_mnp(pll, &cfg);
557 while (p_tohw->pdiv) {
558 if (cfg.p == p_tohw->hw_val) {
580 static int clk_plle_training(struct tegra_clk_pll *pll)
583 unsigned long timeout;
589 * PLLE is already disabled, and setup cleared;
590 * create falling edge on PLLE IDDQ input.
592 val = readl(pll->pmc + PMC_SATA_PWRGT);
593 val |= PMC_SATA_PWRGT_PLLE_IDDQ_VALUE;
594 writel(val, pll->pmc + PMC_SATA_PWRGT);
596 val = readl(pll->pmc + PMC_SATA_PWRGT);
597 val |= PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL;
598 writel(val, pll->pmc + PMC_SATA_PWRGT);
600 val = readl(pll->pmc + PMC_SATA_PWRGT);
601 val &= ~PMC_SATA_PWRGT_PLLE_IDDQ_VALUE;
602 writel(val, pll->pmc + PMC_SATA_PWRGT);
604 val = pll_readl_misc(pll);
606 timeout = jiffies + msecs_to_jiffies(100);
608 val = pll_readl_misc(pll);
609 if (val & PLLE_MISC_READY)
611 if (time_after(jiffies, timeout)) {
612 pr_err("%s: timeout waiting for PLLE\n", __func__);
621 static int clk_plle_enable(struct clk_hw *hw)
623 struct tegra_clk_pll *pll = to_clk_pll(hw);
624 unsigned long input_rate = clk_get_rate(clk_get_parent(hw->clk));
625 struct tegra_clk_pll_freq_table sel;
629 if (_get_table_rate(hw, &sel, pll->fixed_rate, input_rate))
634 val = pll_readl_misc(pll);
635 val &= ~(PLLE_MISC_LOCK_ENABLE | PLLE_MISC_SETUP_MASK);
636 pll_writel_misc(val, pll);
638 val = pll_readl_misc(pll);
639 if (!(val & PLLE_MISC_READY)) {
640 err = clk_plle_training(pll);
645 if (pll->flags & TEGRA_PLLE_CONFIGURE) {
646 /* configure dividers */
647 val = pll_readl_base(pll);
648 val &= ~(divm_mask(pll) | divn_mask(pll) | divp_mask(pll));
649 val &= ~(PLLE_BASE_DIVCML_WIDTH << PLLE_BASE_DIVCML_SHIFT);
650 val |= sel.m << pll->divm_shift;
651 val |= sel.n << pll->divn_shift;
652 val |= sel.p << pll->divp_shift;
653 val |= sel.cpcon << PLLE_BASE_DIVCML_SHIFT;
654 pll_writel_base(val, pll);
657 val = pll_readl_misc(pll);
658 val |= PLLE_MISC_SETUP_VALUE;
659 val |= PLLE_MISC_LOCK_ENABLE;
660 pll_writel_misc(val, pll);
662 val = readl(pll->clk_base + PLLE_SS_CTRL);
663 val |= PLLE_SS_DISABLE;
664 writel(val, pll->clk_base + PLLE_SS_CTRL);
666 val |= pll_readl_base(pll);
667 val |= (PLL_BASE_BYPASS | PLL_BASE_ENABLE);
668 pll_writel_base(val, pll);
670 clk_pll_wait_for_lock(pll);
675 static unsigned long clk_plle_recalc_rate(struct clk_hw *hw,
676 unsigned long parent_rate)
678 struct tegra_clk_pll *pll = to_clk_pll(hw);
679 u32 val = pll_readl_base(pll);
680 u32 divn = 0, divm = 0, divp = 0;
681 u64 rate = parent_rate;
683 divp = (val >> pll->divp_shift) & (divp_mask(pll));
684 divn = (val >> pll->divn_shift) & (divn_mask(pll));
685 divm = (val >> pll->divm_shift) & (divm_mask(pll));
693 const struct clk_ops tegra_clk_pll_ops = {
694 .is_enabled = clk_pll_is_enabled,
695 .enable = clk_pll_enable,
696 .disable = clk_pll_disable,
697 .recalc_rate = clk_pll_recalc_rate,
698 .round_rate = clk_pll_round_rate,
699 .set_rate = clk_pll_set_rate,
702 const struct clk_ops tegra_clk_plle_ops = {
703 .recalc_rate = clk_plle_recalc_rate,
704 .is_enabled = clk_pll_is_enabled,
705 .disable = clk_pll_disable,
706 .enable = clk_plle_enable,
709 #ifdef CONFIG_ARCH_TEGRA_114_SOC
711 static int _pll_fixed_mdiv(struct tegra_clk_pll_params *pll_params,
712 unsigned long parent_rate)
714 if (parent_rate > pll_params->cf_max)
720 static int clk_pll_iddq_enable(struct clk_hw *hw)
722 struct tegra_clk_pll *pll = to_clk_pll(hw);
723 unsigned long flags = 0;
729 spin_lock_irqsave(pll->lock, flags);
731 val = pll_readl(pll->params->iddq_reg, pll);
732 val &= ~BIT(pll->params->iddq_bit_idx);
733 pll_writel(val, pll->params->iddq_reg, pll);
738 ret = clk_pll_wait_for_lock(pll);
741 spin_unlock_irqrestore(pll->lock, flags);
746 static void clk_pll_iddq_disable(struct clk_hw *hw)
748 struct tegra_clk_pll *pll = to_clk_pll(hw);
749 unsigned long flags = 0;
753 spin_lock_irqsave(pll->lock, flags);
755 _clk_pll_disable(hw);
757 val = pll_readl(pll->params->iddq_reg, pll);
758 val |= BIT(pll->params->iddq_bit_idx);
759 pll_writel(val, pll->params->iddq_reg, pll);
763 spin_unlock_irqrestore(pll->lock, flags);
766 static int _calc_dynamic_ramp_rate(struct clk_hw *hw,
767 struct tegra_clk_pll_freq_table *cfg,
768 unsigned long rate, unsigned long parent_rate)
770 struct tegra_clk_pll *pll = to_clk_pll(hw);
776 p = DIV_ROUND_UP(pll->params->vco_min, rate);
777 cfg->m = _pll_fixed_mdiv(pll->params, parent_rate);
779 cfg->output_rate = rate * cfg->p;
780 cfg->n = cfg->output_rate * cfg->m / parent_rate;
782 if (cfg->n > divn_max(pll) || cfg->output_rate > pll->params->vco_max)
788 static int _pll_ramp_calc_pll(struct clk_hw *hw,
789 struct tegra_clk_pll_freq_table *cfg,
790 unsigned long rate, unsigned long parent_rate)
792 struct tegra_clk_pll *pll = to_clk_pll(hw);
795 err = _get_table_rate(hw, cfg, rate, parent_rate);
797 err = _calc_dynamic_ramp_rate(hw, cfg, rate, parent_rate);
798 else if (cfg->m != _pll_fixed_mdiv(pll->params, parent_rate)) {
804 if (!cfg->p || (cfg->p > pll->params->max_p))
811 static int clk_pllxc_set_rate(struct clk_hw *hw, unsigned long rate,
812 unsigned long parent_rate)
814 struct tegra_clk_pll *pll = to_clk_pll(hw);
815 struct tegra_clk_pll_freq_table cfg, old_cfg;
816 unsigned long flags = 0;
820 ret = _pll_ramp_calc_pll(hw, &cfg, rate, parent_rate);
825 spin_lock_irqsave(pll->lock, flags);
827 _get_pll_mnp(pll, &old_cfg);
829 old_p = pllxc_p[old_cfg.p];
830 if (old_cfg.m != cfg.m || old_cfg.n != cfg.n || old_p != cfg.p) {
832 ret = _program_pll(hw, &cfg, rate);
836 spin_unlock_irqrestore(pll->lock, flags);
841 static long clk_pll_ramp_round_rate(struct clk_hw *hw, unsigned long rate,
842 unsigned long *prate)
844 struct tegra_clk_pll_freq_table cfg;
846 u64 output_rate = *prate;
848 ret = _pll_ramp_calc_pll(hw, &cfg, rate, *prate);
852 output_rate *= cfg.n;
853 do_div(output_rate, cfg.m * cfg.p);
858 static int clk_pllm_set_rate(struct clk_hw *hw, unsigned long rate,
859 unsigned long parent_rate)
861 struct tegra_clk_pll_freq_table cfg;
862 struct tegra_clk_pll *pll = to_clk_pll(hw);
863 unsigned long flags = 0;
868 spin_lock_irqsave(pll->lock, flags);
870 state = clk_pll_is_enabled(hw);
872 if (rate != clk_get_rate(hw->clk)) {
873 pr_err("%s: Cannot change active PLLM\n", __func__);
880 ret = _pll_ramp_calc_pll(hw, &cfg, rate, parent_rate);
886 val = readl_relaxed(pll->pmc + PMC_PLLM_WB0_OVERRIDE);
887 if (val & PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE) {
888 val = readl_relaxed(pll->pmc + PMC_PLLM_WB0_OVERRIDE_2);
889 val = cfg.p ? (val | PMC_PLLM_WB0_OVERRIDE_2_DIVP_MASK) :
890 (val & ~PMC_PLLM_WB0_OVERRIDE_2_DIVP_MASK);
891 writel_relaxed(val, pll->pmc + PMC_PLLM_WB0_OVERRIDE_2);
893 val = readl_relaxed(pll->pmc + PMC_PLLM_WB0_OVERRIDE);
894 val &= ~(divn_mask(pll) | divm_mask(pll));
895 val |= (cfg.m << pll->divm_shift) | (cfg.n << pll->divn_shift);
896 writel_relaxed(val, pll->pmc + PMC_PLLM_WB0_OVERRIDE);
898 _update_pll_mnp(pll, &cfg);
903 spin_unlock_irqrestore(pll->lock, flags);
908 static void _pllcx_strobe(struct tegra_clk_pll *pll)
912 val = pll_readl_misc(pll);
913 val |= PLLCX_MISC_STROBE;
914 pll_writel_misc(val, pll);
917 val &= ~PLLCX_MISC_STROBE;
918 pll_writel_misc(val, pll);
921 static int clk_pllc_enable(struct clk_hw *hw)
923 struct tegra_clk_pll *pll = to_clk_pll(hw);
926 unsigned long flags = 0;
929 spin_lock_irqsave(pll->lock, flags);
934 val = pll_readl_misc(pll);
935 val &= ~PLLCX_MISC_RESET;
936 pll_writel_misc(val, pll);
941 ret = clk_pll_wait_for_lock(pll);
944 spin_unlock_irqrestore(pll->lock, flags);
949 static void _clk_pllc_disable(struct clk_hw *hw)
951 struct tegra_clk_pll *pll = to_clk_pll(hw);
954 _clk_pll_disable(hw);
956 val = pll_readl_misc(pll);
957 val |= PLLCX_MISC_RESET;
958 pll_writel_misc(val, pll);
962 static void clk_pllc_disable(struct clk_hw *hw)
964 struct tegra_clk_pll *pll = to_clk_pll(hw);
965 unsigned long flags = 0;
968 spin_lock_irqsave(pll->lock, flags);
970 _clk_pllc_disable(hw);
973 spin_unlock_irqrestore(pll->lock, flags);
976 static int _pllcx_update_dynamic_coef(struct tegra_clk_pll *pll,
977 unsigned long input_rate, u32 n)
979 u32 val, n_threshold;
981 switch (input_rate) {
996 pr_err("%s: Unexpected reference rate %lu\n",
997 __func__, input_rate);
1001 val = pll_readl_misc(pll);
1002 val &= ~(PLLCX_MISC_SDM_DIV_MASK | PLLCX_MISC_FILT_DIV_MASK);
1003 val |= n <= n_threshold ?
1004 PLLCX_MISC_DIV_LOW_RANGE : PLLCX_MISC_DIV_HIGH_RANGE;
1005 pll_writel_misc(val, pll);
1010 static int clk_pllc_set_rate(struct clk_hw *hw, unsigned long rate,
1011 unsigned long parent_rate)
1013 struct tegra_clk_pll_freq_table cfg;
1014 struct tegra_clk_pll *pll = to_clk_pll(hw);
1015 unsigned long flags = 0;
1022 spin_lock_irqsave(pll->lock, flags);
1024 ret = _pll_ramp_calc_pll(hw, &cfg, rate, parent_rate);
1028 val = pll_readl_base(pll);
1029 old_m = (val >> pll->divm_shift) & (divm_mask(pll));
1030 old_n = (val >> pll->divn_shift) & (divn_mask(pll));
1031 old_p = pllcx_p[(val >> pll->divp_shift) & (divp_mask(pll))];
1033 if (cfg.m != old_m) {
1038 if (old_n == cfg.n && old_p == cfg.p)
1043 state = clk_pll_is_enabled(hw);
1045 _clk_pllc_disable(hw);
1047 ret = _pllcx_update_dynamic_coef(pll, parent_rate, cfg.n);
1051 _update_pll_mnp(pll, &cfg);
1054 ret = clk_pllc_enable(hw);
1058 spin_unlock_irqrestore(pll->lock, flags);
1063 static long _pllre_calc_rate(struct tegra_clk_pll *pll,
1064 struct tegra_clk_pll_freq_table *cfg,
1065 unsigned long rate, unsigned long parent_rate)
1068 u64 output_rate = parent_rate;
1070 m = _pll_fixed_mdiv(pll->params, parent_rate);
1071 n = rate * m / parent_rate;
1074 do_div(output_rate, m);
1083 static int clk_pllre_set_rate(struct clk_hw *hw, unsigned long rate,
1084 unsigned long parent_rate)
1086 struct tegra_clk_pll_freq_table cfg, old_cfg;
1087 struct tegra_clk_pll *pll = to_clk_pll(hw);
1088 unsigned long flags = 0;
1092 spin_lock_irqsave(pll->lock, flags);
1094 _pllre_calc_rate(pll, &cfg, rate, parent_rate);
1095 _get_pll_mnp(pll, &old_cfg);
1098 if (cfg.m != old_cfg.m || cfg.n != old_cfg.n) {
1099 state = clk_pll_is_enabled(hw);
1101 _clk_pll_disable(hw);
1103 _update_pll_mnp(pll, &cfg);
1106 _clk_pll_enable(hw);
1107 ret = clk_pll_wait_for_lock(pll);
1112 spin_unlock_irqrestore(pll->lock, flags);
1117 static unsigned long clk_pllre_recalc_rate(struct clk_hw *hw,
1118 unsigned long parent_rate)
1120 struct tegra_clk_pll_freq_table cfg;
1121 struct tegra_clk_pll *pll = to_clk_pll(hw);
1122 u64 rate = parent_rate;
1124 _get_pll_mnp(pll, &cfg);
1127 do_div(rate, cfg.m);
1132 static long clk_pllre_round_rate(struct clk_hw *hw, unsigned long rate,
1133 unsigned long *prate)
1135 struct tegra_clk_pll *pll = to_clk_pll(hw);
1137 return _pllre_calc_rate(pll, NULL, rate, *prate);
1140 static int clk_plle_tegra114_enable(struct clk_hw *hw)
1142 struct tegra_clk_pll *pll = to_clk_pll(hw);
1143 struct tegra_clk_pll_freq_table sel;
1146 unsigned long flags = 0;
1147 unsigned long input_rate = clk_get_rate(clk_get_parent(hw->clk));
1149 if (_get_table_rate(hw, &sel, pll->fixed_rate, input_rate))
1153 spin_lock_irqsave(pll->lock, flags);
1155 val = pll_readl_base(pll);
1156 val &= ~BIT(29); /* Disable lock override */
1157 pll_writel_base(val, pll);
1159 val = pll_readl(pll->params->aux_reg, pll);
1160 val |= PLLE_AUX_ENABLE_SWCTL;
1161 val &= ~PLLE_AUX_SEQ_ENABLE;
1162 pll_writel(val, pll->params->aux_reg, pll);
1165 val = pll_readl_misc(pll);
1166 val |= PLLE_MISC_LOCK_ENABLE;
1167 val |= PLLE_MISC_IDDQ_SW_CTRL;
1168 val &= ~PLLE_MISC_IDDQ_SW_VALUE;
1169 val |= PLLE_MISC_PLLE_PTS;
1170 val |= PLLE_MISC_VREG_BG_CTRL_MASK | PLLE_MISC_VREG_CTRL_MASK;
1171 pll_writel_misc(val, pll);
1174 val = pll_readl(PLLE_SS_CTRL, pll);
1175 val |= PLLE_SS_DISABLE;
1176 pll_writel(val, PLLE_SS_CTRL, pll);
1178 val = pll_readl_base(pll);
1179 val &= ~(divm_mask(pll) | divn_mask(pll) | divp_mask(pll));
1180 val &= ~(PLLE_BASE_DIVCML_WIDTH << PLLE_BASE_DIVCML_SHIFT);
1181 val |= sel.m << pll->divm_shift;
1182 val |= sel.n << pll->divn_shift;
1183 val |= sel.cpcon << PLLE_BASE_DIVCML_SHIFT;
1184 pll_writel_base(val, pll);
1187 _clk_pll_enable(hw);
1188 ret = clk_pll_wait_for_lock(pll);
1193 /* TODO: enable hw control of xusb brick pll */
1197 spin_unlock_irqrestore(pll->lock, flags);
1202 static void clk_plle_tegra114_disable(struct clk_hw *hw)
1204 struct tegra_clk_pll *pll = to_clk_pll(hw);
1205 unsigned long flags = 0;
1209 spin_lock_irqsave(pll->lock, flags);
1211 _clk_pll_disable(hw);
1213 val = pll_readl_misc(pll);
1214 val |= PLLE_MISC_IDDQ_SW_CTRL | PLLE_MISC_IDDQ_SW_VALUE;
1215 pll_writel_misc(val, pll);
1219 spin_unlock_irqrestore(pll->lock, flags);
1223 static struct tegra_clk_pll *_tegra_init_pll(void __iomem *clk_base,
1224 void __iomem *pmc, unsigned long fixed_rate,
1225 struct tegra_clk_pll_params *pll_params, u32 pll_flags,
1226 struct tegra_clk_pll_freq_table *freq_table, spinlock_t *lock)
1228 struct tegra_clk_pll *pll;
1230 pll = kzalloc(sizeof(*pll), GFP_KERNEL);
1232 return ERR_PTR(-ENOMEM);
1234 pll->clk_base = clk_base;
1237 pll->freq_table = freq_table;
1238 pll->params = pll_params;
1239 pll->fixed_rate = fixed_rate;
1240 pll->flags = pll_flags;
1243 pll->divp_shift = PLL_BASE_DIVP_SHIFT;
1244 pll->divp_width = PLL_BASE_DIVP_WIDTH;
1245 pll->divn_shift = PLL_BASE_DIVN_SHIFT;
1246 pll->divn_width = PLL_BASE_DIVN_WIDTH;
1247 pll->divm_shift = PLL_BASE_DIVM_SHIFT;
1248 pll->divm_width = PLL_BASE_DIVM_WIDTH;
1253 static struct clk *_tegra_clk_register_pll(struct tegra_clk_pll *pll,
1254 const char *name, const char *parent_name, unsigned long flags,
1255 const struct clk_ops *ops)
1257 struct clk_init_data init;
1262 init.parent_names = (parent_name ? &parent_name : NULL);
1263 init.num_parents = (parent_name ? 1 : 0);
1265 /* Data in .init is copied by clk_register(), so stack variable OK */
1266 pll->hw.init = &init;
1268 return clk_register(NULL, &pll->hw);
1271 struct clk *tegra_clk_register_pll(const char *name, const char *parent_name,
1272 void __iomem *clk_base, void __iomem *pmc,
1273 unsigned long flags, unsigned long fixed_rate,
1274 struct tegra_clk_pll_params *pll_params, u32 pll_flags,
1275 struct tegra_clk_pll_freq_table *freq_table, spinlock_t *lock)
1277 struct tegra_clk_pll *pll;
1280 pll_flags |= TEGRA_PLL_BYPASS;
1281 pll_flags |= TEGRA_PLL_HAS_LOCK_ENABLE;
1282 pll = _tegra_init_pll(clk_base, pmc, fixed_rate, pll_params, pll_flags,
1285 return ERR_CAST(pll);
1287 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1288 &tegra_clk_pll_ops);
1295 struct clk *tegra_clk_register_plle(const char *name, const char *parent_name,
1296 void __iomem *clk_base, void __iomem *pmc,
1297 unsigned long flags, unsigned long fixed_rate,
1298 struct tegra_clk_pll_params *pll_params, u32 pll_flags,
1299 struct tegra_clk_pll_freq_table *freq_table, spinlock_t *lock)
1301 struct tegra_clk_pll *pll;
1304 pll_flags |= TEGRA_PLL_LOCK_MISC | TEGRA_PLL_BYPASS;
1305 pll_flags |= TEGRA_PLL_HAS_LOCK_ENABLE;
1306 pll = _tegra_init_pll(clk_base, pmc, fixed_rate, pll_params, pll_flags,
1309 return ERR_CAST(pll);
1311 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1312 &tegra_clk_plle_ops);
1319 #ifdef CONFIG_ARCH_TEGRA_114_SOC
1320 const struct clk_ops tegra_clk_pllxc_ops = {
1321 .is_enabled = clk_pll_is_enabled,
1322 .enable = clk_pll_iddq_enable,
1323 .disable = clk_pll_iddq_disable,
1324 .recalc_rate = clk_pll_recalc_rate,
1325 .round_rate = clk_pll_ramp_round_rate,
1326 .set_rate = clk_pllxc_set_rate,
1329 const struct clk_ops tegra_clk_pllm_ops = {
1330 .is_enabled = clk_pll_is_enabled,
1331 .enable = clk_pll_iddq_enable,
1332 .disable = clk_pll_iddq_disable,
1333 .recalc_rate = clk_pll_recalc_rate,
1334 .round_rate = clk_pll_ramp_round_rate,
1335 .set_rate = clk_pllm_set_rate,
1338 const struct clk_ops tegra_clk_pllc_ops = {
1339 .is_enabled = clk_pll_is_enabled,
1340 .enable = clk_pllc_enable,
1341 .disable = clk_pllc_disable,
1342 .recalc_rate = clk_pll_recalc_rate,
1343 .round_rate = clk_pll_ramp_round_rate,
1344 .set_rate = clk_pllc_set_rate,
1347 const struct clk_ops tegra_clk_pllre_ops = {
1348 .is_enabled = clk_pll_is_enabled,
1349 .enable = clk_pll_iddq_enable,
1350 .disable = clk_pll_iddq_disable,
1351 .recalc_rate = clk_pllre_recalc_rate,
1352 .round_rate = clk_pllre_round_rate,
1353 .set_rate = clk_pllre_set_rate,
1356 const struct clk_ops tegra_clk_plle_tegra114_ops = {
1357 .is_enabled = clk_pll_is_enabled,
1358 .enable = clk_plle_tegra114_enable,
1359 .disable = clk_plle_tegra114_disable,
1360 .recalc_rate = clk_pll_recalc_rate,
1364 struct clk *tegra_clk_register_pllxc(const char *name, const char *parent_name,
1365 void __iomem *clk_base, void __iomem *pmc,
1366 unsigned long flags, unsigned long fixed_rate,
1367 struct tegra_clk_pll_params *pll_params,
1369 struct tegra_clk_pll_freq_table *freq_table,
1372 struct tegra_clk_pll *pll;
1375 if (!pll_params->pdiv_tohw)
1376 return ERR_PTR(-EINVAL);
1378 pll_flags |= TEGRA_PLL_HAS_LOCK_ENABLE;
1379 pll = _tegra_init_pll(clk_base, pmc, fixed_rate, pll_params, pll_flags,
1382 return ERR_CAST(pll);
1384 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1385 &tegra_clk_pllxc_ops);
1392 struct clk *tegra_clk_register_pllre(const char *name, const char *parent_name,
1393 void __iomem *clk_base, void __iomem *pmc,
1394 unsigned long flags, unsigned long fixed_rate,
1395 struct tegra_clk_pll_params *pll_params,
1397 struct tegra_clk_pll_freq_table *freq_table,
1398 spinlock_t *lock, unsigned long parent_rate)
1401 struct tegra_clk_pll *pll;
1404 pll_flags |= TEGRA_PLL_HAS_LOCK_ENABLE;
1405 pll = _tegra_init_pll(clk_base, pmc, fixed_rate, pll_params, pll_flags,
1408 return ERR_CAST(pll);
1410 /* program minimum rate by default */
1412 val = pll_readl_base(pll);
1413 if (val & PLL_BASE_ENABLE)
1414 WARN_ON(val & pll_params->iddq_bit_idx);
1418 m = _pll_fixed_mdiv(pll_params, parent_rate);
1419 val = m << PLL_BASE_DIVM_SHIFT;
1420 val |= (pll_params->vco_min / parent_rate)
1421 << PLL_BASE_DIVN_SHIFT;
1422 pll_writel_base(val, pll);
1425 /* disable lock override */
1427 val = pll_readl_misc(pll);
1429 pll_writel_misc(val, pll);
1431 pll_flags |= TEGRA_PLL_LOCK_MISC;
1432 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1433 &tegra_clk_pllre_ops);
1440 struct clk *tegra_clk_register_pllm(const char *name, const char *parent_name,
1441 void __iomem *clk_base, void __iomem *pmc,
1442 unsigned long flags, unsigned long fixed_rate,
1443 struct tegra_clk_pll_params *pll_params,
1445 struct tegra_clk_pll_freq_table *freq_table,
1448 struct tegra_clk_pll *pll;
1451 if (!pll_params->pdiv_tohw)
1452 return ERR_PTR(-EINVAL);
1454 pll_flags |= TEGRA_PLL_BYPASS;
1455 pll_flags |= TEGRA_PLL_HAS_LOCK_ENABLE;
1456 pll = _tegra_init_pll(clk_base, pmc, fixed_rate, pll_params, pll_flags,
1459 return ERR_CAST(pll);
1461 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1462 &tegra_clk_pllm_ops);
1469 struct clk *tegra_clk_register_pllc(const char *name, const char *parent_name,
1470 void __iomem *clk_base, void __iomem *pmc,
1471 unsigned long flags, unsigned long fixed_rate,
1472 struct tegra_clk_pll_params *pll_params,
1474 struct tegra_clk_pll_freq_table *freq_table,
1477 struct clk *parent, *clk;
1478 struct pdiv_map *p_tohw = pll_params->pdiv_tohw;
1479 struct tegra_clk_pll *pll;
1480 struct tegra_clk_pll_freq_table cfg;
1481 unsigned long parent_rate;
1484 return ERR_PTR(-EINVAL);
1486 parent = __clk_lookup(parent_name);
1487 if (IS_ERR(parent)) {
1488 WARN(1, "parent clk %s of %s must be registered first\n",
1490 return ERR_PTR(-EINVAL);
1493 pll_flags |= TEGRA_PLL_BYPASS;
1494 pll = _tegra_init_pll(clk_base, pmc, fixed_rate, pll_params, pll_flags,
1497 return ERR_CAST(pll);
1499 parent_rate = __clk_get_rate(parent);
1502 * Most of PLLC register fields are shadowed, and can not be read
1503 * directly from PLL h/w. Hence, actual PLLC boot state is unknown.
1504 * Initialize PLL to default state: disabled, reset; shadow registers
1505 * loaded with default parameters; dividers are preset for half of
1506 * minimum VCO rate (the latter assured that shadowed divider settings
1507 * are within supported range).
1510 cfg.m = _pll_fixed_mdiv(pll_params, parent_rate);
1511 cfg.n = cfg.m * pll_params->vco_min / parent_rate;
1513 while (p_tohw->pdiv) {
1514 if (p_tohw->pdiv == 2) {
1515 cfg.p = p_tohw->hw_val;
1521 if (!p_tohw->pdiv) {
1523 return ERR_PTR(-EINVAL);
1526 pll_writel_base(0, pll);
1527 _update_pll_mnp(pll, &cfg);
1529 pll_writel_misc(PLLCX_MISC_DEFAULT, pll);
1530 pll_writel(PLLCX_MISC1_DEFAULT, pll_params->ext_misc_reg[0], pll);
1531 pll_writel(PLLCX_MISC2_DEFAULT, pll_params->ext_misc_reg[1], pll);
1532 pll_writel(PLLCX_MISC3_DEFAULT, pll_params->ext_misc_reg[2], pll);
1534 _pllcx_update_dynamic_coef(pll, parent_rate, cfg.n);
1536 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1537 &tegra_clk_pllc_ops);
1544 struct clk *tegra_clk_register_plle_tegra114(const char *name,
1545 const char *parent_name,
1546 void __iomem *clk_base, unsigned long flags,
1547 unsigned long fixed_rate,
1548 struct tegra_clk_pll_params *pll_params,
1549 struct tegra_clk_pll_freq_table *freq_table,
1552 struct tegra_clk_pll *pll;
1556 pll = _tegra_init_pll(clk_base, NULL, fixed_rate, pll_params,
1557 TEGRA_PLL_HAS_LOCK_ENABLE, freq_table, lock);
1559 return ERR_CAST(pll);
1561 /* ensure parent is set to pll_re_vco */
1563 val = pll_readl_base(pll);
1564 val_aux = pll_readl(pll_params->aux_reg, pll);
1566 if (val & PLL_BASE_ENABLE) {
1567 if (!(val_aux & PLLE_AUX_PLLRE_SEL))
1568 WARN(1, "pll_e enabled with unsupported parent %s\n",
1569 (val & PLLE_AUX_PLLP_SEL) ? "pllp_out0" : "pll_ref");
1571 val_aux |= PLLE_AUX_PLLRE_SEL;
1572 pll_writel(val, pll_params->aux_reg, pll);
1575 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1576 &tegra_clk_plle_tegra114_ops);