2 * Copyright (c) 2012, 2013, NVIDIA CORPORATION. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
18 #include <linux/clk.h>
19 #include <linux/clk-provider.h>
21 #include <linux/of_address.h>
22 #include <linux/delay.h>
23 #include <linux/export.h>
24 #include <linux/clk/tegra.h>
30 #define OSC_CTRL_OSC_FREQ_SHIFT 28
31 #define OSC_CTRL_PLL_REF_DIV_SHIFT 26
33 int __init tegra_osc_clk_init(void __iomem *clk_base,
34 struct tegra_clk *tegra_clks,
35 unsigned long *input_freqs, int num,
36 unsigned long *osc_freq,
37 unsigned long *pll_ref_freq)
44 val = readl_relaxed(clk_base + OSC_CTRL);
45 osc_idx = val >> OSC_CTRL_OSC_FREQ_SHIFT;
48 *osc_freq = input_freqs[osc_idx];
57 dt_clk = tegra_lookup_dt_id(tegra_clk_clk_m, tegra_clks);
61 clk = clk_register_fixed_rate(NULL, "clk_m", NULL, CLK_IS_ROOT,
66 val = (val >> OSC_CTRL_PLL_REF_DIV_SHIFT) & 3;
67 pll_ref_div = 1 << val;
68 dt_clk = tegra_lookup_dt_id(tegra_clk_pll_ref, tegra_clks);
72 clk = clk_register_fixed_factor(NULL, "pll_ref", "clk_m",
77 *pll_ref_freq = *osc_freq / pll_ref_div;
82 void __init tegra_fixed_clk_init(struct tegra_clk *tegra_clks)
88 dt_clk = tegra_lookup_dt_id(tegra_clk_clk_32k, tegra_clks);
90 clk = clk_register_fixed_rate(NULL, "clk_32k", NULL,
96 dt_clk = tegra_lookup_dt_id(tegra_clk_clk_m_div2, tegra_clks);
98 clk = clk_register_fixed_factor(NULL, "clk_m_div2", "clk_m",
99 CLK_SET_RATE_PARENT, 1, 2);
104 dt_clk = tegra_lookup_dt_id(tegra_clk_clk_m_div4, tegra_clks);
106 clk = clk_register_fixed_factor(NULL, "clk_m_div4", "clk_m",
107 CLK_SET_RATE_PARENT, 1, 4);