2 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
18 #include <linux/delay.h>
19 #include <linux/clk.h>
20 #include <linux/clk-provider.h>
21 #include <linux/clkdev.h>
23 #include <linux/of_address.h>
24 #include <linux/clk/tegra.h>
25 #include <linux/tegra-powergate.h>
29 #define RST_DEVICES_L 0x004
30 #define RST_DEVICES_H 0x008
31 #define RST_DEVICES_U 0x00c
32 #define RST_DEVICES_V 0x358
33 #define RST_DEVICES_W 0x35c
34 #define RST_DEVICES_SET_L 0x300
35 #define RST_DEVICES_CLR_L 0x304
36 #define RST_DEVICES_SET_H 0x308
37 #define RST_DEVICES_CLR_H 0x30c
38 #define RST_DEVICES_SET_U 0x310
39 #define RST_DEVICES_CLR_U 0x314
40 #define RST_DEVICES_SET_V 0x430
41 #define RST_DEVICES_CLR_V 0x434
42 #define RST_DEVICES_SET_W 0x438
43 #define RST_DEVICES_CLR_W 0x43c
44 #define RST_DEVICES_NUM 5
46 #define CLK_OUT_ENB_L 0x010
47 #define CLK_OUT_ENB_H 0x014
48 #define CLK_OUT_ENB_U 0x018
49 #define CLK_OUT_ENB_V 0x360
50 #define CLK_OUT_ENB_W 0x364
51 #define CLK_OUT_ENB_SET_L 0x320
52 #define CLK_OUT_ENB_CLR_L 0x324
53 #define CLK_OUT_ENB_SET_H 0x328
54 #define CLK_OUT_ENB_CLR_H 0x32c
55 #define CLK_OUT_ENB_SET_U 0x330
56 #define CLK_OUT_ENB_CLR_U 0x334
57 #define CLK_OUT_ENB_SET_V 0x440
58 #define CLK_OUT_ENB_CLR_V 0x444
59 #define CLK_OUT_ENB_SET_W 0x448
60 #define CLK_OUT_ENB_CLR_W 0x44c
61 #define CLK_OUT_ENB_NUM 5
64 #define OSC_CTRL_OSC_FREQ_MASK (0xF<<28)
65 #define OSC_CTRL_OSC_FREQ_13MHZ (0X0<<28)
66 #define OSC_CTRL_OSC_FREQ_19_2MHZ (0X4<<28)
67 #define OSC_CTRL_OSC_FREQ_12MHZ (0X8<<28)
68 #define OSC_CTRL_OSC_FREQ_26MHZ (0XC<<28)
69 #define OSC_CTRL_OSC_FREQ_16_8MHZ (0X1<<28)
70 #define OSC_CTRL_OSC_FREQ_38_4MHZ (0X5<<28)
71 #define OSC_CTRL_OSC_FREQ_48MHZ (0X9<<28)
72 #define OSC_CTRL_MASK (0x3f2 | OSC_CTRL_OSC_FREQ_MASK)
74 #define OSC_CTRL_PLL_REF_DIV_MASK (3<<26)
75 #define OSC_CTRL_PLL_REF_DIV_1 (0<<26)
76 #define OSC_CTRL_PLL_REF_DIV_2 (1<<26)
77 #define OSC_CTRL_PLL_REF_DIV_4 (2<<26)
79 #define OSC_FREQ_DET 0x58
80 #define OSC_FREQ_DET_TRIG BIT(31)
82 #define OSC_FREQ_DET_STATUS 0x5c
83 #define OSC_FREQ_DET_BUSY BIT(31)
84 #define OSC_FREQ_DET_CNT_MASK 0xffff
86 #define CCLKG_BURST_POLICY 0x368
87 #define SUPER_CCLKG_DIVIDER 0x36c
88 #define CCLKLP_BURST_POLICY 0x370
89 #define SUPER_CCLKLP_DIVIDER 0x374
90 #define SCLK_BURST_POLICY 0x028
91 #define SUPER_SCLK_DIVIDER 0x02c
93 #define SYSTEM_CLK_RATE 0x030
95 #define PLLC_BASE 0x80
96 #define PLLC_MISC 0x8c
97 #define PLLM_BASE 0x90
98 #define PLLM_MISC 0x9c
99 #define PLLP_BASE 0xa0
100 #define PLLP_MISC 0xac
101 #define PLLX_BASE 0xe0
102 #define PLLX_MISC 0xe4
103 #define PLLD_BASE 0xd0
104 #define PLLD_MISC 0xdc
105 #define PLLD2_BASE 0x4b8
106 #define PLLD2_MISC 0x4bc
107 #define PLLE_BASE 0xe8
108 #define PLLE_MISC 0xec
109 #define PLLA_BASE 0xb0
110 #define PLLA_MISC 0xbc
111 #define PLLU_BASE 0xc0
112 #define PLLU_MISC 0xcc
114 #define PLL_MISC_LOCK_ENABLE 18
115 #define PLLDU_MISC_LOCK_ENABLE 22
116 #define PLLE_MISC_LOCK_ENABLE 9
118 #define PLL_BASE_LOCK BIT(27)
119 #define PLLE_MISC_LOCK BIT(11)
121 #define PLLE_AUX 0x48c
122 #define PLLC_OUT 0x84
123 #define PLLM_OUT 0x94
124 #define PLLP_OUTA 0xa4
125 #define PLLP_OUTB 0xa8
126 #define PLLA_OUT 0xb4
128 #define AUDIO_SYNC_CLK_I2S0 0x4a0
129 #define AUDIO_SYNC_CLK_I2S1 0x4a4
130 #define AUDIO_SYNC_CLK_I2S2 0x4a8
131 #define AUDIO_SYNC_CLK_I2S3 0x4ac
132 #define AUDIO_SYNC_CLK_I2S4 0x4b0
133 #define AUDIO_SYNC_CLK_SPDIF 0x4b4
135 #define PMC_CLK_OUT_CNTRL 0x1a8
137 #define CLK_SOURCE_I2S0 0x1d8
138 #define CLK_SOURCE_I2S1 0x100
139 #define CLK_SOURCE_I2S2 0x104
140 #define CLK_SOURCE_I2S3 0x3bc
141 #define CLK_SOURCE_I2S4 0x3c0
142 #define CLK_SOURCE_SPDIF_OUT 0x108
143 #define CLK_SOURCE_SPDIF_IN 0x10c
144 #define CLK_SOURCE_PWM 0x110
145 #define CLK_SOURCE_D_AUDIO 0x3d0
146 #define CLK_SOURCE_DAM0 0x3d8
147 #define CLK_SOURCE_DAM1 0x3dc
148 #define CLK_SOURCE_DAM2 0x3e0
149 #define CLK_SOURCE_HDA 0x428
150 #define CLK_SOURCE_HDA2CODEC_2X 0x3e4
151 #define CLK_SOURCE_SBC1 0x134
152 #define CLK_SOURCE_SBC2 0x118
153 #define CLK_SOURCE_SBC3 0x11c
154 #define CLK_SOURCE_SBC4 0x1b4
155 #define CLK_SOURCE_SBC5 0x3c8
156 #define CLK_SOURCE_SBC6 0x3cc
157 #define CLK_SOURCE_SATA_OOB 0x420
158 #define CLK_SOURCE_SATA 0x424
159 #define CLK_SOURCE_NDFLASH 0x160
160 #define CLK_SOURCE_NDSPEED 0x3f8
161 #define CLK_SOURCE_VFIR 0x168
162 #define CLK_SOURCE_SDMMC1 0x150
163 #define CLK_SOURCE_SDMMC2 0x154
164 #define CLK_SOURCE_SDMMC3 0x1bc
165 #define CLK_SOURCE_SDMMC4 0x164
166 #define CLK_SOURCE_VDE 0x1c8
167 #define CLK_SOURCE_CSITE 0x1d4
168 #define CLK_SOURCE_LA 0x1f8
169 #define CLK_SOURCE_OWR 0x1cc
170 #define CLK_SOURCE_NOR 0x1d0
171 #define CLK_SOURCE_MIPI 0x174
172 #define CLK_SOURCE_I2C1 0x124
173 #define CLK_SOURCE_I2C2 0x198
174 #define CLK_SOURCE_I2C3 0x1b8
175 #define CLK_SOURCE_I2C4 0x3c4
176 #define CLK_SOURCE_I2C5 0x128
177 #define CLK_SOURCE_UARTA 0x178
178 #define CLK_SOURCE_UARTB 0x17c
179 #define CLK_SOURCE_UARTC 0x1a0
180 #define CLK_SOURCE_UARTD 0x1c0
181 #define CLK_SOURCE_UARTE 0x1c4
182 #define CLK_SOURCE_VI 0x148
183 #define CLK_SOURCE_VI_SENSOR 0x1a8
184 #define CLK_SOURCE_3D 0x158
185 #define CLK_SOURCE_3D2 0x3b0
186 #define CLK_SOURCE_2D 0x15c
187 #define CLK_SOURCE_EPP 0x16c
188 #define CLK_SOURCE_MPE 0x170
189 #define CLK_SOURCE_HOST1X 0x180
190 #define CLK_SOURCE_CVE 0x140
191 #define CLK_SOURCE_TVO 0x188
192 #define CLK_SOURCE_DTV 0x1dc
193 #define CLK_SOURCE_HDMI 0x18c
194 #define CLK_SOURCE_TVDAC 0x194
195 #define CLK_SOURCE_DISP1 0x138
196 #define CLK_SOURCE_DISP2 0x13c
197 #define CLK_SOURCE_DSIB 0xd0
198 #define CLK_SOURCE_TSENSOR 0x3b8
199 #define CLK_SOURCE_ACTMON 0x3e8
200 #define CLK_SOURCE_EXTERN1 0x3ec
201 #define CLK_SOURCE_EXTERN2 0x3f0
202 #define CLK_SOURCE_EXTERN3 0x3f4
203 #define CLK_SOURCE_I2CSLOW 0x3fc
204 #define CLK_SOURCE_SE 0x42c
205 #define CLK_SOURCE_MSELECT 0x3b4
206 #define CLK_SOURCE_EMC 0x19c
208 #define AUDIO_SYNC_DOUBLER 0x49c
211 #define PMC_CTRL_BLINK_ENB 7
213 #define PMC_DPD_PADS_ORIDE 0x1c
214 #define PMC_DPD_PADS_ORIDE_BLINK_ENB 20
215 #define PMC_BLINK_TIMER 0x40
217 #define UTMIP_PLL_CFG2 0x488
218 #define UTMIP_PLL_CFG2_STABLE_COUNT(x) (((x) & 0xffff) << 6)
219 #define UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(x) (((x) & 0x3f) << 18)
220 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN BIT(0)
221 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN BIT(2)
222 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN BIT(4)
224 #define UTMIP_PLL_CFG1 0x484
225 #define UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 6)
226 #define UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(x) (((x) & 0xfff) << 0)
227 #define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN BIT(14)
228 #define UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN BIT(12)
229 #define UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN BIT(16)
231 /* Tegra CPU clock and reset control regs */
232 #define TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX 0x4c
233 #define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET 0x340
234 #define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR 0x344
235 #define TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR 0x34c
236 #define TEGRA30_CLK_RST_CONTROLLER_CPU_CMPLX_STATUS 0x470
238 #define CPU_CLOCK(cpu) (0x1 << (8 + cpu))
239 #define CPU_RESET(cpu) (0x1111ul << (cpu))
241 #define CLK_RESET_CCLK_BURST 0x20
242 #define CLK_RESET_CCLK_DIVIDER 0x24
243 #define CLK_RESET_PLLX_BASE 0xe0
244 #define CLK_RESET_PLLX_MISC 0xe4
246 #define CLK_RESET_SOURCE_CSITE 0x1d4
248 #define CLK_RESET_CCLK_BURST_POLICY_SHIFT 28
249 #define CLK_RESET_CCLK_RUN_POLICY_SHIFT 4
250 #define CLK_RESET_CCLK_IDLE_POLICY_SHIFT 0
251 #define CLK_RESET_CCLK_IDLE_POLICY 1
252 #define CLK_RESET_CCLK_RUN_POLICY 2
253 #define CLK_RESET_CCLK_BURST_POLICY_PLLX 8
255 #ifdef CONFIG_PM_SLEEP
256 static struct cpu_clk_suspend_context {
263 } tegra30_cpu_clk_sctx;
266 static int periph_clk_enb_refcnt[CLK_OUT_ENB_NUM * 32];
268 static void __iomem *clk_base;
269 static void __iomem *pmc_base;
270 static unsigned long input_freq;
272 static DEFINE_SPINLOCK(clk_doubler_lock);
273 static DEFINE_SPINLOCK(clk_out_lock);
274 static DEFINE_SPINLOCK(pll_div_lock);
275 static DEFINE_SPINLOCK(cml_lock);
276 static DEFINE_SPINLOCK(pll_d_lock);
277 static DEFINE_SPINLOCK(sysrate_lock);
279 #define TEGRA_INIT_DATA_MUX(_name, _con_id, _dev_id, _parents, _offset, \
280 _clk_num, _regs, _gate_flags, _clk_id) \
281 TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parents, _offset, \
282 30, 2, 0, 0, 8, 1, 0, _regs, _clk_num, \
283 periph_clk_enb_refcnt, _gate_flags, _clk_id)
285 #define TEGRA_INIT_DATA_DIV16(_name, _con_id, _dev_id, _parents, _offset, \
286 _clk_num, _regs, _gate_flags, _clk_id) \
287 TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parents, _offset, \
288 30, 2, 0, 0, 16, 0, TEGRA_DIVIDER_ROUND_UP, \
289 _regs, _clk_num, periph_clk_enb_refcnt, \
290 _gate_flags, _clk_id)
292 #define TEGRA_INIT_DATA_MUX8(_name, _con_id, _dev_id, _parents, _offset, \
293 _clk_num, _regs, _gate_flags, _clk_id) \
294 TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parents, _offset, \
295 29, 3, 0, 0, 8, 1, 0, _regs, _clk_num, \
296 periph_clk_enb_refcnt, _gate_flags, _clk_id)
298 #define TEGRA_INIT_DATA_INT(_name, _con_id, _dev_id, _parents, _offset, \
299 _clk_num, _regs, _gate_flags, _clk_id) \
300 TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parents, _offset, \
301 30, 2, 0, 0, 8, 1, TEGRA_DIVIDER_INT, _regs, \
302 _clk_num, periph_clk_enb_refcnt, _gate_flags, \
305 #define TEGRA_INIT_DATA_UART(_name, _con_id, _dev_id, _parents, _offset,\
306 _clk_num, _regs, _clk_id) \
307 TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parents, _offset, \
308 30, 2, 0, 0, 16, 1, TEGRA_DIVIDER_UART, _regs, \
309 _clk_num, periph_clk_enb_refcnt, 0, _clk_id)
311 #define TEGRA_INIT_DATA_NODIV(_name, _con_id, _dev_id, _parents, _offset, \
312 _mux_shift, _mux_width, _clk_num, _regs, \
313 _gate_flags, _clk_id) \
314 TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parents, _offset, \
315 _mux_shift, _mux_width, 0, 0, 0, 0, 0, _regs, \
316 _clk_num, periph_clk_enb_refcnt, _gate_flags, \
320 * IDs assigned here must be in sync with DT bindings definition
321 * for Tegra30 clocks.
324 cpu, rtc = 4, timer, uarta, gpio = 8, sdmmc2, i2s1 = 11, i2c1, ndflash,
325 sdmmc1, sdmmc4, pwm = 17, i2s2, epp, gr2d = 21, usbd, isp, gr3d,
326 disp2 = 26, disp1, host1x, vcp, i2s0, cop_cache, mc, ahbdma, apbdma,
327 kbc = 36, statmon, pmc, kfuse = 40, sbc1, nor, sbc2 = 44, sbc3 = 46,
328 i2c5, dsia, mipi = 50, hdmi, csi, tvdac, i2c2, uartc, emc = 57, usb2,
329 usb3, mpe, vde, bsea, bsev, speedo, uartd, uarte, i2c3, sbc4, sdmmc3,
330 pcie, owr, afi, csite, pciex, avpucq, la, dtv = 79, ndspeed, i2cslow,
331 dsib, irama = 84, iramb, iramc, iramd, cram2, audio_2x = 90, csus = 92,
332 cdev2, cdev1, cpu_g = 96, cpu_lp, gr3d2, mselect, tsensor, i2s3, i2s4,
333 i2c4, sbc5, sbc6, d_audio, apbif, dam0, dam1, dam2, hda2codec_2x,
334 atomics, audio0_2x, audio1_2x, audio2_2x, audio3_2x, audio4_2x,
335 spdif_2x, actmon, extern1, extern2, extern3, sata_oob, sata, hda,
336 se = 127, hda2hdmi, sata_cold, uartb = 160, vfir, spdif_in, spdif_out,
337 vi, vi_sensor, fuse, fuse_burn, cve, tvo, clk_32k, clk_m, clk_m_div2,
338 clk_m_div4, pll_ref, pll_c, pll_c_out1, pll_m, pll_m_out1, pll_p,
339 pll_p_out1, pll_p_out2, pll_p_out3, pll_p_out4, pll_a, pll_a_out0,
340 pll_d, pll_d_out0, pll_d2, pll_d2_out0, pll_u, pll_x, pll_x_out0, pll_e,
341 spdif_in_sync, i2s0_sync, i2s1_sync, i2s2_sync, i2s3_sync, i2s4_sync,
342 vimclk_sync, audio0, audio1, audio2, audio3, audio4, spdif, clk_out_1,
343 clk_out_2, clk_out_3, sclk, blink, cclk_g, cclk_lp, twd, cml0, cml1,
344 hclk, pclk, clk_out_1_mux = 300, clk_max
347 static struct clk *clks[clk_max];
348 static struct clk_onecell_data clk_data;
351 * Structure defining the fields for USB UTMI clocks Parameters.
353 struct utmi_clk_param {
354 /* Oscillator Frequency in KHz */
356 /* UTMIP PLL Enable Delay Count */
357 u8 enable_delay_count;
358 /* UTMIP PLL Stable count */
360 /* UTMIP PLL Active delay count */
361 u8 active_delay_count;
362 /* UTMIP PLL Xtal frequency count */
366 static const struct utmi_clk_param utmi_parameters[] = {
367 /* OSC_FREQUENCY, ENABLE_DLY, STABLE_CNT, ACTIVE_DLY, XTAL_FREQ_CNT */
368 {13000000, 0x02, 0x33, 0x05, 0x7F},
369 {19200000, 0x03, 0x4B, 0x06, 0xBB},
370 {12000000, 0x02, 0x2F, 0x04, 0x76},
371 {26000000, 0x04, 0x66, 0x09, 0xFE},
372 {16800000, 0x03, 0x41, 0x0A, 0xA4},
375 static struct tegra_clk_pll_freq_table pll_c_freq_table[] = {
376 { 12000000, 1040000000, 520, 6, 0, 8},
377 { 13000000, 1040000000, 480, 6, 0, 8},
378 { 16800000, 1040000000, 495, 8, 0, 8}, /* actual: 1039.5 MHz */
379 { 19200000, 1040000000, 325, 6, 0, 6},
380 { 26000000, 1040000000, 520, 13, 0, 8},
382 { 12000000, 832000000, 416, 6, 0, 8},
383 { 13000000, 832000000, 832, 13, 0, 8},
384 { 16800000, 832000000, 396, 8, 0, 8}, /* actual: 831.6 MHz */
385 { 19200000, 832000000, 260, 6, 0, 8},
386 { 26000000, 832000000, 416, 13, 0, 8},
388 { 12000000, 624000000, 624, 12, 0, 8},
389 { 13000000, 624000000, 624, 13, 0, 8},
390 { 16800000, 600000000, 520, 14, 0, 8},
391 { 19200000, 624000000, 520, 16, 0, 8},
392 { 26000000, 624000000, 624, 26, 0, 8},
394 { 12000000, 600000000, 600, 12, 0, 8},
395 { 13000000, 600000000, 600, 13, 0, 8},
396 { 16800000, 600000000, 500, 14, 0, 8},
397 { 19200000, 600000000, 375, 12, 0, 6},
398 { 26000000, 600000000, 600, 26, 0, 8},
400 { 12000000, 520000000, 520, 12, 0, 8},
401 { 13000000, 520000000, 520, 13, 0, 8},
402 { 16800000, 520000000, 495, 16, 0, 8}, /* actual: 519.75 MHz */
403 { 19200000, 520000000, 325, 12, 0, 6},
404 { 26000000, 520000000, 520, 26, 0, 8},
406 { 12000000, 416000000, 416, 12, 0, 8},
407 { 13000000, 416000000, 416, 13, 0, 8},
408 { 16800000, 416000000, 396, 16, 0, 8}, /* actual: 415.8 MHz */
409 { 19200000, 416000000, 260, 12, 0, 6},
410 { 26000000, 416000000, 416, 26, 0, 8},
411 { 0, 0, 0, 0, 0, 0 },
414 static struct tegra_clk_pll_freq_table pll_m_freq_table[] = {
415 { 12000000, 666000000, 666, 12, 0, 8},
416 { 13000000, 666000000, 666, 13, 0, 8},
417 { 16800000, 666000000, 555, 14, 0, 8},
418 { 19200000, 666000000, 555, 16, 0, 8},
419 { 26000000, 666000000, 666, 26, 0, 8},
420 { 12000000, 600000000, 600, 12, 0, 8},
421 { 13000000, 600000000, 600, 13, 0, 8},
422 { 16800000, 600000000, 500, 14, 0, 8},
423 { 19200000, 600000000, 375, 12, 0, 6},
424 { 26000000, 600000000, 600, 26, 0, 8},
425 { 0, 0, 0, 0, 0, 0 },
428 static struct tegra_clk_pll_freq_table pll_p_freq_table[] = {
429 { 12000000, 216000000, 432, 12, 1, 8},
430 { 13000000, 216000000, 432, 13, 1, 8},
431 { 16800000, 216000000, 360, 14, 1, 8},
432 { 19200000, 216000000, 360, 16, 1, 8},
433 { 26000000, 216000000, 432, 26, 1, 8},
434 { 0, 0, 0, 0, 0, 0 },
437 static struct tegra_clk_pll_freq_table pll_a_freq_table[] = {
438 { 9600000, 564480000, 294, 5, 0, 4},
439 { 9600000, 552960000, 288, 5, 0, 4},
440 { 9600000, 24000000, 5, 2, 0, 1},
442 { 28800000, 56448000, 49, 25, 0, 1},
443 { 28800000, 73728000, 64, 25, 0, 1},
444 { 28800000, 24000000, 5, 6, 0, 1},
445 { 0, 0, 0, 0, 0, 0 },
448 static struct tegra_clk_pll_freq_table pll_d_freq_table[] = {
449 { 12000000, 216000000, 216, 12, 0, 4},
450 { 13000000, 216000000, 216, 13, 0, 4},
451 { 16800000, 216000000, 180, 14, 0, 4},
452 { 19200000, 216000000, 180, 16, 0, 4},
453 { 26000000, 216000000, 216, 26, 0, 4},
455 { 12000000, 594000000, 594, 12, 0, 8},
456 { 13000000, 594000000, 594, 13, 0, 8},
457 { 16800000, 594000000, 495, 14, 0, 8},
458 { 19200000, 594000000, 495, 16, 0, 8},
459 { 26000000, 594000000, 594, 26, 0, 8},
461 { 12000000, 1000000000, 1000, 12, 0, 12},
462 { 13000000, 1000000000, 1000, 13, 0, 12},
463 { 19200000, 1000000000, 625, 12, 0, 8},
464 { 26000000, 1000000000, 1000, 26, 0, 12},
466 { 0, 0, 0, 0, 0, 0 },
469 static struct pdiv_map pllu_p[] = {
470 { .pdiv = 1, .hw_val = 1 },
471 { .pdiv = 2, .hw_val = 0 },
472 { .pdiv = 0, .hw_val = 0 },
475 static struct tegra_clk_pll_freq_table pll_u_freq_table[] = {
476 { 12000000, 480000000, 960, 12, 0, 12},
477 { 13000000, 480000000, 960, 13, 0, 12},
478 { 16800000, 480000000, 400, 7, 0, 5},
479 { 19200000, 480000000, 200, 4, 0, 3},
480 { 26000000, 480000000, 960, 26, 0, 12},
481 { 0, 0, 0, 0, 0, 0 },
484 static struct tegra_clk_pll_freq_table pll_x_freq_table[] = {
486 { 12000000, 1700000000, 850, 6, 0, 8},
487 { 13000000, 1700000000, 915, 7, 0, 8}, /* actual: 1699.2 MHz */
488 { 16800000, 1700000000, 708, 7, 0, 8}, /* actual: 1699.2 MHz */
489 { 19200000, 1700000000, 885, 10, 0, 8}, /* actual: 1699.2 MHz */
490 { 26000000, 1700000000, 850, 13, 0, 8},
493 { 12000000, 1600000000, 800, 6, 0, 8},
494 { 13000000, 1600000000, 738, 6, 0, 8}, /* actual: 1599.0 MHz */
495 { 16800000, 1600000000, 857, 9, 0, 8}, /* actual: 1599.7 MHz */
496 { 19200000, 1600000000, 500, 6, 0, 8},
497 { 26000000, 1600000000, 800, 13, 0, 8},
500 { 12000000, 1500000000, 750, 6, 0, 8},
501 { 13000000, 1500000000, 923, 8, 0, 8}, /* actual: 1499.8 MHz */
502 { 16800000, 1500000000, 625, 7, 0, 8},
503 { 19200000, 1500000000, 625, 8, 0, 8},
504 { 26000000, 1500000000, 750, 13, 0, 8},
507 { 12000000, 1400000000, 700, 6, 0, 8},
508 { 13000000, 1400000000, 969, 9, 0, 8}, /* actual: 1399.7 MHz */
509 { 16800000, 1400000000, 1000, 12, 0, 8},
510 { 19200000, 1400000000, 875, 12, 0, 8},
511 { 26000000, 1400000000, 700, 13, 0, 8},
514 { 12000000, 1300000000, 975, 9, 0, 8},
515 { 13000000, 1300000000, 1000, 10, 0, 8},
516 { 16800000, 1300000000, 928, 12, 0, 8}, /* actual: 1299.2 MHz */
517 { 19200000, 1300000000, 812, 12, 0, 8}, /* actual: 1299.2 MHz */
518 { 26000000, 1300000000, 650, 13, 0, 8},
521 { 12000000, 1200000000, 1000, 10, 0, 8},
522 { 13000000, 1200000000, 923, 10, 0, 8}, /* actual: 1199.9 MHz */
523 { 16800000, 1200000000, 1000, 14, 0, 8},
524 { 19200000, 1200000000, 1000, 16, 0, 8},
525 { 26000000, 1200000000, 600, 13, 0, 8},
528 { 12000000, 1100000000, 825, 9, 0, 8},
529 { 13000000, 1100000000, 846, 10, 0, 8}, /* actual: 1099.8 MHz */
530 { 16800000, 1100000000, 982, 15, 0, 8}, /* actual: 1099.8 MHz */
531 { 19200000, 1100000000, 859, 15, 0, 8}, /* actual: 1099.5 MHz */
532 { 26000000, 1100000000, 550, 13, 0, 8},
535 { 12000000, 1000000000, 1000, 12, 0, 8},
536 { 13000000, 1000000000, 1000, 13, 0, 8},
537 { 16800000, 1000000000, 833, 14, 0, 8}, /* actual: 999.6 MHz */
538 { 19200000, 1000000000, 625, 12, 0, 8},
539 { 26000000, 1000000000, 1000, 26, 0, 8},
541 { 0, 0, 0, 0, 0, 0 },
544 static struct tegra_clk_pll_freq_table pll_e_freq_table[] = {
545 /* PLLE special case: use cpcon field to store cml divider value */
546 { 12000000, 100000000, 150, 1, 18, 11},
547 { 216000000, 100000000, 200, 18, 24, 13},
548 { 0, 0, 0, 0, 0, 0 },
552 static struct tegra_clk_pll_params pll_c_params = {
553 .input_min = 2000000,
554 .input_max = 31000000,
558 .vco_max = 1400000000,
559 .base_reg = PLLC_BASE,
560 .misc_reg = PLLC_MISC,
561 .lock_mask = PLL_BASE_LOCK,
562 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
566 static struct tegra_clk_pll_params pll_m_params = {
567 .input_min = 2000000,
568 .input_max = 31000000,
572 .vco_max = 1200000000,
573 .base_reg = PLLM_BASE,
574 .misc_reg = PLLM_MISC,
575 .lock_mask = PLL_BASE_LOCK,
576 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
580 static struct tegra_clk_pll_params pll_p_params = {
581 .input_min = 2000000,
582 .input_max = 31000000,
586 .vco_max = 1400000000,
587 .base_reg = PLLP_BASE,
588 .misc_reg = PLLP_MISC,
589 .lock_mask = PLL_BASE_LOCK,
590 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
594 static struct tegra_clk_pll_params pll_a_params = {
595 .input_min = 2000000,
596 .input_max = 31000000,
600 .vco_max = 1400000000,
601 .base_reg = PLLA_BASE,
602 .misc_reg = PLLA_MISC,
603 .lock_mask = PLL_BASE_LOCK,
604 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
608 static struct tegra_clk_pll_params pll_d_params = {
609 .input_min = 2000000,
610 .input_max = 40000000,
614 .vco_max = 1000000000,
615 .base_reg = PLLD_BASE,
616 .misc_reg = PLLD_MISC,
617 .lock_mask = PLL_BASE_LOCK,
618 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
622 static struct tegra_clk_pll_params pll_d2_params = {
623 .input_min = 2000000,
624 .input_max = 40000000,
628 .vco_max = 1000000000,
629 .base_reg = PLLD2_BASE,
630 .misc_reg = PLLD2_MISC,
631 .lock_mask = PLL_BASE_LOCK,
632 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
636 static struct tegra_clk_pll_params pll_u_params = {
637 .input_min = 2000000,
638 .input_max = 40000000,
642 .vco_max = 960000000,
643 .base_reg = PLLU_BASE,
644 .misc_reg = PLLU_MISC,
645 .lock_mask = PLL_BASE_LOCK,
646 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
651 static struct tegra_clk_pll_params pll_x_params = {
652 .input_min = 2000000,
653 .input_max = 31000000,
657 .vco_max = 1700000000,
658 .base_reg = PLLX_BASE,
659 .misc_reg = PLLX_MISC,
660 .lock_mask = PLL_BASE_LOCK,
661 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
665 static struct tegra_clk_pll_params pll_e_params = {
666 .input_min = 12000000,
667 .input_max = 216000000,
670 .vco_min = 1200000000,
671 .vco_max = 2400000000U,
672 .base_reg = PLLE_BASE,
673 .misc_reg = PLLE_MISC,
674 .lock_mask = PLLE_MISC_LOCK,
675 .lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE,
679 /* Peripheral clock registers */
680 static struct tegra_clk_periph_regs periph_l_regs = {
681 .enb_reg = CLK_OUT_ENB_L,
682 .enb_set_reg = CLK_OUT_ENB_SET_L,
683 .enb_clr_reg = CLK_OUT_ENB_CLR_L,
684 .rst_reg = RST_DEVICES_L,
685 .rst_set_reg = RST_DEVICES_SET_L,
686 .rst_clr_reg = RST_DEVICES_CLR_L,
689 static struct tegra_clk_periph_regs periph_h_regs = {
690 .enb_reg = CLK_OUT_ENB_H,
691 .enb_set_reg = CLK_OUT_ENB_SET_H,
692 .enb_clr_reg = CLK_OUT_ENB_CLR_H,
693 .rst_reg = RST_DEVICES_H,
694 .rst_set_reg = RST_DEVICES_SET_H,
695 .rst_clr_reg = RST_DEVICES_CLR_H,
698 static struct tegra_clk_periph_regs periph_u_regs = {
699 .enb_reg = CLK_OUT_ENB_U,
700 .enb_set_reg = CLK_OUT_ENB_SET_U,
701 .enb_clr_reg = CLK_OUT_ENB_CLR_U,
702 .rst_reg = RST_DEVICES_U,
703 .rst_set_reg = RST_DEVICES_SET_U,
704 .rst_clr_reg = RST_DEVICES_CLR_U,
707 static struct tegra_clk_periph_regs periph_v_regs = {
708 .enb_reg = CLK_OUT_ENB_V,
709 .enb_set_reg = CLK_OUT_ENB_SET_V,
710 .enb_clr_reg = CLK_OUT_ENB_CLR_V,
711 .rst_reg = RST_DEVICES_V,
712 .rst_set_reg = RST_DEVICES_SET_V,
713 .rst_clr_reg = RST_DEVICES_CLR_V,
716 static struct tegra_clk_periph_regs periph_w_regs = {
717 .enb_reg = CLK_OUT_ENB_W,
718 .enb_set_reg = CLK_OUT_ENB_SET_W,
719 .enb_clr_reg = CLK_OUT_ENB_CLR_W,
720 .rst_reg = RST_DEVICES_W,
721 .rst_set_reg = RST_DEVICES_SET_W,
722 .rst_clr_reg = RST_DEVICES_CLR_W,
725 static void tegra30_clk_measure_input_freq(void)
727 u32 osc_ctrl = readl_relaxed(clk_base + OSC_CTRL);
728 u32 auto_clk_control = osc_ctrl & OSC_CTRL_OSC_FREQ_MASK;
729 u32 pll_ref_div = osc_ctrl & OSC_CTRL_PLL_REF_DIV_MASK;
731 switch (auto_clk_control) {
732 case OSC_CTRL_OSC_FREQ_12MHZ:
733 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
734 input_freq = 12000000;
736 case OSC_CTRL_OSC_FREQ_13MHZ:
737 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
738 input_freq = 13000000;
740 case OSC_CTRL_OSC_FREQ_19_2MHZ:
741 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
742 input_freq = 19200000;
744 case OSC_CTRL_OSC_FREQ_26MHZ:
745 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
746 input_freq = 26000000;
748 case OSC_CTRL_OSC_FREQ_16_8MHZ:
749 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
750 input_freq = 16800000;
752 case OSC_CTRL_OSC_FREQ_38_4MHZ:
753 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_2);
754 input_freq = 38400000;
756 case OSC_CTRL_OSC_FREQ_48MHZ:
757 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_4);
758 input_freq = 48000000;
761 pr_err("Unexpected auto clock control value %d",
768 static unsigned int tegra30_get_pll_ref_div(void)
770 u32 pll_ref_div = readl_relaxed(clk_base + OSC_CTRL) &
771 OSC_CTRL_PLL_REF_DIV_MASK;
773 switch (pll_ref_div) {
774 case OSC_CTRL_PLL_REF_DIV_1:
776 case OSC_CTRL_PLL_REF_DIV_2:
778 case OSC_CTRL_PLL_REF_DIV_4:
781 pr_err("Invalid pll ref divider %d", pll_ref_div);
787 static void tegra30_utmi_param_configure(void)
792 for (i = 0; i < ARRAY_SIZE(utmi_parameters); i++) {
793 if (input_freq == utmi_parameters[i].osc_frequency)
797 if (i >= ARRAY_SIZE(utmi_parameters)) {
798 pr_err("%s: Unexpected input rate %lu\n", __func__, input_freq);
802 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG2);
804 /* Program UTMIP PLL stable and active counts */
805 reg &= ~UTMIP_PLL_CFG2_STABLE_COUNT(~0);
806 reg |= UTMIP_PLL_CFG2_STABLE_COUNT(
807 utmi_parameters[i].stable_count);
809 reg &= ~UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(~0);
811 reg |= UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(
812 utmi_parameters[i].active_delay_count);
814 /* Remove power downs from UTMIP PLL control bits */
815 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN;
816 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN;
817 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN;
819 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG2);
821 /* Program UTMIP PLL delay and oscillator frequency counts */
822 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1);
823 reg &= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0);
825 reg |= UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(
826 utmi_parameters[i].enable_delay_count);
828 reg &= ~UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(~0);
829 reg |= UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(
830 utmi_parameters[i].xtal_freq_count);
832 /* Remove power downs from UTMIP PLL control bits */
833 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
834 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN;
835 reg &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN;
837 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1);
840 static const char *pll_e_parents[] = {"pll_ref", "pll_p"};
842 static void __init tegra30_pll_init(void)
847 clk = tegra_clk_register_pll("pll_c", "pll_ref", clk_base, pmc_base, 0,
849 TEGRA_PLL_HAS_CPCON | TEGRA_PLL_USE_LOCK,
850 pll_c_freq_table, NULL);
851 clk_register_clkdev(clk, "pll_c", NULL);
855 clk = tegra_clk_register_divider("pll_c_out1_div", "pll_c",
856 clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
858 clk = tegra_clk_register_pll_out("pll_c_out1", "pll_c_out1_div",
859 clk_base + PLLC_OUT, 1, 0, CLK_SET_RATE_PARENT,
861 clk_register_clkdev(clk, "pll_c_out1", NULL);
862 clks[pll_c_out1] = clk;
865 clk = tegra_clk_register_pll("pll_p", "pll_ref", clk_base, pmc_base, 0,
866 408000000, &pll_p_params,
867 TEGRA_PLL_FIXED | TEGRA_PLL_HAS_CPCON |
868 TEGRA_PLL_USE_LOCK, pll_p_freq_table, NULL);
869 clk_register_clkdev(clk, "pll_p", NULL);
873 clk = tegra_clk_register_divider("pll_p_out1_div", "pll_p",
874 clk_base + PLLP_OUTA, 0, TEGRA_DIVIDER_FIXED |
875 TEGRA_DIVIDER_ROUND_UP, 8, 8, 1,
877 clk = tegra_clk_register_pll_out("pll_p_out1", "pll_p_out1_div",
878 clk_base + PLLP_OUTA, 1, 0,
879 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0,
881 clk_register_clkdev(clk, "pll_p_out1", NULL);
882 clks[pll_p_out1] = clk;
885 clk = tegra_clk_register_divider("pll_p_out2_div", "pll_p",
886 clk_base + PLLP_OUTA, 0, TEGRA_DIVIDER_FIXED |
887 TEGRA_DIVIDER_ROUND_UP, 24, 8, 1,
889 clk = tegra_clk_register_pll_out("pll_p_out2", "pll_p_out2_div",
890 clk_base + PLLP_OUTA, 17, 16,
891 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0,
893 clk_register_clkdev(clk, "pll_p_out2", NULL);
894 clks[pll_p_out2] = clk;
897 clk = tegra_clk_register_divider("pll_p_out3_div", "pll_p",
898 clk_base + PLLP_OUTB, 0, TEGRA_DIVIDER_FIXED |
899 TEGRA_DIVIDER_ROUND_UP, 8, 8, 1,
901 clk = tegra_clk_register_pll_out("pll_p_out3", "pll_p_out3_div",
902 clk_base + PLLP_OUTB, 1, 0,
903 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0,
905 clk_register_clkdev(clk, "pll_p_out3", NULL);
906 clks[pll_p_out3] = clk;
909 clk = tegra_clk_register_divider("pll_p_out4_div", "pll_p",
910 clk_base + PLLP_OUTB, 0, TEGRA_DIVIDER_FIXED |
911 TEGRA_DIVIDER_ROUND_UP, 24, 8, 1,
913 clk = tegra_clk_register_pll_out("pll_p_out4", "pll_p_out4_div",
914 clk_base + PLLP_OUTB, 17, 16,
915 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0,
917 clk_register_clkdev(clk, "pll_p_out4", NULL);
918 clks[pll_p_out4] = clk;
921 clk = tegra_clk_register_pll("pll_m", "pll_ref", clk_base, pmc_base,
922 CLK_IGNORE_UNUSED | CLK_SET_RATE_GATE, 0,
923 &pll_m_params, TEGRA_PLLM | TEGRA_PLL_HAS_CPCON |
924 TEGRA_PLL_SET_DCCON | TEGRA_PLL_USE_LOCK,
925 pll_m_freq_table, NULL);
926 clk_register_clkdev(clk, "pll_m", NULL);
930 clk = tegra_clk_register_divider("pll_m_out1_div", "pll_m",
931 clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
933 clk = tegra_clk_register_pll_out("pll_m_out1", "pll_m_out1_div",
934 clk_base + PLLM_OUT, 1, 0, CLK_IGNORE_UNUSED |
935 CLK_SET_RATE_PARENT, 0, NULL);
936 clk_register_clkdev(clk, "pll_m_out1", NULL);
937 clks[pll_m_out1] = clk;
940 clk = tegra_clk_register_pll("pll_x", "pll_ref", clk_base, pmc_base, 0,
941 0, &pll_x_params, TEGRA_PLL_HAS_CPCON |
942 TEGRA_PLL_SET_DCCON | TEGRA_PLL_USE_LOCK,
943 pll_x_freq_table, NULL);
944 clk_register_clkdev(clk, "pll_x", NULL);
948 clk = clk_register_fixed_factor(NULL, "pll_x_out0", "pll_x",
949 CLK_SET_RATE_PARENT, 1, 2);
950 clk_register_clkdev(clk, "pll_x_out0", NULL);
951 clks[pll_x_out0] = clk;
954 clk = tegra_clk_register_pll("pll_u", "pll_ref", clk_base, pmc_base, 0,
955 0, &pll_u_params, TEGRA_PLLU | TEGRA_PLL_HAS_CPCON |
956 TEGRA_PLL_SET_LFCON | TEGRA_PLL_USE_LOCK,
959 clk_register_clkdev(clk, "pll_u", NULL);
962 tegra30_utmi_param_configure();
965 clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, pmc_base, 0,
966 0, &pll_d_params, TEGRA_PLL_HAS_CPCON |
967 TEGRA_PLL_SET_LFCON | TEGRA_PLL_USE_LOCK,
968 pll_d_freq_table, &pll_d_lock);
969 clk_register_clkdev(clk, "pll_d", NULL);
973 clk = clk_register_fixed_factor(NULL, "pll_d_out0", "pll_d",
974 CLK_SET_RATE_PARENT, 1, 2);
975 clk_register_clkdev(clk, "pll_d_out0", NULL);
976 clks[pll_d_out0] = clk;
979 clk = tegra_clk_register_pll("pll_d2", "pll_ref", clk_base, pmc_base, 0,
980 0, &pll_d2_params, TEGRA_PLL_HAS_CPCON |
981 TEGRA_PLL_SET_LFCON | TEGRA_PLL_USE_LOCK,
982 pll_d_freq_table, NULL);
983 clk_register_clkdev(clk, "pll_d2", NULL);
987 clk = clk_register_fixed_factor(NULL, "pll_d2_out0", "pll_d2",
988 CLK_SET_RATE_PARENT, 1, 2);
989 clk_register_clkdev(clk, "pll_d2_out0", NULL);
990 clks[pll_d2_out0] = clk;
993 clk = tegra_clk_register_pll("pll_a", "pll_p_out1", clk_base, pmc_base,
994 0, 0, &pll_a_params, TEGRA_PLL_HAS_CPCON |
995 TEGRA_PLL_USE_LOCK, pll_a_freq_table, NULL);
996 clk_register_clkdev(clk, "pll_a", NULL);
1000 clk = tegra_clk_register_divider("pll_a_out0_div", "pll_a",
1001 clk_base + PLLA_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
1003 clk = tegra_clk_register_pll_out("pll_a_out0", "pll_a_out0_div",
1004 clk_base + PLLA_OUT, 1, 0, CLK_IGNORE_UNUSED |
1005 CLK_SET_RATE_PARENT, 0, NULL);
1006 clk_register_clkdev(clk, "pll_a_out0", NULL);
1007 clks[pll_a_out0] = clk;
1010 clk = clk_register_mux(NULL, "pll_e_mux", pll_e_parents,
1011 ARRAY_SIZE(pll_e_parents), 0,
1012 clk_base + PLLE_AUX, 2, 1, 0, NULL);
1013 clk = tegra_clk_register_plle("pll_e", "pll_e_mux", clk_base, pmc_base,
1014 CLK_GET_RATE_NOCACHE, 100000000, &pll_e_params,
1015 TEGRA_PLLE_CONFIGURE, pll_e_freq_table, NULL);
1016 clk_register_clkdev(clk, "pll_e", NULL);
1020 static const char *mux_audio_sync_clk[] = { "spdif_in_sync", "i2s0_sync",
1021 "i2s1_sync", "i2s2_sync", "i2s3_sync", "i2s4_sync", "vimclk_sync",};
1022 static const char *clk_out1_parents[] = { "clk_m", "clk_m_div2",
1023 "clk_m_div4", "extern1", };
1024 static const char *clk_out2_parents[] = { "clk_m", "clk_m_div2",
1025 "clk_m_div4", "extern2", };
1026 static const char *clk_out3_parents[] = { "clk_m", "clk_m_div2",
1027 "clk_m_div4", "extern3", };
1029 static void __init tegra30_audio_clk_init(void)
1034 clk = tegra_clk_register_sync_source("spdif_in_sync", 24000000,
1036 clk_register_clkdev(clk, "spdif_in_sync", NULL);
1037 clks[spdif_in_sync] = clk;
1040 clk = tegra_clk_register_sync_source("i2s0_sync", 24000000, 24000000);
1041 clk_register_clkdev(clk, "i2s0_sync", NULL);
1042 clks[i2s0_sync] = clk;
1045 clk = tegra_clk_register_sync_source("i2s1_sync", 24000000, 24000000);
1046 clk_register_clkdev(clk, "i2s1_sync", NULL);
1047 clks[i2s1_sync] = clk;
1050 clk = tegra_clk_register_sync_source("i2s2_sync", 24000000, 24000000);
1051 clk_register_clkdev(clk, "i2s2_sync", NULL);
1052 clks[i2s2_sync] = clk;
1055 clk = tegra_clk_register_sync_source("i2s3_sync", 24000000, 24000000);
1056 clk_register_clkdev(clk, "i2s3_sync", NULL);
1057 clks[i2s3_sync] = clk;
1060 clk = tegra_clk_register_sync_source("i2s4_sync", 24000000, 24000000);
1061 clk_register_clkdev(clk, "i2s4_sync", NULL);
1062 clks[i2s4_sync] = clk;
1065 clk = tegra_clk_register_sync_source("vimclk_sync", 24000000, 24000000);
1066 clk_register_clkdev(clk, "vimclk_sync", NULL);
1067 clks[vimclk_sync] = clk;
1070 clk = clk_register_mux(NULL, "audio0_mux", mux_audio_sync_clk,
1071 ARRAY_SIZE(mux_audio_sync_clk), 0,
1072 clk_base + AUDIO_SYNC_CLK_I2S0, 0, 3, 0, NULL);
1073 clk = clk_register_gate(NULL, "audio0", "audio0_mux", 0,
1074 clk_base + AUDIO_SYNC_CLK_I2S0, 4,
1075 CLK_GATE_SET_TO_DISABLE, NULL);
1076 clk_register_clkdev(clk, "audio0", NULL);
1080 clk = clk_register_mux(NULL, "audio1_mux", mux_audio_sync_clk,
1081 ARRAY_SIZE(mux_audio_sync_clk), 0,
1082 clk_base + AUDIO_SYNC_CLK_I2S1, 0, 3, 0, NULL);
1083 clk = clk_register_gate(NULL, "audio1", "audio1_mux", 0,
1084 clk_base + AUDIO_SYNC_CLK_I2S1, 4,
1085 CLK_GATE_SET_TO_DISABLE, NULL);
1086 clk_register_clkdev(clk, "audio1", NULL);
1090 clk = clk_register_mux(NULL, "audio2_mux", mux_audio_sync_clk,
1091 ARRAY_SIZE(mux_audio_sync_clk), 0,
1092 clk_base + AUDIO_SYNC_CLK_I2S2, 0, 3, 0, NULL);
1093 clk = clk_register_gate(NULL, "audio2", "audio2_mux", 0,
1094 clk_base + AUDIO_SYNC_CLK_I2S2, 4,
1095 CLK_GATE_SET_TO_DISABLE, NULL);
1096 clk_register_clkdev(clk, "audio2", NULL);
1100 clk = clk_register_mux(NULL, "audio3_mux", mux_audio_sync_clk,
1101 ARRAY_SIZE(mux_audio_sync_clk), 0,
1102 clk_base + AUDIO_SYNC_CLK_I2S3, 0, 3, 0, NULL);
1103 clk = clk_register_gate(NULL, "audio3", "audio3_mux", 0,
1104 clk_base + AUDIO_SYNC_CLK_I2S3, 4,
1105 CLK_GATE_SET_TO_DISABLE, NULL);
1106 clk_register_clkdev(clk, "audio3", NULL);
1110 clk = clk_register_mux(NULL, "audio4_mux", mux_audio_sync_clk,
1111 ARRAY_SIZE(mux_audio_sync_clk), 0,
1112 clk_base + AUDIO_SYNC_CLK_I2S4, 0, 3, 0, NULL);
1113 clk = clk_register_gate(NULL, "audio4", "audio4_mux", 0,
1114 clk_base + AUDIO_SYNC_CLK_I2S4, 4,
1115 CLK_GATE_SET_TO_DISABLE, NULL);
1116 clk_register_clkdev(clk, "audio4", NULL);
1120 clk = clk_register_mux(NULL, "spdif_mux", mux_audio_sync_clk,
1121 ARRAY_SIZE(mux_audio_sync_clk), 0,
1122 clk_base + AUDIO_SYNC_CLK_SPDIF, 0, 3, 0, NULL);
1123 clk = clk_register_gate(NULL, "spdif", "spdif_mux", 0,
1124 clk_base + AUDIO_SYNC_CLK_SPDIF, 4,
1125 CLK_GATE_SET_TO_DISABLE, NULL);
1126 clk_register_clkdev(clk, "spdif", NULL);
1130 clk = clk_register_fixed_factor(NULL, "audio0_doubler", "audio0",
1131 CLK_SET_RATE_PARENT, 2, 1);
1132 clk = tegra_clk_register_divider("audio0_div", "audio0_doubler",
1133 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 24, 1, 0,
1135 clk = tegra_clk_register_periph_gate("audio0_2x", "audio0_div",
1136 TEGRA_PERIPH_NO_RESET, clk_base,
1137 CLK_SET_RATE_PARENT, 113, &periph_v_regs,
1138 periph_clk_enb_refcnt);
1139 clk_register_clkdev(clk, "audio0_2x", NULL);
1140 clks[audio0_2x] = clk;
1143 clk = clk_register_fixed_factor(NULL, "audio1_doubler", "audio1",
1144 CLK_SET_RATE_PARENT, 2, 1);
1145 clk = tegra_clk_register_divider("audio1_div", "audio1_doubler",
1146 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 25, 1, 0,
1148 clk = tegra_clk_register_periph_gate("audio1_2x", "audio1_div",
1149 TEGRA_PERIPH_NO_RESET, clk_base,
1150 CLK_SET_RATE_PARENT, 114, &periph_v_regs,
1151 periph_clk_enb_refcnt);
1152 clk_register_clkdev(clk, "audio1_2x", NULL);
1153 clks[audio1_2x] = clk;
1156 clk = clk_register_fixed_factor(NULL, "audio2_doubler", "audio2",
1157 CLK_SET_RATE_PARENT, 2, 1);
1158 clk = tegra_clk_register_divider("audio2_div", "audio2_doubler",
1159 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 26, 1, 0,
1161 clk = tegra_clk_register_periph_gate("audio2_2x", "audio2_div",
1162 TEGRA_PERIPH_NO_RESET, clk_base,
1163 CLK_SET_RATE_PARENT, 115, &periph_v_regs,
1164 periph_clk_enb_refcnt);
1165 clk_register_clkdev(clk, "audio2_2x", NULL);
1166 clks[audio2_2x] = clk;
1169 clk = clk_register_fixed_factor(NULL, "audio3_doubler", "audio3",
1170 CLK_SET_RATE_PARENT, 2, 1);
1171 clk = tegra_clk_register_divider("audio3_div", "audio3_doubler",
1172 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 27, 1, 0,
1174 clk = tegra_clk_register_periph_gate("audio3_2x", "audio3_div",
1175 TEGRA_PERIPH_NO_RESET, clk_base,
1176 CLK_SET_RATE_PARENT, 116, &periph_v_regs,
1177 periph_clk_enb_refcnt);
1178 clk_register_clkdev(clk, "audio3_2x", NULL);
1179 clks[audio3_2x] = clk;
1182 clk = clk_register_fixed_factor(NULL, "audio4_doubler", "audio4",
1183 CLK_SET_RATE_PARENT, 2, 1);
1184 clk = tegra_clk_register_divider("audio4_div", "audio4_doubler",
1185 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 28, 1, 0,
1187 clk = tegra_clk_register_periph_gate("audio4_2x", "audio4_div",
1188 TEGRA_PERIPH_NO_RESET, clk_base,
1189 CLK_SET_RATE_PARENT, 117, &periph_v_regs,
1190 periph_clk_enb_refcnt);
1191 clk_register_clkdev(clk, "audio4_2x", NULL);
1192 clks[audio4_2x] = clk;
1195 clk = clk_register_fixed_factor(NULL, "spdif_doubler", "spdif",
1196 CLK_SET_RATE_PARENT, 2, 1);
1197 clk = tegra_clk_register_divider("spdif_div", "spdif_doubler",
1198 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 29, 1, 0,
1200 clk = tegra_clk_register_periph_gate("spdif_2x", "spdif_div",
1201 TEGRA_PERIPH_NO_RESET, clk_base,
1202 CLK_SET_RATE_PARENT, 118, &periph_v_regs,
1203 periph_clk_enb_refcnt);
1204 clk_register_clkdev(clk, "spdif_2x", NULL);
1205 clks[spdif_2x] = clk;
1208 static void __init tegra30_pmc_clk_init(void)
1213 clk = clk_register_mux(NULL, "clk_out_1_mux", clk_out1_parents,
1214 ARRAY_SIZE(clk_out1_parents), 0,
1215 pmc_base + PMC_CLK_OUT_CNTRL, 6, 3, 0,
1217 clks[clk_out_1_mux] = clk;
1218 clk = clk_register_gate(NULL, "clk_out_1", "clk_out_1_mux", 0,
1219 pmc_base + PMC_CLK_OUT_CNTRL, 2, 0,
1221 clk_register_clkdev(clk, "extern1", "clk_out_1");
1222 clks[clk_out_1] = clk;
1225 clk = clk_register_mux(NULL, "clk_out_2_mux", clk_out2_parents,
1226 ARRAY_SIZE(clk_out1_parents), 0,
1227 pmc_base + PMC_CLK_OUT_CNTRL, 14, 3, 0,
1229 clk = clk_register_gate(NULL, "clk_out_2", "clk_out_2_mux", 0,
1230 pmc_base + PMC_CLK_OUT_CNTRL, 10, 0,
1232 clk_register_clkdev(clk, "extern2", "clk_out_2");
1233 clks[clk_out_2] = clk;
1236 clk = clk_register_mux(NULL, "clk_out_3_mux", clk_out3_parents,
1237 ARRAY_SIZE(clk_out1_parents), 0,
1238 pmc_base + PMC_CLK_OUT_CNTRL, 22, 3, 0,
1240 clk = clk_register_gate(NULL, "clk_out_3", "clk_out_3_mux", 0,
1241 pmc_base + PMC_CLK_OUT_CNTRL, 18, 0,
1243 clk_register_clkdev(clk, "extern3", "clk_out_3");
1244 clks[clk_out_3] = clk;
1247 writel_relaxed(0, pmc_base + PMC_BLINK_TIMER);
1248 clk = clk_register_gate(NULL, "blink_override", "clk_32k", 0,
1249 pmc_base + PMC_DPD_PADS_ORIDE,
1250 PMC_DPD_PADS_ORIDE_BLINK_ENB, 0, NULL);
1251 clk = clk_register_gate(NULL, "blink", "blink_override", 0,
1252 pmc_base + PMC_CTRL,
1253 PMC_CTRL_BLINK_ENB, 0, NULL);
1254 clk_register_clkdev(clk, "blink", NULL);
1259 static const char *cclk_g_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m",
1260 "pll_p_cclkg", "pll_p_out4_cclkg",
1261 "pll_p_out3_cclkg", "unused", "pll_x" };
1262 static const char *cclk_lp_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m",
1263 "pll_p_cclklp", "pll_p_out4_cclklp",
1264 "pll_p_out3_cclklp", "unused", "pll_x",
1266 static const char *sclk_parents[] = { "clk_m", "pll_c_out1", "pll_p_out4",
1267 "pll_p_out3", "pll_p_out2", "unused",
1268 "clk_32k", "pll_m_out1" };
1270 static void __init tegra30_super_clk_init(void)
1275 * Clock input to cclk_g divided from pll_p using
1276 * U71 divider of cclk_g.
1278 clk = tegra_clk_register_divider("pll_p_cclkg", "pll_p",
1279 clk_base + SUPER_CCLKG_DIVIDER, 0,
1280 TEGRA_DIVIDER_INT, 16, 8, 1, NULL);
1281 clk_register_clkdev(clk, "pll_p_cclkg", NULL);
1284 * Clock input to cclk_g divided from pll_p_out3 using
1285 * U71 divider of cclk_g.
1287 clk = tegra_clk_register_divider("pll_p_out3_cclkg", "pll_p_out3",
1288 clk_base + SUPER_CCLKG_DIVIDER, 0,
1289 TEGRA_DIVIDER_INT, 16, 8, 1, NULL);
1290 clk_register_clkdev(clk, "pll_p_out3_cclkg", NULL);
1293 * Clock input to cclk_g divided from pll_p_out4 using
1294 * U71 divider of cclk_g.
1296 clk = tegra_clk_register_divider("pll_p_out4_cclkg", "pll_p_out4",
1297 clk_base + SUPER_CCLKG_DIVIDER, 0,
1298 TEGRA_DIVIDER_INT, 16, 8, 1, NULL);
1299 clk_register_clkdev(clk, "pll_p_out4_cclkg", NULL);
1302 clk = tegra_clk_register_super_mux("cclk_g", cclk_g_parents,
1303 ARRAY_SIZE(cclk_g_parents),
1304 CLK_SET_RATE_PARENT,
1305 clk_base + CCLKG_BURST_POLICY,
1307 clk_register_clkdev(clk, "cclk_g", NULL);
1311 * Clock input to cclk_lp divided from pll_p using
1312 * U71 divider of cclk_lp.
1314 clk = tegra_clk_register_divider("pll_p_cclklp", "pll_p",
1315 clk_base + SUPER_CCLKLP_DIVIDER, 0,
1316 TEGRA_DIVIDER_INT, 16, 8, 1, NULL);
1317 clk_register_clkdev(clk, "pll_p_cclklp", NULL);
1320 * Clock input to cclk_lp divided from pll_p_out3 using
1321 * U71 divider of cclk_lp.
1323 clk = tegra_clk_register_divider("pll_p_out3_cclklp", "pll_p_out3",
1324 clk_base + SUPER_CCLKG_DIVIDER, 0,
1325 TEGRA_DIVIDER_INT, 16, 8, 1, NULL);
1326 clk_register_clkdev(clk, "pll_p_out3_cclklp", NULL);
1329 * Clock input to cclk_lp divided from pll_p_out4 using
1330 * U71 divider of cclk_lp.
1332 clk = tegra_clk_register_divider("pll_p_out4_cclklp", "pll_p_out4",
1333 clk_base + SUPER_CCLKLP_DIVIDER, 0,
1334 TEGRA_DIVIDER_INT, 16, 8, 1, NULL);
1335 clk_register_clkdev(clk, "pll_p_out4_cclklp", NULL);
1338 clk = tegra_clk_register_super_mux("cclk_lp", cclk_lp_parents,
1339 ARRAY_SIZE(cclk_lp_parents),
1340 CLK_SET_RATE_PARENT,
1341 clk_base + CCLKLP_BURST_POLICY,
1342 TEGRA_DIVIDER_2, 4, 8, 9,
1344 clk_register_clkdev(clk, "cclk_lp", NULL);
1345 clks[cclk_lp] = clk;
1348 clk = tegra_clk_register_super_mux("sclk", sclk_parents,
1349 ARRAY_SIZE(sclk_parents),
1350 CLK_SET_RATE_PARENT,
1351 clk_base + SCLK_BURST_POLICY,
1353 clk_register_clkdev(clk, "sclk", NULL);
1357 clk = clk_register_divider(NULL, "hclk_div", "sclk", 0,
1358 clk_base + SYSTEM_CLK_RATE, 4, 2, 0,
1360 clk = clk_register_gate(NULL, "hclk", "hclk_div", CLK_SET_RATE_PARENT,
1361 clk_base + SYSTEM_CLK_RATE, 7,
1362 CLK_GATE_SET_TO_DISABLE, &sysrate_lock);
1363 clk_register_clkdev(clk, "hclk", NULL);
1367 clk = clk_register_divider(NULL, "pclk_div", "hclk", 0,
1368 clk_base + SYSTEM_CLK_RATE, 0, 2, 0,
1370 clk = clk_register_gate(NULL, "pclk", "pclk_div", CLK_SET_RATE_PARENT,
1371 clk_base + SYSTEM_CLK_RATE, 3,
1372 CLK_GATE_SET_TO_DISABLE, &sysrate_lock);
1373 clk_register_clkdev(clk, "pclk", NULL);
1377 clk = clk_register_fixed_factor(NULL, "twd", "cclk_g",
1378 CLK_SET_RATE_PARENT, 1, 2);
1379 clk_register_clkdev(clk, "twd", NULL);
1383 static const char *mux_pllacp_clkm[] = { "pll_a_out0", "unused", "pll_p",
1385 static const char *mux_pllpcm_clkm[] = { "pll_p", "pll_c", "pll_m", "clk_m" };
1386 static const char *mux_pllmcp_clkm[] = { "pll_m", "pll_c", "pll_p", "clk_m" };
1387 static const char *i2s0_parents[] = { "pll_a_out0", "audio0_2x", "pll_p",
1389 static const char *i2s1_parents[] = { "pll_a_out0", "audio1_2x", "pll_p",
1391 static const char *i2s2_parents[] = { "pll_a_out0", "audio2_2x", "pll_p",
1393 static const char *i2s3_parents[] = { "pll_a_out0", "audio3_2x", "pll_p",
1395 static const char *i2s4_parents[] = { "pll_a_out0", "audio4_2x", "pll_p",
1397 static const char *spdif_out_parents[] = { "pll_a_out0", "spdif_2x", "pll_p",
1399 static const char *spdif_in_parents[] = { "pll_p", "pll_c", "pll_m" };
1400 static const char *mux_pllpc_clk32k_clkm[] = { "pll_p", "pll_c", "clk_32k",
1402 static const char *mux_pllpc_clkm_clk32k[] = { "pll_p", "pll_c", "clk_m",
1404 static const char *mux_pllmcpa[] = { "pll_m", "pll_c", "pll_p", "pll_a_out0" };
1405 static const char *mux_pllpdc_clkm[] = { "pll_p", "pll_d_out0", "pll_c",
1407 static const char *mux_pllp_clkm[] = { "pll_p", "unused", "unused", "clk_m" };
1408 static const char *mux_pllpmdacd2_clkm[] = { "pll_p", "pll_m", "pll_d_out0",
1409 "pll_a_out0", "pll_c",
1410 "pll_d2_out0", "clk_m" };
1411 static const char *mux_plla_clk32k_pllp_clkm_plle[] = { "pll_a_out0",
1414 static const char *mux_plld_out0_plld2_out0[] = { "pll_d_out0",
1417 static struct tegra_periph_init_data tegra_periph_clk_list[] = {
1418 TEGRA_INIT_DATA_MUX("i2s0", NULL, "tegra30-i2s.0", i2s0_parents, CLK_SOURCE_I2S0, 30, &periph_l_regs, TEGRA_PERIPH_ON_APB, i2s0),
1419 TEGRA_INIT_DATA_MUX("i2s1", NULL, "tegra30-i2s.1", i2s1_parents, CLK_SOURCE_I2S1, 11, &periph_l_regs, TEGRA_PERIPH_ON_APB, i2s1),
1420 TEGRA_INIT_DATA_MUX("i2s2", NULL, "tegra30-i2s.2", i2s2_parents, CLK_SOURCE_I2S2, 18, &periph_l_regs, TEGRA_PERIPH_ON_APB, i2s2),
1421 TEGRA_INIT_DATA_MUX("i2s3", NULL, "tegra30-i2s.3", i2s3_parents, CLK_SOURCE_I2S3, 101, &periph_v_regs, TEGRA_PERIPH_ON_APB, i2s3),
1422 TEGRA_INIT_DATA_MUX("i2s4", NULL, "tegra30-i2s.4", i2s4_parents, CLK_SOURCE_I2S4, 102, &periph_v_regs, TEGRA_PERIPH_ON_APB, i2s4),
1423 TEGRA_INIT_DATA_MUX("spdif_out", "spdif_out", "tegra30-spdif", spdif_out_parents, CLK_SOURCE_SPDIF_OUT, 10, &periph_l_regs, TEGRA_PERIPH_ON_APB, spdif_out),
1424 TEGRA_INIT_DATA_MUX("spdif_in", "spdif_in", "tegra30-spdif", spdif_in_parents, CLK_SOURCE_SPDIF_IN, 10, &periph_l_regs, TEGRA_PERIPH_ON_APB, spdif_in),
1425 TEGRA_INIT_DATA_MUX("d_audio", "d_audio", "tegra30-ahub", mux_pllacp_clkm, CLK_SOURCE_D_AUDIO, 106, &periph_v_regs, 0, d_audio),
1426 TEGRA_INIT_DATA_MUX("dam0", NULL, "tegra30-dam.0", mux_pllacp_clkm, CLK_SOURCE_DAM0, 108, &periph_v_regs, 0, dam0),
1427 TEGRA_INIT_DATA_MUX("dam1", NULL, "tegra30-dam.1", mux_pllacp_clkm, CLK_SOURCE_DAM1, 109, &periph_v_regs, 0, dam1),
1428 TEGRA_INIT_DATA_MUX("dam2", NULL, "tegra30-dam.2", mux_pllacp_clkm, CLK_SOURCE_DAM2, 110, &periph_v_regs, 0, dam2),
1429 TEGRA_INIT_DATA_MUX("hda", "hda", "tegra30-hda", mux_pllpcm_clkm, CLK_SOURCE_HDA, 125, &periph_v_regs, 0, hda),
1430 TEGRA_INIT_DATA_MUX("hda2codec_2x", "hda2codec", "tegra30-hda", mux_pllpcm_clkm, CLK_SOURCE_HDA2CODEC_2X, 111, &periph_v_regs, 0, hda2codec_2x),
1431 TEGRA_INIT_DATA_MUX("sbc1", NULL, "spi_tegra.0", mux_pllpcm_clkm, CLK_SOURCE_SBC1, 41, &periph_h_regs, TEGRA_PERIPH_ON_APB, sbc1),
1432 TEGRA_INIT_DATA_MUX("sbc2", NULL, "spi_tegra.1", mux_pllpcm_clkm, CLK_SOURCE_SBC2, 44, &periph_h_regs, TEGRA_PERIPH_ON_APB, sbc2),
1433 TEGRA_INIT_DATA_MUX("sbc3", NULL, "spi_tegra.2", mux_pllpcm_clkm, CLK_SOURCE_SBC3, 46, &periph_h_regs, TEGRA_PERIPH_ON_APB, sbc3),
1434 TEGRA_INIT_DATA_MUX("sbc4", NULL, "spi_tegra.3", mux_pllpcm_clkm, CLK_SOURCE_SBC4, 68, &periph_u_regs, TEGRA_PERIPH_ON_APB, sbc4),
1435 TEGRA_INIT_DATA_MUX("sbc5", NULL, "spi_tegra.4", mux_pllpcm_clkm, CLK_SOURCE_SBC5, 104, &periph_v_regs, TEGRA_PERIPH_ON_APB, sbc5),
1436 TEGRA_INIT_DATA_MUX("sbc6", NULL, "spi_tegra.5", mux_pllpcm_clkm, CLK_SOURCE_SBC6, 105, &periph_v_regs, TEGRA_PERIPH_ON_APB, sbc6),
1437 TEGRA_INIT_DATA_MUX("sata_oob", NULL, "tegra_sata_oob", mux_pllpcm_clkm, CLK_SOURCE_SATA_OOB, 123, &periph_v_regs, TEGRA_PERIPH_ON_APB, sata_oob),
1438 TEGRA_INIT_DATA_MUX("sata", NULL, "tegra_sata", mux_pllpcm_clkm, CLK_SOURCE_SATA, 124, &periph_v_regs, TEGRA_PERIPH_ON_APB, sata),
1439 TEGRA_INIT_DATA_MUX("ndflash", NULL, "tegra_nand", mux_pllpcm_clkm, CLK_SOURCE_NDFLASH, 13, &periph_l_regs, TEGRA_PERIPH_ON_APB, ndflash),
1440 TEGRA_INIT_DATA_MUX("ndspeed", NULL, "tegra_nand_speed", mux_pllpcm_clkm, CLK_SOURCE_NDSPEED, 80, &periph_u_regs, TEGRA_PERIPH_ON_APB, ndspeed),
1441 TEGRA_INIT_DATA_MUX("vfir", NULL, "vfir", mux_pllpcm_clkm, CLK_SOURCE_VFIR, 7, &periph_l_regs, TEGRA_PERIPH_ON_APB, vfir),
1442 TEGRA_INIT_DATA_MUX("csite", NULL, "csite", mux_pllpcm_clkm, CLK_SOURCE_CSITE, 73, &periph_u_regs, TEGRA_PERIPH_ON_APB, csite),
1443 TEGRA_INIT_DATA_MUX("la", NULL, "la", mux_pllpcm_clkm, CLK_SOURCE_LA, 76, &periph_u_regs, TEGRA_PERIPH_ON_APB, la),
1444 TEGRA_INIT_DATA_MUX("owr", NULL, "tegra_w1", mux_pllpcm_clkm, CLK_SOURCE_OWR, 71, &periph_u_regs, TEGRA_PERIPH_ON_APB, owr),
1445 TEGRA_INIT_DATA_MUX("mipi", NULL, "mipi", mux_pllpcm_clkm, CLK_SOURCE_MIPI, 50, &periph_h_regs, TEGRA_PERIPH_ON_APB, mipi),
1446 TEGRA_INIT_DATA_MUX("tsensor", NULL, "tegra-tsensor", mux_pllpc_clkm_clk32k, CLK_SOURCE_TSENSOR, 100, &periph_v_regs, TEGRA_PERIPH_ON_APB, tsensor),
1447 TEGRA_INIT_DATA_MUX("i2cslow", NULL, "i2cslow", mux_pllpc_clk32k_clkm, CLK_SOURCE_I2CSLOW, 81, &periph_u_regs, TEGRA_PERIPH_ON_APB, i2cslow),
1448 TEGRA_INIT_DATA_INT("vde", NULL, "vde", mux_pllpcm_clkm, CLK_SOURCE_VDE, 61, &periph_h_regs, 0, vde),
1449 TEGRA_INIT_DATA_INT("vi", "vi", "tegra_camera", mux_pllmcpa, CLK_SOURCE_VI, 20, &periph_l_regs, 0, vi),
1450 TEGRA_INIT_DATA_INT("epp", NULL, "epp", mux_pllmcpa, CLK_SOURCE_EPP, 19, &periph_l_regs, 0, epp),
1451 TEGRA_INIT_DATA_INT("mpe", NULL, "mpe", mux_pllmcpa, CLK_SOURCE_MPE, 60, &periph_h_regs, 0, mpe),
1452 TEGRA_INIT_DATA_INT("host1x", NULL, "host1x", mux_pllmcpa, CLK_SOURCE_HOST1X, 28, &periph_l_regs, 0, host1x),
1453 TEGRA_INIT_DATA_INT("3d", NULL, "3d", mux_pllmcpa, CLK_SOURCE_3D, 24, &periph_l_regs, TEGRA_PERIPH_MANUAL_RESET, gr3d),
1454 TEGRA_INIT_DATA_INT("3d2", NULL, "3d2", mux_pllmcpa, CLK_SOURCE_3D2, 98, &periph_v_regs, TEGRA_PERIPH_MANUAL_RESET, gr3d2),
1455 TEGRA_INIT_DATA_INT("2d", NULL, "2d", mux_pllmcpa, CLK_SOURCE_2D, 21, &periph_l_regs, 0, gr2d),
1456 TEGRA_INIT_DATA_INT("se", NULL, "se", mux_pllpcm_clkm, CLK_SOURCE_SE, 127, &periph_v_regs, 0, se),
1457 TEGRA_INIT_DATA_MUX("mselect", NULL, "mselect", mux_pllp_clkm, CLK_SOURCE_MSELECT, 99, &periph_v_regs, 0, mselect),
1458 TEGRA_INIT_DATA_MUX("nor", NULL, "tegra-nor", mux_pllpcm_clkm, CLK_SOURCE_NOR, 42, &periph_h_regs, 0, nor),
1459 TEGRA_INIT_DATA_MUX("sdmmc1", NULL, "sdhci-tegra.0", mux_pllpcm_clkm, CLK_SOURCE_SDMMC1, 14, &periph_l_regs, 0, sdmmc1),
1460 TEGRA_INIT_DATA_MUX("sdmmc2", NULL, "sdhci-tegra.1", mux_pllpcm_clkm, CLK_SOURCE_SDMMC2, 9, &periph_l_regs, 0, sdmmc2),
1461 TEGRA_INIT_DATA_MUX("sdmmc3", NULL, "sdhci-tegra.2", mux_pllpcm_clkm, CLK_SOURCE_SDMMC3, 69, &periph_u_regs, 0, sdmmc3),
1462 TEGRA_INIT_DATA_MUX("sdmmc4", NULL, "sdhci-tegra.3", mux_pllpcm_clkm, CLK_SOURCE_SDMMC4, 15, &periph_l_regs, 0, sdmmc4),
1463 TEGRA_INIT_DATA_MUX("cve", NULL, "cve", mux_pllpdc_clkm, CLK_SOURCE_CVE, 49, &periph_h_regs, 0, cve),
1464 TEGRA_INIT_DATA_MUX("tvo", NULL, "tvo", mux_pllpdc_clkm, CLK_SOURCE_TVO, 49, &periph_h_regs, 0, tvo),
1465 TEGRA_INIT_DATA_MUX("tvdac", NULL, "tvdac", mux_pllpdc_clkm, CLK_SOURCE_TVDAC, 53, &periph_h_regs, 0, tvdac),
1466 TEGRA_INIT_DATA_MUX("actmon", NULL, "actmon", mux_pllpc_clk32k_clkm, CLK_SOURCE_ACTMON, 119, &periph_v_regs, 0, actmon),
1467 TEGRA_INIT_DATA_MUX("vi_sensor", "vi_sensor", "tegra_camera", mux_pllmcpa, CLK_SOURCE_VI_SENSOR, 20, &periph_l_regs, TEGRA_PERIPH_NO_RESET, vi_sensor),
1468 TEGRA_INIT_DATA_DIV16("i2c1", "div-clk", "tegra-i2c.0", mux_pllp_clkm, CLK_SOURCE_I2C1, 12, &periph_l_regs, TEGRA_PERIPH_ON_APB, i2c1),
1469 TEGRA_INIT_DATA_DIV16("i2c2", "div-clk", "tegra-i2c.1", mux_pllp_clkm, CLK_SOURCE_I2C2, 54, &periph_h_regs, TEGRA_PERIPH_ON_APB, i2c2),
1470 TEGRA_INIT_DATA_DIV16("i2c3", "div-clk", "tegra-i2c.2", mux_pllp_clkm, CLK_SOURCE_I2C3, 67, &periph_u_regs, TEGRA_PERIPH_ON_APB, i2c3),
1471 TEGRA_INIT_DATA_DIV16("i2c4", "div-clk", "tegra-i2c.3", mux_pllp_clkm, CLK_SOURCE_I2C4, 103, &periph_v_regs, TEGRA_PERIPH_ON_APB, i2c4),
1472 TEGRA_INIT_DATA_DIV16("i2c5", "div-clk", "tegra-i2c.4", mux_pllp_clkm, CLK_SOURCE_I2C5, 47, &periph_h_regs, TEGRA_PERIPH_ON_APB, i2c5),
1473 TEGRA_INIT_DATA_UART("uarta", NULL, "tegra_uart.0", mux_pllpcm_clkm, CLK_SOURCE_UARTA, 6, &periph_l_regs, uarta),
1474 TEGRA_INIT_DATA_UART("uartb", NULL, "tegra_uart.1", mux_pllpcm_clkm, CLK_SOURCE_UARTB, 7, &periph_l_regs, uartb),
1475 TEGRA_INIT_DATA_UART("uartc", NULL, "tegra_uart.2", mux_pllpcm_clkm, CLK_SOURCE_UARTC, 55, &periph_h_regs, uartc),
1476 TEGRA_INIT_DATA_UART("uartd", NULL, "tegra_uart.3", mux_pllpcm_clkm, CLK_SOURCE_UARTD, 65, &periph_u_regs, uartd),
1477 TEGRA_INIT_DATA_UART("uarte", NULL, "tegra_uart.4", mux_pllpcm_clkm, CLK_SOURCE_UARTE, 66, &periph_u_regs, uarte),
1478 TEGRA_INIT_DATA_MUX8("hdmi", NULL, "hdmi", mux_pllpmdacd2_clkm, CLK_SOURCE_HDMI, 51, &periph_h_regs, 0, hdmi),
1479 TEGRA_INIT_DATA_MUX8("extern1", NULL, "extern1", mux_plla_clk32k_pllp_clkm_plle, CLK_SOURCE_EXTERN1, 120, &periph_v_regs, 0, extern1),
1480 TEGRA_INIT_DATA_MUX8("extern2", NULL, "extern2", mux_plla_clk32k_pllp_clkm_plle, CLK_SOURCE_EXTERN2, 121, &periph_v_regs, 0, extern2),
1481 TEGRA_INIT_DATA_MUX8("extern3", NULL, "extern3", mux_plla_clk32k_pllp_clkm_plle, CLK_SOURCE_EXTERN3, 122, &periph_v_regs, 0, extern3),
1482 TEGRA_INIT_DATA("pwm", NULL, "pwm", mux_pllpc_clk32k_clkm, CLK_SOURCE_PWM, 28, 2, 0, 0, 8, 1, 0, &periph_l_regs, 17, periph_clk_enb_refcnt, 0, pwm),
1485 static struct tegra_periph_init_data tegra_periph_nodiv_clk_list[] = {
1486 TEGRA_INIT_DATA_NODIV("disp1", NULL, "tegradc.0", mux_pllpmdacd2_clkm, CLK_SOURCE_DISP1, 29, 3, 27, &periph_l_regs, 0, disp1),
1487 TEGRA_INIT_DATA_NODIV("disp2", NULL, "tegradc.1", mux_pllpmdacd2_clkm, CLK_SOURCE_DISP2, 29, 3, 26, &periph_l_regs, 0, disp2),
1488 TEGRA_INIT_DATA_NODIV("dsib", NULL, "tegradc.1", mux_plld_out0_plld2_out0, CLK_SOURCE_DSIB, 25, 1, 82, &periph_u_regs, 0, dsib),
1491 static void __init tegra30_periph_clk_init(void)
1493 struct tegra_periph_init_data *data;
1498 clk = tegra_clk_register_periph_gate("apbdma", "clk_m", 0, clk_base, 0, 34,
1499 &periph_h_regs, periph_clk_enb_refcnt);
1500 clk_register_clkdev(clk, NULL, "tegra-apbdma");
1504 clk = tegra_clk_register_periph_gate("rtc", "clk_32k",
1505 TEGRA_PERIPH_NO_RESET | TEGRA_PERIPH_ON_APB,
1506 clk_base, 0, 4, &periph_l_regs,
1507 periph_clk_enb_refcnt);
1508 clk_register_clkdev(clk, NULL, "rtc-tegra");
1512 clk = tegra_clk_register_periph_gate("timer", "clk_m", 0, clk_base, 0,
1513 5, &periph_l_regs, periph_clk_enb_refcnt);
1514 clk_register_clkdev(clk, NULL, "timer");
1518 clk = tegra_clk_register_periph_gate("kbc", "clk_32k",
1519 TEGRA_PERIPH_NO_RESET | TEGRA_PERIPH_ON_APB,
1520 clk_base, 0, 36, &periph_h_regs,
1521 periph_clk_enb_refcnt);
1522 clk_register_clkdev(clk, NULL, "tegra-kbc");
1526 clk = tegra_clk_register_periph_gate("csus", "clk_m",
1527 TEGRA_PERIPH_NO_RESET | TEGRA_PERIPH_ON_APB,
1528 clk_base, 0, 92, &periph_u_regs,
1529 periph_clk_enb_refcnt);
1530 clk_register_clkdev(clk, "csus", "tengra_camera");
1534 clk = tegra_clk_register_periph_gate("vcp", "clk_m", 0, clk_base, 0, 29,
1535 &periph_l_regs, periph_clk_enb_refcnt);
1536 clk_register_clkdev(clk, "vcp", "tegra-avp");
1540 clk = tegra_clk_register_periph_gate("bsea", "clk_m", 0, clk_base, 0,
1541 62, &periph_h_regs, periph_clk_enb_refcnt);
1542 clk_register_clkdev(clk, "bsea", "tegra-avp");
1546 clk = tegra_clk_register_periph_gate("bsev", "clk_m", 0, clk_base, 0,
1547 63, &periph_h_regs, periph_clk_enb_refcnt);
1548 clk_register_clkdev(clk, "bsev", "tegra-aes");
1552 clk = tegra_clk_register_periph_gate("usbd", "clk_m", 0, clk_base, 0,
1553 22, &periph_l_regs, periph_clk_enb_refcnt);
1554 clk_register_clkdev(clk, NULL, "fsl-tegra-udc");
1558 clk = tegra_clk_register_periph_gate("usb2", "clk_m", 0, clk_base, 0,
1559 58, &periph_h_regs, periph_clk_enb_refcnt);
1560 clk_register_clkdev(clk, NULL, "tegra-ehci.1");
1564 clk = tegra_clk_register_periph_gate("usb3", "clk_m", 0, clk_base, 0,
1565 59, &periph_h_regs, periph_clk_enb_refcnt);
1566 clk_register_clkdev(clk, NULL, "tegra-ehci.2");
1570 clk = tegra_clk_register_periph_gate("dsia", "pll_d_out0", 0, clk_base,
1571 0, 48, &periph_h_regs,
1572 periph_clk_enb_refcnt);
1573 clk_register_clkdev(clk, "dsia", "tegradc.0");
1577 clk = tegra_clk_register_periph_gate("csi", "pll_p_out3", 0, clk_base,
1578 0, 52, &periph_h_regs,
1579 periph_clk_enb_refcnt);
1580 clk_register_clkdev(clk, "csi", "tegra_camera");
1584 clk = tegra_clk_register_periph_gate("isp", "clk_m", 0, clk_base, 0, 23,
1585 &periph_l_regs, periph_clk_enb_refcnt);
1586 clk_register_clkdev(clk, "isp", "tegra_camera");
1590 clk = tegra_clk_register_periph_gate("pcie", "clk_m", 0, clk_base, 0,
1591 70, &periph_u_regs, periph_clk_enb_refcnt);
1592 clk_register_clkdev(clk, "pcie", "tegra-pcie");
1596 clk = tegra_clk_register_periph_gate("afi", "clk_m", 0, clk_base, 0, 72,
1597 &periph_u_regs, periph_clk_enb_refcnt);
1598 clk_register_clkdev(clk, "afi", "tegra-pcie");
1602 clk = tegra_clk_register_periph_gate("kfuse", "clk_m",
1603 TEGRA_PERIPH_ON_APB,
1604 clk_base, 0, 40, &periph_h_regs,
1605 periph_clk_enb_refcnt);
1606 clk_register_clkdev(clk, NULL, "kfuse-tegra");
1610 clk = tegra_clk_register_periph_gate("fuse", "clk_m",
1611 TEGRA_PERIPH_ON_APB,
1612 clk_base, 0, 39, &periph_h_regs,
1613 periph_clk_enb_refcnt);
1614 clk_register_clkdev(clk, "fuse", "fuse-tegra");
1618 clk = tegra_clk_register_periph_gate("fuse_burn", "clk_m",
1619 TEGRA_PERIPH_ON_APB,
1620 clk_base, 0, 39, &periph_h_regs,
1621 periph_clk_enb_refcnt);
1622 clk_register_clkdev(clk, "fuse_burn", "fuse-tegra");
1623 clks[fuse_burn] = clk;
1626 clk = tegra_clk_register_periph_gate("apbif", "clk_m", 0,
1627 clk_base, 0, 107, &periph_v_regs,
1628 periph_clk_enb_refcnt);
1629 clk_register_clkdev(clk, "apbif", "tegra30-ahub");
1633 clk = tegra_clk_register_periph_gate("hda2hdmi", "clk_m",
1634 TEGRA_PERIPH_ON_APB,
1635 clk_base, 0, 128, &periph_w_regs,
1636 periph_clk_enb_refcnt);
1637 clk_register_clkdev(clk, "hda2hdmi", "tegra30-hda");
1638 clks[hda2hdmi] = clk;
1641 clk = tegra_clk_register_periph_gate("sata_cold", "clk_m",
1642 TEGRA_PERIPH_ON_APB,
1643 clk_base, 0, 129, &periph_w_regs,
1644 periph_clk_enb_refcnt);
1645 clk_register_clkdev(clk, NULL, "tegra_sata_cold");
1646 clks[sata_cold] = clk;
1649 clk = tegra_clk_register_periph_gate("dtv", "clk_m",
1650 TEGRA_PERIPH_ON_APB,
1651 clk_base, 0, 79, &periph_u_regs,
1652 periph_clk_enb_refcnt);
1653 clk_register_clkdev(clk, NULL, "dtv");
1657 clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm,
1658 ARRAY_SIZE(mux_pllmcp_clkm), 0,
1659 clk_base + CLK_SOURCE_EMC,
1661 clk = tegra_clk_register_periph_gate("emc", "emc_mux", 0, clk_base, 0,
1662 57, &periph_h_regs, periph_clk_enb_refcnt);
1663 clk_register_clkdev(clk, "emc", NULL);
1666 for (i = 0; i < ARRAY_SIZE(tegra_periph_clk_list); i++) {
1667 data = &tegra_periph_clk_list[i];
1668 clk = tegra_clk_register_periph(data->name, data->parent_names,
1669 data->num_parents, &data->periph,
1670 clk_base, data->offset, data->flags);
1671 clk_register_clkdev(clk, data->con_id, data->dev_id);
1672 clks[data->clk_id] = clk;
1675 for (i = 0; i < ARRAY_SIZE(tegra_periph_nodiv_clk_list); i++) {
1676 data = &tegra_periph_nodiv_clk_list[i];
1677 clk = tegra_clk_register_periph_nodiv(data->name,
1679 data->num_parents, &data->periph,
1680 clk_base, data->offset);
1681 clk_register_clkdev(clk, data->con_id, data->dev_id);
1682 clks[data->clk_id] = clk;
1686 static void __init tegra30_fixed_clk_init(void)
1691 clk = clk_register_fixed_rate(NULL, "clk_32k", NULL, CLK_IS_ROOT,
1693 clk_register_clkdev(clk, "clk_32k", NULL);
1694 clks[clk_32k] = clk;
1697 clk = clk_register_fixed_factor(NULL, "clk_m_div2", "clk_m",
1698 CLK_SET_RATE_PARENT, 1, 2);
1699 clk_register_clkdev(clk, "clk_m_div2", NULL);
1700 clks[clk_m_div2] = clk;
1703 clk = clk_register_fixed_factor(NULL, "clk_m_div4", "clk_m",
1704 CLK_SET_RATE_PARENT, 1, 4);
1705 clk_register_clkdev(clk, "clk_m_div4", NULL);
1706 clks[clk_m_div4] = clk;
1709 clk = clk_register_gate(NULL, "cml0", "pll_e", 0, clk_base + PLLE_AUX,
1711 clk_register_clkdev(clk, "cml0", NULL);
1715 clk = clk_register_gate(NULL, "cml1", "pll_e", 0, clk_base + PLLE_AUX,
1717 clk_register_clkdev(clk, "cml1", NULL);
1721 clk = clk_register_fixed_rate(NULL, "pciex", "pll_e", 0, 100000000);
1722 clk_register_clkdev(clk, "pciex", NULL);
1726 static void __init tegra30_osc_clk_init(void)
1729 unsigned int pll_ref_div;
1731 tegra30_clk_measure_input_freq();
1734 clk = clk_register_fixed_rate(NULL, "clk_m", NULL, CLK_IS_ROOT,
1736 clk_register_clkdev(clk, "clk_m", NULL);
1740 pll_ref_div = tegra30_get_pll_ref_div();
1741 clk = clk_register_fixed_factor(NULL, "pll_ref", "clk_m",
1742 CLK_SET_RATE_PARENT, 1, pll_ref_div);
1743 clk_register_clkdev(clk, "pll_ref", NULL);
1744 clks[pll_ref] = clk;
1747 /* Tegra30 CPU clock and reset control functions */
1748 static void tegra30_wait_cpu_in_reset(u32 cpu)
1753 reg = readl(clk_base +
1754 TEGRA30_CLK_RST_CONTROLLER_CPU_CMPLX_STATUS);
1756 } while (!(reg & (1 << cpu))); /* check CPU been reset or not */
1761 static void tegra30_put_cpu_in_reset(u32 cpu)
1763 writel(CPU_RESET(cpu),
1764 clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET);
1768 static void tegra30_cpu_out_of_reset(u32 cpu)
1770 writel(CPU_RESET(cpu),
1771 clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR);
1776 static void tegra30_enable_cpu_clock(u32 cpu)
1780 writel(CPU_CLOCK(cpu),
1781 clk_base + TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR);
1782 reg = readl(clk_base +
1783 TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR);
1786 static void tegra30_disable_cpu_clock(u32 cpu)
1791 reg = readl(clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
1792 writel(reg | CPU_CLOCK(cpu),
1793 clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
1796 #ifdef CONFIG_PM_SLEEP
1797 static bool tegra30_cpu_rail_off_ready(void)
1799 unsigned int cpu_rst_status;
1802 cpu_rst_status = readl(clk_base +
1803 TEGRA30_CLK_RST_CONTROLLER_CPU_CMPLX_STATUS);
1804 cpu_pwr_status = tegra_powergate_is_powered(TEGRA_POWERGATE_CPU1) ||
1805 tegra_powergate_is_powered(TEGRA_POWERGATE_CPU2) ||
1806 tegra_powergate_is_powered(TEGRA_POWERGATE_CPU3);
1808 if (((cpu_rst_status & 0xE) != 0xE) || cpu_pwr_status)
1814 static void tegra30_cpu_clock_suspend(void)
1816 /* switch coresite to clk_m, save off original source */
1817 tegra30_cpu_clk_sctx.clk_csite_src =
1818 readl(clk_base + CLK_RESET_SOURCE_CSITE);
1819 writel(3<<30, clk_base + CLK_RESET_SOURCE_CSITE);
1821 tegra30_cpu_clk_sctx.cpu_burst =
1822 readl(clk_base + CLK_RESET_CCLK_BURST);
1823 tegra30_cpu_clk_sctx.pllx_base =
1824 readl(clk_base + CLK_RESET_PLLX_BASE);
1825 tegra30_cpu_clk_sctx.pllx_misc =
1826 readl(clk_base + CLK_RESET_PLLX_MISC);
1827 tegra30_cpu_clk_sctx.cclk_divider =
1828 readl(clk_base + CLK_RESET_CCLK_DIVIDER);
1831 static void tegra30_cpu_clock_resume(void)
1833 unsigned int reg, policy;
1835 /* Is CPU complex already running on PLLX? */
1836 reg = readl(clk_base + CLK_RESET_CCLK_BURST);
1837 policy = (reg >> CLK_RESET_CCLK_BURST_POLICY_SHIFT) & 0xF;
1839 if (policy == CLK_RESET_CCLK_IDLE_POLICY)
1840 reg = (reg >> CLK_RESET_CCLK_IDLE_POLICY_SHIFT) & 0xF;
1841 else if (policy == CLK_RESET_CCLK_RUN_POLICY)
1842 reg = (reg >> CLK_RESET_CCLK_RUN_POLICY_SHIFT) & 0xF;
1846 if (reg != CLK_RESET_CCLK_BURST_POLICY_PLLX) {
1847 /* restore PLLX settings if CPU is on different PLL */
1848 writel(tegra30_cpu_clk_sctx.pllx_misc,
1849 clk_base + CLK_RESET_PLLX_MISC);
1850 writel(tegra30_cpu_clk_sctx.pllx_base,
1851 clk_base + CLK_RESET_PLLX_BASE);
1853 /* wait for PLL stabilization if PLLX was enabled */
1854 if (tegra30_cpu_clk_sctx.pllx_base & (1 << 30))
1859 * Restore original burst policy setting for calls resulting from CPU
1860 * LP2 in idle or system suspend.
1862 writel(tegra30_cpu_clk_sctx.cclk_divider,
1863 clk_base + CLK_RESET_CCLK_DIVIDER);
1864 writel(tegra30_cpu_clk_sctx.cpu_burst,
1865 clk_base + CLK_RESET_CCLK_BURST);
1867 writel(tegra30_cpu_clk_sctx.clk_csite_src,
1868 clk_base + CLK_RESET_SOURCE_CSITE);
1872 static struct tegra_cpu_car_ops tegra30_cpu_car_ops = {
1873 .wait_for_reset = tegra30_wait_cpu_in_reset,
1874 .put_in_reset = tegra30_put_cpu_in_reset,
1875 .out_of_reset = tegra30_cpu_out_of_reset,
1876 .enable_clock = tegra30_enable_cpu_clock,
1877 .disable_clock = tegra30_disable_cpu_clock,
1878 #ifdef CONFIG_PM_SLEEP
1879 .rail_off_ready = tegra30_cpu_rail_off_ready,
1880 .suspend = tegra30_cpu_clock_suspend,
1881 .resume = tegra30_cpu_clock_resume,
1885 static __initdata struct tegra_clk_init_table init_table[] = {
1886 {uarta, pll_p, 408000000, 0},
1887 {uartb, pll_p, 408000000, 0},
1888 {uartc, pll_p, 408000000, 0},
1889 {uartd, pll_p, 408000000, 0},
1890 {uarte, pll_p, 408000000, 0},
1891 {pll_a, clk_max, 564480000, 1},
1892 {pll_a_out0, clk_max, 11289600, 1},
1893 {extern1, pll_a_out0, 0, 1},
1894 {clk_out_1_mux, extern1, 0, 0},
1895 {clk_out_1, clk_max, 0, 1},
1896 {blink, clk_max, 0, 1},
1897 {i2s0, pll_a_out0, 11289600, 0},
1898 {i2s1, pll_a_out0, 11289600, 0},
1899 {i2s2, pll_a_out0, 11289600, 0},
1900 {i2s3, pll_a_out0, 11289600, 0},
1901 {i2s4, pll_a_out0, 11289600, 0},
1902 {sdmmc1, pll_p, 48000000, 0},
1903 {sdmmc2, pll_p, 48000000, 0},
1904 {sdmmc3, pll_p, 48000000, 0},
1905 {pll_m, clk_max, 0, 1},
1906 {pclk, clk_max, 0, 1},
1907 {csite, clk_max, 0, 1},
1908 {emc, clk_max, 0, 1},
1909 {mselect, clk_max, 0, 1},
1910 {sbc1, pll_p, 100000000, 0},
1911 {sbc2, pll_p, 100000000, 0},
1912 {sbc3, pll_p, 100000000, 0},
1913 {sbc4, pll_p, 100000000, 0},
1914 {sbc5, pll_p, 100000000, 0},
1915 {sbc6, pll_p, 100000000, 0},
1916 {host1x, pll_c, 150000000, 0},
1917 {disp1, pll_p, 600000000, 0},
1918 {disp2, pll_p, 600000000, 0},
1919 {twd, clk_max, 0, 1},
1920 {gr2d, pll_c, 300000000, 0},
1921 {gr3d, pll_c, 300000000, 0},
1922 {clk_max, clk_max, 0, 0}, /* This MUST be the last entry. */
1925 static void __init tegra30_clock_apply_init_table(void)
1927 tegra_init_from_table(init_table, clks, clk_max);
1931 * Some clocks may be used by different drivers depending on the board
1932 * configuration. List those here to register them twice in the clock lookup
1933 * table under two names.
1935 static struct tegra_clk_duplicate tegra_clk_duplicates[] = {
1936 TEGRA_CLK_DUPLICATE(usbd, "utmip-pad", NULL),
1937 TEGRA_CLK_DUPLICATE(usbd, "tegra-ehci.0", NULL),
1938 TEGRA_CLK_DUPLICATE(usbd, "tegra-otg", NULL),
1939 TEGRA_CLK_DUPLICATE(bsev, "tegra-avp", "bsev"),
1940 TEGRA_CLK_DUPLICATE(bsev, "nvavp", "bsev"),
1941 TEGRA_CLK_DUPLICATE(vde, "tegra-aes", "vde"),
1942 TEGRA_CLK_DUPLICATE(bsea, "tegra-aes", "bsea"),
1943 TEGRA_CLK_DUPLICATE(bsea, "nvavp", "bsea"),
1944 TEGRA_CLK_DUPLICATE(cml1, "tegra_sata_cml", NULL),
1945 TEGRA_CLK_DUPLICATE(cml0, "tegra_pcie", "cml"),
1946 TEGRA_CLK_DUPLICATE(pciex, "tegra_pcie", "pciex"),
1947 TEGRA_CLK_DUPLICATE(vcp, "nvavp", "vcp"),
1948 TEGRA_CLK_DUPLICATE(clk_max, NULL, NULL), /* MUST be the last entry */
1951 static const struct of_device_id pmc_match[] __initconst = {
1952 { .compatible = "nvidia,tegra30-pmc" },
1956 void __init tegra30_clock_init(struct device_node *np)
1958 struct device_node *node;
1961 clk_base = of_iomap(np, 0);
1963 pr_err("ioremap tegra30 CAR failed\n");
1967 node = of_find_matching_node(NULL, pmc_match);
1969 pr_err("Failed to find pmc node\n");
1973 pmc_base = of_iomap(node, 0);
1975 pr_err("Can't map pmc registers\n");
1979 tegra30_osc_clk_init();
1980 tegra30_fixed_clk_init();
1982 tegra30_super_clk_init();
1983 tegra30_periph_clk_init();
1984 tegra30_audio_clk_init();
1985 tegra30_pmc_clk_init();
1987 for (i = 0; i < ARRAY_SIZE(clks); i++) {
1988 if (IS_ERR(clks[i])) {
1989 pr_err("Tegra30 clk %d: register failed with %ld\n",
1990 i, PTR_ERR(clks[i]));
1994 clks[i] = ERR_PTR(-EINVAL);
1997 tegra_init_dup_clks(tegra_clk_duplicates, clks, clk_max);
1999 clk_data.clks = clks;
2000 clk_data.clk_num = ARRAY_SIZE(clks);
2001 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
2003 tegra_clk_apply_init_table = tegra30_clock_apply_init_table;
2005 tegra_cpu_car_ops = &tegra30_cpu_car_ops;