2 * TI Clock driver internal definitions
4 * Copyright (C) 2014 Texas Instruments, Inc
5 * Tero Kristo (t-kristo@ti.com)
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation version 2.
11 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
12 * kind, whether express or implied; without even the implied warranty
13 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 #ifndef __DRIVERS_CLK_TI_CLOCK__
17 #define __DRIVERS_CLK_TI_CLOCK__
30 #define CLKF_INDEX_POWER_OF_TWO (1 << 0)
31 #define CLKF_INDEX_STARTS_AT_ONE (1 << 1)
32 #define CLKF_SET_RATE_PARENT (1 << 2)
33 #define CLKF_OMAP3 (1 << 3)
34 #define CLKF_AM35XX (1 << 4)
37 #define CLKF_SET_BIT_TO_DISABLE (1 << 5)
38 #define CLKF_INTERFACE (1 << 6)
39 #define CLKF_SSI (1 << 7)
40 #define CLKF_DSS (1 << 8)
41 #define CLKF_HSOTGUSB (1 << 9)
42 #define CLKF_WAIT (1 << 10)
43 #define CLKF_NO_WAIT (1 << 11)
44 #define CLKF_HSDIV (1 << 12)
45 #define CLKF_CLKDM (1 << 13)
48 #define CLKF_LOW_POWER_STOP (1 << 5)
49 #define CLKF_LOCK (1 << 6)
50 #define CLKF_LOW_POWER_BYPASS (1 << 7)
51 #define CLKF_PER (1 << 8)
52 #define CLKF_CORE (1 << 9)
53 #define CLKF_J_TYPE (1 << 10)
55 #define CLK(dev, con, ck) \
66 const char *clkdm_name;
76 struct list_head link;
93 struct ti_clk_divider {
104 struct ti_clk_fixed_factor {
119 struct ti_clk_composite {
120 struct ti_clk_divider *divider;
121 struct ti_clk_mux *mux;
122 struct ti_clk_gate *gate;
126 struct ti_clk_clkdm_gate {
138 const char **parents;
157 /* Composite clock component types */
159 CLK_COMPONENT_TYPE_GATE = 0,
160 CLK_COMPONENT_TYPE_DIVIDER,
161 CLK_COMPONENT_TYPE_MUX,
162 CLK_COMPONENT_TYPE_MAX,
166 * struct ti_dt_clk - OMAP DT clock alias declarations
167 * @lk: clock lookup definition
168 * @node_name: clock DT node to map to
171 struct clk_lookup lk;
175 #define DT_CLK(dev, con, name) \
184 typedef void (*ti_of_clk_init_cb_t)(struct clk_hw *, struct device_node *);
186 struct clk *ti_clk_register_gate(struct ti_clk *setup);
187 struct clk *ti_clk_register_interface(struct ti_clk *setup);
188 struct clk *ti_clk_register_mux(struct ti_clk *setup);
189 struct clk *ti_clk_register_divider(struct ti_clk *setup);
190 struct clk *ti_clk_register_composite(struct ti_clk *setup);
191 struct clk *ti_clk_register_dpll(struct ti_clk *setup);
193 struct clk_hw *ti_clk_build_component_div(struct ti_clk_divider *setup);
194 struct clk_hw *ti_clk_build_component_gate(struct ti_clk_gate *setup);
195 struct clk_hw *ti_clk_build_component_mux(struct ti_clk_mux *setup);
197 void ti_clk_patch_legacy_clks(struct ti_clk **patch);
198 struct clk *ti_clk_register_clk(struct ti_clk *setup);
199 int ti_clk_register_legacy_clks(struct ti_clk_alias *clks);
201 void __iomem *ti_clk_get_reg_addr(struct device_node *node, int index);
202 void ti_dt_clocks_register(struct ti_dt_clk *oclks);
203 int ti_clk_retry_init(struct device_node *node, struct clk_hw *hw,
204 ti_of_clk_init_cb_t func);
205 int ti_clk_add_component(struct device_node *node, struct clk_hw *hw, int type);
207 void omap2_init_clk_hw_omap_clocks(struct clk_hw *hw);
208 int of_ti_clk_autoidle_setup(struct device_node *node);
209 void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks);
211 extern const struct clk_hw_omap_ops clkhwops_omap3_dpll;
212 extern const struct clk_hw_omap_ops clkhwops_omap4_dpllmx;
213 extern const struct clk_hw_omap_ops clkhwops_wait;
214 extern const struct clk_hw_omap_ops clkhwops_iclk;
215 extern const struct clk_hw_omap_ops clkhwops_iclk_wait;
216 extern const struct clk_hw_omap_ops clkhwops_omap2430_i2chs_wait;
217 extern const struct clk_hw_omap_ops clkhwops_omap3430es2_dss_usbhost_wait;
218 extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_hsotgusb_wait;
219 extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_dss_usbhost_wait;
220 extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_ssi_wait;
221 extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_module_wait;
222 extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_wait;
224 extern const struct clk_ops ti_clk_divider_ops;
225 extern const struct clk_ops ti_clk_mux_ops;
227 int omap2_clkops_enable_clkdm(struct clk_hw *hw);
228 void omap2_clkops_disable_clkdm(struct clk_hw *hw);
230 int omap2_dflt_clk_enable(struct clk_hw *hw);
231 void omap2_dflt_clk_disable(struct clk_hw *hw);
232 int omap2_dflt_clk_is_enabled(struct clk_hw *hw);
233 void omap2_clk_dflt_find_companion(struct clk_hw_omap *clk,
234 void __iomem **other_reg,
236 void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk,
237 void __iomem **idlest_reg,
238 u8 *idlest_bit, u8 *idlest_val);
240 void omap2_clkt_iclk_allow_idle(struct clk_hw_omap *clk);
241 void omap2_clkt_iclk_deny_idle(struct clk_hw_omap *clk);
243 u8 omap2_init_dpll_parent(struct clk_hw *hw);
244 int omap3_noncore_dpll_enable(struct clk_hw *hw);
245 void omap3_noncore_dpll_disable(struct clk_hw *hw);
246 int omap3_noncore_dpll_set_parent(struct clk_hw *hw, u8 index);
247 int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate,
248 unsigned long parent_rate);
249 int omap3_noncore_dpll_set_rate_and_parent(struct clk_hw *hw,
251 unsigned long parent_rate,
253 int omap3_noncore_dpll_determine_rate(struct clk_hw *hw,
254 struct clk_rate_request *req);
255 long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate,
256 unsigned long *parent_rate);
257 unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw,
258 unsigned long parent_rate);
260 unsigned long omap3_dpll_recalc(struct clk_hw *hw, unsigned long parent_rate);
261 int omap3_dpll4_set_rate(struct clk_hw *clk, unsigned long rate,
262 unsigned long parent_rate);
263 int omap3_dpll4_set_rate_and_parent(struct clk_hw *hw, unsigned long rate,
264 unsigned long parent_rate, u8 index);
265 void omap3_clk_lock_dpll5(void);
267 unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw,
268 unsigned long parent_rate);
269 long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw,
270 unsigned long target_rate,
271 unsigned long *parent_rate);
272 int omap4_dpll_regm4xen_determine_rate(struct clk_hw *hw,
273 struct clk_rate_request *req);
275 extern struct ti_clk_ll_ops *ti_clk_ll_ops;