4 * Copyright (C) 2013 Texas Instruments, Inc.
6 * Tero Kristo <t-kristo@ti.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
13 * kind, whether express or implied; without even the implied warranty
14 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
18 #include <linux/clk-provider.h>
19 #include <linux/slab.h>
20 #include <linux/err.h>
22 #include <linux/of_address.h>
23 #include <linux/clk/ti.h>
26 #define pr_fmt(fmt) "%s: " fmt, __func__
28 #define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw)
30 #define div_mask(d) ((1 << ((d)->width)) - 1)
32 static unsigned int _get_table_maxdiv(const struct clk_div_table *table)
34 unsigned int maxdiv = 0;
35 const struct clk_div_table *clkt;
37 for (clkt = table; clkt->div; clkt++)
38 if (clkt->div > maxdiv)
43 static unsigned int _get_maxdiv(struct clk_divider *divider)
45 if (divider->flags & CLK_DIVIDER_ONE_BASED)
46 return div_mask(divider);
47 if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
48 return 1 << div_mask(divider);
50 return _get_table_maxdiv(divider->table);
51 return div_mask(divider) + 1;
54 static unsigned int _get_table_div(const struct clk_div_table *table,
57 const struct clk_div_table *clkt;
59 for (clkt = table; clkt->div; clkt++)
65 static unsigned int _get_div(struct clk_divider *divider, unsigned int val)
67 if (divider->flags & CLK_DIVIDER_ONE_BASED)
69 if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
72 return _get_table_div(divider->table, val);
76 static unsigned int _get_table_val(const struct clk_div_table *table,
79 const struct clk_div_table *clkt;
81 for (clkt = table; clkt->div; clkt++)
87 static unsigned int _get_val(struct clk_divider *divider, u8 div)
89 if (divider->flags & CLK_DIVIDER_ONE_BASED)
91 if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
94 return _get_table_val(divider->table, div);
98 static unsigned long ti_clk_divider_recalc_rate(struct clk_hw *hw,
99 unsigned long parent_rate)
101 struct clk_divider *divider = to_clk_divider(hw);
102 unsigned int div, val;
104 val = ti_clk_ll_ops->clk_readl(divider->reg) >> divider->shift;
105 val &= div_mask(divider);
107 div = _get_div(divider, val);
109 WARN(!(divider->flags & CLK_DIVIDER_ALLOW_ZERO),
110 "%s: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set\n",
111 __clk_get_name(hw->clk));
115 return DIV_ROUND_UP(parent_rate, div);
119 * The reverse of DIV_ROUND_UP: The maximum number which
122 #define MULT_ROUND_UP(r, m) ((r) * (m) + (m) - 1)
124 static bool _is_valid_table_div(const struct clk_div_table *table,
127 const struct clk_div_table *clkt;
129 for (clkt = table; clkt->div; clkt++)
130 if (clkt->div == div)
135 static bool _is_valid_div(struct clk_divider *divider, unsigned int div)
137 if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
138 return is_power_of_2(div);
140 return _is_valid_table_div(divider->table, div);
144 static int ti_clk_divider_bestdiv(struct clk_hw *hw, unsigned long rate,
145 unsigned long *best_parent_rate)
147 struct clk_divider *divider = to_clk_divider(hw);
149 unsigned long parent_rate, best = 0, now, maxdiv;
150 unsigned long parent_rate_saved = *best_parent_rate;
155 maxdiv = _get_maxdiv(divider);
157 if (!(__clk_get_flags(hw->clk) & CLK_SET_RATE_PARENT)) {
158 parent_rate = *best_parent_rate;
159 bestdiv = DIV_ROUND_UP(parent_rate, rate);
160 bestdiv = bestdiv == 0 ? 1 : bestdiv;
161 bestdiv = bestdiv > maxdiv ? maxdiv : bestdiv;
166 * The maximum divider we can use without overflowing
167 * unsigned long in rate * i below
169 maxdiv = min(ULONG_MAX / rate, maxdiv);
171 for (i = 1; i <= maxdiv; i++) {
172 if (!_is_valid_div(divider, i))
174 if (rate * i == parent_rate_saved) {
176 * It's the most ideal case if the requested rate can be
177 * divided from parent clock without needing to change
178 * parent rate, so return the divider immediately.
180 *best_parent_rate = parent_rate_saved;
183 parent_rate = __clk_round_rate(__clk_get_parent(hw->clk),
184 MULT_ROUND_UP(rate, i));
185 now = DIV_ROUND_UP(parent_rate, i);
186 if (now <= rate && now > best) {
189 *best_parent_rate = parent_rate;
194 bestdiv = _get_maxdiv(divider);
196 __clk_round_rate(__clk_get_parent(hw->clk), 1);
202 static long ti_clk_divider_round_rate(struct clk_hw *hw, unsigned long rate,
203 unsigned long *prate)
206 div = ti_clk_divider_bestdiv(hw, rate, prate);
208 return DIV_ROUND_UP(*prate, div);
211 static int ti_clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,
212 unsigned long parent_rate)
214 struct clk_divider *divider;
215 unsigned int div, value;
216 unsigned long flags = 0;
222 divider = to_clk_divider(hw);
224 div = DIV_ROUND_UP(parent_rate, rate);
225 value = _get_val(divider, div);
227 if (value > div_mask(divider))
228 value = div_mask(divider);
231 spin_lock_irqsave(divider->lock, flags);
233 if (divider->flags & CLK_DIVIDER_HIWORD_MASK) {
234 val = div_mask(divider) << (divider->shift + 16);
236 val = ti_clk_ll_ops->clk_readl(divider->reg);
237 val &= ~(div_mask(divider) << divider->shift);
239 val |= value << divider->shift;
240 ti_clk_ll_ops->clk_writel(val, divider->reg);
243 spin_unlock_irqrestore(divider->lock, flags);
248 const struct clk_ops ti_clk_divider_ops = {
249 .recalc_rate = ti_clk_divider_recalc_rate,
250 .round_rate = ti_clk_divider_round_rate,
251 .set_rate = ti_clk_divider_set_rate,
254 static struct clk *_register_divider(struct device *dev, const char *name,
255 const char *parent_name,
256 unsigned long flags, void __iomem *reg,
257 u8 shift, u8 width, u8 clk_divider_flags,
258 const struct clk_div_table *table,
261 struct clk_divider *div;
263 struct clk_init_data init;
265 if (clk_divider_flags & CLK_DIVIDER_HIWORD_MASK) {
266 if (width + shift > 16) {
267 pr_warn("divider value exceeds LOWORD field\n");
268 return ERR_PTR(-EINVAL);
272 /* allocate the divider */
273 div = kzalloc(sizeof(*div), GFP_KERNEL);
275 pr_err("%s: could not allocate divider clk\n", __func__);
276 return ERR_PTR(-ENOMEM);
280 init.ops = &ti_clk_divider_ops;
281 init.flags = flags | CLK_IS_BASIC;
282 init.parent_names = (parent_name ? &parent_name : NULL);
283 init.num_parents = (parent_name ? 1 : 0);
285 /* struct clk_divider assignments */
289 div->flags = clk_divider_flags;
291 div->hw.init = &init;
294 /* register the clock */
295 clk = clk_register(dev, &div->hw);
303 static struct clk_div_table *
304 __init ti_clk_get_div_table(struct device_node *node)
306 struct clk_div_table *table;
307 const __be32 *divspec;
313 divspec = of_get_property(node, "ti,dividers", &num_div);
322 /* Determine required size for divider table */
323 for (i = 0; i < num_div; i++) {
324 of_property_read_u32_index(node, "ti,dividers", i, &val);
330 pr_err("no valid dividers for %s table\n", node->name);
331 return ERR_PTR(-EINVAL);
334 table = kzalloc(sizeof(*table) * (valid_div + 1), GFP_KERNEL);
337 return ERR_PTR(-ENOMEM);
341 for (i = 0; i < num_div; i++) {
342 of_property_read_u32_index(node, "ti,dividers", i, &val);
344 table[valid_div].div = val;
345 table[valid_div].val = i;
353 static int _get_divider_width(struct device_node *node,
354 const struct clk_div_table *table,
363 /* Clk divider table not provided, determine min/max divs */
364 if (of_property_read_u32(node, "ti,min-div", &min_div))
367 if (of_property_read_u32(node, "ti,max-div", &max_div)) {
368 pr_err("no max-div for %s!\n", node->name);
372 /* Determine bit width for the field */
373 if (flags & CLK_DIVIDER_ONE_BASED)
378 while (div < max_div) {
379 if (flags & CLK_DIVIDER_POWER_OF_TWO)
388 while (table[div].div) {
389 val = table[div].val;
397 static int __init ti_clk_divider_populate(struct device_node *node,
398 void __iomem **reg, const struct clk_div_table **table,
399 u32 *flags, u8 *div_flags, u8 *width, u8 *shift)
403 *reg = ti_clk_get_reg_addr(node, 0);
407 if (!of_property_read_u32(node, "ti,bit-shift", &val))
415 if (of_property_read_bool(node, "ti,index-starts-at-one"))
416 *div_flags |= CLK_DIVIDER_ONE_BASED;
418 if (of_property_read_bool(node, "ti,index-power-of-two"))
419 *div_flags |= CLK_DIVIDER_POWER_OF_TWO;
421 if (of_property_read_bool(node, "ti,set-rate-parent"))
422 *flags |= CLK_SET_RATE_PARENT;
424 *table = ti_clk_get_div_table(node);
427 return PTR_ERR(*table);
429 *width = _get_divider_width(node, *table, *div_flags);
435 * of_ti_divider_clk_setup - Setup function for simple div rate clock
436 * @node: device node for this clock
438 * Sets up a basic divider clock.
440 static void __init of_ti_divider_clk_setup(struct device_node *node)
443 const char *parent_name;
445 u8 clk_divider_flags = 0;
448 const struct clk_div_table *table = NULL;
451 parent_name = of_clk_get_parent_name(node, 0);
453 if (ti_clk_divider_populate(node, ®, &table, &flags,
454 &clk_divider_flags, &width, &shift))
457 clk = _register_divider(NULL, node->name, parent_name, flags, reg,
458 shift, width, clk_divider_flags, table, NULL);
461 of_clk_add_provider(node, of_clk_src_simple_get, clk);
462 of_ti_clk_autoidle_setup(node);
469 CLK_OF_DECLARE(divider_clk, "ti,divider-clock", of_ti_divider_clk_setup);
471 static void __init of_ti_composite_divider_clk_setup(struct device_node *node)
473 struct clk_divider *div;
476 div = kzalloc(sizeof(*div), GFP_KERNEL);
480 if (ti_clk_divider_populate(node, &div->reg, &div->table, &val,
481 &div->flags, &div->width, &div->shift) < 0)
484 if (!ti_clk_add_component(node, &div->hw, CLK_COMPONENT_TYPE_DIVIDER))
491 CLK_OF_DECLARE(ti_composite_divider_clk, "ti,composite-divider-clock",
492 of_ti_composite_divider_clk_setup);