2 * OMAP DPLL clock support
4 * Copyright (C) 2013 Texas Instruments, Inc.
6 * Tero Kristo <t-kristo@ti.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
13 * kind, whether express or implied; without even the implied warranty
14 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
18 #include <linux/clk-provider.h>
19 #include <linux/slab.h>
20 #include <linux/err.h>
22 #include <linux/of_address.h>
23 #include <linux/clk/ti.h>
27 #define pr_fmt(fmt) "%s: " fmt, __func__
29 #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
30 defined(CONFIG_SOC_DRA7XX)
31 static const struct clk_ops dpll_m4xen_ck_ops = {
32 .enable = &omap3_noncore_dpll_enable,
33 .disable = &omap3_noncore_dpll_disable,
34 .recalc_rate = &omap4_dpll_regm4xen_recalc,
35 .round_rate = &omap4_dpll_regm4xen_round_rate,
36 .set_rate = &omap3_noncore_dpll_set_rate,
37 .set_parent = &omap3_noncore_dpll_set_parent,
38 .set_rate_and_parent = &omap3_noncore_dpll_set_rate_and_parent,
39 .determine_rate = &omap4_dpll_regm4xen_determine_rate,
40 .get_parent = &omap2_init_dpll_parent,
43 static const struct clk_ops dpll_m4xen_ck_ops = {};
46 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) || \
47 defined(CONFIG_SOC_OMAP5) || defined(CONFIG_SOC_DRA7XX) || \
48 defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)
49 static const struct clk_ops dpll_core_ck_ops = {
50 .recalc_rate = &omap3_dpll_recalc,
51 .get_parent = &omap2_init_dpll_parent,
54 static const struct clk_ops dpll_ck_ops = {
55 .enable = &omap3_noncore_dpll_enable,
56 .disable = &omap3_noncore_dpll_disable,
57 .recalc_rate = &omap3_dpll_recalc,
58 .round_rate = &omap2_dpll_round_rate,
59 .set_rate = &omap3_noncore_dpll_set_rate,
60 .set_parent = &omap3_noncore_dpll_set_parent,
61 .set_rate_and_parent = &omap3_noncore_dpll_set_rate_and_parent,
62 .determine_rate = &omap3_noncore_dpll_determine_rate,
63 .get_parent = &omap2_init_dpll_parent,
66 static const struct clk_ops dpll_no_gate_ck_ops = {
67 .recalc_rate = &omap3_dpll_recalc,
68 .get_parent = &omap2_init_dpll_parent,
69 .round_rate = &omap2_dpll_round_rate,
70 .set_rate = &omap3_noncore_dpll_set_rate,
71 .set_parent = &omap3_noncore_dpll_set_parent,
72 .set_rate_and_parent = &omap3_noncore_dpll_set_rate_and_parent,
73 .determine_rate = &omap3_noncore_dpll_determine_rate,
76 static const struct clk_ops dpll_core_ck_ops = {};
77 static const struct clk_ops dpll_ck_ops = {};
78 static const struct clk_ops dpll_no_gate_ck_ops = {};
79 const struct clk_hw_omap_ops clkhwops_omap3_dpll = {};
82 #ifdef CONFIG_ARCH_OMAP2
83 static const struct clk_ops omap2_dpll_core_ck_ops = {
84 .get_parent = &omap2_init_dpll_parent,
85 .recalc_rate = &omap2_dpllcore_recalc,
86 .round_rate = &omap2_dpll_round_rate,
87 .set_rate = &omap2_reprogram_dpllcore,
90 static const struct clk_ops omap2_dpll_core_ck_ops = {};
93 #ifdef CONFIG_ARCH_OMAP3
94 static const struct clk_ops omap3_dpll_core_ck_ops = {
95 .get_parent = &omap2_init_dpll_parent,
96 .recalc_rate = &omap3_dpll_recalc,
97 .round_rate = &omap2_dpll_round_rate,
100 static const struct clk_ops omap3_dpll_core_ck_ops = {};
103 #ifdef CONFIG_ARCH_OMAP3
104 static const struct clk_ops omap3_dpll_ck_ops = {
105 .enable = &omap3_noncore_dpll_enable,
106 .disable = &omap3_noncore_dpll_disable,
107 .get_parent = &omap2_init_dpll_parent,
108 .recalc_rate = &omap3_dpll_recalc,
109 .set_rate = &omap3_noncore_dpll_set_rate,
110 .set_parent = &omap3_noncore_dpll_set_parent,
111 .set_rate_and_parent = &omap3_noncore_dpll_set_rate_and_parent,
112 .determine_rate = &omap3_noncore_dpll_determine_rate,
113 .round_rate = &omap2_dpll_round_rate,
116 static const struct clk_ops omap3_dpll_per_ck_ops = {
117 .enable = &omap3_noncore_dpll_enable,
118 .disable = &omap3_noncore_dpll_disable,
119 .get_parent = &omap2_init_dpll_parent,
120 .recalc_rate = &omap3_dpll_recalc,
121 .set_rate = &omap3_dpll4_set_rate,
122 .set_parent = &omap3_noncore_dpll_set_parent,
123 .set_rate_and_parent = &omap3_dpll4_set_rate_and_parent,
124 .determine_rate = &omap3_noncore_dpll_determine_rate,
125 .round_rate = &omap2_dpll_round_rate,
129 static const struct clk_ops dpll_x2_ck_ops = {
130 .recalc_rate = &omap3_clkoutx2_recalc,
134 * _register_dpll - low level registration of a DPLL clock
135 * @hw: hardware clock definition for the clock
136 * @node: device node for the clock
138 * Finalizes DPLL registration process. In case a failure (clk-ref or
139 * clk-bypass is missing), the clock is added to retry list and
140 * the initialization is retried on later stage.
142 static void __init _register_dpll(struct clk_hw *hw,
143 struct device_node *node)
145 struct clk_hw_omap *clk_hw = to_clk_hw_omap(hw);
146 struct dpll_data *dd = clk_hw->dpll_data;
149 dd->clk_ref = of_clk_get(node, 0);
150 dd->clk_bypass = of_clk_get(node, 1);
152 if (IS_ERR(dd->clk_ref) || IS_ERR(dd->clk_bypass)) {
153 pr_debug("clk-ref or clk-bypass missing for %s, retry later\n",
155 if (!ti_clk_retry_init(node, hw, _register_dpll))
161 /* register the clock */
162 clk = clk_register(NULL, &clk_hw->hw);
165 omap2_init_clk_hw_omap_clocks(clk);
166 of_clk_add_provider(node, of_clk_src_simple_get, clk);
167 kfree(clk_hw->hw.init->parent_names);
168 kfree(clk_hw->hw.init);
173 kfree(clk_hw->dpll_data);
174 kfree(clk_hw->hw.init->parent_names);
175 kfree(clk_hw->hw.init);
179 #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_ATAGS)
180 void __iomem *_get_reg(u8 module, u16 offset)
183 struct clk_omap_reg *reg_setup;
185 reg_setup = (struct clk_omap_reg *)®
187 reg_setup->index = module;
188 reg_setup->offset = offset;
190 return (void __iomem *)reg;
193 struct clk *ti_clk_register_dpll(struct ti_clk *setup)
195 struct clk_hw_omap *clk_hw;
196 struct clk_init_data init = { NULL };
197 struct dpll_data *dd;
199 struct ti_clk_dpll *dpll;
200 const struct clk_ops *ops = &omap3_dpll_ck_ops;
202 struct clk *clk_bypass;
206 if (dpll->num_parents < 2)
207 return ERR_PTR(-EINVAL);
209 clk_ref = clk_get_sys(NULL, dpll->parents[0]);
210 clk_bypass = clk_get_sys(NULL, dpll->parents[1]);
212 if (IS_ERR_OR_NULL(clk_ref) || IS_ERR_OR_NULL(clk_bypass))
213 return ERR_PTR(-EAGAIN);
215 dd = kzalloc(sizeof(*dd), GFP_KERNEL);
216 clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
217 if (!dd || !clk_hw) {
218 clk = ERR_PTR(-ENOMEM);
222 clk_hw->dpll_data = dd;
223 clk_hw->ops = &clkhwops_omap3_dpll;
224 clk_hw->hw.init = &init;
225 clk_hw->flags = MEMMAP_ADDRESSING;
227 init.name = setup->name;
230 init.num_parents = dpll->num_parents;
231 init.parent_names = dpll->parents;
233 dd->control_reg = _get_reg(dpll->module, dpll->control_reg);
234 dd->idlest_reg = _get_reg(dpll->module, dpll->idlest_reg);
235 dd->mult_div1_reg = _get_reg(dpll->module, dpll->mult_div1_reg);
236 dd->autoidle_reg = _get_reg(dpll->module, dpll->autoidle_reg);
238 dd->modes = dpll->modes;
239 dd->div1_mask = dpll->div1_mask;
240 dd->idlest_mask = dpll->idlest_mask;
241 dd->mult_mask = dpll->mult_mask;
242 dd->autoidle_mask = dpll->autoidle_mask;
243 dd->enable_mask = dpll->enable_mask;
244 dd->sddiv_mask = dpll->sddiv_mask;
245 dd->dco_mask = dpll->dco_mask;
246 dd->max_divider = dpll->max_divider;
247 dd->min_divider = dpll->min_divider;
248 dd->max_multiplier = dpll->max_multiplier;
249 dd->auto_recal_bit = dpll->auto_recal_bit;
250 dd->recal_en_bit = dpll->recal_en_bit;
251 dd->recal_st_bit = dpll->recal_st_bit;
253 dd->clk_ref = clk_ref;
254 dd->clk_bypass = clk_bypass;
256 if (dpll->flags & CLKF_CORE)
257 ops = &omap3_dpll_core_ck_ops;
259 if (dpll->flags & CLKF_PER)
260 ops = &omap3_dpll_per_ck_ops;
262 if (dpll->flags & CLKF_J_TYPE)
263 dd->flags |= DPLL_J_TYPE;
265 clk = clk_register(NULL, &clk_hw->hw);
277 #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
278 defined(CONFIG_SOC_DRA7XX) || defined(CONFIG_SOC_AM33XX) || \
279 defined(CONFIG_SOC_AM43XX)
281 * _register_dpll_x2 - Registers a DPLLx2 clock
282 * @node: device node for this clock
283 * @ops: clk_ops for this clock
284 * @hw_ops: clk_hw_ops for this clock
286 * Initializes a DPLL x 2 clock from device tree data.
288 static void _register_dpll_x2(struct device_node *node,
289 const struct clk_ops *ops,
290 const struct clk_hw_omap_ops *hw_ops)
293 struct clk_init_data init = { NULL };
294 struct clk_hw_omap *clk_hw;
295 const char *name = node->name;
296 const char *parent_name;
298 parent_name = of_clk_get_parent_name(node, 0);
300 pr_err("%s must have parent\n", node->name);
304 clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
308 clk_hw->ops = hw_ops;
309 clk_hw->hw.init = &init;
313 init.parent_names = &parent_name;
314 init.num_parents = 1;
316 /* register the clock */
317 clk = clk_register(NULL, &clk_hw->hw);
322 omap2_init_clk_hw_omap_clocks(clk);
323 of_clk_add_provider(node, of_clk_src_simple_get, clk);
329 * of_ti_dpll_setup - Setup function for OMAP DPLL clocks
330 * @node: device node containing the DPLL info
331 * @ops: ops for the DPLL
332 * @ddt: DPLL data template to use
334 * Initializes a DPLL clock from device tree data.
336 static void __init of_ti_dpll_setup(struct device_node *node,
337 const struct clk_ops *ops,
338 const struct dpll_data *ddt)
340 struct clk_hw_omap *clk_hw = NULL;
341 struct clk_init_data *init = NULL;
342 const char **parent_names = NULL;
343 struct dpll_data *dd = NULL;
347 dd = kzalloc(sizeof(*dd), GFP_KERNEL);
348 clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
349 init = kzalloc(sizeof(*init), GFP_KERNEL);
350 if (!dd || !clk_hw || !init)
353 memcpy(dd, ddt, sizeof(*dd));
355 clk_hw->dpll_data = dd;
356 clk_hw->ops = &clkhwops_omap3_dpll;
357 clk_hw->hw.init = init;
358 clk_hw->flags = MEMMAP_ADDRESSING;
360 init->name = node->name;
363 init->num_parents = of_clk_get_parent_count(node);
364 if (init->num_parents < 1) {
365 pr_err("%s must have parent(s)\n", node->name);
369 parent_names = kzalloc(sizeof(char *) * init->num_parents, GFP_KERNEL);
373 for (i = 0; i < init->num_parents; i++)
374 parent_names[i] = of_clk_get_parent_name(node, i);
376 init->parent_names = parent_names;
378 dd->control_reg = ti_clk_get_reg_addr(node, 0);
381 * Special case for OMAP2 DPLL, register order is different due to
382 * missing idlest_reg, also clkhwops is different. Detected from
383 * missing idlest_mask.
385 if (!dd->idlest_mask) {
386 dd->mult_div1_reg = ti_clk_get_reg_addr(node, 1);
387 #ifdef CONFIG_ARCH_OMAP2
388 clk_hw->ops = &clkhwops_omap2xxx_dpll;
389 omap2xxx_clkt_dpllcore_init(&clk_hw->hw);
392 dd->idlest_reg = ti_clk_get_reg_addr(node, 1);
393 if (IS_ERR(dd->idlest_reg))
396 dd->mult_div1_reg = ti_clk_get_reg_addr(node, 2);
399 if (IS_ERR(dd->control_reg) || IS_ERR(dd->mult_div1_reg))
402 if (dd->autoidle_mask) {
403 dd->autoidle_reg = ti_clk_get_reg_addr(node, 3);
404 if (IS_ERR(dd->autoidle_reg))
408 if (of_property_read_bool(node, "ti,low-power-stop"))
409 dpll_mode |= 1 << DPLL_LOW_POWER_STOP;
411 if (of_property_read_bool(node, "ti,low-power-bypass"))
412 dpll_mode |= 1 << DPLL_LOW_POWER_BYPASS;
414 if (of_property_read_bool(node, "ti,lock"))
415 dpll_mode |= 1 << DPLL_LOCKED;
418 dd->modes = dpll_mode;
420 _register_dpll(&clk_hw->hw, node);
430 #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
431 defined(CONFIG_SOC_DRA7XX)
432 static void __init of_ti_omap4_dpll_x2_setup(struct device_node *node)
434 _register_dpll_x2(node, &dpll_x2_ck_ops, &clkhwops_omap4_dpllmx);
436 CLK_OF_DECLARE(ti_omap4_dpll_x2_clock, "ti,omap4-dpll-x2-clock",
437 of_ti_omap4_dpll_x2_setup);
440 #if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)
441 static void __init of_ti_am3_dpll_x2_setup(struct device_node *node)
443 _register_dpll_x2(node, &dpll_x2_ck_ops, NULL);
445 CLK_OF_DECLARE(ti_am3_dpll_x2_clock, "ti,am3-dpll-x2-clock",
446 of_ti_am3_dpll_x2_setup);
449 #ifdef CONFIG_ARCH_OMAP3
450 static void __init of_ti_omap3_dpll_setup(struct device_node *node)
452 const struct dpll_data dd = {
455 .autoidle_mask = 0x7,
456 .mult_mask = 0x7ff << 8,
458 .max_multiplier = 2047,
461 .freqsel_mask = 0xf0,
462 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
465 of_ti_dpll_setup(node, &omap3_dpll_ck_ops, &dd);
467 CLK_OF_DECLARE(ti_omap3_dpll_clock, "ti,omap3-dpll-clock",
468 of_ti_omap3_dpll_setup);
470 static void __init of_ti_omap3_core_dpll_setup(struct device_node *node)
472 const struct dpll_data dd = {
475 .autoidle_mask = 0x7,
476 .mult_mask = 0x7ff << 16,
477 .div1_mask = 0x7f << 8,
478 .max_multiplier = 2047,
481 .freqsel_mask = 0xf0,
484 of_ti_dpll_setup(node, &omap3_dpll_core_ck_ops, &dd);
486 CLK_OF_DECLARE(ti_omap3_core_dpll_clock, "ti,omap3-dpll-core-clock",
487 of_ti_omap3_core_dpll_setup);
489 static void __init of_ti_omap3_per_dpll_setup(struct device_node *node)
491 const struct dpll_data dd = {
492 .idlest_mask = 0x1 << 1,
493 .enable_mask = 0x7 << 16,
494 .autoidle_mask = 0x7 << 3,
495 .mult_mask = 0x7ff << 8,
497 .max_multiplier = 2047,
500 .freqsel_mask = 0xf00000,
501 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
504 of_ti_dpll_setup(node, &omap3_dpll_per_ck_ops, &dd);
506 CLK_OF_DECLARE(ti_omap3_per_dpll_clock, "ti,omap3-dpll-per-clock",
507 of_ti_omap3_per_dpll_setup);
509 static void __init of_ti_omap3_per_jtype_dpll_setup(struct device_node *node)
511 const struct dpll_data dd = {
512 .idlest_mask = 0x1 << 1,
513 .enable_mask = 0x7 << 16,
514 .autoidle_mask = 0x7 << 3,
515 .mult_mask = 0xfff << 8,
517 .max_multiplier = 4095,
520 .sddiv_mask = 0xff << 24,
521 .dco_mask = 0xe << 20,
522 .flags = DPLL_J_TYPE,
523 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
526 of_ti_dpll_setup(node, &omap3_dpll_per_ck_ops, &dd);
528 CLK_OF_DECLARE(ti_omap3_per_jtype_dpll_clock, "ti,omap3-dpll-per-j-type-clock",
529 of_ti_omap3_per_jtype_dpll_setup);
532 static void __init of_ti_omap4_dpll_setup(struct device_node *node)
534 const struct dpll_data dd = {
537 .autoidle_mask = 0x7,
538 .mult_mask = 0x7ff << 8,
540 .max_multiplier = 2047,
543 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
546 of_ti_dpll_setup(node, &dpll_ck_ops, &dd);
548 CLK_OF_DECLARE(ti_omap4_dpll_clock, "ti,omap4-dpll-clock",
549 of_ti_omap4_dpll_setup);
551 static void __init of_ti_omap5_mpu_dpll_setup(struct device_node *node)
553 const struct dpll_data dd = {
556 .autoidle_mask = 0x7,
557 .mult_mask = 0x7ff << 8,
559 .max_multiplier = 2047,
562 .dcc_rate = 1400000000, /* DCC beyond 1.4GHz */
564 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
567 of_ti_dpll_setup(node, &dpll_ck_ops, &dd);
569 CLK_OF_DECLARE(of_ti_omap5_mpu_dpll_clock, "ti,omap5-mpu-dpll-clock",
570 of_ti_omap5_mpu_dpll_setup);
572 static void __init of_ti_omap4_core_dpll_setup(struct device_node *node)
574 const struct dpll_data dd = {
577 .autoidle_mask = 0x7,
578 .mult_mask = 0x7ff << 8,
580 .max_multiplier = 2047,
583 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
586 of_ti_dpll_setup(node, &dpll_core_ck_ops, &dd);
588 CLK_OF_DECLARE(ti_omap4_core_dpll_clock, "ti,omap4-dpll-core-clock",
589 of_ti_omap4_core_dpll_setup);
591 #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
592 defined(CONFIG_SOC_DRA7XX)
593 static void __init of_ti_omap4_m4xen_dpll_setup(struct device_node *node)
595 const struct dpll_data dd = {
598 .autoidle_mask = 0x7,
599 .mult_mask = 0x7ff << 8,
601 .max_multiplier = 2047,
605 .lpmode_mask = 1 << 10,
606 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
609 of_ti_dpll_setup(node, &dpll_m4xen_ck_ops, &dd);
611 CLK_OF_DECLARE(ti_omap4_m4xen_dpll_clock, "ti,omap4-dpll-m4xen-clock",
612 of_ti_omap4_m4xen_dpll_setup);
614 static void __init of_ti_omap4_jtype_dpll_setup(struct device_node *node)
616 const struct dpll_data dd = {
619 .autoidle_mask = 0x7,
620 .mult_mask = 0xfff << 8,
622 .max_multiplier = 4095,
625 .sddiv_mask = 0xff << 24,
626 .flags = DPLL_J_TYPE,
627 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
630 of_ti_dpll_setup(node, &dpll_m4xen_ck_ops, &dd);
632 CLK_OF_DECLARE(ti_omap4_jtype_dpll_clock, "ti,omap4-dpll-j-type-clock",
633 of_ti_omap4_jtype_dpll_setup);
636 static void __init of_ti_am3_no_gate_dpll_setup(struct device_node *node)
638 const struct dpll_data dd = {
641 .mult_mask = 0x7ff << 8,
643 .max_multiplier = 2047,
646 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
649 of_ti_dpll_setup(node, &dpll_no_gate_ck_ops, &dd);
651 CLK_OF_DECLARE(ti_am3_no_gate_dpll_clock, "ti,am3-dpll-no-gate-clock",
652 of_ti_am3_no_gate_dpll_setup);
654 static void __init of_ti_am3_jtype_dpll_setup(struct device_node *node)
656 const struct dpll_data dd = {
659 .mult_mask = 0x7ff << 8,
661 .max_multiplier = 4095,
664 .flags = DPLL_J_TYPE,
665 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
668 of_ti_dpll_setup(node, &dpll_ck_ops, &dd);
670 CLK_OF_DECLARE(ti_am3_jtype_dpll_clock, "ti,am3-dpll-j-type-clock",
671 of_ti_am3_jtype_dpll_setup);
673 static void __init of_ti_am3_no_gate_jtype_dpll_setup(struct device_node *node)
675 const struct dpll_data dd = {
678 .mult_mask = 0x7ff << 8,
680 .max_multiplier = 2047,
683 .flags = DPLL_J_TYPE,
684 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
687 of_ti_dpll_setup(node, &dpll_no_gate_ck_ops, &dd);
689 CLK_OF_DECLARE(ti_am3_no_gate_jtype_dpll_clock,
690 "ti,am3-dpll-no-gate-j-type-clock",
691 of_ti_am3_no_gate_jtype_dpll_setup);
693 static void __init of_ti_am3_dpll_setup(struct device_node *node)
695 const struct dpll_data dd = {
698 .mult_mask = 0x7ff << 8,
700 .max_multiplier = 2047,
703 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
706 of_ti_dpll_setup(node, &dpll_ck_ops, &dd);
708 CLK_OF_DECLARE(ti_am3_dpll_clock, "ti,am3-dpll-clock", of_ti_am3_dpll_setup);
710 static void __init of_ti_am3_core_dpll_setup(struct device_node *node)
712 const struct dpll_data dd = {
715 .mult_mask = 0x7ff << 8,
717 .max_multiplier = 2047,
720 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
723 of_ti_dpll_setup(node, &dpll_core_ck_ops, &dd);
725 CLK_OF_DECLARE(ti_am3_core_dpll_clock, "ti,am3-dpll-core-clock",
726 of_ti_am3_core_dpll_setup);
728 static void __init of_ti_omap2_core_dpll_setup(struct device_node *node)
730 const struct dpll_data dd = {
732 .mult_mask = 0x3ff << 12,
733 .div1_mask = 0xf << 8,
738 of_ti_dpll_setup(node, &omap2_dpll_core_ck_ops, &dd);
740 CLK_OF_DECLARE(ti_omap2_core_dpll_clock, "ti,omap2-dpll-core-clock",
741 of_ti_omap2_core_dpll_setup);