2 * OMAP DPLL clock support
4 * Copyright (C) 2013 Texas Instruments, Inc.
6 * Tero Kristo <t-kristo@ti.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
13 * kind, whether express or implied; without even the implied warranty
14 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
18 #include <linux/clk-provider.h>
19 #include <linux/slab.h>
20 #include <linux/err.h>
22 #include <linux/of_address.h>
23 #include <linux/clk/ti.h>
26 #define pr_fmt(fmt) "%s: " fmt, __func__
28 #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
29 defined(CONFIG_SOC_DRA7XX)
30 static const struct clk_ops dpll_m4xen_ck_ops = {
31 .enable = &omap3_noncore_dpll_enable,
32 .disable = &omap3_noncore_dpll_disable,
33 .recalc_rate = &omap4_dpll_regm4xen_recalc,
34 .round_rate = &omap4_dpll_regm4xen_round_rate,
35 .set_rate = &omap3_noncore_dpll_set_rate,
36 .get_parent = &omap2_init_dpll_parent,
39 static const struct clk_ops dpll_m4xen_ck_ops = {};
42 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) || \
43 defined(CONFIG_SOC_OMAP5) || defined(CONFIG_SOC_DRA7XX) || \
44 defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)
45 static const struct clk_ops dpll_core_ck_ops = {
46 .recalc_rate = &omap3_dpll_recalc,
47 .get_parent = &omap2_init_dpll_parent,
50 static const struct clk_ops dpll_ck_ops = {
51 .enable = &omap3_noncore_dpll_enable,
52 .disable = &omap3_noncore_dpll_disable,
53 .recalc_rate = &omap3_dpll_recalc,
54 .round_rate = &omap2_dpll_round_rate,
55 .set_rate = &omap3_noncore_dpll_set_rate,
56 .get_parent = &omap2_init_dpll_parent,
59 static const struct clk_ops dpll_no_gate_ck_ops = {
60 .recalc_rate = &omap3_dpll_recalc,
61 .get_parent = &omap2_init_dpll_parent,
62 .round_rate = &omap2_dpll_round_rate,
63 .set_rate = &omap3_noncore_dpll_set_rate,
66 static const struct clk_ops dpll_core_ck_ops = {};
67 static const struct clk_ops dpll_ck_ops = {};
68 static const struct clk_ops dpll_no_gate_ck_ops = {};
69 const struct clk_hw_omap_ops clkhwops_omap3_dpll = {};
72 #ifdef CONFIG_ARCH_OMAP2
73 static const struct clk_ops omap2_dpll_core_ck_ops = {
74 .get_parent = &omap2_init_dpll_parent,
75 .recalc_rate = &omap2_dpllcore_recalc,
76 .round_rate = &omap2_dpll_round_rate,
77 .set_rate = &omap2_reprogram_dpllcore,
80 static const struct clk_ops omap2_dpll_core_ck_ops = {};
83 #ifdef CONFIG_ARCH_OMAP3
84 static const struct clk_ops omap3_dpll_core_ck_ops = {
85 .get_parent = &omap2_init_dpll_parent,
86 .recalc_rate = &omap3_dpll_recalc,
87 .round_rate = &omap2_dpll_round_rate,
90 static const struct clk_ops omap3_dpll_core_ck_ops = {};
93 #ifdef CONFIG_ARCH_OMAP3
94 static const struct clk_ops omap3_dpll_ck_ops = {
95 .enable = &omap3_noncore_dpll_enable,
96 .disable = &omap3_noncore_dpll_disable,
97 .get_parent = &omap2_init_dpll_parent,
98 .recalc_rate = &omap3_dpll_recalc,
99 .set_rate = &omap3_noncore_dpll_set_rate,
100 .round_rate = &omap2_dpll_round_rate,
103 static const struct clk_ops omap3_dpll_per_ck_ops = {
104 .enable = &omap3_noncore_dpll_enable,
105 .disable = &omap3_noncore_dpll_disable,
106 .get_parent = &omap2_init_dpll_parent,
107 .recalc_rate = &omap3_dpll_recalc,
108 .set_rate = &omap3_dpll4_set_rate,
109 .round_rate = &omap2_dpll_round_rate,
113 static const struct clk_ops dpll_x2_ck_ops = {
114 .recalc_rate = &omap3_clkoutx2_recalc,
118 * ti_clk_register_dpll - low level registration of a DPLL clock
119 * @hw: hardware clock definition for the clock
120 * @node: device node for the clock
122 * Finalizes DPLL registration process. In case a failure (clk-ref or
123 * clk-bypass is missing), the clock is added to retry list and
124 * the initialization is retried on later stage.
126 static void __init ti_clk_register_dpll(struct clk_hw *hw,
127 struct device_node *node)
129 struct clk_hw_omap *clk_hw = to_clk_hw_omap(hw);
130 struct dpll_data *dd = clk_hw->dpll_data;
133 dd->clk_ref = of_clk_get(node, 0);
134 dd->clk_bypass = of_clk_get(node, 1);
136 if (IS_ERR(dd->clk_ref) || IS_ERR(dd->clk_bypass)) {
137 pr_debug("clk-ref or clk-bypass missing for %s, retry later\n",
139 if (!ti_clk_retry_init(node, hw, ti_clk_register_dpll))
145 /* register the clock */
146 clk = clk_register(NULL, &clk_hw->hw);
149 omap2_init_clk_hw_omap_clocks(clk);
150 of_clk_add_provider(node, of_clk_src_simple_get, clk);
151 kfree(clk_hw->hw.init->parent_names);
152 kfree(clk_hw->hw.init);
157 kfree(clk_hw->dpll_data);
158 kfree(clk_hw->hw.init->parent_names);
159 kfree(clk_hw->hw.init);
163 #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
164 defined(CONFIG_SOC_DRA7XX) || defined(CONFIG_SOC_AM33XX) || \
165 defined(CONFIG_SOC_AM43XX)
167 * ti_clk_register_dpll_x2 - Registers a DPLLx2 clock
168 * @node: device node for this clock
169 * @ops: clk_ops for this clock
170 * @hw_ops: clk_hw_ops for this clock
172 * Initializes a DPLL x 2 clock from device tree data.
174 static void ti_clk_register_dpll_x2(struct device_node *node,
175 const struct clk_ops *ops,
176 const struct clk_hw_omap_ops *hw_ops)
179 struct clk_init_data init = { NULL };
180 struct clk_hw_omap *clk_hw;
181 const char *name = node->name;
182 const char *parent_name;
184 parent_name = of_clk_get_parent_name(node, 0);
186 pr_err("%s must have parent\n", node->name);
190 clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
194 clk_hw->ops = hw_ops;
195 clk_hw->hw.init = &init;
199 init.parent_names = &parent_name;
200 init.num_parents = 1;
202 /* register the clock */
203 clk = clk_register(NULL, &clk_hw->hw);
208 omap2_init_clk_hw_omap_clocks(clk);
209 of_clk_add_provider(node, of_clk_src_simple_get, clk);
215 * of_ti_dpll_setup - Setup function for OMAP DPLL clocks
216 * @node: device node containing the DPLL info
217 * @ops: ops for the DPLL
218 * @ddt: DPLL data template to use
220 * Initializes a DPLL clock from device tree data.
222 static void __init of_ti_dpll_setup(struct device_node *node,
223 const struct clk_ops *ops,
224 const struct dpll_data *ddt)
226 struct clk_hw_omap *clk_hw = NULL;
227 struct clk_init_data *init = NULL;
228 const char **parent_names = NULL;
229 struct dpll_data *dd = NULL;
233 dd = kzalloc(sizeof(*dd), GFP_KERNEL);
234 clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
235 init = kzalloc(sizeof(*init), GFP_KERNEL);
236 if (!dd || !clk_hw || !init)
239 memcpy(dd, ddt, sizeof(*dd));
241 clk_hw->dpll_data = dd;
242 clk_hw->ops = &clkhwops_omap3_dpll;
243 clk_hw->hw.init = init;
244 clk_hw->flags = MEMMAP_ADDRESSING;
246 init->name = node->name;
249 init->num_parents = of_clk_get_parent_count(node);
250 if (init->num_parents < 1) {
251 pr_err("%s must have parent(s)\n", node->name);
255 parent_names = kzalloc(sizeof(char *) * init->num_parents, GFP_KERNEL);
259 for (i = 0; i < init->num_parents; i++)
260 parent_names[i] = of_clk_get_parent_name(node, i);
262 init->parent_names = parent_names;
264 dd->control_reg = ti_clk_get_reg_addr(node, 0);
267 * Special case for OMAP2 DPLL, register order is different due to
268 * missing idlest_reg, also clkhwops is different. Detected from
269 * missing idlest_mask.
271 if (!dd->idlest_mask) {
272 dd->mult_div1_reg = ti_clk_get_reg_addr(node, 1);
273 #ifdef CONFIG_ARCH_OMAP2
274 clk_hw->ops = &clkhwops_omap2xxx_dpll;
275 omap2xxx_clkt_dpllcore_init(&clk_hw->hw);
278 dd->idlest_reg = ti_clk_get_reg_addr(node, 1);
282 dd->mult_div1_reg = ti_clk_get_reg_addr(node, 2);
285 if (!dd->control_reg || !dd->mult_div1_reg)
288 if (dd->autoidle_mask) {
289 dd->autoidle_reg = ti_clk_get_reg_addr(node, 3);
290 if (!dd->autoidle_reg)
294 if (of_property_read_bool(node, "ti,low-power-stop"))
295 dpll_mode |= 1 << DPLL_LOW_POWER_STOP;
297 if (of_property_read_bool(node, "ti,low-power-bypass"))
298 dpll_mode |= 1 << DPLL_LOW_POWER_BYPASS;
300 if (of_property_read_bool(node, "ti,lock"))
301 dpll_mode |= 1 << DPLL_LOCKED;
304 dd->modes = dpll_mode;
306 ti_clk_register_dpll(&clk_hw->hw, node);
316 #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
317 defined(CONFIG_SOC_DRA7XX)
318 static void __init of_ti_omap4_dpll_x2_setup(struct device_node *node)
320 ti_clk_register_dpll_x2(node, &dpll_x2_ck_ops, &clkhwops_omap4_dpllmx);
322 CLK_OF_DECLARE(ti_omap4_dpll_x2_clock, "ti,omap4-dpll-x2-clock",
323 of_ti_omap4_dpll_x2_setup);
326 #if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)
327 static void __init of_ti_am3_dpll_x2_setup(struct device_node *node)
329 ti_clk_register_dpll_x2(node, &dpll_x2_ck_ops, NULL);
331 CLK_OF_DECLARE(ti_am3_dpll_x2_clock, "ti,am3-dpll-x2-clock",
332 of_ti_am3_dpll_x2_setup);
335 #ifdef CONFIG_ARCH_OMAP3
336 static void __init of_ti_omap3_dpll_setup(struct device_node *node)
338 const struct dpll_data dd = {
341 .autoidle_mask = 0x7,
342 .mult_mask = 0x7ff << 8,
344 .max_multiplier = 2047,
347 .freqsel_mask = 0xf0,
348 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
351 of_ti_dpll_setup(node, &omap3_dpll_ck_ops, &dd);
353 CLK_OF_DECLARE(ti_omap3_dpll_clock, "ti,omap3-dpll-clock",
354 of_ti_omap3_dpll_setup);
356 static void __init of_ti_omap3_core_dpll_setup(struct device_node *node)
358 const struct dpll_data dd = {
361 .autoidle_mask = 0x7,
362 .mult_mask = 0x7ff << 16,
363 .div1_mask = 0x7f << 8,
364 .max_multiplier = 2047,
367 .freqsel_mask = 0xf0,
370 of_ti_dpll_setup(node, &omap3_dpll_core_ck_ops, &dd);
372 CLK_OF_DECLARE(ti_omap3_core_dpll_clock, "ti,omap3-dpll-core-clock",
373 of_ti_omap3_core_dpll_setup);
375 static void __init of_ti_omap3_per_dpll_setup(struct device_node *node)
377 const struct dpll_data dd = {
378 .idlest_mask = 0x1 << 1,
379 .enable_mask = 0x7 << 16,
380 .autoidle_mask = 0x7 << 3,
381 .mult_mask = 0x7ff << 8,
383 .max_multiplier = 2047,
386 .freqsel_mask = 0xf00000,
387 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
390 of_ti_dpll_setup(node, &omap3_dpll_per_ck_ops, &dd);
392 CLK_OF_DECLARE(ti_omap3_per_dpll_clock, "ti,omap3-dpll-per-clock",
393 of_ti_omap3_per_dpll_setup);
395 static void __init of_ti_omap3_per_jtype_dpll_setup(struct device_node *node)
397 const struct dpll_data dd = {
398 .idlest_mask = 0x1 << 1,
399 .enable_mask = 0x7 << 16,
400 .autoidle_mask = 0x7 << 3,
401 .mult_mask = 0xfff << 8,
403 .max_multiplier = 4095,
406 .sddiv_mask = 0xff << 24,
407 .dco_mask = 0xe << 20,
408 .flags = DPLL_J_TYPE,
409 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
412 of_ti_dpll_setup(node, &omap3_dpll_per_ck_ops, &dd);
414 CLK_OF_DECLARE(ti_omap3_per_jtype_dpll_clock, "ti,omap3-dpll-per-j-type-clock",
415 of_ti_omap3_per_jtype_dpll_setup);
418 static void __init of_ti_omap4_dpll_setup(struct device_node *node)
420 const struct dpll_data dd = {
423 .autoidle_mask = 0x7,
424 .mult_mask = 0x7ff << 8,
426 .max_multiplier = 2047,
429 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
432 of_ti_dpll_setup(node, &dpll_ck_ops, &dd);
434 CLK_OF_DECLARE(ti_omap4_dpll_clock, "ti,omap4-dpll-clock",
435 of_ti_omap4_dpll_setup);
437 static void __init of_ti_omap5_mpu_dpll_setup(struct device_node *node)
439 const struct dpll_data dd = {
442 .autoidle_mask = 0x7,
443 .mult_mask = 0x7ff << 8,
445 .max_multiplier = 2047,
448 .dcc_rate = 1400000000, /* DCC beyond 1.4GHz */
450 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
453 of_ti_dpll_setup(node, &dpll_ck_ops, &dd);
455 CLK_OF_DECLARE(of_ti_omap5_mpu_dpll_clock, "ti,omap5-mpu-dpll-clock",
456 of_ti_omap5_mpu_dpll_setup);
458 static void __init of_ti_omap4_core_dpll_setup(struct device_node *node)
460 const struct dpll_data dd = {
463 .autoidle_mask = 0x7,
464 .mult_mask = 0x7ff << 8,
466 .max_multiplier = 2047,
469 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
472 of_ti_dpll_setup(node, &dpll_core_ck_ops, &dd);
474 CLK_OF_DECLARE(ti_omap4_core_dpll_clock, "ti,omap4-dpll-core-clock",
475 of_ti_omap4_core_dpll_setup);
477 #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
478 defined(CONFIG_SOC_DRA7XX)
479 static void __init of_ti_omap4_m4xen_dpll_setup(struct device_node *node)
481 const struct dpll_data dd = {
484 .autoidle_mask = 0x7,
485 .mult_mask = 0x7ff << 8,
487 .max_multiplier = 2047,
491 .lpmode_mask = 1 << 10,
492 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
495 of_ti_dpll_setup(node, &dpll_m4xen_ck_ops, &dd);
497 CLK_OF_DECLARE(ti_omap4_m4xen_dpll_clock, "ti,omap4-dpll-m4xen-clock",
498 of_ti_omap4_m4xen_dpll_setup);
500 static void __init of_ti_omap4_jtype_dpll_setup(struct device_node *node)
502 const struct dpll_data dd = {
505 .autoidle_mask = 0x7,
506 .mult_mask = 0xfff << 8,
508 .max_multiplier = 4095,
511 .sddiv_mask = 0xff << 24,
512 .flags = DPLL_J_TYPE,
513 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
516 of_ti_dpll_setup(node, &dpll_m4xen_ck_ops, &dd);
518 CLK_OF_DECLARE(ti_omap4_jtype_dpll_clock, "ti,omap4-dpll-j-type-clock",
519 of_ti_omap4_jtype_dpll_setup);
522 static void __init of_ti_am3_no_gate_dpll_setup(struct device_node *node)
524 const struct dpll_data dd = {
527 .mult_mask = 0x7ff << 8,
529 .max_multiplier = 2047,
532 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
535 of_ti_dpll_setup(node, &dpll_no_gate_ck_ops, &dd);
537 CLK_OF_DECLARE(ti_am3_no_gate_dpll_clock, "ti,am3-dpll-no-gate-clock",
538 of_ti_am3_no_gate_dpll_setup);
540 static void __init of_ti_am3_jtype_dpll_setup(struct device_node *node)
542 const struct dpll_data dd = {
545 .mult_mask = 0x7ff << 8,
547 .max_multiplier = 4095,
550 .flags = DPLL_J_TYPE,
551 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
554 of_ti_dpll_setup(node, &dpll_ck_ops, &dd);
556 CLK_OF_DECLARE(ti_am3_jtype_dpll_clock, "ti,am3-dpll-j-type-clock",
557 of_ti_am3_jtype_dpll_setup);
559 static void __init of_ti_am3_no_gate_jtype_dpll_setup(struct device_node *node)
561 const struct dpll_data dd = {
564 .mult_mask = 0x7ff << 8,
566 .max_multiplier = 2047,
569 .flags = DPLL_J_TYPE,
570 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
573 of_ti_dpll_setup(node, &dpll_no_gate_ck_ops, &dd);
575 CLK_OF_DECLARE(ti_am3_no_gate_jtype_dpll_clock,
576 "ti,am3-dpll-no-gate-j-type-clock",
577 of_ti_am3_no_gate_jtype_dpll_setup);
579 static void __init of_ti_am3_dpll_setup(struct device_node *node)
581 const struct dpll_data dd = {
584 .mult_mask = 0x7ff << 8,
586 .max_multiplier = 2047,
589 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
592 of_ti_dpll_setup(node, &dpll_ck_ops, &dd);
594 CLK_OF_DECLARE(ti_am3_dpll_clock, "ti,am3-dpll-clock", of_ti_am3_dpll_setup);
596 static void __init of_ti_am3_core_dpll_setup(struct device_node *node)
598 const struct dpll_data dd = {
601 .mult_mask = 0x7ff << 8,
603 .max_multiplier = 2047,
606 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
609 of_ti_dpll_setup(node, &dpll_core_ck_ops, &dd);
611 CLK_OF_DECLARE(ti_am3_core_dpll_clock, "ti,am3-dpll-core-clock",
612 of_ti_am3_core_dpll_setup);
614 static void __init of_ti_omap2_core_dpll_setup(struct device_node *node)
616 const struct dpll_data dd = {
618 .mult_mask = 0x3ff << 12,
619 .div1_mask = 0xf << 8,
624 of_ti_dpll_setup(node, &omap2_dpll_core_ck_ops, &dd);
626 CLK_OF_DECLARE(ti_omap2_core_dpll_clock, "ti,omap2-dpll-core-clock",
627 of_ti_omap2_core_dpll_setup);