2 * OMAP DPLL clock support
4 * Copyright (C) 2013 Texas Instruments, Inc.
6 * Tero Kristo <t-kristo@ti.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
13 * kind, whether express or implied; without even the implied warranty
14 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
18 #include <linux/clk-provider.h>
19 #include <linux/slab.h>
20 #include <linux/err.h>
22 #include <linux/of_address.h>
23 #include <linux/clk/ti.h>
26 #define pr_fmt(fmt) "%s: " fmt, __func__
28 #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
29 defined(CONFIG_SOC_DRA7XX)
30 static const struct clk_ops dpll_m4xen_ck_ops = {
31 .enable = &omap3_noncore_dpll_enable,
32 .disable = &omap3_noncore_dpll_disable,
33 .recalc_rate = &omap4_dpll_regm4xen_recalc,
34 .round_rate = &omap4_dpll_regm4xen_round_rate,
35 .set_rate = &omap3_noncore_dpll_set_rate,
36 .get_parent = &omap2_init_dpll_parent,
39 static const struct clk_ops dpll_m4xen_ck_ops = {};
42 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) || \
43 defined(CONFIG_SOC_OMAP5) || defined(CONFIG_SOC_DRA7XX) || \
44 defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)
45 static const struct clk_ops dpll_core_ck_ops = {
46 .recalc_rate = &omap3_dpll_recalc,
47 .get_parent = &omap2_init_dpll_parent,
50 static const struct clk_ops dpll_ck_ops = {
51 .enable = &omap3_noncore_dpll_enable,
52 .disable = &omap3_noncore_dpll_disable,
53 .recalc_rate = &omap3_dpll_recalc,
54 .round_rate = &omap2_dpll_round_rate,
55 .set_rate = &omap3_noncore_dpll_set_rate,
56 .get_parent = &omap2_init_dpll_parent,
59 static const struct clk_ops dpll_no_gate_ck_ops = {
60 .recalc_rate = &omap3_dpll_recalc,
61 .get_parent = &omap2_init_dpll_parent,
62 .round_rate = &omap2_dpll_round_rate,
63 .set_rate = &omap3_noncore_dpll_set_rate,
66 static const struct clk_ops dpll_core_ck_ops = {};
67 static const struct clk_ops dpll_ck_ops = {};
68 static const struct clk_ops dpll_no_gate_ck_ops = {};
69 const struct clk_hw_omap_ops clkhwops_omap3_dpll = {};
72 #ifdef CONFIG_ARCH_OMAP2
73 static const struct clk_ops omap2_dpll_core_ck_ops = {
74 .get_parent = &omap2_init_dpll_parent,
75 .recalc_rate = &omap2_dpllcore_recalc,
76 .round_rate = &omap2_dpll_round_rate,
77 .set_rate = &omap2_reprogram_dpllcore,
80 static const struct clk_ops omap2_dpll_core_ck_ops = {};
83 #ifdef CONFIG_ARCH_OMAP3
84 static const struct clk_ops omap3_dpll_core_ck_ops = {
85 .get_parent = &omap2_init_dpll_parent,
86 .recalc_rate = &omap3_dpll_recalc,
87 .round_rate = &omap2_dpll_round_rate,
90 static const struct clk_ops omap3_dpll_core_ck_ops = {};
93 #ifdef CONFIG_ARCH_OMAP3
94 static const struct clk_ops omap3_dpll_ck_ops = {
95 .enable = &omap3_noncore_dpll_enable,
96 .disable = &omap3_noncore_dpll_disable,
97 .get_parent = &omap2_init_dpll_parent,
98 .recalc_rate = &omap3_dpll_recalc,
99 .set_rate = &omap3_noncore_dpll_set_rate,
100 .round_rate = &omap2_dpll_round_rate,
103 static const struct clk_ops omap3_dpll_per_ck_ops = {
104 .enable = &omap3_noncore_dpll_enable,
105 .disable = &omap3_noncore_dpll_disable,
106 .get_parent = &omap2_init_dpll_parent,
107 .recalc_rate = &omap3_dpll_recalc,
108 .set_rate = &omap3_dpll4_set_rate,
109 .round_rate = &omap2_dpll_round_rate,
113 static const struct clk_ops dpll_x2_ck_ops = {
114 .recalc_rate = &omap3_clkoutx2_recalc,
118 * ti_clk_register_dpll - low level registration of a DPLL clock
119 * @hw: hardware clock definition for the clock
120 * @node: device node for the clock
122 * Finalizes DPLL registration process. In case a failure (clk-ref or
123 * clk-bypass is missing), the clock is added to retry list and
124 * the initialization is retried on later stage.
126 static void __init ti_clk_register_dpll(struct clk_hw *hw,
127 struct device_node *node)
129 struct clk_hw_omap *clk_hw = to_clk_hw_omap(hw);
130 struct dpll_data *dd = clk_hw->dpll_data;
133 dd->clk_ref = of_clk_get(node, 0);
134 dd->clk_bypass = of_clk_get(node, 1);
136 if (IS_ERR(dd->clk_ref) || IS_ERR(dd->clk_bypass)) {
137 pr_debug("clk-ref or clk-bypass missing for %s, retry later\n",
139 if (!ti_clk_retry_init(node, hw, ti_clk_register_dpll))
145 /* register the clock */
146 clk = clk_register(NULL, &clk_hw->hw);
149 omap2_init_clk_hw_omap_clocks(clk);
150 of_clk_add_provider(node, of_clk_src_simple_get, clk);
151 kfree(clk_hw->hw.init->parent_names);
152 kfree(clk_hw->hw.init);
157 kfree(clk_hw->dpll_data);
158 kfree(clk_hw->hw.init->parent_names);
159 kfree(clk_hw->hw.init);
163 #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
164 defined(CONFIG_SOC_DRA7XX) || defined(CONFIG_SOC_AM33XX)
166 * ti_clk_register_dpll_x2 - Registers a DPLLx2 clock
167 * @node: device node for this clock
168 * @ops: clk_ops for this clock
169 * @hw_ops: clk_hw_ops for this clock
171 * Initializes a DPLL x 2 clock from device tree data.
173 static void ti_clk_register_dpll_x2(struct device_node *node,
174 const struct clk_ops *ops,
175 const struct clk_hw_omap_ops *hw_ops)
178 struct clk_init_data init = { NULL };
179 struct clk_hw_omap *clk_hw;
180 const char *name = node->name;
181 const char *parent_name;
183 parent_name = of_clk_get_parent_name(node, 0);
185 pr_err("%s must have parent\n", node->name);
189 clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
193 clk_hw->ops = hw_ops;
194 clk_hw->hw.init = &init;
198 init.parent_names = &parent_name;
199 init.num_parents = 1;
201 /* register the clock */
202 clk = clk_register(NULL, &clk_hw->hw);
207 omap2_init_clk_hw_omap_clocks(clk);
208 of_clk_add_provider(node, of_clk_src_simple_get, clk);
214 * of_ti_dpll_setup - Setup function for OMAP DPLL clocks
215 * @node: device node containing the DPLL info
216 * @ops: ops for the DPLL
217 * @ddt: DPLL data template to use
219 * Initializes a DPLL clock from device tree data.
221 static void __init of_ti_dpll_setup(struct device_node *node,
222 const struct clk_ops *ops,
223 const struct dpll_data *ddt)
225 struct clk_hw_omap *clk_hw = NULL;
226 struct clk_init_data *init = NULL;
227 const char **parent_names = NULL;
228 struct dpll_data *dd = NULL;
232 dd = kzalloc(sizeof(*dd), GFP_KERNEL);
233 clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
234 init = kzalloc(sizeof(*init), GFP_KERNEL);
235 if (!dd || !clk_hw || !init)
238 memcpy(dd, ddt, sizeof(*dd));
240 clk_hw->dpll_data = dd;
241 clk_hw->ops = &clkhwops_omap3_dpll;
242 clk_hw->hw.init = init;
243 clk_hw->flags = MEMMAP_ADDRESSING;
245 init->name = node->name;
248 init->num_parents = of_clk_get_parent_count(node);
249 if (init->num_parents < 1) {
250 pr_err("%s must have parent(s)\n", node->name);
254 parent_names = kzalloc(sizeof(char *) * init->num_parents, GFP_KERNEL);
258 for (i = 0; i < init->num_parents; i++)
259 parent_names[i] = of_clk_get_parent_name(node, i);
261 init->parent_names = parent_names;
263 dd->control_reg = ti_clk_get_reg_addr(node, 0);
266 * Special case for OMAP2 DPLL, register order is different due to
267 * missing idlest_reg, also clkhwops is different. Detected from
268 * missing idlest_mask.
270 if (!dd->idlest_mask) {
271 dd->mult_div1_reg = ti_clk_get_reg_addr(node, 1);
272 #ifdef CONFIG_ARCH_OMAP2
273 clk_hw->ops = &clkhwops_omap2xxx_dpll;
274 omap2xxx_clkt_dpllcore_init(&clk_hw->hw);
277 dd->idlest_reg = ti_clk_get_reg_addr(node, 1);
281 dd->mult_div1_reg = ti_clk_get_reg_addr(node, 2);
284 if (!dd->control_reg || !dd->mult_div1_reg)
287 if (dd->autoidle_mask) {
288 dd->autoidle_reg = ti_clk_get_reg_addr(node, 3);
289 if (!dd->autoidle_reg)
293 if (of_property_read_bool(node, "ti,low-power-stop"))
294 dpll_mode |= 1 << DPLL_LOW_POWER_STOP;
296 if (of_property_read_bool(node, "ti,low-power-bypass"))
297 dpll_mode |= 1 << DPLL_LOW_POWER_BYPASS;
299 if (of_property_read_bool(node, "ti,lock"))
300 dpll_mode |= 1 << DPLL_LOCKED;
303 dd->modes = dpll_mode;
305 ti_clk_register_dpll(&clk_hw->hw, node);
315 #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
316 defined(CONFIG_SOC_DRA7XX)
317 static void __init of_ti_omap4_dpll_x2_setup(struct device_node *node)
319 ti_clk_register_dpll_x2(node, &dpll_x2_ck_ops, &clkhwops_omap4_dpllmx);
321 CLK_OF_DECLARE(ti_omap4_dpll_x2_clock, "ti,omap4-dpll-x2-clock",
322 of_ti_omap4_dpll_x2_setup);
325 #ifdef CONFIG_SOC_AM33XX
326 static void __init of_ti_am3_dpll_x2_setup(struct device_node *node)
328 ti_clk_register_dpll_x2(node, &dpll_x2_ck_ops, NULL);
330 CLK_OF_DECLARE(ti_am3_dpll_x2_clock, "ti,am3-dpll-x2-clock",
331 of_ti_am3_dpll_x2_setup);
334 #ifdef CONFIG_ARCH_OMAP3
335 static void __init of_ti_omap3_dpll_setup(struct device_node *node)
337 const struct dpll_data dd = {
340 .autoidle_mask = 0x7,
341 .mult_mask = 0x7ff << 8,
343 .max_multiplier = 2047,
346 .freqsel_mask = 0xf0,
347 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
350 of_ti_dpll_setup(node, &omap3_dpll_ck_ops, &dd);
352 CLK_OF_DECLARE(ti_omap3_dpll_clock, "ti,omap3-dpll-clock",
353 of_ti_omap3_dpll_setup);
355 static void __init of_ti_omap3_core_dpll_setup(struct device_node *node)
357 const struct dpll_data dd = {
360 .autoidle_mask = 0x7,
361 .mult_mask = 0x7ff << 16,
362 .div1_mask = 0x7f << 8,
363 .max_multiplier = 2047,
366 .freqsel_mask = 0xf0,
369 of_ti_dpll_setup(node, &omap3_dpll_core_ck_ops, &dd);
371 CLK_OF_DECLARE(ti_omap3_core_dpll_clock, "ti,omap3-dpll-core-clock",
372 of_ti_omap3_core_dpll_setup);
374 static void __init of_ti_omap3_per_dpll_setup(struct device_node *node)
376 const struct dpll_data dd = {
377 .idlest_mask = 0x1 << 1,
378 .enable_mask = 0x7 << 16,
379 .autoidle_mask = 0x7 << 3,
380 .mult_mask = 0x7ff << 8,
382 .max_multiplier = 2047,
385 .freqsel_mask = 0xf00000,
386 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
389 of_ti_dpll_setup(node, &omap3_dpll_per_ck_ops, &dd);
391 CLK_OF_DECLARE(ti_omap3_per_dpll_clock, "ti,omap3-dpll-per-clock",
392 of_ti_omap3_per_dpll_setup);
394 static void __init of_ti_omap3_per_jtype_dpll_setup(struct device_node *node)
396 const struct dpll_data dd = {
397 .idlest_mask = 0x1 << 1,
398 .enable_mask = 0x7 << 16,
399 .autoidle_mask = 0x7 << 3,
400 .mult_mask = 0xfff << 8,
402 .max_multiplier = 4095,
405 .sddiv_mask = 0xff << 24,
406 .dco_mask = 0xe << 20,
407 .flags = DPLL_J_TYPE,
408 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
411 of_ti_dpll_setup(node, &omap3_dpll_per_ck_ops, &dd);
413 CLK_OF_DECLARE(ti_omap3_per_jtype_dpll_clock, "ti,omap3-dpll-per-j-type-clock",
414 of_ti_omap3_per_jtype_dpll_setup);
417 static void __init of_ti_omap4_dpll_setup(struct device_node *node)
419 const struct dpll_data dd = {
422 .autoidle_mask = 0x7,
423 .mult_mask = 0x7ff << 8,
425 .max_multiplier = 2047,
428 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
431 of_ti_dpll_setup(node, &dpll_ck_ops, &dd);
433 CLK_OF_DECLARE(ti_omap4_dpll_clock, "ti,omap4-dpll-clock",
434 of_ti_omap4_dpll_setup);
436 static void __init of_ti_omap5_mpu_dpll_setup(struct device_node *node)
438 const struct dpll_data dd = {
441 .autoidle_mask = 0x7,
442 .mult_mask = 0x7ff << 8,
444 .max_multiplier = 2047,
447 .dcc_rate = 1400000000, /* DCC beyond 1.4GHz */
449 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
452 of_ti_dpll_setup(node, &dpll_ck_ops, &dd);
454 CLK_OF_DECLARE(of_ti_omap5_mpu_dpll_clock, "ti,omap5-mpu-dpll-clock",
455 of_ti_omap5_mpu_dpll_setup);
457 static void __init of_ti_omap4_core_dpll_setup(struct device_node *node)
459 const struct dpll_data dd = {
462 .autoidle_mask = 0x7,
463 .mult_mask = 0x7ff << 8,
465 .max_multiplier = 2047,
468 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
471 of_ti_dpll_setup(node, &dpll_core_ck_ops, &dd);
473 CLK_OF_DECLARE(ti_omap4_core_dpll_clock, "ti,omap4-dpll-core-clock",
474 of_ti_omap4_core_dpll_setup);
476 #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
477 defined(CONFIG_SOC_DRA7XX)
478 static void __init of_ti_omap4_m4xen_dpll_setup(struct device_node *node)
480 const struct dpll_data dd = {
483 .autoidle_mask = 0x7,
484 .mult_mask = 0x7ff << 8,
486 .max_multiplier = 2047,
490 .lpmode_mask = 1 << 10,
491 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
494 of_ti_dpll_setup(node, &dpll_m4xen_ck_ops, &dd);
496 CLK_OF_DECLARE(ti_omap4_m4xen_dpll_clock, "ti,omap4-dpll-m4xen-clock",
497 of_ti_omap4_m4xen_dpll_setup);
499 static void __init of_ti_omap4_jtype_dpll_setup(struct device_node *node)
501 const struct dpll_data dd = {
504 .autoidle_mask = 0x7,
505 .mult_mask = 0xfff << 8,
507 .max_multiplier = 4095,
510 .sddiv_mask = 0xff << 24,
511 .flags = DPLL_J_TYPE,
512 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
515 of_ti_dpll_setup(node, &dpll_m4xen_ck_ops, &dd);
517 CLK_OF_DECLARE(ti_omap4_jtype_dpll_clock, "ti,omap4-dpll-j-type-clock",
518 of_ti_omap4_jtype_dpll_setup);
521 static void __init of_ti_am3_no_gate_dpll_setup(struct device_node *node)
523 const struct dpll_data dd = {
526 .mult_mask = 0x7ff << 8,
528 .max_multiplier = 2047,
531 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
534 of_ti_dpll_setup(node, &dpll_no_gate_ck_ops, &dd);
536 CLK_OF_DECLARE(ti_am3_no_gate_dpll_clock, "ti,am3-dpll-no-gate-clock",
537 of_ti_am3_no_gate_dpll_setup);
539 static void __init of_ti_am3_jtype_dpll_setup(struct device_node *node)
541 const struct dpll_data dd = {
544 .mult_mask = 0x7ff << 8,
546 .max_multiplier = 4095,
549 .flags = DPLL_J_TYPE,
550 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
553 of_ti_dpll_setup(node, &dpll_ck_ops, &dd);
555 CLK_OF_DECLARE(ti_am3_jtype_dpll_clock, "ti,am3-dpll-j-type-clock",
556 of_ti_am3_jtype_dpll_setup);
558 static void __init of_ti_am3_no_gate_jtype_dpll_setup(struct device_node *node)
560 const struct dpll_data dd = {
563 .mult_mask = 0x7ff << 8,
565 .max_multiplier = 2047,
568 .flags = DPLL_J_TYPE,
569 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
572 of_ti_dpll_setup(node, &dpll_no_gate_ck_ops, &dd);
574 CLK_OF_DECLARE(ti_am3_no_gate_jtype_dpll_clock,
575 "ti,am3-dpll-no-gate-j-type-clock",
576 of_ti_am3_no_gate_jtype_dpll_setup);
578 static void __init of_ti_am3_dpll_setup(struct device_node *node)
580 const struct dpll_data dd = {
583 .mult_mask = 0x7ff << 8,
585 .max_multiplier = 2047,
588 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
591 of_ti_dpll_setup(node, &dpll_ck_ops, &dd);
593 CLK_OF_DECLARE(ti_am3_dpll_clock, "ti,am3-dpll-clock", of_ti_am3_dpll_setup);
595 static void __init of_ti_am3_core_dpll_setup(struct device_node *node)
597 const struct dpll_data dd = {
600 .mult_mask = 0x7ff << 8,
602 .max_multiplier = 2047,
605 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
608 of_ti_dpll_setup(node, &dpll_core_ck_ops, &dd);
610 CLK_OF_DECLARE(ti_am3_core_dpll_clock, "ti,am3-dpll-core-clock",
611 of_ti_am3_core_dpll_setup);
613 static void __init of_ti_omap2_core_dpll_setup(struct device_node *node)
615 const struct dpll_data dd = {
617 .mult_mask = 0x3ff << 12,
618 .div1_mask = 0xf << 8,
623 of_ti_dpll_setup(node, &omap2_dpll_core_ck_ops, &dd);
625 CLK_OF_DECLARE(ti_omap2_core_dpll_clock, "ti,omap2-dpll-core-clock",
626 of_ti_omap2_core_dpll_setup);