2 * OMAP3/4 - specific DPLL control functions
4 * Copyright (C) 2009-2010 Texas Instruments, Inc.
5 * Copyright (C) 2009-2010 Nokia Corporation
7 * Written by Paul Walmsley
8 * Testing and integration fixes by Jouni Högander
10 * 36xx support added by Vishwanath BS, Richard Woodruff, and Nishanth
13 * Parts of this code are based on code written by
14 * Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as
18 * published by the Free Software Foundation.
21 #include <linux/kernel.h>
22 #include <linux/device.h>
23 #include <linux/list.h>
24 #include <linux/errno.h>
25 #include <linux/delay.h>
26 #include <linux/clk.h>
28 #include <linux/bitops.h>
29 #include <linux/clkdev.h>
30 #include <linux/clk/ti.h>
34 /* CM_AUTOIDLE_PLL*.AUTO_* bit values */
35 #define DPLL_AUTOIDLE_DISABLE 0x0
36 #define DPLL_AUTOIDLE_LOW_POWER_STOP 0x1
38 #define MAX_DPLL_WAIT_TRIES 1000000
40 #define OMAP3XXX_EN_DPLL_LOCKED 0x7
42 /* Forward declarations */
43 static u32 omap3_dpll_autoidle_read(struct clk_hw_omap *clk);
44 static void omap3_dpll_deny_idle(struct clk_hw_omap *clk);
45 static void omap3_dpll_allow_idle(struct clk_hw_omap *clk);
47 /* Private functions */
49 /* _omap3_dpll_write_clken - write clken_bits arg to a DPLL's enable bits */
50 static void _omap3_dpll_write_clken(struct clk_hw_omap *clk, u8 clken_bits)
52 const struct dpll_data *dd;
57 v = ti_clk_ll_ops->clk_readl(dd->control_reg);
58 v &= ~dd->enable_mask;
59 v |= clken_bits << __ffs(dd->enable_mask);
60 ti_clk_ll_ops->clk_writel(v, dd->control_reg);
63 /* _omap3_wait_dpll_status: wait for a DPLL to enter a specific state */
64 static int _omap3_wait_dpll_status(struct clk_hw_omap *clk, u8 state)
66 const struct dpll_data *dd;
72 clk_name = clk_hw_get_name(&clk->hw);
74 state <<= __ffs(dd->idlest_mask);
76 while (((ti_clk_ll_ops->clk_readl(dd->idlest_reg) & dd->idlest_mask)
77 != state) && i < MAX_DPLL_WAIT_TRIES) {
82 if (i == MAX_DPLL_WAIT_TRIES) {
83 pr_err("clock: %s failed transition to '%s'\n",
84 clk_name, (state) ? "locked" : "bypassed");
86 pr_debug("clock: %s transition to '%s' in %d loops\n",
87 clk_name, (state) ? "locked" : "bypassed", i);
95 /* From 3430 TRM ES2 4.7.6.2 */
96 static u16 _omap3_dpll_compute_freqsel(struct clk_hw_omap *clk, u8 n)
101 fint = clk_get_rate(clk->dpll_data->clk_ref) / n;
103 pr_debug("clock: fint is %lu\n", fint);
105 if (fint >= 750000 && fint <= 1000000)
107 else if (fint > 1000000 && fint <= 1250000)
109 else if (fint > 1250000 && fint <= 1500000)
111 else if (fint > 1500000 && fint <= 1750000)
113 else if (fint > 1750000 && fint <= 2100000)
115 else if (fint > 7500000 && fint <= 10000000)
117 else if (fint > 10000000 && fint <= 12500000)
119 else if (fint > 12500000 && fint <= 15000000)
121 else if (fint > 15000000 && fint <= 17500000)
123 else if (fint > 17500000 && fint <= 21000000)
126 pr_debug("clock: unknown freqsel setting for %d\n", n);
132 * _omap3_noncore_dpll_lock - instruct a DPLL to lock and wait for readiness
133 * @clk: pointer to a DPLL struct clk
135 * Instructs a non-CORE DPLL to lock. Waits for the DPLL to report
136 * readiness before returning. Will save and restore the DPLL's
137 * autoidle state across the enable, per the CDP code. If the DPLL
138 * locked successfully, return 0; if the DPLL did not lock in the time
139 * allotted, or DPLL3 was passed in, return -EINVAL.
141 static int _omap3_noncore_dpll_lock(struct clk_hw_omap *clk)
143 const struct dpll_data *dd;
148 pr_debug("clock: locking DPLL %s\n", clk_hw_get_name(&clk->hw));
151 state <<= __ffs(dd->idlest_mask);
153 /* Check if already locked */
154 if ((ti_clk_ll_ops->clk_readl(dd->idlest_reg) & dd->idlest_mask) ==
158 ai = omap3_dpll_autoidle_read(clk);
161 omap3_dpll_deny_idle(clk);
163 _omap3_dpll_write_clken(clk, DPLL_LOCKED);
165 r = _omap3_wait_dpll_status(clk, 1);
168 omap3_dpll_allow_idle(clk);
175 * _omap3_noncore_dpll_bypass - instruct a DPLL to bypass and wait for readiness
176 * @clk: pointer to a DPLL struct clk
178 * Instructs a non-CORE DPLL to enter low-power bypass mode. In
179 * bypass mode, the DPLL's rate is set equal to its parent clock's
180 * rate. Waits for the DPLL to report readiness before returning.
181 * Will save and restore the DPLL's autoidle state across the enable,
182 * per the CDP code. If the DPLL entered bypass mode successfully,
183 * return 0; if the DPLL did not enter bypass in the time allotted, or
184 * DPLL3 was passed in, or the DPLL does not support low-power bypass,
187 static int _omap3_noncore_dpll_bypass(struct clk_hw_omap *clk)
192 if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_BYPASS)))
195 pr_debug("clock: configuring DPLL %s for low-power bypass\n",
196 clk_hw_get_name(&clk->hw));
198 ai = omap3_dpll_autoidle_read(clk);
200 _omap3_dpll_write_clken(clk, DPLL_LOW_POWER_BYPASS);
202 r = _omap3_wait_dpll_status(clk, 0);
205 omap3_dpll_allow_idle(clk);
211 * _omap3_noncore_dpll_stop - instruct a DPLL to stop
212 * @clk: pointer to a DPLL struct clk
214 * Instructs a non-CORE DPLL to enter low-power stop. Will save and
215 * restore the DPLL's autoidle state across the stop, per the CDP
216 * code. If DPLL3 was passed in, or the DPLL does not support
217 * low-power stop, return -EINVAL; otherwise, return 0.
219 static int _omap3_noncore_dpll_stop(struct clk_hw_omap *clk)
223 if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_STOP)))
226 pr_debug("clock: stopping DPLL %s\n", clk_hw_get_name(&clk->hw));
228 ai = omap3_dpll_autoidle_read(clk);
230 _omap3_dpll_write_clken(clk, DPLL_LOW_POWER_STOP);
233 omap3_dpll_allow_idle(clk);
239 * _lookup_dco - Lookup DCO used by j-type DPLL
240 * @clk: pointer to a DPLL struct clk
241 * @dco: digital control oscillator selector
242 * @m: DPLL multiplier to set
243 * @n: DPLL divider to set
245 * See 36xx TRM section 3.5.3.3.3.2 "Type B DPLL (Low-Jitter)"
247 * XXX This code is not needed for 3430/AM35xx; can it be optimized
248 * out in non-multi-OMAP builds for those chips?
250 static void _lookup_dco(struct clk_hw_omap *clk, u8 *dco, u16 m, u8 n)
252 unsigned long fint, clkinp; /* watch out for overflow */
254 clkinp = clk_hw_get_rate(clk_hw_get_parent(&clk->hw));
255 fint = (clkinp / n) * m;
257 if (fint < 1000000000)
264 * _lookup_sddiv - Calculate sigma delta divider for j-type DPLL
265 * @clk: pointer to a DPLL struct clk
266 * @sd_div: target sigma-delta divider
267 * @m: DPLL multiplier to set
268 * @n: DPLL divider to set
270 * See 36xx TRM section 3.5.3.3.3.2 "Type B DPLL (Low-Jitter)"
272 * XXX This code is not needed for 3430/AM35xx; can it be optimized
273 * out in non-multi-OMAP builds for those chips?
275 static void _lookup_sddiv(struct clk_hw_omap *clk, u8 *sd_div, u16 m, u8 n)
277 unsigned long clkinp, sd; /* watch out for overflow */
280 clkinp = clk_hw_get_rate(clk_hw_get_parent(&clk->hw));
283 * target sigma-delta to near 250MHz
284 * sd = ceil[(m/(n+1)) * (clkinp_MHz / 250)]
286 clkinp /= 100000; /* shift from MHz to 10*Hz for 38.4 and 19.2 */
287 mod1 = (clkinp * m) % (250 * n);
288 sd = (clkinp * m) / (250 * n);
298 * _omap3_noncore_dpll_program - set non-core DPLL M,N values directly
299 * @clk: struct clk * of DPLL to set
300 * @freqsel: FREQSEL value to set
302 * Program the DPLL with the last M, N values calculated, and wait for
303 * the DPLL to lock. Returns -EINVAL upon error, or 0 upon success.
305 static int omap3_noncore_dpll_program(struct clk_hw_omap *clk, u16 freqsel)
307 struct dpll_data *dd = clk->dpll_data;
311 /* 3430 ES2 TRM: 4.7.6.9 DPLL Programming Sequence */
312 _omap3_noncore_dpll_bypass(clk);
315 * Set jitter correction. Jitter correction applicable for OMAP343X
316 * only since freqsel field is no longer present on other devices.
318 if (ti_clk_get_features()->flags & TI_CLK_DPLL_HAS_FREQSEL) {
319 v = ti_clk_ll_ops->clk_readl(dd->control_reg);
320 v &= ~dd->freqsel_mask;
321 v |= freqsel << __ffs(dd->freqsel_mask);
322 ti_clk_ll_ops->clk_writel(v, dd->control_reg);
325 /* Set DPLL multiplier, divider */
326 v = ti_clk_ll_ops->clk_readl(dd->mult_div1_reg);
328 /* Handle Duty Cycle Correction */
330 if (dd->last_rounded_rate >= dd->dcc_rate)
331 v |= dd->dcc_mask; /* Enable DCC */
333 v &= ~dd->dcc_mask; /* Disable DCC */
336 v &= ~(dd->mult_mask | dd->div1_mask);
337 v |= dd->last_rounded_m << __ffs(dd->mult_mask);
338 v |= (dd->last_rounded_n - 1) << __ffs(dd->div1_mask);
340 /* Configure dco and sd_div for dplls that have these fields */
342 _lookup_dco(clk, &dco, dd->last_rounded_m, dd->last_rounded_n);
343 v &= ~(dd->dco_mask);
344 v |= dco << __ffs(dd->dco_mask);
346 if (dd->sddiv_mask) {
347 _lookup_sddiv(clk, &sd_div, dd->last_rounded_m,
349 v &= ~(dd->sddiv_mask);
350 v |= sd_div << __ffs(dd->sddiv_mask);
353 ti_clk_ll_ops->clk_writel(v, dd->mult_div1_reg);
355 /* Set 4X multiplier and low-power mode */
356 if (dd->m4xen_mask || dd->lpmode_mask) {
357 v = ti_clk_ll_ops->clk_readl(dd->control_reg);
359 if (dd->m4xen_mask) {
360 if (dd->last_rounded_m4xen)
363 v &= ~dd->m4xen_mask;
366 if (dd->lpmode_mask) {
367 if (dd->last_rounded_lpmode)
368 v |= dd->lpmode_mask;
370 v &= ~dd->lpmode_mask;
373 ti_clk_ll_ops->clk_writel(v, dd->control_reg);
376 /* We let the clock framework set the other output dividers later */
378 /* REVISIT: Set ramp-up delay? */
380 _omap3_noncore_dpll_lock(clk);
385 /* Public functions */
388 * omap3_dpll_recalc - recalculate DPLL rate
389 * @clk: DPLL struct clk
391 * Recalculate and propagate the DPLL rate.
393 unsigned long omap3_dpll_recalc(struct clk_hw *hw, unsigned long parent_rate)
395 struct clk_hw_omap *clk = to_clk_hw_omap(hw);
397 return omap2_get_dpll_rate(clk);
400 /* Non-CORE DPLL (e.g., DPLLs that do not control SDRC) clock functions */
403 * omap3_noncore_dpll_enable - instruct a DPLL to enter bypass or lock mode
404 * @clk: pointer to a DPLL struct clk
406 * Instructs a non-CORE DPLL to enable, e.g., to enter bypass or lock.
407 * The choice of modes depends on the DPLL's programmed rate: if it is
408 * the same as the DPLL's parent clock, it will enter bypass;
409 * otherwise, it will enter lock. This code will wait for the DPLL to
410 * indicate readiness before returning, unless the DPLL takes too long
411 * to enter the target state. Intended to be used as the struct clk's
412 * enable function. If DPLL3 was passed in, or the DPLL does not
413 * support low-power stop, or if the DPLL took too long to enter
414 * bypass or lock, return -EINVAL; otherwise, return 0.
416 int omap3_noncore_dpll_enable(struct clk_hw *hw)
418 struct clk_hw_omap *clk = to_clk_hw_omap(hw);
420 struct dpll_data *dd;
421 struct clk_hw *parent;
428 r = ti_clk_ll_ops->clkdm_clk_enable(clk->clkdm, hw->clk);
431 "%s: could not enable %s's clockdomain %s: %d\n",
432 __func__, clk_hw_get_name(hw),
438 parent = clk_hw_get_parent(hw);
440 if (clk_hw_get_rate(hw) == clk_get_rate(dd->clk_bypass)) {
441 WARN_ON(parent != __clk_get_hw(dd->clk_bypass));
442 r = _omap3_noncore_dpll_bypass(clk);
444 WARN_ON(parent != __clk_get_hw(dd->clk_ref));
445 r = _omap3_noncore_dpll_lock(clk);
452 * omap3_noncore_dpll_disable - instruct a DPLL to enter low-power stop
453 * @clk: pointer to a DPLL struct clk
455 * Instructs a non-CORE DPLL to enter low-power stop. This function is
456 * intended for use in struct clkops. No return value.
458 void omap3_noncore_dpll_disable(struct clk_hw *hw)
460 struct clk_hw_omap *clk = to_clk_hw_omap(hw);
462 _omap3_noncore_dpll_stop(clk);
464 ti_clk_ll_ops->clkdm_clk_disable(clk->clkdm, hw->clk);
467 /* Non-CORE DPLL rate set code */
470 * omap3_noncore_dpll_determine_rate - determine rate for a DPLL
471 * @hw: pointer to the clock to determine rate for
472 * @req: target rate request
474 * Determines which DPLL mode to use for reaching a desired target rate.
475 * Checks whether the DPLL shall be in bypass or locked mode, and if
476 * locked, calculates the M,N values for the DPLL via round-rate.
477 * Returns a 0 on success, negative error value in failure.
479 int omap3_noncore_dpll_determine_rate(struct clk_hw *hw,
480 struct clk_rate_request *req)
482 struct clk_hw_omap *clk = to_clk_hw_omap(hw);
483 struct dpll_data *dd;
492 if (clk_get_rate(dd->clk_bypass) == req->rate &&
493 (dd->modes & (1 << DPLL_LOW_POWER_BYPASS))) {
494 req->best_parent_hw = __clk_get_hw(dd->clk_bypass);
496 req->rate = omap2_dpll_round_rate(hw, req->rate,
497 &req->best_parent_rate);
498 req->best_parent_hw = __clk_get_hw(dd->clk_ref);
501 req->best_parent_rate = req->rate;
507 * omap3_noncore_dpll_set_parent - set parent for a DPLL clock
508 * @hw: pointer to the clock to set parent for
509 * @index: parent index to select
511 * Sets parent for a DPLL clock. This sets the DPLL into bypass or
512 * locked mode. Returns 0 with success, negative error value otherwise.
514 int omap3_noncore_dpll_set_parent(struct clk_hw *hw, u8 index)
516 struct clk_hw_omap *clk = to_clk_hw_omap(hw);
523 ret = _omap3_noncore_dpll_bypass(clk);
525 ret = _omap3_noncore_dpll_lock(clk);
531 * omap3_noncore_dpll_set_rate - set rate for a DPLL clock
532 * @hw: pointer to the clock to set parent for
533 * @rate: target rate for the clock
534 * @parent_rate: rate of the parent clock
536 * Sets rate for a DPLL clock. First checks if the clock parent is
537 * reference clock (in bypass mode, the rate of the clock can't be
538 * changed) and proceeds with the rate change operation. Returns 0
539 * with success, negative error value otherwise.
541 int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate,
542 unsigned long parent_rate)
544 struct clk_hw_omap *clk = to_clk_hw_omap(hw);
545 struct dpll_data *dd;
556 if (clk_hw_get_parent(hw) != __clk_get_hw(dd->clk_ref))
559 if (dd->last_rounded_rate == 0)
562 /* Freqsel is available only on OMAP343X devices */
563 if (ti_clk_get_features()->flags & TI_CLK_DPLL_HAS_FREQSEL) {
564 freqsel = _omap3_dpll_compute_freqsel(clk, dd->last_rounded_n);
568 pr_debug("%s: %s: set rate: locking rate to %lu.\n", __func__,
569 clk_hw_get_name(hw), rate);
571 ret = omap3_noncore_dpll_program(clk, freqsel);
577 * omap3_noncore_dpll_set_rate_and_parent - set rate and parent for a DPLL clock
578 * @hw: pointer to the clock to set rate and parent for
579 * @rate: target rate for the DPLL
580 * @parent_rate: clock rate of the DPLL parent
581 * @index: new parent index for the DPLL, 0 - reference, 1 - bypass
583 * Sets rate and parent for a DPLL clock. If new parent is the bypass
584 * clock, only selects the parent. Otherwise proceeds with a rate
585 * change, as this will effectively also change the parent as the
586 * DPLL is put into locked mode. Returns 0 with success, negative error
589 int omap3_noncore_dpll_set_rate_and_parent(struct clk_hw *hw,
591 unsigned long parent_rate,
600 * clk-ref at index[0], in which case we only need to set rate,
601 * the parent will be changed automatically with the lock sequence.
602 * With clk-bypass case we only need to change parent.
605 ret = omap3_noncore_dpll_set_parent(hw, index);
607 ret = omap3_noncore_dpll_set_rate(hw, rate, parent_rate);
612 /* DPLL autoidle read/set code */
615 * omap3_dpll_autoidle_read - read a DPLL's autoidle bits
616 * @clk: struct clk * of the DPLL to read
618 * Return the DPLL's autoidle bits, shifted down to bit 0. Returns
619 * -EINVAL if passed a null pointer or if the struct clk does not
620 * appear to refer to a DPLL.
622 static u32 omap3_dpll_autoidle_read(struct clk_hw_omap *clk)
624 const struct dpll_data *dd;
627 if (!clk || !clk->dpll_data)
632 if (!dd->autoidle_reg)
635 v = ti_clk_ll_ops->clk_readl(dd->autoidle_reg);
636 v &= dd->autoidle_mask;
637 v >>= __ffs(dd->autoidle_mask);
643 * omap3_dpll_allow_idle - enable DPLL autoidle bits
644 * @clk: struct clk * of the DPLL to operate on
646 * Enable DPLL automatic idle control. This automatic idle mode
647 * switching takes effect only when the DPLL is locked, at least on
648 * OMAP3430. The DPLL will enter low-power stop when its downstream
649 * clocks are gated. No return value.
651 static void omap3_dpll_allow_idle(struct clk_hw_omap *clk)
653 const struct dpll_data *dd;
656 if (!clk || !clk->dpll_data)
661 if (!dd->autoidle_reg)
665 * REVISIT: CORE DPLL can optionally enter low-power bypass
666 * by writing 0x5 instead of 0x1. Add some mechanism to
667 * optionally enter this mode.
669 v = ti_clk_ll_ops->clk_readl(dd->autoidle_reg);
670 v &= ~dd->autoidle_mask;
671 v |= DPLL_AUTOIDLE_LOW_POWER_STOP << __ffs(dd->autoidle_mask);
672 ti_clk_ll_ops->clk_writel(v, dd->autoidle_reg);
676 * omap3_dpll_deny_idle - prevent DPLL from automatically idling
677 * @clk: struct clk * of the DPLL to operate on
679 * Disable DPLL automatic idle control. No return value.
681 static void omap3_dpll_deny_idle(struct clk_hw_omap *clk)
683 const struct dpll_data *dd;
686 if (!clk || !clk->dpll_data)
691 if (!dd->autoidle_reg)
694 v = ti_clk_ll_ops->clk_readl(dd->autoidle_reg);
695 v &= ~dd->autoidle_mask;
696 v |= DPLL_AUTOIDLE_DISABLE << __ffs(dd->autoidle_mask);
697 ti_clk_ll_ops->clk_writel(v, dd->autoidle_reg);
700 /* Clock control for DPLL outputs */
702 /* Find the parent DPLL for the given clkoutx2 clock */
703 static struct clk_hw_omap *omap3_find_clkoutx2_dpll(struct clk_hw *hw)
705 struct clk_hw_omap *pclk = NULL;
707 /* Walk up the parents of clk, looking for a DPLL */
710 hw = clk_hw_get_parent(hw);
711 } while (hw && (clk_hw_get_flags(hw) & CLK_IS_BASIC));
714 pclk = to_clk_hw_omap(hw);
715 } while (pclk && !pclk->dpll_data);
717 /* clk does not have a DPLL as a parent? error in the clock data */
727 * omap3_clkoutx2_recalc - recalculate DPLL X2 output virtual clock rate
728 * @clk: DPLL output struct clk
730 * Using parent clock DPLL data, look up DPLL state. If locked, set our
731 * rate to the dpll_clk * 2; otherwise, just use dpll_clk.
733 unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw,
734 unsigned long parent_rate)
736 const struct dpll_data *dd;
739 struct clk_hw_omap *pclk = NULL;
744 pclk = omap3_find_clkoutx2_dpll(hw);
749 dd = pclk->dpll_data;
751 WARN_ON(!dd->enable_mask);
753 v = ti_clk_ll_ops->clk_readl(dd->control_reg) & dd->enable_mask;
754 v >>= __ffs(dd->enable_mask);
755 if ((v != OMAP3XXX_EN_DPLL_LOCKED) || (dd->flags & DPLL_J_TYPE))
758 rate = parent_rate * 2;
762 /* OMAP3/4 non-CORE DPLL clkops */
763 const struct clk_hw_omap_ops clkhwops_omap3_dpll = {
764 .allow_idle = omap3_dpll_allow_idle,
765 .deny_idle = omap3_dpll_deny_idle,
769 * omap3_dpll4_set_rate - set rate for omap3 per-dpll
770 * @hw: clock to change
771 * @rate: target rate for clock
772 * @parent_rate: rate of the parent clock
774 * Check if the current SoC supports the per-dpll reprogram operation
775 * or not, and then do the rate change if supported. Returns -EINVAL
776 * if not supported, 0 for success, and potential error codes from the
779 int omap3_dpll4_set_rate(struct clk_hw *hw, unsigned long rate,
780 unsigned long parent_rate)
783 * According to the 12-5 CDP code from TI, "Limitation 2.5"
784 * on 3430ES1 prevents us from changing DPLL multipliers or dividers
787 if (ti_clk_get_features()->flags & TI_CLK_DPLL4_DENY_REPROGRAM) {
788 pr_err("clock: DPLL4 cannot change rate due to silicon 'Limitation 2.5' on 3430ES1.\n");
792 return omap3_noncore_dpll_set_rate(hw, rate, parent_rate);
796 * omap3_dpll4_set_rate_and_parent - set rate and parent for omap3 per-dpll
797 * @hw: clock to change
798 * @rate: target rate for clock
799 * @parent_rate: rate of the parent clock
800 * @index: parent index, 0 - reference clock, 1 - bypass clock
802 * Check if the current SoC support the per-dpll reprogram operation
803 * or not, and then do the rate + parent change if supported. Returns
804 * -EINVAL if not supported, 0 for success, and potential error codes
805 * from the clock rate change.
807 int omap3_dpll4_set_rate_and_parent(struct clk_hw *hw, unsigned long rate,
808 unsigned long parent_rate, u8 index)
810 if (ti_clk_get_features()->flags & TI_CLK_DPLL4_DENY_REPROGRAM) {
811 pr_err("clock: DPLL4 cannot change rate due to silicon 'Limitation 2.5' on 3430ES1.\n");
815 return omap3_noncore_dpll_set_rate_and_parent(hw, rate, parent_rate,