4 * Copyright (C) 2013 Texas Instruments, Inc.
6 * Tero Kristo <t-kristo@ti.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
13 * kind, whether express or implied; without even the implied warranty
14 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
18 #include <linux/clk-provider.h>
19 #include <linux/slab.h>
20 #include <linux/err.h>
22 #include <linux/of_address.h>
23 #include <linux/clk/ti.h>
27 #define pr_fmt(fmt) "%s: " fmt, __func__
29 #define to_clk_mux(_hw) container_of(_hw, struct clk_mux, hw)
31 static u8 ti_clk_mux_get_parent(struct clk_hw *hw)
33 struct clk_mux *mux = to_clk_mux(hw);
34 int num_parents = clk_hw_get_num_parents(hw);
38 * FIXME need a mux-specific flag to determine if val is bitwise or
39 * numeric. e.g. sys_clkin_ck's clksel field is 3 bits wide, but ranges
40 * from 0x1 to 0x7 (index starts at one)
41 * OTOH, pmd_trace_clk_mux_ck uses a separate bit for each clock, so
42 * val = 0x4 really means "bit 2, index starts at bit 0"
44 val = ti_clk_ll_ops->clk_readl(mux->reg) >> mux->shift;
50 for (i = 0; i < num_parents; i++)
51 if (mux->table[i] == val)
56 if (val && (mux->flags & CLK_MUX_INDEX_BIT))
59 if (val && (mux->flags & CLK_MUX_INDEX_ONE))
62 if (val >= num_parents)
68 static int ti_clk_mux_set_parent(struct clk_hw *hw, u8 index)
70 struct clk_mux *mux = to_clk_mux(hw);
72 unsigned long flags = 0;
75 index = mux->table[index];
77 if (mux->flags & CLK_MUX_INDEX_BIT)
78 index = (1 << ffs(index));
80 if (mux->flags & CLK_MUX_INDEX_ONE)
85 spin_lock_irqsave(mux->lock, flags);
87 if (mux->flags & CLK_MUX_HIWORD_MASK) {
88 val = mux->mask << (mux->shift + 16);
90 val = ti_clk_ll_ops->clk_readl(mux->reg);
91 val &= ~(mux->mask << mux->shift);
93 val |= index << mux->shift;
94 ti_clk_ll_ops->clk_writel(val, mux->reg);
97 spin_unlock_irqrestore(mux->lock, flags);
102 const struct clk_ops ti_clk_mux_ops = {
103 .get_parent = ti_clk_mux_get_parent,
104 .set_parent = ti_clk_mux_set_parent,
105 .determine_rate = __clk_mux_determine_rate,
108 static struct clk *_register_mux(struct device *dev, const char *name,
109 const char **parent_names, u8 num_parents,
110 unsigned long flags, void __iomem *reg,
111 u8 shift, u32 mask, u8 clk_mux_flags,
112 u32 *table, spinlock_t *lock)
116 struct clk_init_data init;
118 /* allocate the mux */
119 mux = kzalloc(sizeof(*mux), GFP_KERNEL);
121 pr_err("%s: could not allocate mux clk\n", __func__);
122 return ERR_PTR(-ENOMEM);
126 init.ops = &ti_clk_mux_ops;
127 init.flags = flags | CLK_IS_BASIC;
128 init.parent_names = parent_names;
129 init.num_parents = num_parents;
131 /* struct clk_mux assignments */
135 mux->flags = clk_mux_flags;
138 mux->hw.init = &init;
140 clk = clk_register(dev, &mux->hw);
148 struct clk *ti_clk_register_mux(struct ti_clk *setup)
150 struct ti_clk_mux *mux;
153 struct clk_omap_reg *reg_setup;
157 reg_setup = (struct clk_omap_reg *)®
160 flags = CLK_SET_RATE_NO_REPARENT;
162 mask = mux->num_parents;
163 if (!(mux->flags & CLKF_INDEX_STARTS_AT_ONE))
166 mask = (1 << fls(mask)) - 1;
167 reg_setup->index = mux->module;
168 reg_setup->offset = mux->reg;
170 if (mux->flags & CLKF_INDEX_STARTS_AT_ONE)
171 mux_flags |= CLK_MUX_INDEX_ONE;
173 if (mux->flags & CLKF_SET_RATE_PARENT)
174 flags |= CLK_SET_RATE_PARENT;
176 return _register_mux(NULL, setup->name, mux->parents, mux->num_parents,
177 flags, (void __iomem *)reg, mux->bit_shift, mask,
178 mux_flags, NULL, NULL);
182 * of_mux_clk_setup - Setup function for simple mux rate clock
183 * @node: DT node for the clock
185 * Sets up a basic clock multiplexer.
187 static void of_mux_clk_setup(struct device_node *node)
192 const char **parent_names;
193 u8 clk_mux_flags = 0;
196 u32 flags = CLK_SET_RATE_NO_REPARENT;
198 num_parents = of_clk_get_parent_count(node);
199 if (num_parents < 2) {
200 pr_err("mux-clock %s must have parents\n", node->name);
203 parent_names = kzalloc((sizeof(char *) * num_parents), GFP_KERNEL);
207 of_clk_parent_fill(node, parent_names, num_parents);
209 reg = ti_clk_get_reg_addr(node, 0);
214 of_property_read_u32(node, "ti,bit-shift", &shift);
216 if (of_property_read_bool(node, "ti,index-starts-at-one"))
217 clk_mux_flags |= CLK_MUX_INDEX_ONE;
219 if (of_property_read_bool(node, "ti,set-rate-parent"))
220 flags |= CLK_SET_RATE_PARENT;
222 /* Generate bit-mask based on parent info */
224 if (!(clk_mux_flags & CLK_MUX_INDEX_ONE))
227 mask = (1 << fls(mask)) - 1;
229 clk = _register_mux(NULL, node->name, parent_names, num_parents,
230 flags, reg, shift, mask, clk_mux_flags, NULL,
234 of_clk_add_provider(node, of_clk_src_simple_get, clk);
239 CLK_OF_DECLARE(mux_clk, "ti,mux-clock", of_mux_clk_setup);
241 struct clk_hw *ti_clk_build_component_mux(struct ti_clk_mux *setup)
244 struct clk_omap_reg *reg;
250 mux = kzalloc(sizeof(*mux), GFP_KERNEL);
252 return ERR_PTR(-ENOMEM);
254 reg = (struct clk_omap_reg *)&mux->reg;
256 mux->shift = setup->bit_shift;
258 reg->index = setup->module;
259 reg->offset = setup->reg;
261 if (setup->flags & CLKF_INDEX_STARTS_AT_ONE)
262 mux->flags |= CLK_MUX_INDEX_ONE;
264 num_parents = setup->num_parents;
266 mux->mask = num_parents - 1;
267 mux->mask = (1 << fls(mux->mask)) - 1;
272 static void __init of_ti_composite_mux_clk_setup(struct device_node *node)
278 mux = kzalloc(sizeof(*mux), GFP_KERNEL);
282 mux->reg = ti_clk_get_reg_addr(node, 0);
284 if (IS_ERR(mux->reg))
287 if (!of_property_read_u32(node, "ti,bit-shift", &val))
290 if (of_property_read_bool(node, "ti,index-starts-at-one"))
291 mux->flags |= CLK_MUX_INDEX_ONE;
293 num_parents = of_clk_get_parent_count(node);
295 if (num_parents < 2) {
296 pr_err("%s must have parents\n", node->name);
300 mux->mask = num_parents - 1;
301 mux->mask = (1 << fls(mux->mask)) - 1;
303 if (!ti_clk_add_component(node, &mux->hw, CLK_COMPONENT_TYPE_MUX))
309 CLK_OF_DECLARE(ti_composite_mux_clk_setup, "ti,composite-mux-clock",
310 of_ti_composite_mux_clk_setup);