drivers/clk/ux500/u8500_clk.c

   1 /*
   2  * Clock definitions for u8500 platform.
   3  *
   4  * Copyright (C) 2012 ST-Ericsson SA
   5  * Author: Ulf Hansson <ulf.hansson@linaro.org>
   6  *
   7  * License terms: GNU General Public License (GPL) version 2
   8  */
   9
  10 #include <linux/clk.h>
  11 #include <linux/clkdev.h>
  12 #include <linux/clk-provider.h>
  13 #include <linux/mfd/dbx500-prcmu.h>
  14 #include <linux/platform_data/clk-ux500.h>
  15 #include "clk.h"
  16
  17 void u8500_clk_init(u32 clkrst1_base, u32 clkrst2_base, u32 clkrst3_base,
  18                     u32 clkrst5_base, u32 clkrst6_base)
  19 {
  20         struct prcmu_fw_version *fw_version;
  21         const char *sgaclk_parent = NULL;
  22         struct clk *clk;
  23
  24         /* Clock sources */
  25         clk = clk_reg_prcmu_gate("soc0_pll", NULL, PRCMU_PLLSOC0,
  26                                 CLK_IS_ROOT|CLK_IGNORE_UNUSED);
  27         clk_register_clkdev(clk, "soc0_pll", NULL);
  28
  29         clk = clk_reg_prcmu_gate("soc1_pll", NULL, PRCMU_PLLSOC1,
  30                                 CLK_IS_ROOT|CLK_IGNORE_UNUSED);
  31         clk_register_clkdev(clk, "soc1_pll", NULL);
  32
  33         clk = clk_reg_prcmu_gate("ddr_pll", NULL, PRCMU_PLLDDR,
  34                                 CLK_IS_ROOT|CLK_IGNORE_UNUSED);
  35         clk_register_clkdev(clk, "ddr_pll", NULL);
  36
  37         /* FIXME: Add sys, ulp and int clocks here. */
  38
  39         clk = clk_register_fixed_rate(NULL, "rtc32k", "NULL",
  40                                 CLK_IS_ROOT|CLK_IGNORE_UNUSED,
  41                                 32768);
  42         clk_register_clkdev(clk, "clk32k", NULL);
  43         clk_register_clkdev(clk, "apb_pclk", "rtc-pl031");
  44
  45         /* PRCMU clocks */
  46         fw_version = prcmu_get_fw_version();
  47         if (fw_version != NULL) {
  48                 switch (fw_version->project) {
  49                 case PRCMU_FW_PROJECT_U8500_C2:
  50                 case PRCMU_FW_PROJECT_U8520:
  51                 case PRCMU_FW_PROJECT_U8420:
  52                         sgaclk_parent = "soc0_pll";
  53                         break;
  54                 default:
  55                         break;
  56                 }
  57         }
  58
  59         if (sgaclk_parent)
  60                 clk = clk_reg_prcmu_gate("sgclk", sgaclk_parent,
  61                                         PRCMU_SGACLK, 0);
  62         else
  63                 clk = clk_reg_prcmu_gate("sgclk", NULL,
  64                                         PRCMU_SGACLK, CLK_IS_ROOT);
  65         clk_register_clkdev(clk, NULL, "mali");
  66
  67         clk = clk_reg_prcmu_gate("uartclk", NULL, PRCMU_UARTCLK, CLK_IS_ROOT);
  68         clk_register_clkdev(clk, NULL, "UART");
  69
  70         clk = clk_reg_prcmu_gate("msp02clk", NULL, PRCMU_MSP02CLK, CLK_IS_ROOT);
  71         clk_register_clkdev(clk, NULL, "MSP02");
  72
  73         clk = clk_reg_prcmu_gate("msp1clk", NULL, PRCMU_MSP1CLK, CLK_IS_ROOT);
  74         clk_register_clkdev(clk, NULL, "MSP1");
  75
  76         clk = clk_reg_prcmu_gate("i2cclk", NULL, PRCMU_I2CCLK, CLK_IS_ROOT);
  77         clk_register_clkdev(clk, NULL, "I2C");
  78
  79         clk = clk_reg_prcmu_gate("slimclk", NULL, PRCMU_SLIMCLK, CLK_IS_ROOT);
  80         clk_register_clkdev(clk, NULL, "slim");
  81
  82         clk = clk_reg_prcmu_gate("per1clk", NULL, PRCMU_PER1CLK, CLK_IS_ROOT);
  83         clk_register_clkdev(clk, NULL, "PERIPH1");
  84
  85         clk = clk_reg_prcmu_gate("per2clk", NULL, PRCMU_PER2CLK, CLK_IS_ROOT);
  86         clk_register_clkdev(clk, NULL, "PERIPH2");
  87
  88         clk = clk_reg_prcmu_gate("per3clk", NULL, PRCMU_PER3CLK, CLK_IS_ROOT);
  89         clk_register_clkdev(clk, NULL, "PERIPH3");
  90
  91         clk = clk_reg_prcmu_gate("per5clk", NULL, PRCMU_PER5CLK, CLK_IS_ROOT);
  92         clk_register_clkdev(clk, NULL, "PERIPH5");
  93
  94         clk = clk_reg_prcmu_gate("per6clk", NULL, PRCMU_PER6CLK, CLK_IS_ROOT);
  95         clk_register_clkdev(clk, NULL, "PERIPH6");
  96
  97         clk = clk_reg_prcmu_gate("per7clk", NULL, PRCMU_PER7CLK, CLK_IS_ROOT);
  98         clk_register_clkdev(clk, NULL, "PERIPH7");
  99
 100         clk = clk_reg_prcmu_scalable("lcdclk", NULL, PRCMU_LCDCLK, 0,
 101                                 CLK_IS_ROOT|CLK_SET_RATE_GATE);
 102         clk_register_clkdev(clk, NULL, "lcd");
 103         clk_register_clkdev(clk, "lcd", "mcde");
 104
 105         clk = clk_reg_prcmu_opp_gate("bmlclk", NULL, PRCMU_BMLCLK, CLK_IS_ROOT);
 106         clk_register_clkdev(clk, NULL, "bml");
 107
 108         clk = clk_reg_prcmu_scalable("hsitxclk", NULL, PRCMU_HSITXCLK, 0,
 109                                 CLK_IS_ROOT|CLK_SET_RATE_GATE);
 110
 111         clk = clk_reg_prcmu_scalable("hsirxclk", NULL, PRCMU_HSIRXCLK, 0,
 112                                 CLK_IS_ROOT|CLK_SET_RATE_GATE);
 113
 114         clk = clk_reg_prcmu_scalable("hdmiclk", NULL, PRCMU_HDMICLK, 0,
 115                                 CLK_IS_ROOT|CLK_SET_RATE_GATE);
 116         clk_register_clkdev(clk, NULL, "hdmi");
 117         clk_register_clkdev(clk, "hdmi", "mcde");
 118
 119         clk = clk_reg_prcmu_scalable("apeatclk", NULL, PRCMU_APEATCLK, 0,
 120                                      CLK_IS_ROOT|CLK_SET_RATE_GATE);
 121         clk_register_clkdev(clk, NULL, "apeat");
 122
 123         clk = clk_reg_prcmu_scalable("apetraceclk", NULL, PRCMU_APETRACECLK, 0,
 124                                 CLK_IS_ROOT|CLK_SET_RATE_GATE);
 125         clk_register_clkdev(clk, NULL, "apetrace");
 126
 127         clk = clk_reg_prcmu_gate("mcdeclk", NULL, PRCMU_MCDECLK, CLK_IS_ROOT);
 128         clk_register_clkdev(clk, NULL, "mcde");
 129         clk_register_clkdev(clk, "mcde", "mcde");
 130         clk_register_clkdev(clk, "dsisys", "dsilink.0");
 131         clk_register_clkdev(clk, "dsisys", "dsilink.1");
 132         clk_register_clkdev(clk, "dsisys", "dsilink.2");
 133
 134         clk = clk_reg_prcmu_opp_gate("ipi2cclk", NULL, PRCMU_IPI2CCLK,
 135                                 CLK_IS_ROOT);
 136         clk_register_clkdev(clk, NULL, "ipi2");
 137
 138         clk = clk_reg_prcmu_gate("dsialtclk", NULL, PRCMU_DSIALTCLK,
 139                                 CLK_IS_ROOT);
 140         clk_register_clkdev(clk, NULL, "dsialt");
 141
 142         clk = clk_reg_prcmu_gate("dmaclk", NULL, PRCMU_DMACLK, CLK_IS_ROOT);
 143         clk_register_clkdev(clk, NULL, "dma40.0");
 144
 145         clk = clk_reg_prcmu_gate("b2r2clk", NULL, PRCMU_B2R2CLK, CLK_IS_ROOT);
 146         clk_register_clkdev(clk, NULL, "b2r2");
 147         clk_register_clkdev(clk, NULL, "b2r2_core");
 148         clk_register_clkdev(clk, NULL, "U8500-B2R2.0");
 149
 150         clk = clk_reg_prcmu_scalable("tvclk", NULL, PRCMU_TVCLK, 0,
 151                                 CLK_IS_ROOT|CLK_SET_RATE_GATE);
 152         clk_register_clkdev(clk, NULL, "tv");
 153         clk_register_clkdev(clk, "tv", "mcde");
 154
 155         clk = clk_reg_prcmu_gate("sspclk", NULL, PRCMU_SSPCLK, CLK_IS_ROOT);
 156         clk_register_clkdev(clk, NULL, "SSP");
 157
 158         clk = clk_reg_prcmu_gate("rngclk", NULL, PRCMU_RNGCLK, CLK_IS_ROOT);
 159         clk_register_clkdev(clk, NULL, "rngclk");
 160
 161         clk = clk_reg_prcmu_gate("uiccclk", NULL, PRCMU_UICCCLK, CLK_IS_ROOT);
 162         clk_register_clkdev(clk, NULL, "uicc");
 163
 164         clk = clk_reg_prcmu_gate("timclk", NULL, PRCMU_TIMCLK, CLK_IS_ROOT);
 165         clk_register_clkdev(clk, NULL, "mtu0");
 166         clk_register_clkdev(clk, NULL, "mtu1");
 167
 168         clk = clk_reg_prcmu_opp_volt_scalable("sdmmcclk", NULL, PRCMU_SDMMCCLK,
 169                                         100000000,
 170                                         CLK_IS_ROOT|CLK_SET_RATE_GATE);
 171         clk_register_clkdev(clk, NULL, "sdmmc");
 172
 173         clk = clk_reg_prcmu_scalable("dsi_pll", "hdmiclk",
 174                                 PRCMU_PLLDSI, 0, CLK_SET_RATE_GATE);
 175         clk_register_clkdev(clk, "dsihs2", "mcde");
 176         clk_register_clkdev(clk, "dsihs2", "dsilink.2");
 177
 178
 179         clk = clk_reg_prcmu_scalable("dsi0clk", "dsi_pll",
 180                                 PRCMU_DSI0CLK, 0, CLK_SET_RATE_GATE);
 181         clk_register_clkdev(clk, "dsihs0", "mcde");
 182         clk_register_clkdev(clk, "dsihs0", "dsilink.0");
 183
 184         clk = clk_reg_prcmu_scalable("dsi1clk", "dsi_pll",
 185                                 PRCMU_DSI1CLK, 0, CLK_SET_RATE_GATE);
 186         clk_register_clkdev(clk, "dsihs1", "mcde");
 187         clk_register_clkdev(clk, "dsihs1", "dsilink.1");
 188
 189         clk = clk_reg_prcmu_scalable("dsi0escclk", "tvclk",
 190                                 PRCMU_DSI0ESCCLK, 0, CLK_SET_RATE_GATE);
 191         clk_register_clkdev(clk, "dsilp0", "dsilink.0");
 192         clk_register_clkdev(clk, "dsilp0", "mcde");
 193
 194         clk = clk_reg_prcmu_scalable("dsi1escclk", "tvclk",
 195                                 PRCMU_DSI1ESCCLK, 0, CLK_SET_RATE_GATE);
 196         clk_register_clkdev(clk, "dsilp1", "dsilink.1");
 197         clk_register_clkdev(clk, "dsilp1", "mcde");
 198
 199         clk = clk_reg_prcmu_scalable("dsi2escclk", "tvclk",
 200                                 PRCMU_DSI2ESCCLK, 0, CLK_SET_RATE_GATE);
 201         clk_register_clkdev(clk, "dsilp2", "dsilink.2");
 202         clk_register_clkdev(clk, "dsilp2", "mcde");
 203
 204         clk = clk_reg_prcmu_scalable_rate("armss", NULL,
 205                                 PRCMU_ARMSS, 0, CLK_IS_ROOT|CLK_IGNORE_UNUSED);
 206         clk_register_clkdev(clk, "armss", NULL);
 207
 208         clk = clk_register_fixed_factor(NULL, "smp_twd", "armss",
 209                                 CLK_IGNORE_UNUSED, 1, 2);
 210         clk_register_clkdev(clk, NULL, "smp_twd");
 211
 212         /*
 213          * FIXME: Add special handled PRCMU clocks here:
 214          * 1. clkout0yuv, use PRCMU as parent + need regulator + pinctrl.
 215          * 2. ab9540_clkout1yuv, see clkout0yuv
 216          */
 217
 218         /* PRCC P-clocks */
 219         clk = clk_reg_prcc_pclk("p1_pclk0", "per1clk", clkrst1_base,
 220                                 BIT(0), 0);
 221         clk_register_clkdev(clk, "apb_pclk", "uart0");
 222
 223         clk = clk_reg_prcc_pclk("p1_pclk1", "per1clk", clkrst1_base,
 224                                 BIT(1), 0);
 225         clk_register_clkdev(clk, "apb_pclk", "uart1");
 226
 227         clk = clk_reg_prcc_pclk("p1_pclk2", "per1clk", clkrst1_base,
 228                                 BIT(2), 0);
 229         clk_register_clkdev(clk, "apb_pclk", "nmk-i2c.1");
 230
 231         clk = clk_reg_prcc_pclk("p1_pclk3", "per1clk", clkrst1_base,
 232                                 BIT(3), 0);
 233         clk_register_clkdev(clk, "apb_pclk", "msp0");
 234         clk_register_clkdev(clk, "apb_pclk", "ux500-msp-i2s.0");
 235
 236         clk = clk_reg_prcc_pclk("p1_pclk4", "per1clk", clkrst1_base,
 237                                 BIT(4), 0);
 238         clk_register_clkdev(clk, "apb_pclk", "msp1");
 239         clk_register_clkdev(clk, "apb_pclk", "ux500-msp-i2s.1");
 240
 241         clk = clk_reg_prcc_pclk("p1_pclk5", "per1clk", clkrst1_base,
 242                                 BIT(5), 0);
 243         clk_register_clkdev(clk, "apb_pclk", "sdi0");
 244
 245         clk = clk_reg_prcc_pclk("p1_pclk6", "per1clk", clkrst1_base,
 246                                 BIT(6), 0);
 247         clk_register_clkdev(clk, "apb_pclk", "nmk-i2c.2");
 248
 249         clk = clk_reg_prcc_pclk("p1_pclk7", "per1clk", clkrst1_base,
 250                                 BIT(7), 0);
 251         clk_register_clkdev(clk, NULL, "spi3");
 252
 253         clk = clk_reg_prcc_pclk("p1_pclk8", "per1clk", clkrst1_base,
 254                                 BIT(8), 0);
 255         clk_register_clkdev(clk, "apb_pclk", "slimbus0");
 256
 257         clk = clk_reg_prcc_pclk("p1_pclk9", "per1clk", clkrst1_base,
 258                                 BIT(9), 0);
 259         clk_register_clkdev(clk, NULL, "gpio.0");
 260         clk_register_clkdev(clk, NULL, "gpio.1");
 261         clk_register_clkdev(clk, NULL, "gpioblock0");
 262
 263         clk = clk_reg_prcc_pclk("p1_pclk10", "per1clk", clkrst1_base,
 264                                 BIT(10), 0);
 265         clk_register_clkdev(clk, "apb_pclk", "nmk-i2c.4");
 266
 267         clk = clk_reg_prcc_pclk("p1_pclk11", "per1clk", clkrst1_base,
 268                                 BIT(11), 0);
 269         clk_register_clkdev(clk, "apb_pclk", "msp3");
 270         clk_register_clkdev(clk, "apb_pclk", "ux500-msp-i2s.3");
 271
 272         clk = clk_reg_prcc_pclk("p2_pclk0", "per2clk", clkrst2_base,
 273                                 BIT(0), 0);
 274         clk_register_clkdev(clk, "apb_pclk", "nmk-i2c.3");
 275
 276         clk = clk_reg_prcc_pclk("p2_pclk1", "per2clk", clkrst2_base,
 277                                 BIT(1), 0);
 278         clk_register_clkdev(clk, NULL, "spi2");
 279
 280         clk = clk_reg_prcc_pclk("p2_pclk2", "per2clk", clkrst2_base,
 281                                 BIT(2), 0);
 282         clk_register_clkdev(clk, NULL, "spi1");
 283
 284         clk = clk_reg_prcc_pclk("p2_pclk3", "per2clk", clkrst2_base,
 285                                 BIT(3), 0);
 286         clk_register_clkdev(clk, NULL, "pwl");
 287
 288         clk = clk_reg_prcc_pclk("p2_pclk4", "per2clk", clkrst2_base,
 289                                 BIT(4), 0);
 290         clk_register_clkdev(clk, "apb_pclk", "sdi4");
 291
 292         clk = clk_reg_prcc_pclk("p2_pclk5", "per2clk", clkrst2_base,
 293                                 BIT(5), 0);
 294         clk_register_clkdev(clk, "apb_pclk", "msp2");
 295         clk_register_clkdev(clk, "apb_pclk", "ux500-msp-i2s.2");
 296
 297         clk = clk_reg_prcc_pclk("p2_pclk6", "per2clk", clkrst2_base,
 298                                 BIT(6), 0);
 299         clk_register_clkdev(clk, "apb_pclk", "sdi1");
 300
 301         clk = clk_reg_prcc_pclk("p2_pclk7", "per2clk", clkrst2_base,
 302                                 BIT(7), 0);
 303         clk_register_clkdev(clk, "apb_pclk", "sdi3");
 304
 305         clk = clk_reg_prcc_pclk("p2_pclk8", "per2clk", clkrst2_base,
 306                                 BIT(8), 0);
 307         clk_register_clkdev(clk, NULL, "spi0");
 308
 309         clk = clk_reg_prcc_pclk("p2_pclk9", "per2clk", clkrst2_base,
 310                                 BIT(9), 0);
 311         clk_register_clkdev(clk, "hsir_hclk", "ste_hsi.0");
 312
 313         clk = clk_reg_prcc_pclk("p2_pclk10", "per2clk", clkrst2_base,
 314                                 BIT(10), 0);
 315         clk_register_clkdev(clk, "hsit_hclk", "ste_hsi.0");
 316
 317         clk = clk_reg_prcc_pclk("p2_pclk11", "per2clk", clkrst2_base,
 318                                 BIT(11), 0);
 319         clk_register_clkdev(clk, NULL, "gpio.6");
 320         clk_register_clkdev(clk, NULL, "gpio.7");
 321         clk_register_clkdev(clk, NULL, "gpioblock1");
 322
 323         clk = clk_reg_prcc_pclk("p2_pclk12", "per2clk", clkrst2_base,
 324                                 BIT(12), 0);
 325
 326         clk = clk_reg_prcc_pclk("p3_pclk0", "per3clk", clkrst3_base,
 327                                 BIT(0), 0);
 328         clk_register_clkdev(clk, "fsmc", NULL);
 329         clk_register_clkdev(clk, NULL, "smsc911x.0");
 330
 331         clk = clk_reg_prcc_pclk("p3_pclk1", "per3clk", clkrst3_base,
 332                                 BIT(1), 0);
 333         clk_register_clkdev(clk, "apb_pclk", "ssp0");
 334
 335         clk = clk_reg_prcc_pclk("p3_pclk2", "per3clk", clkrst3_base,
 336                                 BIT(2), 0);
 337         clk_register_clkdev(clk, "apb_pclk", "ssp1");
 338
 339         clk = clk_reg_prcc_pclk("p3_pclk3", "per3clk", clkrst3_base,
 340                                 BIT(3), 0);
 341         clk_register_clkdev(clk, "apb_pclk", "nmk-i2c.0");
 342
 343         clk = clk_reg_prcc_pclk("p3_pclk4", "per3clk", clkrst3_base,
 344                                 BIT(4), 0);
 345         clk_register_clkdev(clk, "apb_pclk", "sdi2");
 346
 347         clk = clk_reg_prcc_pclk("p3_pclk5", "per3clk", clkrst3_base,
 348                                 BIT(5), 0);
 349         clk_register_clkdev(clk, "apb_pclk", "ske");
 350         clk_register_clkdev(clk, "apb_pclk", "nmk-ske-keypad");
 351
 352         clk = clk_reg_prcc_pclk("p3_pclk6", "per3clk", clkrst3_base,
 353                                 BIT(6), 0);
 354         clk_register_clkdev(clk, "apb_pclk", "uart2");
 355
 356         clk = clk_reg_prcc_pclk("p3_pclk7", "per3clk", clkrst3_base,
 357                                 BIT(7), 0);
 358         clk_register_clkdev(clk, "apb_pclk", "sdi5");
 359
 360         clk = clk_reg_prcc_pclk("p3_pclk8", "per3clk", clkrst3_base,
 361                                 BIT(8), 0);
 362         clk_register_clkdev(clk, NULL, "gpio.2");
 363         clk_register_clkdev(clk, NULL, "gpio.3");
 364         clk_register_clkdev(clk, NULL, "gpio.4");
 365         clk_register_clkdev(clk, NULL, "gpio.5");
 366         clk_register_clkdev(clk, NULL, "gpioblock2");
 367
 368         clk = clk_reg_prcc_pclk("p5_pclk0", "per5clk", clkrst5_base,
 369                                 BIT(0), 0);
 370         clk_register_clkdev(clk, "usb", "musb-ux500.0");
 371
 372         clk = clk_reg_prcc_pclk("p5_pclk1", "per5clk", clkrst5_base,
 373                                 BIT(1), 0);
 374         clk_register_clkdev(clk, NULL, "gpio.8");
 375         clk_register_clkdev(clk, NULL, "gpioblock3");
 376
 377         clk = clk_reg_prcc_pclk("p6_pclk0", "per6clk", clkrst6_base,
 378                                 BIT(0), 0);
 379         clk_register_clkdev(clk, "apb_pclk", "rng");
 380
 381         clk = clk_reg_prcc_pclk("p6_pclk1", "per6clk", clkrst6_base,
 382                                 BIT(1), 0);
 383         clk_register_clkdev(clk, NULL, "cryp0");
 384         clk_register_clkdev(clk, NULL, "cryp1");
 385
 386         clk = clk_reg_prcc_pclk("p6_pclk2", "per6clk", clkrst6_base,
 387                                 BIT(2), 0);
 388         clk_register_clkdev(clk, NULL, "hash0");
 389
 390         clk = clk_reg_prcc_pclk("p6_pclk3", "per6clk", clkrst6_base,
 391                                 BIT(3), 0);
 392         clk_register_clkdev(clk, NULL, "pka");
 393
 394         clk = clk_reg_prcc_pclk("p6_pclk4", "per6clk", clkrst6_base,
 395                                 BIT(4), 0);
 396         clk_register_clkdev(clk, NULL, "hash1");
 397
 398         clk = clk_reg_prcc_pclk("p6_pclk5", "per6clk", clkrst6_base,
 399                                 BIT(5), 0);
 400         clk_register_clkdev(clk, NULL, "cfgreg");
 401
 402         clk = clk_reg_prcc_pclk("p6_pclk6", "per6clk", clkrst6_base,
 403                                 BIT(6), 0);
 404         clk_register_clkdev(clk, "apb_pclk", "mtu0");
 405
 406         clk = clk_reg_prcc_pclk("p6_pclk7", "per6clk", clkrst6_base,
 407                                 BIT(7), 0);
 408         clk_register_clkdev(clk, "apb_pclk", "mtu1");
 409
 410         /* PRCC K-clocks
 411          *
 412          * FIXME: Some drivers requires PERPIH[n| to be automatically enabled
 413          * by enabling just the K-clock, even if it is not a valid parent to
 414          * the K-clock. Until drivers get fixed we might need some kind of
 415          * "parent muxed join".
 416          */
 417
 418         /* Periph1 */
 419         clk = clk_reg_prcc_kclk("p1_uart0_kclk", "uartclk",
 420                         clkrst1_base, BIT(0), CLK_SET_RATE_GATE);
 421         clk_register_clkdev(clk, NULL, "uart0");
 422
 423         clk = clk_reg_prcc_kclk("p1_uart1_kclk", "uartclk",
 424                         clkrst1_base, BIT(1), CLK_SET_RATE_GATE);
 425         clk_register_clkdev(clk, NULL, "uart1");
 426
 427         clk = clk_reg_prcc_kclk("p1_i2c1_kclk", "i2cclk",
 428                         clkrst1_base, BIT(2), CLK_SET_RATE_GATE);
 429         clk_register_clkdev(clk, NULL, "nmk-i2c.1");
 430
 431         clk = clk_reg_prcc_kclk("p1_msp0_kclk", "msp02clk",
 432                         clkrst1_base, BIT(3), CLK_SET_RATE_GATE);
 433         clk_register_clkdev(clk, NULL, "msp0");
 434         clk_register_clkdev(clk, NULL, "ux500-msp-i2s.0");
 435
 436         clk = clk_reg_prcc_kclk("p1_msp1_kclk", "msp1clk",
 437                         clkrst1_base, BIT(4), CLK_SET_RATE_GATE);
 438         clk_register_clkdev(clk, NULL, "msp1");
 439         clk_register_clkdev(clk, NULL, "ux500-msp-i2s.1");
 440
 441         clk = clk_reg_prcc_kclk("p1_sdi0_kclk", "sdmmcclk",
 442                         clkrst1_base, BIT(5), CLK_SET_RATE_GATE);
 443         clk_register_clkdev(clk, NULL, "sdi0");
 444
 445         clk = clk_reg_prcc_kclk("p1_i2c2_kclk", "i2cclk",
 446                         clkrst1_base, BIT(6), CLK_SET_RATE_GATE);
 447         clk_register_clkdev(clk, NULL, "nmk-i2c.2");
 448
 449         clk = clk_reg_prcc_kclk("p1_slimbus0_kclk", "slimclk",
 450                         clkrst1_base, BIT(8), CLK_SET_RATE_GATE);
 451         clk_register_clkdev(clk, NULL, "slimbus0");
 452
 453         clk = clk_reg_prcc_kclk("p1_i2c4_kclk", "i2cclk",
 454                         clkrst1_base, BIT(9), CLK_SET_RATE_GATE);
 455         clk_register_clkdev(clk, NULL, "nmk-i2c.4");
 456
 457         clk = clk_reg_prcc_kclk("p1_msp3_kclk", "msp1clk",
 458                         clkrst1_base, BIT(10), CLK_SET_RATE_GATE);
 459         clk_register_clkdev(clk, NULL, "msp3");
 460         clk_register_clkdev(clk, NULL, "ux500-msp-i2s.3");
 461
 462         /* Periph2 */
 463         clk = clk_reg_prcc_kclk("p2_i2c3_kclk", "i2cclk",
 464                         clkrst2_base, BIT(0), CLK_SET_RATE_GATE);
 465         clk_register_clkdev(clk, NULL, "nmk-i2c.3");
 466
 467         clk = clk_reg_prcc_kclk("p2_sdi4_kclk", "sdmmcclk",
 468                         clkrst2_base, BIT(2), CLK_SET_RATE_GATE);
 469         clk_register_clkdev(clk, NULL, "sdi4");
 470
 471         clk = clk_reg_prcc_kclk("p2_msp2_kclk", "msp02clk",
 472                         clkrst2_base, BIT(3), CLK_SET_RATE_GATE);
 473         clk_register_clkdev(clk, NULL, "msp2");
 474         clk_register_clkdev(clk, NULL, "ux500-msp-i2s.2");
 475
 476         clk = clk_reg_prcc_kclk("p2_sdi1_kclk", "sdmmcclk",
 477                         clkrst2_base, BIT(4), CLK_SET_RATE_GATE);
 478         clk_register_clkdev(clk, NULL, "sdi1");
 479
 480         clk = clk_reg_prcc_kclk("p2_sdi3_kclk", "sdmmcclk",
 481                         clkrst2_base, BIT(5), CLK_SET_RATE_GATE);
 482         clk_register_clkdev(clk, NULL, "sdi3");
 483
 484         /* Note that rate is received from parent. */
 485         clk = clk_reg_prcc_kclk("p2_ssirx_kclk", "hsirxclk",
 486                         clkrst2_base, BIT(6),
 487                         CLK_SET_RATE_GATE|CLK_SET_RATE_PARENT);
 488         clk = clk_reg_prcc_kclk("p2_ssitx_kclk", "hsitxclk",
 489                         clkrst2_base, BIT(7),
 490                         CLK_SET_RATE_GATE|CLK_SET_RATE_PARENT);
 491
 492         /* Periph3 */
 493         clk = clk_reg_prcc_kclk("p3_ssp0_kclk", "sspclk",
 494                         clkrst3_base, BIT(1), CLK_SET_RATE_GATE);
 495         clk_register_clkdev(clk, NULL, "ssp0");
 496
 497         clk = clk_reg_prcc_kclk("p3_ssp1_kclk", "sspclk",
 498                         clkrst3_base, BIT(2), CLK_SET_RATE_GATE);
 499         clk_register_clkdev(clk, NULL, "ssp1");
 500
 501         clk = clk_reg_prcc_kclk("p3_i2c0_kclk", "i2cclk",
 502                         clkrst3_base, BIT(3), CLK_SET_RATE_GATE);
 503         clk_register_clkdev(clk, NULL, "nmk-i2c.0");
 504
 505         clk = clk_reg_prcc_kclk("p3_sdi2_kclk", "sdmmcclk",
 506                         clkrst3_base, BIT(4), CLK_SET_RATE_GATE);
 507         clk_register_clkdev(clk, NULL, "sdi2");
 508
 509         clk = clk_reg_prcc_kclk("p3_ske_kclk", "rtc32k",
 510                         clkrst3_base, BIT(5), CLK_SET_RATE_GATE);
 511         clk_register_clkdev(clk, NULL, "ske");
 512         clk_register_clkdev(clk, NULL, "nmk-ske-keypad");
 513
 514         clk = clk_reg_prcc_kclk("p3_uart2_kclk", "uartclk",
 515                         clkrst3_base, BIT(6), CLK_SET_RATE_GATE);
 516         clk_register_clkdev(clk, NULL, "uart2");
 517
 518         clk = clk_reg_prcc_kclk("p3_sdi5_kclk", "sdmmcclk",
 519                         clkrst3_base, BIT(7), CLK_SET_RATE_GATE);
 520         clk_register_clkdev(clk, NULL, "sdi5");
 521
 522         /* Periph6 */
 523         clk = clk_reg_prcc_kclk("p3_rng_kclk", "rngclk",
 524                         clkrst6_base, BIT(0), CLK_SET_RATE_GATE);
 525         clk_register_clkdev(clk, NULL, "rng");
 526 }