2 * Clock definitions for u8500 platform.
4 * Copyright (C) 2012 ST-Ericsson SA
5 * Author: Ulf Hansson <ulf.hansson@linaro.org>
7 * License terms: GNU General Public License (GPL) version 2
10 #include <linux/clk.h>
11 #include <linux/clkdev.h>
12 #include <linux/clk-provider.h>
13 #include <linux/mfd/dbx500-prcmu.h>
14 #include <linux/platform_data/clk-ux500.h>
17 void u8500_clk_init(u32 clkrst1_base, u32 clkrst2_base, u32 clkrst3_base,
18 u32 clkrst5_base, u32 clkrst6_base)
20 struct prcmu_fw_version *fw_version;
21 const char *sgaclk_parent = NULL;
25 clk = clk_reg_prcmu_gate("soc0_pll", NULL, PRCMU_PLLSOC0,
26 CLK_IS_ROOT|CLK_IGNORE_UNUSED);
27 clk_register_clkdev(clk, "soc0_pll", NULL);
29 clk = clk_reg_prcmu_gate("soc1_pll", NULL, PRCMU_PLLSOC1,
30 CLK_IS_ROOT|CLK_IGNORE_UNUSED);
31 clk_register_clkdev(clk, "soc1_pll", NULL);
33 clk = clk_reg_prcmu_gate("ddr_pll", NULL, PRCMU_PLLDDR,
34 CLK_IS_ROOT|CLK_IGNORE_UNUSED);
35 clk_register_clkdev(clk, "ddr_pll", NULL);
37 /* FIXME: Add sys, ulp and int clocks here. */
39 clk = clk_register_fixed_rate(NULL, "rtc32k", "NULL",
40 CLK_IS_ROOT|CLK_IGNORE_UNUSED,
42 clk_register_clkdev(clk, "clk32k", NULL);
43 clk_register_clkdev(clk, "apb_pclk", "rtc-pl031");
46 fw_version = prcmu_get_fw_version();
47 if (fw_version != NULL) {
48 switch (fw_version->project) {
49 case PRCMU_FW_PROJECT_U8500_C2:
50 case PRCMU_FW_PROJECT_U8520:
51 case PRCMU_FW_PROJECT_U8420:
52 sgaclk_parent = "soc0_pll";
60 clk = clk_reg_prcmu_gate("sgclk", sgaclk_parent,
63 clk = clk_reg_prcmu_gate("sgclk", NULL,
64 PRCMU_SGACLK, CLK_IS_ROOT);
65 clk_register_clkdev(clk, NULL, "mali");
67 clk = clk_reg_prcmu_gate("uartclk", NULL, PRCMU_UARTCLK, CLK_IS_ROOT);
68 clk_register_clkdev(clk, NULL, "UART");
70 clk = clk_reg_prcmu_gate("msp02clk", NULL, PRCMU_MSP02CLK, CLK_IS_ROOT);
71 clk_register_clkdev(clk, NULL, "MSP02");
73 clk = clk_reg_prcmu_gate("msp1clk", NULL, PRCMU_MSP1CLK, CLK_IS_ROOT);
74 clk_register_clkdev(clk, NULL, "MSP1");
76 clk = clk_reg_prcmu_gate("i2cclk", NULL, PRCMU_I2CCLK, CLK_IS_ROOT);
77 clk_register_clkdev(clk, NULL, "I2C");
79 clk = clk_reg_prcmu_gate("slimclk", NULL, PRCMU_SLIMCLK, CLK_IS_ROOT);
80 clk_register_clkdev(clk, NULL, "slim");
82 clk = clk_reg_prcmu_gate("per1clk", NULL, PRCMU_PER1CLK, CLK_IS_ROOT);
83 clk_register_clkdev(clk, NULL, "PERIPH1");
85 clk = clk_reg_prcmu_gate("per2clk", NULL, PRCMU_PER2CLK, CLK_IS_ROOT);
86 clk_register_clkdev(clk, NULL, "PERIPH2");
88 clk = clk_reg_prcmu_gate("per3clk", NULL, PRCMU_PER3CLK, CLK_IS_ROOT);
89 clk_register_clkdev(clk, NULL, "PERIPH3");
91 clk = clk_reg_prcmu_gate("per5clk", NULL, PRCMU_PER5CLK, CLK_IS_ROOT);
92 clk_register_clkdev(clk, NULL, "PERIPH5");
94 clk = clk_reg_prcmu_gate("per6clk", NULL, PRCMU_PER6CLK, CLK_IS_ROOT);
95 clk_register_clkdev(clk, NULL, "PERIPH6");
97 clk = clk_reg_prcmu_gate("per7clk", NULL, PRCMU_PER7CLK, CLK_IS_ROOT);
98 clk_register_clkdev(clk, NULL, "PERIPH7");
100 clk = clk_reg_prcmu_scalable("lcdclk", NULL, PRCMU_LCDCLK, 0,
101 CLK_IS_ROOT|CLK_SET_RATE_GATE);
102 clk_register_clkdev(clk, NULL, "lcd");
103 clk_register_clkdev(clk, "lcd", "mcde");
105 clk = clk_reg_prcmu_opp_gate("bmlclk", NULL, PRCMU_BMLCLK, CLK_IS_ROOT);
106 clk_register_clkdev(clk, NULL, "bml");
108 clk = clk_reg_prcmu_scalable("hsitxclk", NULL, PRCMU_HSITXCLK, 0,
109 CLK_IS_ROOT|CLK_SET_RATE_GATE);
111 clk = clk_reg_prcmu_scalable("hsirxclk", NULL, PRCMU_HSIRXCLK, 0,
112 CLK_IS_ROOT|CLK_SET_RATE_GATE);
114 clk = clk_reg_prcmu_scalable("hdmiclk", NULL, PRCMU_HDMICLK, 0,
115 CLK_IS_ROOT|CLK_SET_RATE_GATE);
116 clk_register_clkdev(clk, NULL, "hdmi");
117 clk_register_clkdev(clk, "hdmi", "mcde");
119 clk = clk_reg_prcmu_scalable("apeatclk", NULL, PRCMU_APEATCLK, 0,
120 CLK_IS_ROOT|CLK_SET_RATE_GATE);
121 clk_register_clkdev(clk, NULL, "apeat");
123 clk = clk_reg_prcmu_scalable("apetraceclk", NULL, PRCMU_APETRACECLK, 0,
124 CLK_IS_ROOT|CLK_SET_RATE_GATE);
125 clk_register_clkdev(clk, NULL, "apetrace");
127 clk = clk_reg_prcmu_gate("mcdeclk", NULL, PRCMU_MCDECLK, CLK_IS_ROOT);
128 clk_register_clkdev(clk, NULL, "mcde");
129 clk_register_clkdev(clk, "mcde", "mcde");
130 clk_register_clkdev(clk, "dsisys", "dsilink.0");
131 clk_register_clkdev(clk, "dsisys", "dsilink.1");
132 clk_register_clkdev(clk, "dsisys", "dsilink.2");
134 clk = clk_reg_prcmu_opp_gate("ipi2cclk", NULL, PRCMU_IPI2CCLK,
136 clk_register_clkdev(clk, NULL, "ipi2");
138 clk = clk_reg_prcmu_gate("dsialtclk", NULL, PRCMU_DSIALTCLK,
140 clk_register_clkdev(clk, NULL, "dsialt");
142 clk = clk_reg_prcmu_gate("dmaclk", NULL, PRCMU_DMACLK, CLK_IS_ROOT);
143 clk_register_clkdev(clk, NULL, "dma40.0");
145 clk = clk_reg_prcmu_gate("b2r2clk", NULL, PRCMU_B2R2CLK, CLK_IS_ROOT);
146 clk_register_clkdev(clk, NULL, "b2r2");
147 clk_register_clkdev(clk, NULL, "b2r2_core");
148 clk_register_clkdev(clk, NULL, "U8500-B2R2.0");
150 clk = clk_reg_prcmu_scalable("tvclk", NULL, PRCMU_TVCLK, 0,
151 CLK_IS_ROOT|CLK_SET_RATE_GATE);
152 clk_register_clkdev(clk, NULL, "tv");
153 clk_register_clkdev(clk, "tv", "mcde");
155 clk = clk_reg_prcmu_gate("sspclk", NULL, PRCMU_SSPCLK, CLK_IS_ROOT);
156 clk_register_clkdev(clk, NULL, "SSP");
158 clk = clk_reg_prcmu_gate("rngclk", NULL, PRCMU_RNGCLK, CLK_IS_ROOT);
159 clk_register_clkdev(clk, NULL, "rngclk");
161 clk = clk_reg_prcmu_gate("uiccclk", NULL, PRCMU_UICCCLK, CLK_IS_ROOT);
162 clk_register_clkdev(clk, NULL, "uicc");
164 clk = clk_reg_prcmu_gate("timclk", NULL, PRCMU_TIMCLK, CLK_IS_ROOT);
165 clk_register_clkdev(clk, NULL, "mtu0");
166 clk_register_clkdev(clk, NULL, "mtu1");
168 clk = clk_reg_prcmu_opp_volt_scalable("sdmmcclk", NULL, PRCMU_SDMMCCLK,
170 CLK_IS_ROOT|CLK_SET_RATE_GATE);
171 clk_register_clkdev(clk, NULL, "sdmmc");
173 clk = clk_reg_prcmu_scalable("dsi_pll", "hdmiclk",
174 PRCMU_PLLDSI, 0, CLK_SET_RATE_GATE);
175 clk_register_clkdev(clk, "dsihs2", "mcde");
176 clk_register_clkdev(clk, "dsihs2", "dsilink.2");
179 clk = clk_reg_prcmu_scalable("dsi0clk", "dsi_pll",
180 PRCMU_DSI0CLK, 0, CLK_SET_RATE_GATE);
181 clk_register_clkdev(clk, "dsihs0", "mcde");
182 clk_register_clkdev(clk, "dsihs0", "dsilink.0");
184 clk = clk_reg_prcmu_scalable("dsi1clk", "dsi_pll",
185 PRCMU_DSI1CLK, 0, CLK_SET_RATE_GATE);
186 clk_register_clkdev(clk, "dsihs1", "mcde");
187 clk_register_clkdev(clk, "dsihs1", "dsilink.1");
189 clk = clk_reg_prcmu_scalable("dsi0escclk", "tvclk",
190 PRCMU_DSI0ESCCLK, 0, CLK_SET_RATE_GATE);
191 clk_register_clkdev(clk, "dsilp0", "dsilink.0");
192 clk_register_clkdev(clk, "dsilp0", "mcde");
194 clk = clk_reg_prcmu_scalable("dsi1escclk", "tvclk",
195 PRCMU_DSI1ESCCLK, 0, CLK_SET_RATE_GATE);
196 clk_register_clkdev(clk, "dsilp1", "dsilink.1");
197 clk_register_clkdev(clk, "dsilp1", "mcde");
199 clk = clk_reg_prcmu_scalable("dsi2escclk", "tvclk",
200 PRCMU_DSI2ESCCLK, 0, CLK_SET_RATE_GATE);
201 clk_register_clkdev(clk, "dsilp2", "dsilink.2");
202 clk_register_clkdev(clk, "dsilp2", "mcde");
204 clk = clk_reg_prcmu_scalable_rate("armss", NULL,
205 PRCMU_ARMSS, 0, CLK_IS_ROOT|CLK_IGNORE_UNUSED);
206 clk_register_clkdev(clk, "armss", NULL);
208 clk = clk_register_fixed_factor(NULL, "smp_twd", "armss",
209 CLK_IGNORE_UNUSED, 1, 2);
210 clk_register_clkdev(clk, NULL, "smp_twd");
213 * FIXME: Add special handled PRCMU clocks here:
214 * 1. clkout0yuv, use PRCMU as parent + need regulator + pinctrl.
215 * 2. ab9540_clkout1yuv, see clkout0yuv
219 clk = clk_reg_prcc_pclk("p1_pclk0", "per1clk", clkrst1_base,
221 clk_register_clkdev(clk, "apb_pclk", "uart0");
223 clk = clk_reg_prcc_pclk("p1_pclk1", "per1clk", clkrst1_base,
225 clk_register_clkdev(clk, "apb_pclk", "uart1");
227 clk = clk_reg_prcc_pclk("p1_pclk2", "per1clk", clkrst1_base,
229 clk_register_clkdev(clk, "apb_pclk", "nmk-i2c.1");
231 clk = clk_reg_prcc_pclk("p1_pclk3", "per1clk", clkrst1_base,
233 clk_register_clkdev(clk, "apb_pclk", "msp0");
234 clk_register_clkdev(clk, "apb_pclk", "ux500-msp-i2s.0");
236 clk = clk_reg_prcc_pclk("p1_pclk4", "per1clk", clkrst1_base,
238 clk_register_clkdev(clk, "apb_pclk", "msp1");
239 clk_register_clkdev(clk, "apb_pclk", "ux500-msp-i2s.1");
241 clk = clk_reg_prcc_pclk("p1_pclk5", "per1clk", clkrst1_base,
243 clk_register_clkdev(clk, "apb_pclk", "sdi0");
245 clk = clk_reg_prcc_pclk("p1_pclk6", "per1clk", clkrst1_base,
247 clk_register_clkdev(clk, "apb_pclk", "nmk-i2c.2");
249 clk = clk_reg_prcc_pclk("p1_pclk7", "per1clk", clkrst1_base,
251 clk_register_clkdev(clk, NULL, "spi3");
253 clk = clk_reg_prcc_pclk("p1_pclk8", "per1clk", clkrst1_base,
255 clk_register_clkdev(clk, "apb_pclk", "slimbus0");
257 clk = clk_reg_prcc_pclk("p1_pclk9", "per1clk", clkrst1_base,
259 clk_register_clkdev(clk, NULL, "gpio.0");
260 clk_register_clkdev(clk, NULL, "gpio.1");
261 clk_register_clkdev(clk, NULL, "gpioblock0");
263 clk = clk_reg_prcc_pclk("p1_pclk10", "per1clk", clkrst1_base,
265 clk_register_clkdev(clk, "apb_pclk", "nmk-i2c.4");
267 clk = clk_reg_prcc_pclk("p1_pclk11", "per1clk", clkrst1_base,
269 clk_register_clkdev(clk, "apb_pclk", "msp3");
270 clk_register_clkdev(clk, "apb_pclk", "ux500-msp-i2s.3");
272 clk = clk_reg_prcc_pclk("p2_pclk0", "per2clk", clkrst2_base,
274 clk_register_clkdev(clk, "apb_pclk", "nmk-i2c.3");
276 clk = clk_reg_prcc_pclk("p2_pclk1", "per2clk", clkrst2_base,
278 clk_register_clkdev(clk, NULL, "spi2");
280 clk = clk_reg_prcc_pclk("p2_pclk2", "per2clk", clkrst2_base,
282 clk_register_clkdev(clk, NULL, "spi1");
284 clk = clk_reg_prcc_pclk("p2_pclk3", "per2clk", clkrst2_base,
286 clk_register_clkdev(clk, NULL, "pwl");
288 clk = clk_reg_prcc_pclk("p2_pclk4", "per2clk", clkrst2_base,
290 clk_register_clkdev(clk, "apb_pclk", "sdi4");
292 clk = clk_reg_prcc_pclk("p2_pclk5", "per2clk", clkrst2_base,
294 clk_register_clkdev(clk, "apb_pclk", "msp2");
295 clk_register_clkdev(clk, "apb_pclk", "ux500-msp-i2s.2");
297 clk = clk_reg_prcc_pclk("p2_pclk6", "per2clk", clkrst2_base,
299 clk_register_clkdev(clk, "apb_pclk", "sdi1");
301 clk = clk_reg_prcc_pclk("p2_pclk7", "per2clk", clkrst2_base,
303 clk_register_clkdev(clk, "apb_pclk", "sdi3");
305 clk = clk_reg_prcc_pclk("p2_pclk8", "per2clk", clkrst2_base,
307 clk_register_clkdev(clk, NULL, "spi0");
309 clk = clk_reg_prcc_pclk("p2_pclk9", "per2clk", clkrst2_base,
311 clk_register_clkdev(clk, "hsir_hclk", "ste_hsi.0");
313 clk = clk_reg_prcc_pclk("p2_pclk10", "per2clk", clkrst2_base,
315 clk_register_clkdev(clk, "hsit_hclk", "ste_hsi.0");
317 clk = clk_reg_prcc_pclk("p2_pclk11", "per2clk", clkrst2_base,
319 clk_register_clkdev(clk, NULL, "gpio.6");
320 clk_register_clkdev(clk, NULL, "gpio.7");
321 clk_register_clkdev(clk, NULL, "gpioblock1");
323 clk = clk_reg_prcc_pclk("p2_pclk12", "per2clk", clkrst2_base,
326 clk = clk_reg_prcc_pclk("p3_pclk0", "per3clk", clkrst3_base,
328 clk_register_clkdev(clk, "fsmc", NULL);
329 clk_register_clkdev(clk, NULL, "smsc911x.0");
331 clk = clk_reg_prcc_pclk("p3_pclk1", "per3clk", clkrst3_base,
333 clk_register_clkdev(clk, "apb_pclk", "ssp0");
335 clk = clk_reg_prcc_pclk("p3_pclk2", "per3clk", clkrst3_base,
337 clk_register_clkdev(clk, "apb_pclk", "ssp1");
339 clk = clk_reg_prcc_pclk("p3_pclk3", "per3clk", clkrst3_base,
341 clk_register_clkdev(clk, "apb_pclk", "nmk-i2c.0");
343 clk = clk_reg_prcc_pclk("p3_pclk4", "per3clk", clkrst3_base,
345 clk_register_clkdev(clk, "apb_pclk", "sdi2");
347 clk = clk_reg_prcc_pclk("p3_pclk5", "per3clk", clkrst3_base,
349 clk_register_clkdev(clk, "apb_pclk", "ske");
350 clk_register_clkdev(clk, "apb_pclk", "nmk-ske-keypad");
352 clk = clk_reg_prcc_pclk("p3_pclk6", "per3clk", clkrst3_base,
354 clk_register_clkdev(clk, "apb_pclk", "uart2");
356 clk = clk_reg_prcc_pclk("p3_pclk7", "per3clk", clkrst3_base,
358 clk_register_clkdev(clk, "apb_pclk", "sdi5");
360 clk = clk_reg_prcc_pclk("p3_pclk8", "per3clk", clkrst3_base,
362 clk_register_clkdev(clk, NULL, "gpio.2");
363 clk_register_clkdev(clk, NULL, "gpio.3");
364 clk_register_clkdev(clk, NULL, "gpio.4");
365 clk_register_clkdev(clk, NULL, "gpio.5");
366 clk_register_clkdev(clk, NULL, "gpioblock2");
368 clk = clk_reg_prcc_pclk("p5_pclk0", "per5clk", clkrst5_base,
370 clk_register_clkdev(clk, "usb", "musb-ux500.0");
372 clk = clk_reg_prcc_pclk("p5_pclk1", "per5clk", clkrst5_base,
374 clk_register_clkdev(clk, NULL, "gpio.8");
375 clk_register_clkdev(clk, NULL, "gpioblock3");
377 clk = clk_reg_prcc_pclk("p6_pclk0", "per6clk", clkrst6_base,
379 clk_register_clkdev(clk, "apb_pclk", "rng");
381 clk = clk_reg_prcc_pclk("p6_pclk1", "per6clk", clkrst6_base,
383 clk_register_clkdev(clk, NULL, "cryp0");
384 clk_register_clkdev(clk, NULL, "cryp1");
386 clk = clk_reg_prcc_pclk("p6_pclk2", "per6clk", clkrst6_base,
388 clk_register_clkdev(clk, NULL, "hash0");
390 clk = clk_reg_prcc_pclk("p6_pclk3", "per6clk", clkrst6_base,
392 clk_register_clkdev(clk, NULL, "pka");
394 clk = clk_reg_prcc_pclk("p6_pclk4", "per6clk", clkrst6_base,
396 clk_register_clkdev(clk, NULL, "hash1");
398 clk = clk_reg_prcc_pclk("p6_pclk5", "per6clk", clkrst6_base,
400 clk_register_clkdev(clk, NULL, "cfgreg");
402 clk = clk_reg_prcc_pclk("p6_pclk6", "per6clk", clkrst6_base,
404 clk_register_clkdev(clk, "apb_pclk", "mtu0");
406 clk = clk_reg_prcc_pclk("p6_pclk7", "per6clk", clkrst6_base,
408 clk_register_clkdev(clk, "apb_pclk", "mtu1");
412 * FIXME: Some drivers requires PERPIH[n| to be automatically enabled
413 * by enabling just the K-clock, even if it is not a valid parent to
414 * the K-clock. Until drivers get fixed we might need some kind of
415 * "parent muxed join".
419 clk = clk_reg_prcc_kclk("p1_uart0_kclk", "uartclk",
420 clkrst1_base, BIT(0), CLK_SET_RATE_GATE);
421 clk_register_clkdev(clk, NULL, "uart0");
423 clk = clk_reg_prcc_kclk("p1_uart1_kclk", "uartclk",
424 clkrst1_base, BIT(1), CLK_SET_RATE_GATE);
425 clk_register_clkdev(clk, NULL, "uart1");
427 clk = clk_reg_prcc_kclk("p1_i2c1_kclk", "i2cclk",
428 clkrst1_base, BIT(2), CLK_SET_RATE_GATE);
429 clk_register_clkdev(clk, NULL, "nmk-i2c.1");
431 clk = clk_reg_prcc_kclk("p1_msp0_kclk", "msp02clk",
432 clkrst1_base, BIT(3), CLK_SET_RATE_GATE);
433 clk_register_clkdev(clk, NULL, "msp0");
434 clk_register_clkdev(clk, NULL, "ux500-msp-i2s.0");
436 clk = clk_reg_prcc_kclk("p1_msp1_kclk", "msp1clk",
437 clkrst1_base, BIT(4), CLK_SET_RATE_GATE);
438 clk_register_clkdev(clk, NULL, "msp1");
439 clk_register_clkdev(clk, NULL, "ux500-msp-i2s.1");
441 clk = clk_reg_prcc_kclk("p1_sdi0_kclk", "sdmmcclk",
442 clkrst1_base, BIT(5), CLK_SET_RATE_GATE);
443 clk_register_clkdev(clk, NULL, "sdi0");
445 clk = clk_reg_prcc_kclk("p1_i2c2_kclk", "i2cclk",
446 clkrst1_base, BIT(6), CLK_SET_RATE_GATE);
447 clk_register_clkdev(clk, NULL, "nmk-i2c.2");
449 clk = clk_reg_prcc_kclk("p1_slimbus0_kclk", "slimclk",
450 clkrst1_base, BIT(8), CLK_SET_RATE_GATE);
451 clk_register_clkdev(clk, NULL, "slimbus0");
453 clk = clk_reg_prcc_kclk("p1_i2c4_kclk", "i2cclk",
454 clkrst1_base, BIT(9), CLK_SET_RATE_GATE);
455 clk_register_clkdev(clk, NULL, "nmk-i2c.4");
457 clk = clk_reg_prcc_kclk("p1_msp3_kclk", "msp1clk",
458 clkrst1_base, BIT(10), CLK_SET_RATE_GATE);
459 clk_register_clkdev(clk, NULL, "msp3");
460 clk_register_clkdev(clk, NULL, "ux500-msp-i2s.3");
463 clk = clk_reg_prcc_kclk("p2_i2c3_kclk", "i2cclk",
464 clkrst2_base, BIT(0), CLK_SET_RATE_GATE);
465 clk_register_clkdev(clk, NULL, "nmk-i2c.3");
467 clk = clk_reg_prcc_kclk("p2_sdi4_kclk", "sdmmcclk",
468 clkrst2_base, BIT(2), CLK_SET_RATE_GATE);
469 clk_register_clkdev(clk, NULL, "sdi4");
471 clk = clk_reg_prcc_kclk("p2_msp2_kclk", "msp02clk",
472 clkrst2_base, BIT(3), CLK_SET_RATE_GATE);
473 clk_register_clkdev(clk, NULL, "msp2");
474 clk_register_clkdev(clk, NULL, "ux500-msp-i2s.2");
476 clk = clk_reg_prcc_kclk("p2_sdi1_kclk", "sdmmcclk",
477 clkrst2_base, BIT(4), CLK_SET_RATE_GATE);
478 clk_register_clkdev(clk, NULL, "sdi1");
480 clk = clk_reg_prcc_kclk("p2_sdi3_kclk", "sdmmcclk",
481 clkrst2_base, BIT(5), CLK_SET_RATE_GATE);
482 clk_register_clkdev(clk, NULL, "sdi3");
484 /* Note that rate is received from parent. */
485 clk = clk_reg_prcc_kclk("p2_ssirx_kclk", "hsirxclk",
486 clkrst2_base, BIT(6),
487 CLK_SET_RATE_GATE|CLK_SET_RATE_PARENT);
488 clk = clk_reg_prcc_kclk("p2_ssitx_kclk", "hsitxclk",
489 clkrst2_base, BIT(7),
490 CLK_SET_RATE_GATE|CLK_SET_RATE_PARENT);
493 clk = clk_reg_prcc_kclk("p3_ssp0_kclk", "sspclk",
494 clkrst3_base, BIT(1), CLK_SET_RATE_GATE);
495 clk_register_clkdev(clk, NULL, "ssp0");
497 clk = clk_reg_prcc_kclk("p3_ssp1_kclk", "sspclk",
498 clkrst3_base, BIT(2), CLK_SET_RATE_GATE);
499 clk_register_clkdev(clk, NULL, "ssp1");
501 clk = clk_reg_prcc_kclk("p3_i2c0_kclk", "i2cclk",
502 clkrst3_base, BIT(3), CLK_SET_RATE_GATE);
503 clk_register_clkdev(clk, NULL, "nmk-i2c.0");
505 clk = clk_reg_prcc_kclk("p3_sdi2_kclk", "sdmmcclk",
506 clkrst3_base, BIT(4), CLK_SET_RATE_GATE);
507 clk_register_clkdev(clk, NULL, "sdi2");
509 clk = clk_reg_prcc_kclk("p3_ske_kclk", "rtc32k",
510 clkrst3_base, BIT(5), CLK_SET_RATE_GATE);
511 clk_register_clkdev(clk, NULL, "ske");
512 clk_register_clkdev(clk, NULL, "nmk-ske-keypad");
514 clk = clk_reg_prcc_kclk("p3_uart2_kclk", "uartclk",
515 clkrst3_base, BIT(6), CLK_SET_RATE_GATE);
516 clk_register_clkdev(clk, NULL, "uart2");
518 clk = clk_reg_prcc_kclk("p3_sdi5_kclk", "sdmmcclk",
519 clkrst3_base, BIT(7), CLK_SET_RATE_GATE);
520 clk_register_clkdev(clk, NULL, "sdi5");
523 clk = clk_reg_prcc_kclk("p3_rng_kclk", "rngclk",
524 clkrst6_base, BIT(0), CLK_SET_RATE_GATE);
525 clk_register_clkdev(clk, NULL, "rng");