2 * linux/drivers/clocksource/arm_arch_timer.c
4 * Copyright (C) 2011 ARM Ltd.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 #include <linux/init.h>
12 #include <linux/kernel.h>
13 #include <linux/device.h>
14 #include <linux/smp.h>
15 #include <linux/cpu.h>
16 #include <linux/cpu_pm.h>
17 #include <linux/clockchips.h>
18 #include <linux/interrupt.h>
19 #include <linux/of_irq.h>
20 #include <linux/of_address.h>
22 #include <linux/slab.h>
23 #include <linux/sched_clock.h>
25 #include <asm/arch_timer.h>
28 #include <clocksource/arm_arch_timer.h>
31 #define CNTTIDR_VIRT(n) (BIT(1) << ((n) * 4))
33 #define CNTVCT_LO 0x08
34 #define CNTVCT_HI 0x0c
36 #define CNTP_TVAL 0x28
38 #define CNTV_TVAL 0x38
41 #define ARCH_CP15_TIMER BIT(0)
42 #define ARCH_MEM_TIMER BIT(1)
43 static unsigned arch_timers_present __initdata;
45 static void __iomem *arch_counter_base;
49 struct clock_event_device evt;
52 #define to_arch_timer(e) container_of(e, struct arch_timer, evt)
54 static u32 arch_timer_rate;
64 static int arch_timer_ppi[MAX_TIMER_PPI];
66 static struct clock_event_device __percpu *arch_timer_evt;
68 static bool arch_timer_use_virtual = true;
69 static bool arch_timer_mem_use_virtual;
72 * Architected system timer support.
75 static __always_inline
76 void arch_timer_reg_write(int access, enum arch_timer_reg reg, u32 val,
77 struct clock_event_device *clk)
79 if (access == ARCH_TIMER_MEM_PHYS_ACCESS) {
80 struct arch_timer *timer = to_arch_timer(clk);
82 case ARCH_TIMER_REG_CTRL:
83 writel_relaxed(val, timer->base + CNTP_CTL);
85 case ARCH_TIMER_REG_TVAL:
86 writel_relaxed(val, timer->base + CNTP_TVAL);
89 } else if (access == ARCH_TIMER_MEM_VIRT_ACCESS) {
90 struct arch_timer *timer = to_arch_timer(clk);
92 case ARCH_TIMER_REG_CTRL:
93 writel_relaxed(val, timer->base + CNTV_CTL);
95 case ARCH_TIMER_REG_TVAL:
96 writel_relaxed(val, timer->base + CNTV_TVAL);
100 arch_timer_reg_write_cp15(access, reg, val);
104 static __always_inline
105 u32 arch_timer_reg_read(int access, enum arch_timer_reg reg,
106 struct clock_event_device *clk)
110 if (access == ARCH_TIMER_MEM_PHYS_ACCESS) {
111 struct arch_timer *timer = to_arch_timer(clk);
113 case ARCH_TIMER_REG_CTRL:
114 val = readl_relaxed(timer->base + CNTP_CTL);
116 case ARCH_TIMER_REG_TVAL:
117 val = readl_relaxed(timer->base + CNTP_TVAL);
120 } else if (access == ARCH_TIMER_MEM_VIRT_ACCESS) {
121 struct arch_timer *timer = to_arch_timer(clk);
123 case ARCH_TIMER_REG_CTRL:
124 val = readl_relaxed(timer->base + CNTV_CTL);
126 case ARCH_TIMER_REG_TVAL:
127 val = readl_relaxed(timer->base + CNTV_TVAL);
131 val = arch_timer_reg_read_cp15(access, reg);
137 static __always_inline irqreturn_t timer_handler(const int access,
138 struct clock_event_device *evt)
142 ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, evt);
143 if (ctrl & ARCH_TIMER_CTRL_IT_STAT) {
144 ctrl |= ARCH_TIMER_CTRL_IT_MASK;
145 arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, evt);
146 evt->event_handler(evt);
153 static irqreturn_t arch_timer_handler_virt(int irq, void *dev_id)
155 struct clock_event_device *evt = dev_id;
157 return timer_handler(ARCH_TIMER_VIRT_ACCESS, evt);
160 static irqreturn_t arch_timer_handler_phys(int irq, void *dev_id)
162 struct clock_event_device *evt = dev_id;
164 return timer_handler(ARCH_TIMER_PHYS_ACCESS, evt);
167 static irqreturn_t arch_timer_handler_phys_mem(int irq, void *dev_id)
169 struct clock_event_device *evt = dev_id;
171 return timer_handler(ARCH_TIMER_MEM_PHYS_ACCESS, evt);
174 static irqreturn_t arch_timer_handler_virt_mem(int irq, void *dev_id)
176 struct clock_event_device *evt = dev_id;
178 return timer_handler(ARCH_TIMER_MEM_VIRT_ACCESS, evt);
181 static __always_inline void timer_set_mode(const int access, int mode,
182 struct clock_event_device *clk)
186 case CLOCK_EVT_MODE_UNUSED:
187 case CLOCK_EVT_MODE_SHUTDOWN:
188 ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, clk);
189 ctrl &= ~ARCH_TIMER_CTRL_ENABLE;
190 arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, clk);
197 static void arch_timer_set_mode_virt(enum clock_event_mode mode,
198 struct clock_event_device *clk)
200 timer_set_mode(ARCH_TIMER_VIRT_ACCESS, mode, clk);
203 static void arch_timer_set_mode_phys(enum clock_event_mode mode,
204 struct clock_event_device *clk)
206 timer_set_mode(ARCH_TIMER_PHYS_ACCESS, mode, clk);
209 static void arch_timer_set_mode_virt_mem(enum clock_event_mode mode,
210 struct clock_event_device *clk)
212 timer_set_mode(ARCH_TIMER_MEM_VIRT_ACCESS, mode, clk);
215 static void arch_timer_set_mode_phys_mem(enum clock_event_mode mode,
216 struct clock_event_device *clk)
218 timer_set_mode(ARCH_TIMER_MEM_PHYS_ACCESS, mode, clk);
221 static __always_inline void set_next_event(const int access, unsigned long evt,
222 struct clock_event_device *clk)
225 ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, clk);
226 ctrl |= ARCH_TIMER_CTRL_ENABLE;
227 ctrl &= ~ARCH_TIMER_CTRL_IT_MASK;
228 arch_timer_reg_write(access, ARCH_TIMER_REG_TVAL, evt, clk);
229 arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, clk);
232 static int arch_timer_set_next_event_virt(unsigned long evt,
233 struct clock_event_device *clk)
235 set_next_event(ARCH_TIMER_VIRT_ACCESS, evt, clk);
239 static int arch_timer_set_next_event_phys(unsigned long evt,
240 struct clock_event_device *clk)
242 set_next_event(ARCH_TIMER_PHYS_ACCESS, evt, clk);
246 static int arch_timer_set_next_event_virt_mem(unsigned long evt,
247 struct clock_event_device *clk)
249 set_next_event(ARCH_TIMER_MEM_VIRT_ACCESS, evt, clk);
253 static int arch_timer_set_next_event_phys_mem(unsigned long evt,
254 struct clock_event_device *clk)
256 set_next_event(ARCH_TIMER_MEM_PHYS_ACCESS, evt, clk);
260 static void __arch_timer_setup(unsigned type,
261 struct clock_event_device *clk)
263 clk->features = CLOCK_EVT_FEAT_ONESHOT;
265 if (type == ARCH_CP15_TIMER) {
266 clk->features |= CLOCK_EVT_FEAT_C3STOP;
267 clk->name = "arch_sys_timer";
269 clk->cpumask = cpumask_of(smp_processor_id());
270 if (arch_timer_use_virtual) {
271 clk->irq = arch_timer_ppi[VIRT_PPI];
272 clk->set_mode = arch_timer_set_mode_virt;
273 clk->set_next_event = arch_timer_set_next_event_virt;
275 clk->irq = arch_timer_ppi[PHYS_SECURE_PPI];
276 clk->set_mode = arch_timer_set_mode_phys;
277 clk->set_next_event = arch_timer_set_next_event_phys;
280 clk->features |= CLOCK_EVT_FEAT_DYNIRQ;
281 clk->name = "arch_mem_timer";
283 clk->cpumask = cpu_all_mask;
284 if (arch_timer_mem_use_virtual) {
285 clk->set_mode = arch_timer_set_mode_virt_mem;
286 clk->set_next_event =
287 arch_timer_set_next_event_virt_mem;
289 clk->set_mode = arch_timer_set_mode_phys_mem;
290 clk->set_next_event =
291 arch_timer_set_next_event_phys_mem;
295 clk->set_mode(CLOCK_EVT_MODE_SHUTDOWN, clk);
297 clockevents_config_and_register(clk, arch_timer_rate, 0xf, 0x7fffffff);
300 static void arch_timer_configure_evtstream(void)
302 int evt_stream_div, pos;
304 /* Find the closest power of two to the divisor */
305 evt_stream_div = arch_timer_rate / ARCH_TIMER_EVT_STREAM_FREQ;
306 pos = fls(evt_stream_div);
307 if (pos > 1 && !(evt_stream_div & (1 << (pos - 2))))
309 /* enable event stream */
310 arch_timer_evtstrm_enable(min(pos, 15));
313 static int arch_timer_setup(struct clock_event_device *clk)
315 __arch_timer_setup(ARCH_CP15_TIMER, clk);
317 if (arch_timer_use_virtual)
318 enable_percpu_irq(arch_timer_ppi[VIRT_PPI], 0);
320 enable_percpu_irq(arch_timer_ppi[PHYS_SECURE_PPI], 0);
321 if (arch_timer_ppi[PHYS_NONSECURE_PPI])
322 enable_percpu_irq(arch_timer_ppi[PHYS_NONSECURE_PPI], 0);
325 arch_counter_set_user_access();
326 if (IS_ENABLED(CONFIG_ARM_ARCH_TIMER_EVTSTREAM))
327 arch_timer_configure_evtstream();
333 arch_timer_detect_rate(void __iomem *cntbase, struct device_node *np)
335 /* Who has more than one independent system counter? */
339 /* Try to determine the frequency from the device tree or CNTFRQ */
340 if (of_property_read_u32(np, "clock-frequency", &arch_timer_rate)) {
342 arch_timer_rate = readl_relaxed(cntbase + CNTFRQ);
344 arch_timer_rate = arch_timer_get_cntfrq();
347 /* Check the timer frequency. */
348 if (arch_timer_rate == 0)
349 pr_warn("Architected timer frequency not available\n");
352 static void arch_timer_banner(unsigned type)
354 pr_info("Architected %s%s%s timer(s) running at %lu.%02luMHz (%s%s%s).\n",
355 type & ARCH_CP15_TIMER ? "cp15" : "",
356 type == (ARCH_CP15_TIMER | ARCH_MEM_TIMER) ? " and " : "",
357 type & ARCH_MEM_TIMER ? "mmio" : "",
358 (unsigned long)arch_timer_rate / 1000000,
359 (unsigned long)(arch_timer_rate / 10000) % 100,
360 type & ARCH_CP15_TIMER ?
361 arch_timer_use_virtual ? "virt" : "phys" :
363 type == (ARCH_CP15_TIMER | ARCH_MEM_TIMER) ? "/" : "",
364 type & ARCH_MEM_TIMER ?
365 arch_timer_mem_use_virtual ? "virt" : "phys" :
369 u32 arch_timer_get_rate(void)
371 return arch_timer_rate;
374 static u64 arch_counter_get_cntvct_mem(void)
376 u32 vct_lo, vct_hi, tmp_hi;
379 vct_hi = readl_relaxed(arch_counter_base + CNTVCT_HI);
380 vct_lo = readl_relaxed(arch_counter_base + CNTVCT_LO);
381 tmp_hi = readl_relaxed(arch_counter_base + CNTVCT_HI);
382 } while (vct_hi != tmp_hi);
384 return ((u64) vct_hi << 32) | vct_lo;
388 * Default to cp15 based access because arm64 uses this function for
389 * sched_clock() before DT is probed and the cp15 method is guaranteed
390 * to exist on arm64. arm doesn't use this before DT is probed so even
391 * if we don't have the cp15 accessors we won't have a problem.
393 u64 (*arch_timer_read_counter)(void) = arch_counter_get_cntvct;
395 static cycle_t arch_counter_read(struct clocksource *cs)
397 return arch_timer_read_counter();
400 static cycle_t arch_counter_read_cc(const struct cyclecounter *cc)
402 return arch_timer_read_counter();
405 static struct clocksource clocksource_counter = {
406 .name = "arch_sys_counter",
408 .read = arch_counter_read,
409 .mask = CLOCKSOURCE_MASK(56),
410 .flags = CLOCK_SOURCE_IS_CONTINUOUS | CLOCK_SOURCE_SUSPEND_NONSTOP,
413 static struct cyclecounter cyclecounter = {
414 .read = arch_counter_read_cc,
415 .mask = CLOCKSOURCE_MASK(56),
418 static struct timecounter timecounter;
420 struct timecounter *arch_timer_get_timecounter(void)
425 static void __init arch_counter_register(unsigned type)
429 /* Register the CP15 based counter if we have one */
430 if (type & ARCH_CP15_TIMER)
431 arch_timer_read_counter = arch_counter_get_cntvct;
433 arch_timer_read_counter = arch_counter_get_cntvct_mem;
435 start_count = arch_timer_read_counter();
436 clocksource_register_hz(&clocksource_counter, arch_timer_rate);
437 cyclecounter.mult = clocksource_counter.mult;
438 cyclecounter.shift = clocksource_counter.shift;
439 timecounter_init(&timecounter, &cyclecounter, start_count);
441 /* 56 bits minimum, so we assume worst case rollover */
442 sched_clock_register(arch_timer_read_counter, 56, arch_timer_rate);
445 static void arch_timer_stop(struct clock_event_device *clk)
447 pr_debug("arch_timer_teardown disable IRQ%d cpu #%d\n",
448 clk->irq, smp_processor_id());
450 if (arch_timer_use_virtual)
451 disable_percpu_irq(arch_timer_ppi[VIRT_PPI]);
453 disable_percpu_irq(arch_timer_ppi[PHYS_SECURE_PPI]);
454 if (arch_timer_ppi[PHYS_NONSECURE_PPI])
455 disable_percpu_irq(arch_timer_ppi[PHYS_NONSECURE_PPI]);
458 clk->set_mode(CLOCK_EVT_MODE_UNUSED, clk);
461 static int arch_timer_cpu_notify(struct notifier_block *self,
462 unsigned long action, void *hcpu)
465 * Grab cpu pointer in each case to avoid spurious
466 * preemptible warnings
468 switch (action & ~CPU_TASKS_FROZEN) {
470 arch_timer_setup(this_cpu_ptr(arch_timer_evt));
473 arch_timer_stop(this_cpu_ptr(arch_timer_evt));
480 static struct notifier_block arch_timer_cpu_nb = {
481 .notifier_call = arch_timer_cpu_notify,
485 static unsigned int saved_cntkctl;
486 static int arch_timer_cpu_pm_notify(struct notifier_block *self,
487 unsigned long action, void *hcpu)
489 if (action == CPU_PM_ENTER)
490 saved_cntkctl = arch_timer_get_cntkctl();
491 else if (action == CPU_PM_ENTER_FAILED || action == CPU_PM_EXIT)
492 arch_timer_set_cntkctl(saved_cntkctl);
496 static struct notifier_block arch_timer_cpu_pm_notifier = {
497 .notifier_call = arch_timer_cpu_pm_notify,
500 static int __init arch_timer_cpu_pm_init(void)
502 return cpu_pm_register_notifier(&arch_timer_cpu_pm_notifier);
505 static int __init arch_timer_cpu_pm_init(void)
511 static int __init arch_timer_register(void)
516 arch_timer_evt = alloc_percpu(struct clock_event_device);
517 if (!arch_timer_evt) {
522 if (arch_timer_use_virtual) {
523 ppi = arch_timer_ppi[VIRT_PPI];
524 err = request_percpu_irq(ppi, arch_timer_handler_virt,
525 "arch_timer", arch_timer_evt);
527 ppi = arch_timer_ppi[PHYS_SECURE_PPI];
528 err = request_percpu_irq(ppi, arch_timer_handler_phys,
529 "arch_timer", arch_timer_evt);
530 if (!err && arch_timer_ppi[PHYS_NONSECURE_PPI]) {
531 ppi = arch_timer_ppi[PHYS_NONSECURE_PPI];
532 err = request_percpu_irq(ppi, arch_timer_handler_phys,
533 "arch_timer", arch_timer_evt);
535 free_percpu_irq(arch_timer_ppi[PHYS_SECURE_PPI],
541 pr_err("arch_timer: can't register interrupt %d (%d)\n",
546 err = register_cpu_notifier(&arch_timer_cpu_nb);
550 err = arch_timer_cpu_pm_init();
552 goto out_unreg_notify;
554 /* Immediately configure the timer on the boot CPU */
555 arch_timer_setup(this_cpu_ptr(arch_timer_evt));
560 unregister_cpu_notifier(&arch_timer_cpu_nb);
562 if (arch_timer_use_virtual)
563 free_percpu_irq(arch_timer_ppi[VIRT_PPI], arch_timer_evt);
565 free_percpu_irq(arch_timer_ppi[PHYS_SECURE_PPI],
567 if (arch_timer_ppi[PHYS_NONSECURE_PPI])
568 free_percpu_irq(arch_timer_ppi[PHYS_NONSECURE_PPI],
573 free_percpu(arch_timer_evt);
578 static int __init arch_timer_mem_register(void __iomem *base, unsigned int irq)
582 struct arch_timer *t;
584 t = kzalloc(sizeof(*t), GFP_KERNEL);
590 __arch_timer_setup(ARCH_MEM_TIMER, &t->evt);
592 if (arch_timer_mem_use_virtual)
593 func = arch_timer_handler_virt_mem;
595 func = arch_timer_handler_phys_mem;
597 ret = request_irq(irq, func, IRQF_TIMER, "arch_mem_timer", &t->evt);
599 pr_err("arch_timer: Failed to request mem timer irq\n");
606 static const struct of_device_id arch_timer_of_match[] __initconst = {
607 { .compatible = "arm,armv7-timer", },
608 { .compatible = "arm,armv8-timer", },
612 static const struct of_device_id arch_timer_mem_of_match[] __initconst = {
613 { .compatible = "arm,armv7-timer-mem", },
617 static void __init arch_timer_common_init(void)
619 unsigned mask = ARCH_CP15_TIMER | ARCH_MEM_TIMER;
621 /* Wait until both nodes are probed if we have two timers */
622 if ((arch_timers_present & mask) != mask) {
623 if (of_find_matching_node(NULL, arch_timer_mem_of_match) &&
624 !(arch_timers_present & ARCH_MEM_TIMER))
626 if (of_find_matching_node(NULL, arch_timer_of_match) &&
627 !(arch_timers_present & ARCH_CP15_TIMER))
631 arch_timer_banner(arch_timers_present);
632 arch_counter_register(arch_timers_present);
633 arch_timer_arch_init();
636 static void __init arch_timer_init(struct device_node *np)
640 if (arch_timers_present & ARCH_CP15_TIMER) {
641 pr_warn("arch_timer: multiple nodes in dt, skipping\n");
645 arch_timers_present |= ARCH_CP15_TIMER;
646 for (i = PHYS_SECURE_PPI; i < MAX_TIMER_PPI; i++)
647 arch_timer_ppi[i] = irq_of_parse_and_map(np, i);
648 arch_timer_detect_rate(NULL, np);
651 * If HYP mode is available, we know that the physical timer
652 * has been configured to be accessible from PL1. Use it, so
653 * that a guest can use the virtual timer instead.
655 * If no interrupt provided for virtual timer, we'll have to
656 * stick to the physical timer. It'd better be accessible...
658 if (is_hyp_mode_available() || !arch_timer_ppi[VIRT_PPI]) {
659 arch_timer_use_virtual = false;
661 if (!arch_timer_ppi[PHYS_SECURE_PPI] ||
662 !arch_timer_ppi[PHYS_NONSECURE_PPI]) {
663 pr_warn("arch_timer: No interrupt available, giving up\n");
668 arch_timer_register();
669 arch_timer_common_init();
671 CLOCKSOURCE_OF_DECLARE(armv7_arch_timer, "arm,armv7-timer", arch_timer_init);
672 CLOCKSOURCE_OF_DECLARE(armv8_arch_timer, "arm,armv8-timer", arch_timer_init);
674 static void __init arch_timer_mem_init(struct device_node *np)
676 struct device_node *frame, *best_frame = NULL;
677 void __iomem *cntctlbase, *base;
681 arch_timers_present |= ARCH_MEM_TIMER;
682 cntctlbase = of_iomap(np, 0);
684 pr_err("arch_timer: Can't find CNTCTLBase\n");
688 cnttidr = readl_relaxed(cntctlbase + CNTTIDR);
692 * Try to find a virtual capable frame. Otherwise fall back to a
693 * physical capable frame.
695 for_each_available_child_of_node(np, frame) {
698 if (of_property_read_u32(frame, "frame-number", &n)) {
699 pr_err("arch_timer: Missing frame-number\n");
700 of_node_put(best_frame);
705 if (cnttidr & CNTTIDR_VIRT(n)) {
706 of_node_put(best_frame);
708 arch_timer_mem_use_virtual = true;
711 of_node_put(best_frame);
712 best_frame = of_node_get(frame);
715 base = arch_counter_base = of_iomap(best_frame, 0);
717 pr_err("arch_timer: Can't map frame's registers\n");
718 of_node_put(best_frame);
722 if (arch_timer_mem_use_virtual)
723 irq = irq_of_parse_and_map(best_frame, 1);
725 irq = irq_of_parse_and_map(best_frame, 0);
726 of_node_put(best_frame);
728 pr_err("arch_timer: Frame missing %s irq",
729 arch_timer_mem_use_virtual ? "virt" : "phys");
733 arch_timer_detect_rate(base, np);
734 arch_timer_mem_register(base, irq);
735 arch_timer_common_init();
737 CLOCKSOURCE_OF_DECLARE(armv7_arch_timer_mem, "arm,armv7-timer-mem",
738 arch_timer_mem_init);