3 * Copyright (C) 2007 Google, Inc.
4 * Copyright (c) 2009-2012,2014, The Linux Foundation. All rights reserved.
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
17 #include <linux/clocksource.h>
18 #include <linux/clockchips.h>
19 #include <linux/cpu.h>
20 #include <linux/init.h>
21 #include <linux/interrupt.h>
22 #include <linux/irq.h>
25 #include <linux/of_address.h>
26 #include <linux/of_irq.h>
27 #include <linux/sched_clock.h>
29 #include <asm/delay.h>
31 #define TIMER_MATCH_VAL 0x0000
32 #define TIMER_COUNT_VAL 0x0004
33 #define TIMER_ENABLE 0x0008
34 #define TIMER_ENABLE_CLR_ON_MATCH_EN BIT(1)
35 #define TIMER_ENABLE_EN BIT(0)
36 #define TIMER_CLEAR 0x000C
37 #define DGT_CLK_CTL 0x10
38 #define DGT_CLK_CTL_DIV_4 0x3
39 #define TIMER_STS_GPT0_CLR_PEND BIT(10)
43 static void __iomem *event_base;
44 static void __iomem *sts_base;
46 static irqreturn_t msm_timer_interrupt(int irq, void *dev_id)
48 struct clock_event_device *evt = dev_id;
49 /* Stop the timer tick */
50 if (evt->mode == CLOCK_EVT_MODE_ONESHOT) {
51 u32 ctrl = readl_relaxed(event_base + TIMER_ENABLE);
52 ctrl &= ~TIMER_ENABLE_EN;
53 writel_relaxed(ctrl, event_base + TIMER_ENABLE);
55 evt->event_handler(evt);
59 static int msm_timer_set_next_event(unsigned long cycles,
60 struct clock_event_device *evt)
62 u32 ctrl = readl_relaxed(event_base + TIMER_ENABLE);
64 ctrl &= ~TIMER_ENABLE_EN;
65 writel_relaxed(ctrl, event_base + TIMER_ENABLE);
67 writel_relaxed(ctrl, event_base + TIMER_CLEAR);
68 writel_relaxed(cycles, event_base + TIMER_MATCH_VAL);
71 while (readl_relaxed(sts_base) & TIMER_STS_GPT0_CLR_PEND)
74 writel_relaxed(ctrl | TIMER_ENABLE_EN, event_base + TIMER_ENABLE);
78 static void msm_timer_set_mode(enum clock_event_mode mode,
79 struct clock_event_device *evt)
83 ctrl = readl_relaxed(event_base + TIMER_ENABLE);
84 ctrl &= ~(TIMER_ENABLE_EN | TIMER_ENABLE_CLR_ON_MATCH_EN);
87 case CLOCK_EVT_MODE_RESUME:
88 case CLOCK_EVT_MODE_PERIODIC:
90 case CLOCK_EVT_MODE_ONESHOT:
91 /* Timer is enabled in set_next_event */
93 case CLOCK_EVT_MODE_UNUSED:
94 case CLOCK_EVT_MODE_SHUTDOWN:
97 writel_relaxed(ctrl, event_base + TIMER_ENABLE);
100 static struct clock_event_device __percpu *msm_evt;
102 static void __iomem *source_base;
104 static notrace cycle_t msm_read_timer_count(struct clocksource *cs)
106 return readl_relaxed(source_base + TIMER_COUNT_VAL);
109 static struct clocksource msm_clocksource = {
112 .read = msm_read_timer_count,
113 .mask = CLOCKSOURCE_MASK(32),
114 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
117 static int msm_timer_irq;
118 static int msm_timer_has_ppi;
120 static int msm_local_timer_setup(struct clock_event_device *evt)
122 int cpu = smp_processor_id();
125 evt->irq = msm_timer_irq;
126 evt->name = "msm_timer";
127 evt->features = CLOCK_EVT_FEAT_ONESHOT;
129 evt->set_mode = msm_timer_set_mode;
130 evt->set_next_event = msm_timer_set_next_event;
131 evt->cpumask = cpumask_of(cpu);
133 clockevents_config_and_register(evt, GPT_HZ, 4, 0xffffffff);
135 if (msm_timer_has_ppi) {
136 enable_percpu_irq(evt->irq, IRQ_TYPE_EDGE_RISING);
138 err = request_irq(evt->irq, msm_timer_interrupt,
139 IRQF_TIMER | IRQF_NOBALANCING |
140 IRQF_TRIGGER_RISING, "gp_timer", evt);
142 pr_err("request_irq failed\n");
148 static void msm_local_timer_stop(struct clock_event_device *evt)
150 evt->set_mode(CLOCK_EVT_MODE_UNUSED, evt);
151 disable_percpu_irq(evt->irq);
154 static int msm_timer_cpu_notify(struct notifier_block *self,
155 unsigned long action, void *hcpu)
158 * Grab cpu pointer in each case to avoid spurious
159 * preemptible warnings
161 switch (action & ~CPU_TASKS_FROZEN) {
163 msm_local_timer_setup(this_cpu_ptr(msm_evt));
166 msm_local_timer_stop(this_cpu_ptr(msm_evt));
173 static struct notifier_block msm_timer_cpu_nb = {
174 .notifier_call = msm_timer_cpu_notify,
177 static u64 notrace msm_sched_clock_read(void)
179 return msm_clocksource.read(&msm_clocksource);
182 static unsigned long msm_read_current_timer(void)
184 return msm_clocksource.read(&msm_clocksource);
187 static struct delay_timer msm_delay_timer = {
188 .read_current_timer = msm_read_current_timer,
191 static void __init msm_timer_init(u32 dgt_hz, int sched_bits, int irq,
194 struct clocksource *cs = &msm_clocksource;
198 msm_timer_has_ppi = percpu;
200 msm_evt = alloc_percpu(struct clock_event_device);
202 pr_err("memory allocation failed for clockevents\n");
207 res = request_percpu_irq(irq, msm_timer_interrupt,
208 "gp_timer", msm_evt);
211 pr_err("request_percpu_irq failed\n");
213 res = register_cpu_notifier(&msm_timer_cpu_nb);
215 free_percpu_irq(irq, msm_evt);
219 /* Immediately configure the timer on the boot CPU */
220 msm_local_timer_setup(raw_cpu_ptr(msm_evt));
224 writel_relaxed(TIMER_ENABLE_EN, source_base + TIMER_ENABLE);
225 res = clocksource_register_hz(cs, dgt_hz);
227 pr_err("clocksource_register failed\n");
228 sched_clock_register(msm_sched_clock_read, sched_bits, dgt_hz);
229 msm_delay_timer.freq = dgt_hz;
230 register_current_timer_delay(&msm_delay_timer);
233 static void __init msm_dt_timer_init(struct device_node *np)
240 void __iomem *cpu0_base;
242 base = of_iomap(np, 0);
244 pr_err("Failed to map event base\n");
248 /* We use GPT0 for the clockevent */
249 irq = irq_of_parse_and_map(np, 1);
251 pr_err("Can't get irq\n");
255 /* We use CPU0's DGT for the clocksource */
256 if (of_property_read_u32(np, "cpu-offset", &percpu_offset))
259 if (of_address_to_resource(np, 0, &res)) {
260 pr_err("Failed to parse DGT resource\n");
264 cpu0_base = ioremap(res.start + percpu_offset, resource_size(&res));
266 pr_err("Failed to map source base\n");
270 if (of_property_read_u32(np, "clock-frequency", &freq)) {
271 pr_err("Unknown frequency\n");
275 event_base = base + 0x4;
276 sts_base = base + 0x88;
277 source_base = cpu0_base + 0x24;
279 writel_relaxed(DGT_CLK_CTL_DIV_4, source_base + DGT_CLK_CTL);
281 msm_timer_init(freq, 32, irq, !!percpu_offset);
283 CLOCKSOURCE_OF_DECLARE(kpss_timer, "qcom,kpss-timer", msm_dt_timer_init);
284 CLOCKSOURCE_OF_DECLARE(scss_timer, "qcom,scss-timer", msm_dt_timer_init);