drivers/clocksource/rockchip_timer.c

   1 /*
   2  * Rockchip timer support
   3  *
   4  * Copyright (C) Daniel Lezcano <daniel.lezcano@linaro.org>
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10 #include <linux/clk.h>
  11 #include <linux/clockchips.h>
  12 #include <linux/init.h>
  13 #include <linux/interrupt.h>
  14 #include <linux/of.h>
  15 #include <linux/of_address.h>
  16 #include <linux/of_irq.h>
  17
  18 #define TIMER_NAME "rk_timer"
  19
  20 #define TIMER_LOAD_COUNT0       0x00
  21 #define TIMER_LOAD_COUNT1       0x04
  22 #define TIMER_V1_CONTROL_REG    0x10
  23 #define TIMER_INT_STATUS        0x18
  24 #define TIMER_V2_CONTROL_REG    0x1c
  25
  26 #define TIMER_DISABLE           0x0
  27 #define TIMER_ENABLE            0x1
  28 #define TIMER_MODE_FREE_RUNNING                 (0 << 1)
  29 #define TIMER_MODE_USER_DEFINED_COUNT           (1 << 1)
  30 #define TIMER_INT_UNMASK                        (1 << 2)
  31
  32 struct bc_timer {
  33         struct clock_event_device ce;
  34         void __iomem *base;
  35         u32 freq;
  36 };
  37
  38 static struct bc_timer bc_timer;
  39
  40 static inline struct bc_timer *rk_timer(struct clock_event_device *ce)
  41 {
  42         return container_of(ce, struct bc_timer, ce);
  43 }
  44
  45 static inline void __iomem *rk_base(struct clock_event_device *ce)
  46 {
  47         return rk_timer(ce)->base;
  48 }
  49
  50 static inline void rk_timer_v1_disable(struct clock_event_device *ce)
  51 {
  52         writel_relaxed(TIMER_DISABLE, rk_base(ce) + TIMER_V1_CONTROL_REG);
  53 }
  54
  55 static inline void rk_timer_v1_enable(struct clock_event_device *ce, u32 flags)
  56 {
  57         writel_relaxed(TIMER_ENABLE | TIMER_INT_UNMASK | flags,
  58                        rk_base(ce) + TIMER_V1_CONTROL_REG);
  59 }
  60
  61 static inline void rk_timer_v2_disable(struct clock_event_device *ce)
  62 {
  63         writel_relaxed(TIMER_DISABLE, rk_base(ce) + TIMER_V2_CONTROL_REG);
  64 }
  65
  66 static inline void rk_timer_v2_enable(struct clock_event_device *ce, u32 flags)
  67 {
  68         writel_relaxed(TIMER_ENABLE | TIMER_INT_UNMASK | flags,
  69                        rk_base(ce) + TIMER_V2_CONTROL_REG);
  70 }
  71
  72 static void rk_timer_update_counter(unsigned long cycles,
  73                                     struct clock_event_device *ce)
  74 {
  75         writel_relaxed(cycles, rk_base(ce) + TIMER_LOAD_COUNT0);
  76         writel_relaxed(0, rk_base(ce) + TIMER_LOAD_COUNT1);
  77 }
  78
  79 static void rk_timer_interrupt_clear(struct clock_event_device *ce)
  80 {
  81         writel_relaxed(1, rk_base(ce) + TIMER_INT_STATUS);
  82 }
  83
  84 static int rk_timer_v1_set_next_event(unsigned long cycles,
  85                                       struct clock_event_device *ce)
  86 {
  87         rk_timer_v1_disable(ce);
  88         rk_timer_update_counter(cycles, ce);
  89         rk_timer_v1_enable(ce, TIMER_MODE_USER_DEFINED_COUNT);
  90         return 0;
  91 }
  92
  93 static int rk_timer_v1_shutdown(struct clock_event_device *ce)
  94 {
  95         rk_timer_v1_disable(ce);
  96         return 0;
  97 }
  98
  99 static int rk_timer_v1_set_periodic(struct clock_event_device *ce)
 100 {
 101         rk_timer_v1_disable(ce);
 102         rk_timer_update_counter(rk_timer(ce)->freq / HZ - 1, ce);
 103         rk_timer_v1_enable(ce, TIMER_MODE_FREE_RUNNING);
 104         return 0;
 105 }
 106
 107 static irqreturn_t rk_timer_v1_interrupt(int irq, void *dev_id)
 108 {
 109         struct clock_event_device *ce = dev_id;
 110
 111         rk_timer_interrupt_clear(ce);
 112
 113         if (clockevent_state_oneshot(ce))
 114                 rk_timer_v1_disable(ce);
 115
 116         ce->event_handler(ce);
 117
 118         return IRQ_HANDLED;
 119 }
 120
 121 static int rk_timer_v2_set_next_event(unsigned long cycles,
 122                                       struct clock_event_device *ce)
 123 {
 124         rk_timer_v2_disable(ce);
 125         rk_timer_update_counter(cycles, ce);
 126         rk_timer_v2_enable(ce, TIMER_MODE_USER_DEFINED_COUNT);
 127         return 0;
 128 }
 129
 130 static int rk_timer_v2_shutdown(struct clock_event_device *ce)
 131 {
 132         rk_timer_v2_disable(ce);
 133         return 0;
 134 }
 135
 136 static int rk_timer_v2_set_periodic(struct clock_event_device *ce)
 137 {
 138         rk_timer_v2_disable(ce);
 139         rk_timer_update_counter(rk_timer(ce)->freq / HZ - 1, ce);
 140         rk_timer_v2_enable(ce, TIMER_MODE_FREE_RUNNING);
 141         return 0;
 142 }
 143
 144 static irqreturn_t rk_timer_v2_interrupt(int irq, void *dev_id)
 145 {
 146         struct clock_event_device *ce = dev_id;
 147
 148         rk_timer_interrupt_clear(ce);
 149
 150         if (clockevent_state_oneshot(ce))
 151                 rk_timer_v2_disable(ce);
 152
 153         ce->event_handler(ce);
 154
 155         return IRQ_HANDLED;
 156 }
 157
 158 static void __init rk_timer_init(struct device_node *np,
 159                                  irq_handler_t rk_timer_interrupt)
 160 {
 161         struct clock_event_device *ce = &bc_timer.ce;
 162         struct clk *timer_clk;
 163         struct clk *pclk;
 164         int ret, irq;
 165
 166         bc_timer.base = of_iomap(np, 0);
 167         if (!bc_timer.base) {
 168                 pr_err("Failed to get base address for '%s'\n", TIMER_NAME);
 169                 return;
 170         }
 171
 172         pclk = of_clk_get_by_name(np, "pclk");
 173         if (IS_ERR(pclk)) {
 174                 pr_err("Failed to get pclk for '%s'\n", TIMER_NAME);
 175                 goto out_unmap;
 176         }
 177
 178         if (clk_prepare_enable(pclk)) {
 179                 pr_err("Failed to enable pclk for '%s'\n", TIMER_NAME);
 180                 goto out_unmap;
 181         }
 182
 183         timer_clk = of_clk_get_by_name(np, "timer");
 184         if (IS_ERR(timer_clk)) {
 185                 pr_err("Failed to get timer clock for '%s'\n", TIMER_NAME);
 186                 goto out_timer_clk;
 187         }
 188
 189         if (clk_prepare_enable(timer_clk)) {
 190                 pr_err("Failed to enable timer clock\n");
 191                 goto out_timer_clk;
 192         }
 193
 194         bc_timer.freq = clk_get_rate(timer_clk);
 195
 196         irq = irq_of_parse_and_map(np, 0);
 197         if (!irq) {
 198                 pr_err("Failed to map interrupts for '%s'\n", TIMER_NAME);
 199                 goto out_irq;
 200         }
 201
 202         ce->name = TIMER_NAME;
 203         ce->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT |
 204                        CLOCK_EVT_FEAT_DYNIRQ;
 205         ce->irq = irq;
 206         ce->cpumask = cpu_all_mask;
 207         ce->rating = 250;
 208
 209         ret = request_irq(irq, rk_timer_interrupt, IRQF_TIMER, TIMER_NAME, ce);
 210         if (ret) {
 211                 pr_err("Failed to initialize '%s': %d\n", TIMER_NAME, ret);
 212                 goto out_irq;
 213         }
 214
 215         clockevents_config_and_register(ce, bc_timer.freq, 1, UINT_MAX);
 216
 217         return;
 218
 219 out_irq:
 220         clk_disable_unprepare(timer_clk);
 221 out_timer_clk:
 222         clk_disable_unprepare(pclk);
 223 out_unmap:
 224         iounmap(bc_timer.base);
 225 }
 226
 227 static void __init rk_timer_v1_init(struct device_node *np)
 228 {
 229         struct clock_event_device *ce = &bc_timer.ce;
 230
 231         ce->set_next_event = rk_timer_v1_set_next_event;
 232         ce->set_state_shutdown = rk_timer_v1_shutdown;
 233         ce->set_state_periodic = rk_timer_v1_set_periodic;
 234
 235         rk_timer_init(np, rk_timer_v1_interrupt);
 236 }
 237
 238 static void __init rk_timer_v2_init(struct device_node *np)
 239 {
 240         struct clock_event_device *ce = &bc_timer.ce;
 241
 242         ce->set_next_event = rk_timer_v2_set_next_event;
 243         ce->set_state_shutdown = rk_timer_v2_shutdown;
 244         ce->set_state_periodic = rk_timer_v2_set_periodic;
 245
 246         rk_timer_init(np, rk_timer_v2_interrupt);
 247 }
 248
 249 CLOCKSOURCE_OF_DECLARE(rk3288_timer, "rockchip,rk3288-timer", rk_timer_v1_init);
 250 CLOCKSOURCE_OF_DECLARE(rk3399_timer, "rockchip,rk3399-timer", rk_timer_v2_init);