2 * Rockchip timer support
4 * Copyright (C) Daniel Lezcano <daniel.lezcano@linaro.org>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 #include <linux/clk.h>
11 #include <linux/clockchips.h>
12 #include <linux/init.h>
13 #include <linux/interrupt.h>
15 #include <linux/of_address.h>
16 #include <linux/of_irq.h>
18 #define TIMER_NAME "rk_timer"
20 #define TIMER_LOAD_COUNT0 0x00
21 #define TIMER_LOAD_COUNT1 0x04
22 #define TIMER_V1_CONTROL_REG 0x10
23 #define TIMER_INT_STATUS 0x18
24 #define TIMER_V2_CONTROL_REG 0x1c
26 #define TIMER_DISABLE 0x0
27 #define TIMER_ENABLE 0x1
28 #define TIMER_MODE_FREE_RUNNING (0 << 1)
29 #define TIMER_MODE_USER_DEFINED_COUNT (1 << 1)
30 #define TIMER_INT_UNMASK (1 << 2)
33 struct clock_event_device ce;
38 static struct bc_timer bc_timer;
40 static inline struct bc_timer *rk_timer(struct clock_event_device *ce)
42 return container_of(ce, struct bc_timer, ce);
45 static inline void __iomem *rk_base(struct clock_event_device *ce)
47 return rk_timer(ce)->base;
50 static inline void rk_timer_v1_disable(struct clock_event_device *ce)
52 writel_relaxed(TIMER_DISABLE, rk_base(ce) + TIMER_V1_CONTROL_REG);
55 static inline void rk_timer_v1_enable(struct clock_event_device *ce, u32 flags)
57 writel_relaxed(TIMER_ENABLE | TIMER_INT_UNMASK | flags,
58 rk_base(ce) + TIMER_V1_CONTROL_REG);
61 static inline void rk_timer_v2_disable(struct clock_event_device *ce)
63 writel_relaxed(TIMER_DISABLE, rk_base(ce) + TIMER_V2_CONTROL_REG);
66 static inline void rk_timer_v2_enable(struct clock_event_device *ce, u32 flags)
68 writel_relaxed(TIMER_ENABLE | TIMER_INT_UNMASK | flags,
69 rk_base(ce) + TIMER_V2_CONTROL_REG);
72 static void rk_timer_update_counter(unsigned long cycles,
73 struct clock_event_device *ce)
75 writel_relaxed(cycles, rk_base(ce) + TIMER_LOAD_COUNT0);
76 writel_relaxed(0, rk_base(ce) + TIMER_LOAD_COUNT1);
79 static void rk_timer_interrupt_clear(struct clock_event_device *ce)
81 writel_relaxed(1, rk_base(ce) + TIMER_INT_STATUS);
84 static int rk_timer_v1_set_next_event(unsigned long cycles,
85 struct clock_event_device *ce)
87 rk_timer_v1_disable(ce);
88 rk_timer_update_counter(cycles, ce);
89 rk_timer_v1_enable(ce, TIMER_MODE_USER_DEFINED_COUNT);
93 static int rk_timer_v1_shutdown(struct clock_event_device *ce)
95 rk_timer_v1_disable(ce);
99 static int rk_timer_v1_set_periodic(struct clock_event_device *ce)
101 rk_timer_v1_disable(ce);
102 rk_timer_update_counter(rk_timer(ce)->freq / HZ - 1, ce);
103 rk_timer_v1_enable(ce, TIMER_MODE_FREE_RUNNING);
107 static irqreturn_t rk_timer_v1_interrupt(int irq, void *dev_id)
109 struct clock_event_device *ce = dev_id;
111 rk_timer_interrupt_clear(ce);
113 if (clockevent_state_oneshot(ce))
114 rk_timer_v1_disable(ce);
116 ce->event_handler(ce);
121 static int rk_timer_v2_set_next_event(unsigned long cycles,
122 struct clock_event_device *ce)
124 rk_timer_v2_disable(ce);
125 rk_timer_update_counter(cycles, ce);
126 rk_timer_v2_enable(ce, TIMER_MODE_USER_DEFINED_COUNT);
130 static int rk_timer_v2_shutdown(struct clock_event_device *ce)
132 rk_timer_v2_disable(ce);
136 static int rk_timer_v2_set_periodic(struct clock_event_device *ce)
138 rk_timer_v2_disable(ce);
139 rk_timer_update_counter(rk_timer(ce)->freq / HZ - 1, ce);
140 rk_timer_v2_enable(ce, TIMER_MODE_FREE_RUNNING);
144 static irqreturn_t rk_timer_v2_interrupt(int irq, void *dev_id)
146 struct clock_event_device *ce = dev_id;
148 rk_timer_interrupt_clear(ce);
150 if (clockevent_state_oneshot(ce))
151 rk_timer_v2_disable(ce);
153 ce->event_handler(ce);
158 static void __init rk_timer_init(struct device_node *np,
159 irq_handler_t rk_timer_interrupt)
161 struct clock_event_device *ce = &bc_timer.ce;
162 struct clk *timer_clk;
166 bc_timer.base = of_iomap(np, 0);
167 if (!bc_timer.base) {
168 pr_err("Failed to get base address for '%s'\n", TIMER_NAME);
172 pclk = of_clk_get_by_name(np, "pclk");
174 pr_err("Failed to get pclk for '%s'\n", TIMER_NAME);
178 if (clk_prepare_enable(pclk)) {
179 pr_err("Failed to enable pclk for '%s'\n", TIMER_NAME);
183 timer_clk = of_clk_get_by_name(np, "timer");
184 if (IS_ERR(timer_clk)) {
185 pr_err("Failed to get timer clock for '%s'\n", TIMER_NAME);
189 if (clk_prepare_enable(timer_clk)) {
190 pr_err("Failed to enable timer clock\n");
194 bc_timer.freq = clk_get_rate(timer_clk);
196 irq = irq_of_parse_and_map(np, 0);
198 pr_err("Failed to map interrupts for '%s'\n", TIMER_NAME);
202 ce->name = TIMER_NAME;
203 ce->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT |
204 CLOCK_EVT_FEAT_DYNIRQ;
206 ce->cpumask = cpu_all_mask;
209 ret = request_irq(irq, rk_timer_interrupt, IRQF_TIMER, TIMER_NAME, ce);
211 pr_err("Failed to initialize '%s': %d\n", TIMER_NAME, ret);
215 clockevents_config_and_register(ce, bc_timer.freq, 1, UINT_MAX);
220 clk_disable_unprepare(timer_clk);
222 clk_disable_unprepare(pclk);
224 iounmap(bc_timer.base);
227 static void __init rk_timer_v1_init(struct device_node *np)
229 struct clock_event_device *ce = &bc_timer.ce;
231 ce->set_next_event = rk_timer_v1_set_next_event;
232 ce->set_state_shutdown = rk_timer_v1_shutdown;
233 ce->set_state_periodic = rk_timer_v1_set_periodic;
235 rk_timer_init(np, rk_timer_v1_interrupt);
238 static void __init rk_timer_v2_init(struct device_node *np)
240 struct clock_event_device *ce = &bc_timer.ce;
242 ce->set_next_event = rk_timer_v2_set_next_event;
243 ce->set_state_shutdown = rk_timer_v2_shutdown;
244 ce->set_state_periodic = rk_timer_v2_set_periodic;
246 rk_timer_init(np, rk_timer_v2_interrupt);
249 CLOCKSOURCE_OF_DECLARE(rk3288_timer, "rockchip,rk3288-timer", rk_timer_v1_init);
250 CLOCKSOURCE_OF_DECLARE(rk3399_timer, "rockchip,rk3399-timer", rk_timer_v2_init);