2 * SuperH Timer Support - CMT
4 * Copyright (C) 2008 Magnus Damm
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #include <linux/init.h>
21 #include <linux/platform_device.h>
22 #include <linux/spinlock.h>
23 #include <linux/interrupt.h>
24 #include <linux/ioport.h>
26 #include <linux/clk.h>
27 #include <linux/irq.h>
28 #include <linux/err.h>
29 #include <linux/clocksource.h>
30 #include <linux/clockchips.h>
31 #include <linux/sh_timer.h>
32 #include <linux/slab.h>
35 void __iomem *mapbase;
37 unsigned long width; /* 16 or 32 bit version of hardware block */
38 unsigned long overflow_bit;
39 unsigned long clear_bits;
40 struct irqaction irqaction;
41 struct platform_device *pdev;
44 unsigned long match_value;
45 unsigned long next_match_value;
46 unsigned long max_match_value;
49 struct clock_event_device ced;
50 struct clocksource cs;
51 unsigned long total_cycles;
54 static DEFINE_SPINLOCK(sh_cmt_lock);
56 #define CMSTR -1 /* shared register */
57 #define CMCSR 0 /* channel register */
58 #define CMCNT 1 /* channel register */
59 #define CMCOR 2 /* channel register */
61 static inline unsigned long sh_cmt_read(struct sh_cmt_priv *p, int reg_nr)
63 struct sh_timer_config *cfg = p->pdev->dev.platform_data;
64 void __iomem *base = p->mapbase;
67 if (reg_nr == CMSTR) {
69 base -= cfg->channel_offset;
77 if ((reg_nr == CMCNT) || (reg_nr == CMCOR))
78 return ioread32(base + offs);
81 return ioread16(base + offs);
84 static inline void sh_cmt_write(struct sh_cmt_priv *p, int reg_nr,
87 struct sh_timer_config *cfg = p->pdev->dev.platform_data;
88 void __iomem *base = p->mapbase;
91 if (reg_nr == CMSTR) {
93 base -= cfg->channel_offset;
101 if ((reg_nr == CMCNT) || (reg_nr == CMCOR)) {
102 iowrite32(value, base + offs);
107 iowrite16(value, base + offs);
110 static unsigned long sh_cmt_get_counter(struct sh_cmt_priv *p,
113 unsigned long v1, v2, v3;
116 o1 = sh_cmt_read(p, CMCSR) & p->overflow_bit;
118 /* Make sure the timer value is stable. Stolen from acpi_pm.c */
121 v1 = sh_cmt_read(p, CMCNT);
122 v2 = sh_cmt_read(p, CMCNT);
123 v3 = sh_cmt_read(p, CMCNT);
124 o1 = sh_cmt_read(p, CMCSR) & p->overflow_bit;
125 } while (unlikely((o1 != o2) || (v1 > v2 && v1 < v3)
126 || (v2 > v3 && v2 < v1) || (v3 > v1 && v3 < v2)));
133 static void sh_cmt_start_stop_ch(struct sh_cmt_priv *p, int start)
135 struct sh_timer_config *cfg = p->pdev->dev.platform_data;
136 unsigned long flags, value;
138 /* start stop register shared by multiple timer channels */
139 spin_lock_irqsave(&sh_cmt_lock, flags);
140 value = sh_cmt_read(p, CMSTR);
143 value |= 1 << cfg->timer_bit;
145 value &= ~(1 << cfg->timer_bit);
147 sh_cmt_write(p, CMSTR, value);
148 spin_unlock_irqrestore(&sh_cmt_lock, flags);
151 static int sh_cmt_enable(struct sh_cmt_priv *p, unsigned long *rate)
156 ret = clk_enable(p->clk);
158 dev_err(&p->pdev->dev, "cannot enable clock\n");
162 /* make sure channel is disabled */
163 sh_cmt_start_stop_ch(p, 0);
165 /* configure channel, periodic mode and maximum timeout */
166 if (p->width == 16) {
167 *rate = clk_get_rate(p->clk) / 512;
168 sh_cmt_write(p, CMCSR, 0x43);
170 *rate = clk_get_rate(p->clk) / 8;
171 sh_cmt_write(p, CMCSR, 0x01a4);
174 sh_cmt_write(p, CMCOR, 0xffffffff);
175 sh_cmt_write(p, CMCNT, 0);
178 sh_cmt_start_stop_ch(p, 1);
182 static void sh_cmt_disable(struct sh_cmt_priv *p)
184 /* disable channel */
185 sh_cmt_start_stop_ch(p, 0);
187 /* disable interrupts in CMT block */
188 sh_cmt_write(p, CMCSR, 0);
195 #define FLAG_CLOCKEVENT (1 << 0)
196 #define FLAG_CLOCKSOURCE (1 << 1)
197 #define FLAG_REPROGRAM (1 << 2)
198 #define FLAG_SKIPEVENT (1 << 3)
199 #define FLAG_IRQCONTEXT (1 << 4)
201 static void sh_cmt_clock_event_program_verify(struct sh_cmt_priv *p,
204 unsigned long new_match;
205 unsigned long value = p->next_match_value;
206 unsigned long delay = 0;
207 unsigned long now = 0;
210 now = sh_cmt_get_counter(p, &has_wrapped);
211 p->flags |= FLAG_REPROGRAM; /* force reprogram */
214 /* we're competing with the interrupt handler.
215 * -> let the interrupt handler reprogram the timer.
216 * -> interrupt number two handles the event.
218 p->flags |= FLAG_SKIPEVENT;
226 /* reprogram the timer hardware,
227 * but don't save the new match value yet.
229 new_match = now + value + delay;
230 if (new_match > p->max_match_value)
231 new_match = p->max_match_value;
233 sh_cmt_write(p, CMCOR, new_match);
235 now = sh_cmt_get_counter(p, &has_wrapped);
236 if (has_wrapped && (new_match > p->match_value)) {
237 /* we are changing to a greater match value,
238 * so this wrap must be caused by the counter
239 * matching the old value.
240 * -> first interrupt reprograms the timer.
241 * -> interrupt number two handles the event.
243 p->flags |= FLAG_SKIPEVENT;
248 /* we are changing to a smaller match value,
249 * so the wrap must be caused by the counter
250 * matching the new value.
251 * -> save programmed match value.
252 * -> let isr handle the event.
254 p->match_value = new_match;
258 /* be safe: verify hardware settings */
259 if (now < new_match) {
260 /* timer value is below match value, all good.
261 * this makes sure we won't miss any match events.
262 * -> save programmed match value.
263 * -> let isr handle the event.
265 p->match_value = new_match;
269 /* the counter has reached a value greater
270 * than our new match value. and since the
271 * has_wrapped flag isn't set we must have
272 * programmed a too close event.
273 * -> increase delay and retry.
281 dev_warn(&p->pdev->dev, "too long delay\n");
286 static void sh_cmt_set_next(struct sh_cmt_priv *p, unsigned long delta)
290 if (delta > p->max_match_value)
291 dev_warn(&p->pdev->dev, "delta out of range\n");
293 spin_lock_irqsave(&p->lock, flags);
294 p->next_match_value = delta;
295 sh_cmt_clock_event_program_verify(p, 0);
296 spin_unlock_irqrestore(&p->lock, flags);
299 static irqreturn_t sh_cmt_interrupt(int irq, void *dev_id)
301 struct sh_cmt_priv *p = dev_id;
304 sh_cmt_write(p, CMCSR, sh_cmt_read(p, CMCSR) & p->clear_bits);
306 /* update clock source counter to begin with if enabled
307 * the wrap flag should be cleared by the timer specific
308 * isr before we end up here.
310 if (p->flags & FLAG_CLOCKSOURCE)
311 p->total_cycles += p->match_value;
313 if (!(p->flags & FLAG_REPROGRAM))
314 p->next_match_value = p->max_match_value;
316 p->flags |= FLAG_IRQCONTEXT;
318 if (p->flags & FLAG_CLOCKEVENT) {
319 if (!(p->flags & FLAG_SKIPEVENT)) {
320 if (p->ced.mode == CLOCK_EVT_MODE_ONESHOT) {
321 p->next_match_value = p->max_match_value;
322 p->flags |= FLAG_REPROGRAM;
325 p->ced.event_handler(&p->ced);
329 p->flags &= ~FLAG_SKIPEVENT;
331 if (p->flags & FLAG_REPROGRAM) {
332 p->flags &= ~FLAG_REPROGRAM;
333 sh_cmt_clock_event_program_verify(p, 1);
335 if (p->flags & FLAG_CLOCKEVENT)
336 if ((p->ced.mode == CLOCK_EVT_MODE_SHUTDOWN)
337 || (p->match_value == p->next_match_value))
338 p->flags &= ~FLAG_REPROGRAM;
341 p->flags &= ~FLAG_IRQCONTEXT;
346 static int sh_cmt_start(struct sh_cmt_priv *p, unsigned long flag)
351 spin_lock_irqsave(&p->lock, flags);
353 if (!(p->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE)))
354 ret = sh_cmt_enable(p, &p->rate);
360 /* setup timeout if no clockevent */
361 if ((flag == FLAG_CLOCKSOURCE) && (!(p->flags & FLAG_CLOCKEVENT)))
362 sh_cmt_set_next(p, p->max_match_value);
364 spin_unlock_irqrestore(&p->lock, flags);
369 static void sh_cmt_stop(struct sh_cmt_priv *p, unsigned long flag)
374 spin_lock_irqsave(&p->lock, flags);
376 f = p->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE);
379 if (f && !(p->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE)))
382 /* adjust the timeout to maximum if only clocksource left */
383 if ((flag == FLAG_CLOCKEVENT) && (p->flags & FLAG_CLOCKSOURCE))
384 sh_cmt_set_next(p, p->max_match_value);
386 spin_unlock_irqrestore(&p->lock, flags);
389 static struct sh_cmt_priv *cs_to_sh_cmt(struct clocksource *cs)
391 return container_of(cs, struct sh_cmt_priv, cs);
394 static cycle_t sh_cmt_clocksource_read(struct clocksource *cs)
396 struct sh_cmt_priv *p = cs_to_sh_cmt(cs);
397 unsigned long flags, raw;
401 spin_lock_irqsave(&p->lock, flags);
402 value = p->total_cycles;
403 raw = sh_cmt_get_counter(p, &has_wrapped);
405 if (unlikely(has_wrapped))
406 raw += p->match_value;
407 spin_unlock_irqrestore(&p->lock, flags);
412 static int sh_cmt_clocksource_enable(struct clocksource *cs)
414 struct sh_cmt_priv *p = cs_to_sh_cmt(cs);
419 ret = sh_cmt_start(p, FLAG_CLOCKSOURCE);
423 /* TODO: calculate good shift from rate and counter bit width */
425 cs->mult = clocksource_hz2mult(p->rate, cs->shift);
429 static void sh_cmt_clocksource_disable(struct clocksource *cs)
431 sh_cmt_stop(cs_to_sh_cmt(cs), FLAG_CLOCKSOURCE);
434 static void sh_cmt_clocksource_resume(struct clocksource *cs)
436 sh_cmt_start(cs_to_sh_cmt(cs), FLAG_CLOCKSOURCE);
439 static int sh_cmt_register_clocksource(struct sh_cmt_priv *p,
440 char *name, unsigned long rating)
442 struct clocksource *cs = &p->cs;
446 cs->read = sh_cmt_clocksource_read;
447 cs->enable = sh_cmt_clocksource_enable;
448 cs->disable = sh_cmt_clocksource_disable;
449 cs->suspend = sh_cmt_clocksource_disable;
450 cs->resume = sh_cmt_clocksource_resume;
451 cs->mask = CLOCKSOURCE_MASK(sizeof(unsigned long) * 8);
452 cs->flags = CLOCK_SOURCE_IS_CONTINUOUS;
453 dev_info(&p->pdev->dev, "used as clock source\n");
454 clocksource_register(cs);
458 static struct sh_cmt_priv *ced_to_sh_cmt(struct clock_event_device *ced)
460 return container_of(ced, struct sh_cmt_priv, ced);
463 static void sh_cmt_clock_event_start(struct sh_cmt_priv *p, int periodic)
465 struct clock_event_device *ced = &p->ced;
467 sh_cmt_start(p, FLAG_CLOCKEVENT);
469 /* TODO: calculate good shift from rate and counter bit width */
472 ced->mult = div_sc(p->rate, NSEC_PER_SEC, ced->shift);
473 ced->max_delta_ns = clockevent_delta2ns(p->max_match_value, ced);
474 ced->min_delta_ns = clockevent_delta2ns(0x1f, ced);
477 sh_cmt_set_next(p, (p->rate + HZ/2) / HZ);
479 sh_cmt_set_next(p, p->max_match_value);
482 static void sh_cmt_clock_event_mode(enum clock_event_mode mode,
483 struct clock_event_device *ced)
485 struct sh_cmt_priv *p = ced_to_sh_cmt(ced);
487 /* deal with old setting first */
489 case CLOCK_EVT_MODE_PERIODIC:
490 case CLOCK_EVT_MODE_ONESHOT:
491 sh_cmt_stop(p, FLAG_CLOCKEVENT);
498 case CLOCK_EVT_MODE_PERIODIC:
499 dev_info(&p->pdev->dev, "used for periodic clock events\n");
500 sh_cmt_clock_event_start(p, 1);
502 case CLOCK_EVT_MODE_ONESHOT:
503 dev_info(&p->pdev->dev, "used for oneshot clock events\n");
504 sh_cmt_clock_event_start(p, 0);
506 case CLOCK_EVT_MODE_SHUTDOWN:
507 case CLOCK_EVT_MODE_UNUSED:
508 sh_cmt_stop(p, FLAG_CLOCKEVENT);
515 static int sh_cmt_clock_event_next(unsigned long delta,
516 struct clock_event_device *ced)
518 struct sh_cmt_priv *p = ced_to_sh_cmt(ced);
520 BUG_ON(ced->mode != CLOCK_EVT_MODE_ONESHOT);
521 if (likely(p->flags & FLAG_IRQCONTEXT))
522 p->next_match_value = delta;
524 sh_cmt_set_next(p, delta);
529 static void sh_cmt_register_clockevent(struct sh_cmt_priv *p,
530 char *name, unsigned long rating)
532 struct clock_event_device *ced = &p->ced;
534 memset(ced, 0, sizeof(*ced));
537 ced->features = CLOCK_EVT_FEAT_PERIODIC;
538 ced->features |= CLOCK_EVT_FEAT_ONESHOT;
539 ced->rating = rating;
540 ced->cpumask = cpumask_of(0);
541 ced->set_next_event = sh_cmt_clock_event_next;
542 ced->set_mode = sh_cmt_clock_event_mode;
544 dev_info(&p->pdev->dev, "used for clock events\n");
545 clockevents_register_device(ced);
548 static int sh_cmt_register(struct sh_cmt_priv *p, char *name,
549 unsigned long clockevent_rating,
550 unsigned long clocksource_rating)
552 if (p->width == (sizeof(p->max_match_value) * 8))
553 p->max_match_value = ~0;
555 p->max_match_value = (1 << p->width) - 1;
557 p->match_value = p->max_match_value;
558 spin_lock_init(&p->lock);
560 if (clockevent_rating)
561 sh_cmt_register_clockevent(p, name, clockevent_rating);
563 if (clocksource_rating)
564 sh_cmt_register_clocksource(p, name, clocksource_rating);
569 static int sh_cmt_setup(struct sh_cmt_priv *p, struct platform_device *pdev)
571 struct sh_timer_config *cfg = pdev->dev.platform_data;
572 struct resource *res;
576 memset(p, 0, sizeof(*p));
580 dev_err(&p->pdev->dev, "missing platform data\n");
584 platform_set_drvdata(pdev, p);
586 res = platform_get_resource(p->pdev, IORESOURCE_MEM, 0);
588 dev_err(&p->pdev->dev, "failed to get I/O memory\n");
592 irq = platform_get_irq(p->pdev, 0);
594 dev_err(&p->pdev->dev, "failed to get irq\n");
598 /* map memory, let mapbase point to our channel */
599 p->mapbase = ioremap_nocache(res->start, resource_size(res));
600 if (p->mapbase == NULL) {
601 dev_err(&p->pdev->dev, "failed to remap I/O memory\n");
605 /* request irq using setup_irq() (too early for request_irq()) */
606 p->irqaction.name = dev_name(&p->pdev->dev);
607 p->irqaction.handler = sh_cmt_interrupt;
608 p->irqaction.dev_id = p;
609 p->irqaction.flags = IRQF_DISABLED | IRQF_TIMER | \
610 IRQF_IRQPOLL | IRQF_NOBALANCING;
612 /* get hold of clock */
613 p->clk = clk_get(&p->pdev->dev, "cmt_fck");
614 if (IS_ERR(p->clk)) {
615 dev_warn(&p->pdev->dev, "using deprecated clock lookup\n");
616 p->clk = clk_get(&p->pdev->dev, cfg->clk);
617 if (IS_ERR(p->clk)) {
618 dev_err(&p->pdev->dev, "cannot get clock\n");
619 ret = PTR_ERR(p->clk);
624 if (resource_size(res) == 6) {
626 p->overflow_bit = 0x80;
627 p->clear_bits = ~0x80;
630 p->overflow_bit = 0x8000;
631 p->clear_bits = ~0xc000;
634 ret = sh_cmt_register(p, (char *)dev_name(&p->pdev->dev),
635 cfg->clockevent_rating,
636 cfg->clocksource_rating);
638 dev_err(&p->pdev->dev, "registration failed\n");
642 ret = setup_irq(irq, &p->irqaction);
644 dev_err(&p->pdev->dev, "failed to request irq %d\n", irq);
656 static int __devinit sh_cmt_probe(struct platform_device *pdev)
658 struct sh_cmt_priv *p = platform_get_drvdata(pdev);
662 dev_info(&pdev->dev, "kept as earlytimer\n");
666 p = kmalloc(sizeof(*p), GFP_KERNEL);
668 dev_err(&pdev->dev, "failed to allocate driver data\n");
672 ret = sh_cmt_setup(p, pdev);
675 platform_set_drvdata(pdev, NULL);
680 static int __devexit sh_cmt_remove(struct platform_device *pdev)
682 return -EBUSY; /* cannot unregister clockevent and clocksource */
685 static struct platform_driver sh_cmt_device_driver = {
686 .probe = sh_cmt_probe,
687 .remove = __devexit_p(sh_cmt_remove),
693 static int __init sh_cmt_init(void)
695 return platform_driver_register(&sh_cmt_device_driver);
698 static void __exit sh_cmt_exit(void)
700 platform_driver_unregister(&sh_cmt_device_driver);
703 early_platform_init("earlytimer", &sh_cmt_device_driver);
704 module_init(sh_cmt_init);
705 module_exit(sh_cmt_exit);
707 MODULE_AUTHOR("Magnus Damm");
708 MODULE_DESCRIPTION("SuperH CMT Timer Driver");
709 MODULE_LICENSE("GPL v2");